1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
39
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
45
46 #include "drm_crtc_internal.h"
47
oui(u8 first,u8 second,u8 third)48 static int oui(u8 first, u8 second, u8 third)
49 {
50 return (first << 16) | (second << 8) | third;
51 }
52
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
56
57 /*
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
62 */
63
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
74 */
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
80 /* Force 8bpc */
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
82 /* Force 12bpc */
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
84 /* Force 6bpc */
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
86 /* Force 10bpc */
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
90 /* Cap the DSC target bitrate to 15bpp */
91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
92
93 #define MICROSOFT_IEEE_OUI 0xca125c
94
95 struct detailed_mode_closure {
96 struct drm_connector *connector;
97 const struct drm_edid *drm_edid;
98 bool preferred;
99 u32 quirks;
100 int modes;
101 };
102
103 #define LEVEL_DMT 0
104 #define LEVEL_GTF 1
105 #define LEVEL_GTF2 2
106 #define LEVEL_CVT 3
107
108 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
109 { \
110 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
111 product_id), \
112 .quirks = _quirks \
113 }
114
115 static const struct edid_quirk {
116 u32 panel_id;
117 u32 quirks;
118 } edid_quirk_list[] = {
119 /* Acer AL1706 */
120 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
121 /* Acer F51 */
122 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
123
124 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
125 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
126
127 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
128 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
129
130 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
131 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
132
133 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
134 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
135
136 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
137 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
138
139 /* Belinea 10 15 55 */
140 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
141 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
142
143 /* Envision Peripherals, Inc. EN-7100e */
144 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
145 /* Envision EN2028 */
146 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
147
148 /* Funai Electronics PM36B */
149 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
150 EDID_QUIRK_DETAILED_IN_CM),
151
152 /* LG 27GP950 */
153 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
154
155 /* LG 27GN950 */
156 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
157
158 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
159 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
160
161 /* LG Philips LCD LP154W01-A5 */
162 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
163 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
164
165 /* Samsung SyncMaster 205BW. Note: irony */
166 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
167 /* Samsung SyncMaster 22[5-6]BW */
168 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
169 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
170
171 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
172 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
173
174 /* ViewSonic VA2026w */
175 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
176
177 /* Medion MD 30217 PG */
178 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
179
180 /* Lenovo G50 */
181 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
182
183 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
184 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
185
186 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
187 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
188
189 /* Valve Index Headset */
190 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
207
208 /* HTC Vive and Vive Pro VR Headsets */
209 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
211
212 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
213 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
217
218 /* Windows Mixed Reality Headsets */
219 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
225
226 /* Sony PlayStation VR Headset */
227 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
228
229 /* Sensics VR Headsets */
230 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
231
232 /* OSVR HDK and HDK2 VR Headsets */
233 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
234 };
235
236 /*
237 * Autogenerated from the DMT spec.
238 * This table is copied from xfree86/modes/xf86EdidModes.c.
239 */
240 static const struct drm_display_mode drm_dmt_modes[] = {
241 /* 0x01 - 640x350@85Hz */
242 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
243 736, 832, 0, 350, 382, 385, 445, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x02 - 640x400@85Hz */
246 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
247 736, 832, 0, 400, 401, 404, 445, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 0x03 - 720x400@85Hz */
250 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
251 828, 936, 0, 400, 401, 404, 446, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x04 - 640x480@60Hz */
254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
255 752, 800, 0, 480, 490, 492, 525, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
257 /* 0x05 - 640x480@72Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
259 704, 832, 0, 480, 489, 492, 520, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x06 - 640x480@75Hz */
262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
263 720, 840, 0, 480, 481, 484, 500, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x07 - 640x480@85Hz */
266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
267 752, 832, 0, 480, 481, 484, 509, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
269 /* 0x08 - 800x600@56Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
271 896, 1024, 0, 600, 601, 603, 625, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x09 - 800x600@60Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
275 968, 1056, 0, 600, 601, 605, 628, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0a - 800x600@72Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
279 976, 1040, 0, 600, 637, 643, 666, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0b - 800x600@75Hz */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
283 896, 1056, 0, 600, 601, 604, 625, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
285 /* 0x0c - 800x600@85Hz */
286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
287 896, 1048, 0, 600, 601, 604, 631, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x0d - 800x600@120Hz RB */
290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
291 880, 960, 0, 600, 603, 607, 636, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 0x0e - 848x480@60Hz */
294 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
295 976, 1088, 0, 480, 486, 494, 517, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x0f - 1024x768@43Hz, interlace */
298 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
299 1208, 1264, 0, 768, 768, 776, 817, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
301 DRM_MODE_FLAG_INTERLACE) },
302 /* 0x10 - 1024x768@60Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
304 1184, 1344, 0, 768, 771, 777, 806, 0,
305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x11 - 1024x768@70Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
308 1184, 1328, 0, 768, 771, 777, 806, 0,
309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
310 /* 0x12 - 1024x768@75Hz */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
312 1136, 1312, 0, 768, 769, 772, 800, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x13 - 1024x768@85Hz */
315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
316 1168, 1376, 0, 768, 769, 772, 808, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x14 - 1024x768@120Hz RB */
319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
320 1104, 1184, 0, 768, 771, 775, 813, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
322 /* 0x15 - 1152x864@75Hz */
323 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
324 1344, 1600, 0, 864, 865, 868, 900, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x55 - 1280x720@60Hz */
327 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
328 1430, 1650, 0, 720, 725, 730, 750, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x16 - 1280x768@60Hz RB */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
332 1360, 1440, 0, 768, 771, 778, 790, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x17 - 1280x768@60Hz */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
336 1472, 1664, 0, 768, 771, 778, 798, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x18 - 1280x768@75Hz */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
340 1488, 1696, 0, 768, 771, 778, 805, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x19 - 1280x768@85Hz */
343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
344 1496, 1712, 0, 768, 771, 778, 809, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x1a - 1280x768@120Hz RB */
347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
348 1360, 1440, 0, 768, 771, 778, 813, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 0x1b - 1280x800@60Hz RB */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
352 1360, 1440, 0, 800, 803, 809, 823, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x1c - 1280x800@60Hz */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
356 1480, 1680, 0, 800, 803, 809, 831, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x1d - 1280x800@75Hz */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
360 1488, 1696, 0, 800, 803, 809, 838, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x1e - 1280x800@85Hz */
363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
364 1496, 1712, 0, 800, 803, 809, 843, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x1f - 1280x800@120Hz RB */
367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
368 1360, 1440, 0, 800, 803, 809, 847, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
370 /* 0x20 - 1280x960@60Hz */
371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
372 1488, 1800, 0, 960, 961, 964, 1000, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x21 - 1280x960@85Hz */
375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
376 1504, 1728, 0, 960, 961, 964, 1011, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x22 - 1280x960@120Hz RB */
379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
380 1360, 1440, 0, 960, 963, 967, 1017, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
382 /* 0x23 - 1280x1024@60Hz */
383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x24 - 1280x1024@75Hz */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x25 - 1280x1024@85Hz */
391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
392 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x26 - 1280x1024@120Hz RB */
395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
396 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x27 - 1360x768@60Hz */
399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
400 1536, 1792, 0, 768, 771, 777, 795, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x28 - 1360x768@120Hz RB */
403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
404 1440, 1520, 0, 768, 771, 776, 813, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
406 /* 0x51 - 1366x768@60Hz */
407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
408 1579, 1792, 0, 768, 771, 774, 798, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x56 - 1366x768@60Hz */
411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
412 1436, 1500, 0, 768, 769, 772, 800, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x29 - 1400x1050@60Hz RB */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
416 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x2a - 1400x1050@60Hz */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
420 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x2b - 1400x1050@75Hz */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
424 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x2c - 1400x1050@85Hz */
427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
428 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x2d - 1400x1050@120Hz RB */
431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
432 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434 /* 0x2e - 1440x900@60Hz RB */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
436 1520, 1600, 0, 900, 903, 909, 926, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x2f - 1440x900@60Hz */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
440 1672, 1904, 0, 900, 903, 909, 934, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x30 - 1440x900@75Hz */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
444 1688, 1936, 0, 900, 903, 909, 942, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x31 - 1440x900@85Hz */
447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
448 1696, 1952, 0, 900, 903, 909, 948, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x32 - 1440x900@120Hz RB */
451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
452 1520, 1600, 0, 900, 903, 909, 953, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 0x53 - 1600x900@60Hz */
455 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
456 1704, 1800, 0, 900, 901, 904, 1000, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x33 - 1600x1200@60Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x34 - 1600x1200@65Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x35 - 1600x1200@70Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x36 - 1600x1200@75Hz */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x37 - 1600x1200@85Hz */
475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x38 - 1600x1200@120Hz RB */
479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
480 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x39 - 1680x1050@60Hz RB */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
484 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x3a - 1680x1050@60Hz */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
488 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3b - 1680x1050@75Hz */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
492 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x3c - 1680x1050@85Hz */
495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
496 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x3d - 1680x1050@120Hz RB */
499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
500 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
502 /* 0x3e - 1792x1344@60Hz */
503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
504 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x3f - 1792x1344@75Hz */
507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
508 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x40 - 1792x1344@120Hz RB */
511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
512 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x41 - 1856x1392@60Hz */
515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
516 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
518 /* 0x42 - 1856x1392@75Hz */
519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
520 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x43 - 1856x1392@120Hz RB */
523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
524 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
526 /* 0x52 - 1920x1080@60Hz */
527 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
528 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
530 /* 0x44 - 1920x1200@60Hz RB */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
532 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
534 /* 0x45 - 1920x1200@60Hz */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
536 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x46 - 1920x1200@75Hz */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
540 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x47 - 1920x1200@85Hz */
543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
544 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x48 - 1920x1200@120Hz RB */
547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
548 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
550 /* 0x49 - 1920x1440@60Hz */
551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
552 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
554 /* 0x4a - 1920x1440@75Hz */
555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
556 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4b - 1920x1440@120Hz RB */
559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
560 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
562 /* 0x54 - 2048x1152@60Hz */
563 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
564 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x4c - 2560x1600@60Hz RB */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
568 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
570 /* 0x4d - 2560x1600@60Hz */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
572 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
574 /* 0x4e - 2560x1600@75Hz */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
576 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
578 /* 0x4f - 2560x1600@85Hz */
579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
580 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
582 /* 0x50 - 2560x1600@120Hz RB */
583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
584 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
586 /* 0x57 - 4096x2160@60Hz RB */
587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
590 /* 0x58 - 4096x2160@59.94Hz RB */
591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
594 };
595
596 /*
597 * These more or less come from the DMT spec. The 720x400 modes are
598 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
599 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
600 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
601 * mode.
602 *
603 * The DMT modes have been fact-checked; the rest are mild guesses.
604 */
605 static const struct drm_display_mode edid_est_modes[] = {
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
607 968, 1056, 0, 600, 601, 605, 628, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
610 896, 1024, 0, 600, 601, 603, 625, 0,
611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
613 720, 840, 0, 480, 481, 484, 500, 0,
614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
616 704, 832, 0, 480, 489, 492, 520, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
619 768, 864, 0, 480, 483, 486, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
622 752, 800, 0, 480, 490, 492, 525, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
625 846, 900, 0, 400, 421, 423, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
628 846, 900, 0, 400, 412, 414, 449, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
630 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
631 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
634 1136, 1312, 0, 768, 769, 772, 800, 0,
635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
637 1184, 1328, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
640 1184, 1344, 0, 768, 771, 777, 806, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
642 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
643 1208, 1264, 0, 768, 768, 776, 817, 0,
644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
645 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
646 928, 1152, 0, 624, 625, 628, 667, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
649 896, 1056, 0, 600, 601, 604, 625, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
652 976, 1040, 0, 600, 637, 643, 666, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
654 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
655 1344, 1600, 0, 864, 865, 868, 900, 0,
656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
657 };
658
659 struct minimode {
660 short w;
661 short h;
662 short r;
663 short rb;
664 };
665
666 static const struct minimode est3_modes[] = {
667 /* byte 6 */
668 { 640, 350, 85, 0 },
669 { 640, 400, 85, 0 },
670 { 720, 400, 85, 0 },
671 { 640, 480, 85, 0 },
672 { 848, 480, 60, 0 },
673 { 800, 600, 85, 0 },
674 { 1024, 768, 85, 0 },
675 { 1152, 864, 75, 0 },
676 /* byte 7 */
677 { 1280, 768, 60, 1 },
678 { 1280, 768, 60, 0 },
679 { 1280, 768, 75, 0 },
680 { 1280, 768, 85, 0 },
681 { 1280, 960, 60, 0 },
682 { 1280, 960, 85, 0 },
683 { 1280, 1024, 60, 0 },
684 { 1280, 1024, 85, 0 },
685 /* byte 8 */
686 { 1360, 768, 60, 0 },
687 { 1440, 900, 60, 1 },
688 { 1440, 900, 60, 0 },
689 { 1440, 900, 75, 0 },
690 { 1440, 900, 85, 0 },
691 { 1400, 1050, 60, 1 },
692 { 1400, 1050, 60, 0 },
693 { 1400, 1050, 75, 0 },
694 /* byte 9 */
695 { 1400, 1050, 85, 0 },
696 { 1680, 1050, 60, 1 },
697 { 1680, 1050, 60, 0 },
698 { 1680, 1050, 75, 0 },
699 { 1680, 1050, 85, 0 },
700 { 1600, 1200, 60, 0 },
701 { 1600, 1200, 65, 0 },
702 { 1600, 1200, 70, 0 },
703 /* byte 10 */
704 { 1600, 1200, 75, 0 },
705 { 1600, 1200, 85, 0 },
706 { 1792, 1344, 60, 0 },
707 { 1792, 1344, 75, 0 },
708 { 1856, 1392, 60, 0 },
709 { 1856, 1392, 75, 0 },
710 { 1920, 1200, 60, 1 },
711 { 1920, 1200, 60, 0 },
712 /* byte 11 */
713 { 1920, 1200, 75, 0 },
714 { 1920, 1200, 85, 0 },
715 { 1920, 1440, 60, 0 },
716 { 1920, 1440, 75, 0 },
717 };
718
719 static const struct minimode extra_modes[] = {
720 { 1024, 576, 60, 0 },
721 { 1366, 768, 60, 0 },
722 { 1600, 900, 60, 0 },
723 { 1680, 945, 60, 0 },
724 { 1920, 1080, 60, 0 },
725 { 2048, 1152, 60, 0 },
726 { 2048, 1536, 60, 0 },
727 };
728
729 /*
730 * From CEA/CTA-861 spec.
731 *
732 * Do not access directly, instead always use cea_mode_for_vic().
733 */
734 static const struct drm_display_mode edid_cea_modes_1[] = {
735 /* 1 - 640x480@60Hz 4:3 */
736 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
737 752, 800, 0, 480, 490, 492, 525, 0,
738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
740 /* 2 - 720x480@60Hz 4:3 */
741 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
742 798, 858, 0, 480, 489, 495, 525, 0,
743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
745 /* 3 - 720x480@60Hz 16:9 */
746 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
747 798, 858, 0, 480, 489, 495, 525, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
750 /* 4 - 1280x720@60Hz 16:9 */
751 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
752 1430, 1650, 0, 720, 725, 730, 750, 0,
753 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
755 /* 5 - 1920x1080i@60Hz 16:9 */
756 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
757 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
759 DRM_MODE_FLAG_INTERLACE),
760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 6 - 720(1440)x480i@60Hz 4:3 */
762 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
763 801, 858, 0, 480, 488, 494, 525, 0,
764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
767 /* 7 - 720(1440)x480i@60Hz 16:9 */
768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
769 801, 858, 0, 480, 488, 494, 525, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
773 /* 8 - 720(1440)x240@60Hz 4:3 */
774 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
775 801, 858, 0, 240, 244, 247, 262, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_DBLCLK),
778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
779 /* 9 - 720(1440)x240@60Hz 16:9 */
780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
781 801, 858, 0, 240, 244, 247, 262, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_DBLCLK),
784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
785 /* 10 - 2880x480i@60Hz 4:3 */
786 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 480, 488, 494, 525, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_INTERLACE),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
791 /* 11 - 2880x480i@60Hz 16:9 */
792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
793 3204, 3432, 0, 480, 488, 494, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE),
796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
797 /* 12 - 2880x240@60Hz 4:3 */
798 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
799 3204, 3432, 0, 240, 244, 247, 262, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
802 /* 13 - 2880x240@60Hz 16:9 */
803 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
804 3204, 3432, 0, 240, 244, 247, 262, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
807 /* 14 - 1440x480@60Hz 4:3 */
808 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
809 1596, 1716, 0, 480, 489, 495, 525, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
812 /* 15 - 1440x480@60Hz 16:9 */
813 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
814 1596, 1716, 0, 480, 489, 495, 525, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
817 /* 16 - 1920x1080@60Hz 16:9 */
818 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
819 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 17 - 720x576@50Hz 4:3 */
823 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
824 796, 864, 0, 576, 581, 586, 625, 0,
825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
827 /* 18 - 720x576@50Hz 16:9 */
828 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
829 796, 864, 0, 576, 581, 586, 625, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 19 - 1280x720@50Hz 16:9 */
833 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
834 1760, 1980, 0, 720, 725, 730, 750, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 20 - 1920x1080i@50Hz 16:9 */
838 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
839 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
841 DRM_MODE_FLAG_INTERLACE),
842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 21 - 720(1440)x576i@50Hz 4:3 */
844 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
845 795, 864, 0, 576, 580, 586, 625, 0,
846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
847 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
849 /* 22 - 720(1440)x576i@50Hz 16:9 */
850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
851 795, 864, 0, 576, 580, 586, 625, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
855 /* 23 - 720(1440)x288@50Hz 4:3 */
856 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
857 795, 864, 0, 288, 290, 293, 312, 0,
858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
859 DRM_MODE_FLAG_DBLCLK),
860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
861 /* 24 - 720(1440)x288@50Hz 16:9 */
862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
863 795, 864, 0, 288, 290, 293, 312, 0,
864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
865 DRM_MODE_FLAG_DBLCLK),
866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
867 /* 25 - 2880x576i@50Hz 4:3 */
868 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 576, 580, 586, 625, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
871 DRM_MODE_FLAG_INTERLACE),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
873 /* 26 - 2880x576i@50Hz 16:9 */
874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
875 3180, 3456, 0, 576, 580, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
877 DRM_MODE_FLAG_INTERLACE),
878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
879 /* 27 - 2880x288@50Hz 4:3 */
880 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
881 3180, 3456, 0, 288, 290, 293, 312, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
884 /* 28 - 2880x288@50Hz 16:9 */
885 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
886 3180, 3456, 0, 288, 290, 293, 312, 0,
887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 29 - 1440x576@50Hz 4:3 */
890 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
891 1592, 1728, 0, 576, 581, 586, 625, 0,
892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
894 /* 30 - 1440x576@50Hz 16:9 */
895 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
896 1592, 1728, 0, 576, 581, 586, 625, 0,
897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
899 /* 31 - 1920x1080@50Hz 16:9 */
900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 32 - 1920x1080@24Hz 16:9 */
905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
906 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
909 /* 33 - 1920x1080@25Hz 16:9 */
910 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
911 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
914 /* 34 - 1920x1080@30Hz 16:9 */
915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
916 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 35 - 2880x480@60Hz 4:3 */
920 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
921 3192, 3432, 0, 480, 489, 495, 525, 0,
922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
924 /* 36 - 2880x480@60Hz 16:9 */
925 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
926 3192, 3432, 0, 480, 489, 495, 525, 0,
927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 37 - 2880x576@50Hz 4:3 */
930 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
931 3184, 3456, 0, 576, 581, 586, 625, 0,
932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
934 /* 38 - 2880x576@50Hz 16:9 */
935 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
936 3184, 3456, 0, 576, 581, 586, 625, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939 /* 39 - 1920x1080i@50Hz 16:9 */
940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
941 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
943 DRM_MODE_FLAG_INTERLACE),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 40 - 1920x1080i@100Hz 16:9 */
946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
947 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
949 DRM_MODE_FLAG_INTERLACE),
950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
951 /* 41 - 1280x720@100Hz 16:9 */
952 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
953 1760, 1980, 0, 720, 725, 730, 750, 0,
954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
956 /* 42 - 720x576@100Hz 4:3 */
957 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
958 796, 864, 0, 576, 581, 586, 625, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
961 /* 43 - 720x576@100Hz 16:9 */
962 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
963 796, 864, 0, 576, 581, 586, 625, 0,
964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 44 - 720(1440)x576i@100Hz 4:3 */
967 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
968 795, 864, 0, 576, 580, 586, 625, 0,
969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
972 /* 45 - 720(1440)x576i@100Hz 16:9 */
973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
974 795, 864, 0, 576, 580, 586, 625, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978 /* 46 - 1920x1080i@120Hz 16:9 */
979 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
980 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
982 DRM_MODE_FLAG_INTERLACE),
983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 47 - 1280x720@120Hz 16:9 */
985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
986 1430, 1650, 0, 720, 725, 730, 750, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
989 /* 48 - 720x480@120Hz 4:3 */
990 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
991 798, 858, 0, 480, 489, 495, 525, 0,
992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
994 /* 49 - 720x480@120Hz 16:9 */
995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
996 798, 858, 0, 480, 489, 495, 525, 0,
997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 50 - 720(1440)x480i@120Hz 4:3 */
1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1001 801, 858, 0, 480, 488, 494, 525, 0,
1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1003 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1005 /* 51 - 720(1440)x480i@120Hz 16:9 */
1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1007 801, 858, 0, 480, 488, 494, 525, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1011 /* 52 - 720x576@200Hz 4:3 */
1012 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1013 796, 864, 0, 576, 581, 586, 625, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1016 /* 53 - 720x576@200Hz 16:9 */
1017 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1018 796, 864, 0, 576, 581, 586, 625, 0,
1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1021 /* 54 - 720(1440)x576i@200Hz 4:3 */
1022 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1023 795, 864, 0, 576, 580, 586, 625, 0,
1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1025 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1027 /* 55 - 720(1440)x576i@200Hz 16:9 */
1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1029 795, 864, 0, 576, 580, 586, 625, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1033 /* 56 - 720x480@240Hz 4:3 */
1034 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1035 798, 858, 0, 480, 489, 495, 525, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1038 /* 57 - 720x480@240Hz 16:9 */
1039 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1040 798, 858, 0, 480, 489, 495, 525, 0,
1041 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1043 /* 58 - 720(1440)x480i@240Hz 4:3 */
1044 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1045 801, 858, 0, 480, 488, 494, 525, 0,
1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1047 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1049 /* 59 - 720(1440)x480i@240Hz 16:9 */
1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1051 801, 858, 0, 480, 488, 494, 525, 0,
1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1055 /* 60 - 1280x720@24Hz 16:9 */
1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1057 3080, 3300, 0, 720, 725, 730, 750, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1060 /* 61 - 1280x720@25Hz 16:9 */
1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1062 3740, 3960, 0, 720, 725, 730, 750, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1065 /* 62 - 1280x720@30Hz 16:9 */
1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1067 3080, 3300, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1070 /* 63 - 1920x1080@120Hz 16:9 */
1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1072 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1075 /* 64 - 1920x1080@100Hz 16:9 */
1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1080 /* 65 - 1280x720@24Hz 64:27 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1082 3080, 3300, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 66 - 1280x720@25Hz 64:27 */
1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1087 3740, 3960, 0, 720, 725, 730, 750, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 67 - 1280x720@30Hz 64:27 */
1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1092 3080, 3300, 0, 720, 725, 730, 750, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 68 - 1280x720@50Hz 64:27 */
1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1097 1760, 1980, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 69 - 1280x720@60Hz 64:27 */
1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1102 1430, 1650, 0, 720, 725, 730, 750, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 70 - 1280x720@100Hz 64:27 */
1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1107 1760, 1980, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 71 - 1280x720@120Hz 64:27 */
1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1112 1430, 1650, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 72 - 1920x1080@24Hz 64:27 */
1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1117 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 73 - 1920x1080@25Hz 64:27 */
1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 74 - 1920x1080@30Hz 64:27 */
1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 75 - 1920x1080@50Hz 64:27 */
1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 76 - 1920x1080@60Hz 64:27 */
1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 77 - 1920x1080@100Hz 64:27 */
1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1142 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 78 - 1920x1080@120Hz 64:27 */
1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1147 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 79 - 1680x720@24Hz 64:27 */
1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1152 3080, 3300, 0, 720, 725, 730, 750, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 80 - 1680x720@25Hz 64:27 */
1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1157 2948, 3168, 0, 720, 725, 730, 750, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 81 - 1680x720@30Hz 64:27 */
1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1162 2420, 2640, 0, 720, 725, 730, 750, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 82 - 1680x720@50Hz 64:27 */
1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1167 1980, 2200, 0, 720, 725, 730, 750, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 83 - 1680x720@60Hz 64:27 */
1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1172 1980, 2200, 0, 720, 725, 730, 750, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 84 - 1680x720@100Hz 64:27 */
1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1177 1780, 2000, 0, 720, 725, 730, 825, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 85 - 1680x720@120Hz 64:27 */
1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1182 1780, 2000, 0, 720, 725, 730, 825, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 86 - 2560x1080@24Hz 64:27 */
1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1187 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 87 - 2560x1080@25Hz 64:27 */
1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1192 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 88 - 2560x1080@30Hz 64:27 */
1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1197 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 89 - 2560x1080@50Hz 64:27 */
1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1202 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1205 /* 90 - 2560x1080@60Hz 64:27 */
1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1207 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1210 /* 91 - 2560x1080@100Hz 64:27 */
1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1212 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1215 /* 92 - 2560x1080@120Hz 64:27 */
1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1217 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1220 /* 93 - 3840x2160@24Hz 16:9 */
1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1222 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1225 /* 94 - 3840x2160@25Hz 16:9 */
1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1230 /* 95 - 3840x2160@30Hz 16:9 */
1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1235 /* 96 - 3840x2160@50Hz 16:9 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1237 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1240 /* 97 - 3840x2160@60Hz 16:9 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1242 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1245 /* 98 - 4096x2160@24Hz 256:135 */
1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1247 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1250 /* 99 - 4096x2160@25Hz 256:135 */
1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1255 /* 100 - 4096x2160@30Hz 256:135 */
1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1260 /* 101 - 4096x2160@50Hz 256:135 */
1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1262 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1265 /* 102 - 4096x2160@60Hz 256:135 */
1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1267 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1270 /* 103 - 3840x2160@24Hz 64:27 */
1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1272 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1275 /* 104 - 3840x2160@25Hz 64:27 */
1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1280 /* 105 - 3840x2160@30Hz 64:27 */
1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1285 /* 106 - 3840x2160@50Hz 64:27 */
1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1287 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1290 /* 107 - 3840x2160@60Hz 64:27 */
1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1292 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1295 /* 108 - 1280x720@48Hz 16:9 */
1296 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1297 2280, 2500, 0, 720, 725, 730, 750, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1300 /* 109 - 1280x720@48Hz 64:27 */
1301 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1302 2280, 2500, 0, 720, 725, 730, 750, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1305 /* 110 - 1680x720@48Hz 64:27 */
1306 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1307 2530, 2750, 0, 720, 725, 730, 750, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1310 /* 111 - 1920x1080@48Hz 16:9 */
1311 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1312 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1315 /* 112 - 1920x1080@48Hz 64:27 */
1316 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1317 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1320 /* 113 - 2560x1080@48Hz 64:27 */
1321 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1322 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1325 /* 114 - 3840x2160@48Hz 16:9 */
1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1327 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1330 /* 115 - 4096x2160@48Hz 256:135 */
1331 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1332 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1335 /* 116 - 3840x2160@48Hz 64:27 */
1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1337 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1340 /* 117 - 3840x2160@100Hz 16:9 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1342 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1345 /* 118 - 3840x2160@120Hz 16:9 */
1346 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1347 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1350 /* 119 - 3840x2160@100Hz 64:27 */
1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1352 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1355 /* 120 - 3840x2160@120Hz 64:27 */
1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1357 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1360 /* 121 - 5120x2160@24Hz 64:27 */
1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1362 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1365 /* 122 - 5120x2160@25Hz 64:27 */
1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1367 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1370 /* 123 - 5120x2160@30Hz 64:27 */
1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1372 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1375 /* 124 - 5120x2160@48Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1377 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1380 /* 125 - 5120x2160@50Hz 64:27 */
1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1382 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1385 /* 126 - 5120x2160@60Hz 64:27 */
1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1387 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 /* 127 - 5120x2160@100Hz 64:27 */
1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1392 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1395 };
1396
1397 /*
1398 * From CEA/CTA-861 spec.
1399 *
1400 * Do not access directly, instead always use cea_mode_for_vic().
1401 */
1402 static const struct drm_display_mode edid_cea_modes_193[] = {
1403 /* 193 - 5120x2160@120Hz 64:27 */
1404 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1405 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1408 /* 194 - 7680x4320@24Hz 16:9 */
1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1413 /* 195 - 7680x4320@25Hz 16:9 */
1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1418 /* 196 - 7680x4320@30Hz 16:9 */
1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1423 /* 197 - 7680x4320@48Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1428 /* 198 - 7680x4320@50Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1433 /* 199 - 7680x4320@60Hz 16:9 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1438 /* 200 - 7680x4320@100Hz 16:9 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1440 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1443 /* 201 - 7680x4320@120Hz 16:9 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1445 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1448 /* 202 - 7680x4320@24Hz 64:27 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1453 /* 203 - 7680x4320@25Hz 64:27 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1458 /* 204 - 7680x4320@30Hz 64:27 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1463 /* 205 - 7680x4320@48Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1468 /* 206 - 7680x4320@50Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1473 /* 207 - 7680x4320@60Hz 64:27 */
1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1478 /* 208 - 7680x4320@100Hz 64:27 */
1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1480 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1483 /* 209 - 7680x4320@120Hz 64:27 */
1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1485 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1488 /* 210 - 10240x4320@24Hz 64:27 */
1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1493 /* 211 - 10240x4320@25Hz 64:27 */
1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1498 /* 212 - 10240x4320@30Hz 64:27 */
1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1503 /* 213 - 10240x4320@48Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1508 /* 214 - 10240x4320@50Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1513 /* 215 - 10240x4320@60Hz 64:27 */
1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1518 /* 216 - 10240x4320@100Hz 64:27 */
1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1520 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1523 /* 217 - 10240x4320@120Hz 64:27 */
1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1525 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1528 /* 218 - 4096x2160@100Hz 256:135 */
1529 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1530 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1533 /* 219 - 4096x2160@120Hz 256:135 */
1534 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1535 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1538 };
1539
1540 /*
1541 * HDMI 1.4 4k modes. Index using the VIC.
1542 */
1543 static const struct drm_display_mode edid_4k_modes[] = {
1544 /* 0 - dummy, VICs start at 1 */
1545 { },
1546 /* 1 - 3840x2160@30Hz */
1547 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1548 3840, 4016, 4104, 4400, 0,
1549 2160, 2168, 2178, 2250, 0,
1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1551 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1552 /* 2 - 3840x2160@25Hz */
1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1554 3840, 4896, 4984, 5280, 0,
1555 2160, 2168, 2178, 2250, 0,
1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1558 /* 3 - 3840x2160@24Hz */
1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1560 3840, 5116, 5204, 5500, 0,
1561 2160, 2168, 2178, 2250, 0,
1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1564 /* 4 - 4096x2160@24Hz (SMPTE) */
1565 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1566 4096, 5116, 5204, 5500, 0,
1567 2160, 2168, 2178, 2250, 0,
1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1570 };
1571
1572 /*** DDC fetch and block validation ***/
1573
1574 /*
1575 * The opaque EDID type, internal to drm_edid.c.
1576 */
1577 struct drm_edid {
1578 /* Size allocated for edid */
1579 size_t size;
1580 const struct edid *edid;
1581 };
1582
version_greater(const struct drm_edid * drm_edid,u8 version,u8 revision)1583 static bool version_greater(const struct drm_edid *drm_edid,
1584 u8 version, u8 revision)
1585 {
1586 const struct edid *edid = drm_edid->edid;
1587
1588 return edid->version > version ||
1589 (edid->version == version && edid->revision > revision);
1590 }
1591
1592 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1593
edid_hfeeodb_block_count(const struct edid * edid)1594 static int edid_hfeeodb_block_count(const struct edid *edid)
1595 {
1596 int eeodb = edid_hfeeodb_extension_block_count(edid);
1597
1598 return eeodb ? eeodb + 1 : 0;
1599 }
1600
edid_extension_block_count(const struct edid * edid)1601 static int edid_extension_block_count(const struct edid *edid)
1602 {
1603 return edid->extensions;
1604 }
1605
edid_block_count(const struct edid * edid)1606 static int edid_block_count(const struct edid *edid)
1607 {
1608 return edid_extension_block_count(edid) + 1;
1609 }
1610
edid_size_by_blocks(int num_blocks)1611 static int edid_size_by_blocks(int num_blocks)
1612 {
1613 return num_blocks * EDID_LENGTH;
1614 }
1615
edid_size(const struct edid * edid)1616 static int edid_size(const struct edid *edid)
1617 {
1618 return edid_size_by_blocks(edid_block_count(edid));
1619 }
1620
edid_block_data(const struct edid * edid,int index)1621 static const void *edid_block_data(const struct edid *edid, int index)
1622 {
1623 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1624
1625 return edid + index;
1626 }
1627
edid_extension_block_data(const struct edid * edid,int index)1628 static const void *edid_extension_block_data(const struct edid *edid, int index)
1629 {
1630 return edid_block_data(edid, index + 1);
1631 }
1632
drm_edid_block_count(const struct drm_edid * drm_edid)1633 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1634 {
1635 int num_blocks;
1636
1637 /* Starting point */
1638 num_blocks = edid_block_count(drm_edid->edid);
1639
1640 /* HF-EEODB override */
1641 if (drm_edid->size >= edid_size_by_blocks(2)) {
1642 int eeodb;
1643
1644 /*
1645 * Note: HF-EEODB may specify a smaller extension count than the
1646 * regular one. Unlike in buffer allocation, here we can use it.
1647 */
1648 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1649 if (eeodb)
1650 num_blocks = eeodb;
1651 }
1652
1653 /* Limit by allocated size */
1654 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH);
1655
1656 return num_blocks;
1657 }
1658
drm_edid_extension_block_count(const struct drm_edid * drm_edid)1659 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1660 {
1661 return drm_edid_block_count(drm_edid) - 1;
1662 }
1663
drm_edid_block_data(const struct drm_edid * drm_edid,int index)1664 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1665 {
1666 return edid_block_data(drm_edid->edid, index);
1667 }
1668
drm_edid_extension_block_data(const struct drm_edid * drm_edid,int index)1669 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1670 int index)
1671 {
1672 return edid_extension_block_data(drm_edid->edid, index);
1673 }
1674
1675 /*
1676 * Initializer helper for legacy interfaces, where we have no choice but to
1677 * trust edid size. Not for general purpose use.
1678 */
drm_edid_legacy_init(struct drm_edid * drm_edid,const struct edid * edid)1679 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1680 const struct edid *edid)
1681 {
1682 if (!edid)
1683 return NULL;
1684
1685 memset(drm_edid, 0, sizeof(*drm_edid));
1686
1687 drm_edid->edid = edid;
1688 drm_edid->size = edid_size(edid);
1689
1690 return drm_edid;
1691 }
1692
1693 /*
1694 * EDID base and extension block iterator.
1695 *
1696 * struct drm_edid_iter iter;
1697 * const u8 *block;
1698 *
1699 * drm_edid_iter_begin(drm_edid, &iter);
1700 * drm_edid_iter_for_each(block, &iter) {
1701 * // do stuff with block
1702 * }
1703 * drm_edid_iter_end(&iter);
1704 */
1705 struct drm_edid_iter {
1706 const struct drm_edid *drm_edid;
1707
1708 /* Current block index. */
1709 int index;
1710 };
1711
drm_edid_iter_begin(const struct drm_edid * drm_edid,struct drm_edid_iter * iter)1712 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1713 struct drm_edid_iter *iter)
1714 {
1715 memset(iter, 0, sizeof(*iter));
1716
1717 iter->drm_edid = drm_edid;
1718 }
1719
__drm_edid_iter_next(struct drm_edid_iter * iter)1720 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1721 {
1722 const void *block = NULL;
1723
1724 if (!iter->drm_edid)
1725 return NULL;
1726
1727 if (iter->index < drm_edid_block_count(iter->drm_edid))
1728 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1729
1730 return block;
1731 }
1732
1733 #define drm_edid_iter_for_each(__block, __iter) \
1734 while (((__block) = __drm_edid_iter_next(__iter)))
1735
drm_edid_iter_end(struct drm_edid_iter * iter)1736 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1737 {
1738 memset(iter, 0, sizeof(*iter));
1739 }
1740
1741 static const u8 edid_header[] = {
1742 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1743 };
1744
edid_header_fix(void * edid)1745 static void edid_header_fix(void *edid)
1746 {
1747 memcpy(edid, edid_header, sizeof(edid_header));
1748 }
1749
1750 /**
1751 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1752 * @_edid: pointer to raw base EDID block
1753 *
1754 * Sanity check the header of the base EDID block.
1755 *
1756 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1757 */
drm_edid_header_is_valid(const void * _edid)1758 int drm_edid_header_is_valid(const void *_edid)
1759 {
1760 const struct edid *edid = _edid;
1761 int i, score = 0;
1762
1763 for (i = 0; i < sizeof(edid_header); i++) {
1764 if (edid->header[i] == edid_header[i])
1765 score++;
1766 }
1767
1768 return score;
1769 }
1770 EXPORT_SYMBOL(drm_edid_header_is_valid);
1771
1772 static int edid_fixup __read_mostly = 6;
1773 module_param_named(edid_fixup, edid_fixup, int, 0400);
1774 MODULE_PARM_DESC(edid_fixup,
1775 "Minimum number of valid EDID header bytes (0-8, default 6)");
1776
edid_block_compute_checksum(const void * _block)1777 static int edid_block_compute_checksum(const void *_block)
1778 {
1779 const u8 *block = _block;
1780 int i;
1781 u8 csum = 0, crc = 0;
1782
1783 for (i = 0; i < EDID_LENGTH - 1; i++)
1784 csum += block[i];
1785
1786 crc = 0x100 - csum;
1787
1788 return crc;
1789 }
1790
edid_block_get_checksum(const void * _block)1791 static int edid_block_get_checksum(const void *_block)
1792 {
1793 const struct edid *block = _block;
1794
1795 return block->checksum;
1796 }
1797
edid_block_tag(const void * _block)1798 static int edid_block_tag(const void *_block)
1799 {
1800 const u8 *block = _block;
1801
1802 return block[0];
1803 }
1804
edid_block_is_zero(const void * edid)1805 static bool edid_block_is_zero(const void *edid)
1806 {
1807 return !memchr_inv(edid, 0, EDID_LENGTH);
1808 }
1809
1810 /**
1811 * drm_edid_are_equal - compare two edid blobs.
1812 * @edid1: pointer to first blob
1813 * @edid2: pointer to second blob
1814 * This helper can be used during probing to determine if
1815 * edid had changed.
1816 */
drm_edid_are_equal(const struct edid * edid1,const struct edid * edid2)1817 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1818 {
1819 int edid1_len, edid2_len;
1820 bool edid1_present = edid1 != NULL;
1821 bool edid2_present = edid2 != NULL;
1822
1823 if (edid1_present != edid2_present)
1824 return false;
1825
1826 if (edid1) {
1827 edid1_len = edid_size(edid1);
1828 edid2_len = edid_size(edid2);
1829
1830 if (edid1_len != edid2_len)
1831 return false;
1832
1833 if (memcmp(edid1, edid2, edid1_len))
1834 return false;
1835 }
1836
1837 return true;
1838 }
1839 EXPORT_SYMBOL(drm_edid_are_equal);
1840
1841 enum edid_block_status {
1842 EDID_BLOCK_OK = 0,
1843 EDID_BLOCK_READ_FAIL,
1844 EDID_BLOCK_NULL,
1845 EDID_BLOCK_ZERO,
1846 EDID_BLOCK_HEADER_CORRUPT,
1847 EDID_BLOCK_HEADER_REPAIR,
1848 EDID_BLOCK_HEADER_FIXED,
1849 EDID_BLOCK_CHECKSUM,
1850 EDID_BLOCK_VERSION,
1851 };
1852
edid_block_check(const void * _block,bool is_base_block)1853 static enum edid_block_status edid_block_check(const void *_block,
1854 bool is_base_block)
1855 {
1856 const struct edid *block = _block;
1857
1858 if (!block)
1859 return EDID_BLOCK_NULL;
1860
1861 if (is_base_block) {
1862 int score = drm_edid_header_is_valid(block);
1863
1864 if (score < clamp(edid_fixup, 0, 8)) {
1865 if (edid_block_is_zero(block))
1866 return EDID_BLOCK_ZERO;
1867 else
1868 return EDID_BLOCK_HEADER_CORRUPT;
1869 }
1870
1871 if (score < 8)
1872 return EDID_BLOCK_HEADER_REPAIR;
1873 }
1874
1875 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1876 if (edid_block_is_zero(block))
1877 return EDID_BLOCK_ZERO;
1878 else
1879 return EDID_BLOCK_CHECKSUM;
1880 }
1881
1882 if (is_base_block) {
1883 if (block->version != 1)
1884 return EDID_BLOCK_VERSION;
1885 }
1886
1887 return EDID_BLOCK_OK;
1888 }
1889
edid_block_status_valid(enum edid_block_status status,int tag)1890 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1891 {
1892 return status == EDID_BLOCK_OK ||
1893 status == EDID_BLOCK_HEADER_FIXED ||
1894 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1895 }
1896
edid_block_valid(const void * block,bool base)1897 static bool edid_block_valid(const void *block, bool base)
1898 {
1899 return edid_block_status_valid(edid_block_check(block, base),
1900 edid_block_tag(block));
1901 }
1902
edid_block_status_print(enum edid_block_status status,const struct edid * block,int block_num)1903 static void edid_block_status_print(enum edid_block_status status,
1904 const struct edid *block,
1905 int block_num)
1906 {
1907 switch (status) {
1908 case EDID_BLOCK_OK:
1909 break;
1910 case EDID_BLOCK_READ_FAIL:
1911 pr_debug("EDID block %d read failed\n", block_num);
1912 break;
1913 case EDID_BLOCK_NULL:
1914 pr_debug("EDID block %d pointer is NULL\n", block_num);
1915 break;
1916 case EDID_BLOCK_ZERO:
1917 pr_notice("EDID block %d is all zeroes\n", block_num);
1918 break;
1919 case EDID_BLOCK_HEADER_CORRUPT:
1920 pr_notice("EDID has corrupt header\n");
1921 break;
1922 case EDID_BLOCK_HEADER_REPAIR:
1923 pr_debug("EDID corrupt header needs repair\n");
1924 break;
1925 case EDID_BLOCK_HEADER_FIXED:
1926 pr_debug("EDID corrupt header fixed\n");
1927 break;
1928 case EDID_BLOCK_CHECKSUM:
1929 if (edid_block_status_valid(status, edid_block_tag(block))) {
1930 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1931 block_num, edid_block_tag(block),
1932 edid_block_compute_checksum(block));
1933 } else {
1934 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1935 block_num, edid_block_tag(block),
1936 edid_block_compute_checksum(block));
1937 }
1938 break;
1939 case EDID_BLOCK_VERSION:
1940 pr_notice("EDID has major version %d, instead of 1\n",
1941 block->version);
1942 break;
1943 default:
1944 WARN(1, "EDID block %d unknown edid block status code %d\n",
1945 block_num, status);
1946 break;
1947 }
1948 }
1949
edid_block_dump(const char * level,const void * block,int block_num)1950 static void edid_block_dump(const char *level, const void *block, int block_num)
1951 {
1952 enum edid_block_status status;
1953 char prefix[20];
1954
1955 status = edid_block_check(block, block_num == 0);
1956 if (status == EDID_BLOCK_ZERO)
1957 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1958 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1959 sprintf(prefix, "\t[%02x] BAD ", block_num);
1960 else
1961 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1962
1963 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1964 block, EDID_LENGTH, false);
1965 }
1966
1967 /**
1968 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1969 * @_block: pointer to raw EDID block
1970 * @block_num: type of block to validate (0 for base, extension otherwise)
1971 * @print_bad_edid: if true, dump bad EDID blocks to the console
1972 * @edid_corrupt: if true, the header or checksum is invalid
1973 *
1974 * Validate a base or extension EDID block and optionally dump bad blocks to
1975 * the console.
1976 *
1977 * Return: True if the block is valid, false otherwise.
1978 */
drm_edid_block_valid(u8 * _block,int block_num,bool print_bad_edid,bool * edid_corrupt)1979 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1980 bool *edid_corrupt)
1981 {
1982 struct edid *block = (struct edid *)_block;
1983 enum edid_block_status status;
1984 bool is_base_block = block_num == 0;
1985 bool valid;
1986
1987 if (WARN_ON(!block))
1988 return false;
1989
1990 status = edid_block_check(block, is_base_block);
1991 if (status == EDID_BLOCK_HEADER_REPAIR) {
1992 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1993 edid_header_fix(block);
1994
1995 /* Retry with fixed header, update status if that worked. */
1996 status = edid_block_check(block, is_base_block);
1997 if (status == EDID_BLOCK_OK)
1998 status = EDID_BLOCK_HEADER_FIXED;
1999 }
2000
2001 if (edid_corrupt) {
2002 /*
2003 * Unknown major version isn't corrupt but we can't use it. Only
2004 * the base block can reset edid_corrupt to false.
2005 */
2006 if (is_base_block &&
2007 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2008 *edid_corrupt = false;
2009 else if (status != EDID_BLOCK_OK)
2010 *edid_corrupt = true;
2011 }
2012
2013 edid_block_status_print(status, block, block_num);
2014
2015 /* Determine whether we can use this block with this status. */
2016 valid = edid_block_status_valid(status, edid_block_tag(block));
2017
2018 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2019 pr_notice("Raw EDID:\n");
2020 edid_block_dump(KERN_NOTICE, block, block_num);
2021 }
2022
2023 return valid;
2024 }
2025 EXPORT_SYMBOL(drm_edid_block_valid);
2026
2027 /**
2028 * drm_edid_is_valid - sanity check EDID data
2029 * @edid: EDID data
2030 *
2031 * Sanity-check an entire EDID record (including extensions)
2032 *
2033 * Return: True if the EDID data is valid, false otherwise.
2034 */
drm_edid_is_valid(struct edid * edid)2035 bool drm_edid_is_valid(struct edid *edid)
2036 {
2037 int i;
2038
2039 if (!edid)
2040 return false;
2041
2042 for (i = 0; i < edid_block_count(edid); i++) {
2043 void *block = (void *)edid_block_data(edid, i);
2044
2045 if (!drm_edid_block_valid(block, i, true, NULL))
2046 return false;
2047 }
2048
2049 return true;
2050 }
2051 EXPORT_SYMBOL(drm_edid_is_valid);
2052
edid_filter_invalid_blocks(struct edid * edid,size_t * alloc_size)2053 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2054 size_t *alloc_size)
2055 {
2056 struct edid *new;
2057 int i, valid_blocks = 0;
2058
2059 /*
2060 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2061 * back to regular extension count here. We don't want to start
2062 * modifying the HF-EEODB extension too.
2063 */
2064 for (i = 0; i < edid_block_count(edid); i++) {
2065 const void *src_block = edid_block_data(edid, i);
2066
2067 if (edid_block_valid(src_block, i == 0)) {
2068 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2069
2070 memmove(dst_block, src_block, EDID_LENGTH);
2071 valid_blocks++;
2072 }
2073 }
2074
2075 /* We already trusted the base block to be valid here... */
2076 if (WARN_ON(!valid_blocks)) {
2077 kfree(edid);
2078 return NULL;
2079 }
2080
2081 edid->extensions = valid_blocks - 1;
2082 edid->checksum = edid_block_compute_checksum(edid);
2083
2084 *alloc_size = edid_size_by_blocks(valid_blocks);
2085
2086 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2087 if (!new)
2088 kfree(edid);
2089
2090 return new;
2091 }
2092
2093 #define DDC_SEGMENT_ADDR 0x30
2094 /**
2095 * drm_do_probe_ddc_edid() - get EDID information via I2C
2096 * @data: I2C device adapter
2097 * @buf: EDID data buffer to be filled
2098 * @block: 128 byte EDID block to start fetching from
2099 * @len: EDID data buffer length to fetch
2100 *
2101 * Try to fetch EDID information by calling I2C driver functions.
2102 *
2103 * Return: 0 on success or -1 on failure.
2104 */
2105 static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)2106 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2107 {
2108 struct i2c_adapter *adapter = data;
2109 unsigned char start = block * EDID_LENGTH;
2110 unsigned char segment = block >> 1;
2111 unsigned char xfers = segment ? 3 : 2;
2112 int ret, retries = 5;
2113
2114 /*
2115 * The core I2C driver will automatically retry the transfer if the
2116 * adapter reports EAGAIN. However, we find that bit-banging transfers
2117 * are susceptible to errors under a heavily loaded machine and
2118 * generate spurious NAKs and timeouts. Retrying the transfer
2119 * of the individual block a few times seems to overcome this.
2120 */
2121 do {
2122 struct i2c_msg msgs[] = {
2123 {
2124 .addr = DDC_SEGMENT_ADDR,
2125 .flags = 0,
2126 .len = 1,
2127 .buf = &segment,
2128 }, {
2129 .addr = DDC_ADDR,
2130 .flags = 0,
2131 .len = 1,
2132 .buf = &start,
2133 }, {
2134 .addr = DDC_ADDR,
2135 .flags = I2C_M_RD,
2136 .len = len,
2137 .buf = buf,
2138 }
2139 };
2140
2141 /*
2142 * Avoid sending the segment addr to not upset non-compliant
2143 * DDC monitors.
2144 */
2145 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2146
2147 if (ret == -ENXIO) {
2148 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2149 adapter->name);
2150 break;
2151 }
2152 } while (ret != xfers && --retries);
2153
2154 return ret == xfers ? 0 : -1;
2155 }
2156
connector_bad_edid(struct drm_connector * connector,const struct edid * edid,int num_blocks)2157 static void connector_bad_edid(struct drm_connector *connector,
2158 const struct edid *edid, int num_blocks)
2159 {
2160 int i;
2161 u8 last_block;
2162
2163 /*
2164 * 0x7e in the EDID is the number of extension blocks. The EDID
2165 * is 1 (base block) + num_ext_blocks big. That means we can think
2166 * of 0x7e in the EDID of the _index_ of the last block in the
2167 * combined chunk of memory.
2168 */
2169 last_block = edid->extensions;
2170
2171 /* Calculate real checksum for the last edid extension block data */
2172 if (last_block < num_blocks)
2173 connector->real_edid_checksum =
2174 edid_block_compute_checksum(edid + last_block);
2175
2176 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2177 return;
2178
2179 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
2180 for (i = 0; i < num_blocks; i++)
2181 edid_block_dump(KERN_DEBUG, edid + i, i);
2182 }
2183
2184 /* Get override or firmware EDID */
drm_get_override_edid(struct drm_connector * connector,size_t * alloc_size)2185 static struct edid *drm_get_override_edid(struct drm_connector *connector,
2186 size_t *alloc_size)
2187 {
2188 struct edid *override = NULL;
2189
2190 if (connector->override_edid)
2191 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
2192
2193 if (!override)
2194 override = drm_load_edid_firmware(connector);
2195
2196 /* FIXME: Get alloc size from deeper down the stack */
2197 if (!IS_ERR_OR_NULL(override) && alloc_size)
2198 *alloc_size = edid_size(override);
2199
2200 return IS_ERR(override) ? NULL : override;
2201 }
2202
2203 /* For debugfs edid_override implementation */
drm_edid_override_set(struct drm_connector * connector,const void * edid,size_t size)2204 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2205 size_t size)
2206 {
2207 int ret;
2208
2209 if (size < EDID_LENGTH || edid_size(edid) > size)
2210 return -EINVAL;
2211
2212 connector->override_edid = false;
2213
2214 ret = drm_connector_update_edid_property(connector, edid);
2215 if (!ret)
2216 connector->override_edid = true;
2217
2218 return ret;
2219 }
2220
2221 /* For debugfs edid_override implementation */
drm_edid_override_reset(struct drm_connector * connector)2222 int drm_edid_override_reset(struct drm_connector *connector)
2223 {
2224 connector->override_edid = false;
2225
2226 return drm_connector_update_edid_property(connector, NULL);
2227 }
2228
2229 /**
2230 * drm_add_override_edid_modes - add modes from override/firmware EDID
2231 * @connector: connector we're probing
2232 *
2233 * Add modes from the override/firmware EDID, if available. Only to be used from
2234 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2235 * failed during drm_get_edid() and caused the override/firmware EDID to be
2236 * skipped.
2237 *
2238 * Return: The number of modes added or 0 if we couldn't find any.
2239 */
drm_add_override_edid_modes(struct drm_connector * connector)2240 int drm_add_override_edid_modes(struct drm_connector *connector)
2241 {
2242 struct edid *override;
2243 int num_modes = 0;
2244
2245 override = drm_get_override_edid(connector, NULL);
2246 if (override) {
2247 drm_connector_update_edid_property(connector, override);
2248 num_modes = drm_add_edid_modes(connector, override);
2249 kfree(override);
2250
2251 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2252 connector->base.id, connector->name, num_modes);
2253 }
2254
2255 return num_modes;
2256 }
2257 EXPORT_SYMBOL(drm_add_override_edid_modes);
2258
2259 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2260
edid_block_read(void * block,unsigned int block_num,read_block_fn read_block,void * context)2261 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2262 read_block_fn read_block,
2263 void *context)
2264 {
2265 enum edid_block_status status;
2266 bool is_base_block = block_num == 0;
2267 int try;
2268
2269 for (try = 0; try < 4; try++) {
2270 if (read_block(context, block, block_num, EDID_LENGTH))
2271 return EDID_BLOCK_READ_FAIL;
2272
2273 status = edid_block_check(block, is_base_block);
2274 if (status == EDID_BLOCK_HEADER_REPAIR) {
2275 edid_header_fix(block);
2276
2277 /* Retry with fixed header, update status if that worked. */
2278 status = edid_block_check(block, is_base_block);
2279 if (status == EDID_BLOCK_OK)
2280 status = EDID_BLOCK_HEADER_FIXED;
2281 }
2282
2283 if (edid_block_status_valid(status, edid_block_tag(block)))
2284 break;
2285
2286 /* Fail early for unrepairable base block all zeros. */
2287 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2288 break;
2289 }
2290
2291 return status;
2292 }
2293
_drm_do_get_edid(struct drm_connector * connector,read_block_fn read_block,void * context,size_t * size)2294 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2295 read_block_fn read_block, void *context,
2296 size_t *size)
2297 {
2298 enum edid_block_status status;
2299 int i, num_blocks, invalid_blocks = 0;
2300 struct edid *edid, *new;
2301 size_t alloc_size = EDID_LENGTH;
2302
2303 edid = drm_get_override_edid(connector, &alloc_size);
2304 if (edid)
2305 goto ok;
2306
2307 edid = kmalloc(alloc_size, GFP_KERNEL);
2308 if (!edid)
2309 return NULL;
2310
2311 status = edid_block_read(edid, 0, read_block, context);
2312
2313 edid_block_status_print(status, edid, 0);
2314
2315 if (status == EDID_BLOCK_READ_FAIL)
2316 goto fail;
2317
2318 /* FIXME: Clarify what a corrupt EDID actually means. */
2319 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2320 connector->edid_corrupt = false;
2321 else
2322 connector->edid_corrupt = true;
2323
2324 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2325 if (status == EDID_BLOCK_ZERO)
2326 connector->null_edid_counter++;
2327
2328 connector_bad_edid(connector, edid, 1);
2329 goto fail;
2330 }
2331
2332 if (!edid_extension_block_count(edid))
2333 goto ok;
2334
2335 alloc_size = edid_size(edid);
2336 new = krealloc(edid, alloc_size, GFP_KERNEL);
2337 if (!new)
2338 goto fail;
2339 edid = new;
2340
2341 num_blocks = edid_block_count(edid);
2342 for (i = 1; i < num_blocks; i++) {
2343 void *block = (void *)edid_block_data(edid, i);
2344
2345 status = edid_block_read(block, i, read_block, context);
2346
2347 edid_block_status_print(status, block, i);
2348
2349 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2350 if (status == EDID_BLOCK_READ_FAIL)
2351 goto fail;
2352 invalid_blocks++;
2353 } else if (i == 1) {
2354 /*
2355 * If the first EDID extension is a CTA extension, and
2356 * the first Data Block is HF-EEODB, override the
2357 * extension block count.
2358 *
2359 * Note: HF-EEODB could specify a smaller extension
2360 * count too, but we can't risk allocating a smaller
2361 * amount.
2362 */
2363 int eeodb = edid_hfeeodb_block_count(edid);
2364
2365 if (eeodb > num_blocks) {
2366 num_blocks = eeodb;
2367 alloc_size = edid_size_by_blocks(num_blocks);
2368 new = krealloc(edid, alloc_size, GFP_KERNEL);
2369 if (!new)
2370 goto fail;
2371 edid = new;
2372 }
2373 }
2374 }
2375
2376 if (invalid_blocks) {
2377 connector_bad_edid(connector, edid, num_blocks);
2378
2379 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2380 }
2381
2382 ok:
2383 if (size)
2384 *size = alloc_size;
2385
2386 return edid;
2387
2388 fail:
2389 kfree(edid);
2390 return NULL;
2391 }
2392
2393 /**
2394 * drm_do_get_edid - get EDID data using a custom EDID block read function
2395 * @connector: connector we're probing
2396 * @read_block: EDID block read function
2397 * @context: private data passed to the block read function
2398 *
2399 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2400 * exposes a different interface to read EDID blocks this function can be used
2401 * to get EDID data using a custom block read function.
2402 *
2403 * As in the general case the DDC bus is accessible by the kernel at the I2C
2404 * level, drivers must make all reasonable efforts to expose it as an I2C
2405 * adapter and use drm_get_edid() instead of abusing this function.
2406 *
2407 * The EDID may be overridden using debugfs override_edid or firmware EDID
2408 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2409 * order. Having either of them bypasses actual EDID reads.
2410 *
2411 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2412 */
drm_do_get_edid(struct drm_connector * connector,read_block_fn read_block,void * context)2413 struct edid *drm_do_get_edid(struct drm_connector *connector,
2414 read_block_fn read_block,
2415 void *context)
2416 {
2417 return _drm_do_get_edid(connector, read_block, context, NULL);
2418 }
2419 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2420
2421 /**
2422 * drm_edid_raw - Get a pointer to the raw EDID data.
2423 * @drm_edid: drm_edid container
2424 *
2425 * Get a pointer to the raw EDID data.
2426 *
2427 * This is for transition only. Avoid using this like the plague.
2428 *
2429 * Return: Pointer to raw EDID data.
2430 */
drm_edid_raw(const struct drm_edid * drm_edid)2431 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2432 {
2433 if (!drm_edid || !drm_edid->size)
2434 return NULL;
2435
2436 /*
2437 * Do not return pointers where relying on EDID extension count would
2438 * lead to buffer overflow.
2439 */
2440 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2441 return NULL;
2442
2443 return drm_edid->edid;
2444 }
2445 EXPORT_SYMBOL(drm_edid_raw);
2446
2447 /* Allocate struct drm_edid container *without* duplicating the edid data */
_drm_edid_alloc(const void * edid,size_t size)2448 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2449 {
2450 struct drm_edid *drm_edid;
2451
2452 if (!edid || !size || size < EDID_LENGTH)
2453 return NULL;
2454
2455 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2456 if (drm_edid) {
2457 drm_edid->edid = edid;
2458 drm_edid->size = size;
2459 }
2460
2461 return drm_edid;
2462 }
2463
2464 /**
2465 * drm_edid_alloc - Allocate a new drm_edid container
2466 * @edid: Pointer to raw EDID data
2467 * @size: Size of memory allocated for EDID
2468 *
2469 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2470 * the actual size that has been allocated for the data. There is no validation
2471 * of the raw EDID data against the size, but at least the EDID base block must
2472 * fit in the buffer.
2473 *
2474 * The returned pointer must be freed using drm_edid_free().
2475 *
2476 * Return: drm_edid container, or NULL on errors
2477 */
drm_edid_alloc(const void * edid,size_t size)2478 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2479 {
2480 const struct drm_edid *drm_edid;
2481
2482 if (!edid || !size || size < EDID_LENGTH)
2483 return NULL;
2484
2485 edid = kmemdup(edid, size, GFP_KERNEL);
2486 if (!edid)
2487 return NULL;
2488
2489 drm_edid = _drm_edid_alloc(edid, size);
2490 if (!drm_edid)
2491 kfree(edid);
2492
2493 return drm_edid;
2494 }
2495 EXPORT_SYMBOL(drm_edid_alloc);
2496
2497 /**
2498 * drm_edid_dup - Duplicate a drm_edid container
2499 * @drm_edid: EDID to duplicate
2500 *
2501 * The returned pointer must be freed using drm_edid_free().
2502 *
2503 * Returns: drm_edid container copy, or NULL on errors
2504 */
drm_edid_dup(const struct drm_edid * drm_edid)2505 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2506 {
2507 if (!drm_edid)
2508 return NULL;
2509
2510 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2511 }
2512 EXPORT_SYMBOL(drm_edid_dup);
2513
2514 /**
2515 * drm_edid_free - Free the drm_edid container
2516 * @drm_edid: EDID to free
2517 */
drm_edid_free(const struct drm_edid * drm_edid)2518 void drm_edid_free(const struct drm_edid *drm_edid)
2519 {
2520 if (!drm_edid)
2521 return;
2522
2523 kfree(drm_edid->edid);
2524 kfree(drm_edid);
2525 }
2526 EXPORT_SYMBOL(drm_edid_free);
2527
2528 /**
2529 * drm_probe_ddc() - probe DDC presence
2530 * @adapter: I2C adapter to probe
2531 *
2532 * Return: True on success, false on failure.
2533 */
2534 bool
drm_probe_ddc(struct i2c_adapter * adapter)2535 drm_probe_ddc(struct i2c_adapter *adapter)
2536 {
2537 unsigned char out;
2538
2539 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2540 }
2541 EXPORT_SYMBOL(drm_probe_ddc);
2542
2543 /**
2544 * drm_get_edid - get EDID data, if available
2545 * @connector: connector we're probing
2546 * @adapter: I2C adapter to use for DDC
2547 *
2548 * Poke the given I2C channel to grab EDID data if possible. If found,
2549 * attach it to the connector.
2550 *
2551 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2552 */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2553 struct edid *drm_get_edid(struct drm_connector *connector,
2554 struct i2c_adapter *adapter)
2555 {
2556 struct edid *edid;
2557
2558 if (connector->force == DRM_FORCE_OFF)
2559 return NULL;
2560
2561 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2562 return NULL;
2563
2564 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2565 drm_connector_update_edid_property(connector, edid);
2566 return edid;
2567 }
2568 EXPORT_SYMBOL(drm_get_edid);
2569
2570 /**
2571 * drm_edid_read_custom - Read EDID data using given EDID block read function
2572 * @connector: Connector to use
2573 * @read_block: EDID block read function
2574 * @context: Private data passed to the block read function
2575 *
2576 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2577 * exposes a different interface to read EDID blocks this function can be used
2578 * to get EDID data using a custom block read function.
2579 *
2580 * As in the general case the DDC bus is accessible by the kernel at the I2C
2581 * level, drivers must make all reasonable efforts to expose it as an I2C
2582 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2583 * this function.
2584 *
2585 * The EDID may be overridden using debugfs override_edid or firmware EDID
2586 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2587 * order. Having either of them bypasses actual EDID reads.
2588 *
2589 * The returned pointer must be freed using drm_edid_free().
2590 *
2591 * Return: Pointer to EDID, or NULL if probe/read failed.
2592 */
drm_edid_read_custom(struct drm_connector * connector,read_block_fn read_block,void * context)2593 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2594 read_block_fn read_block,
2595 void *context)
2596 {
2597 const struct drm_edid *drm_edid;
2598 struct edid *edid;
2599 size_t size = 0;
2600
2601 edid = _drm_do_get_edid(connector, read_block, context, &size);
2602 if (!edid)
2603 return NULL;
2604
2605 /* Sanity check for now */
2606 drm_WARN_ON(connector->dev, !size);
2607
2608 drm_edid = _drm_edid_alloc(edid, size);
2609 if (!drm_edid)
2610 kfree(edid);
2611
2612 return drm_edid;
2613 }
2614 EXPORT_SYMBOL(drm_edid_read_custom);
2615
2616 /**
2617 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2618 * @connector: Connector to use
2619 * @adapter: I2C adapter to use for DDC
2620 *
2621 * Read EDID using the given I2C adapter.
2622 *
2623 * The EDID may be overridden using debugfs override_edid or firmware EDID
2624 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2625 * order. Having either of them bypasses actual EDID reads.
2626 *
2627 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2628 * using drm_edid_read() instead of this function.
2629 *
2630 * The returned pointer must be freed using drm_edid_free().
2631 *
2632 * Return: Pointer to EDID, or NULL if probe/read failed.
2633 */
drm_edid_read_ddc(struct drm_connector * connector,struct i2c_adapter * adapter)2634 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2635 struct i2c_adapter *adapter)
2636 {
2637 const struct drm_edid *drm_edid;
2638
2639 if (connector->force == DRM_FORCE_OFF)
2640 return NULL;
2641
2642 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2643 return NULL;
2644
2645 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2646
2647 /* Note: Do *not* call connector updates here. */
2648
2649 return drm_edid;
2650 }
2651 EXPORT_SYMBOL(drm_edid_read_ddc);
2652
2653 /**
2654 * drm_edid_read - Read EDID data using connector's I2C adapter
2655 * @connector: Connector to use
2656 *
2657 * Read EDID using the connector's I2C adapter.
2658 *
2659 * The EDID may be overridden using debugfs override_edid or firmware EDID
2660 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2661 * order. Having either of them bypasses actual EDID reads.
2662 *
2663 * The returned pointer must be freed using drm_edid_free().
2664 *
2665 * Return: Pointer to EDID, or NULL if probe/read failed.
2666 */
drm_edid_read(struct drm_connector * connector)2667 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2668 {
2669 if (drm_WARN_ON(connector->dev, !connector->ddc))
2670 return NULL;
2671
2672 return drm_edid_read_ddc(connector, connector->ddc);
2673 }
2674 EXPORT_SYMBOL(drm_edid_read);
2675
edid_extract_panel_id(const struct edid * edid)2676 static u32 edid_extract_panel_id(const struct edid *edid)
2677 {
2678 /*
2679 * We represent the ID as a 32-bit number so it can easily be compared
2680 * with "==".
2681 *
2682 * NOTE that we deal with endianness differently for the top half
2683 * of this ID than for the bottom half. The bottom half (the product
2684 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2685 * that's how everyone seems to interpret it. The top half (the mfg_id)
2686 * gets stored as big endian because that makes
2687 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2688 * to write (it's easier to extract the ASCII). It doesn't really
2689 * matter, though, as long as the number here is unique.
2690 */
2691 return (u32)edid->mfg_id[0] << 24 |
2692 (u32)edid->mfg_id[1] << 16 |
2693 (u32)EDID_PRODUCT_ID(edid);
2694 }
2695
2696 /**
2697 * drm_edid_get_panel_id - Get a panel's ID through DDC
2698 * @adapter: I2C adapter to use for DDC
2699 *
2700 * This function reads the first block of the EDID of a panel and (assuming
2701 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2702 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2703 * supposed to be different for each different modem of panel.
2704 *
2705 * This function is intended to be used during early probing on devices where
2706 * more than one panel might be present. Because of its intended use it must
2707 * assume that the EDID of the panel is correct, at least as far as the ID
2708 * is concerned (in other words, we don't process any overrides here).
2709 *
2710 * NOTE: it's expected that this function and drm_do_get_edid() will both
2711 * be read the EDID, but there is no caching between them. Since we're only
2712 * reading the first block, hopefully this extra overhead won't be too big.
2713 *
2714 * Return: A 32-bit ID that should be different for each make/model of panel.
2715 * See the functions drm_edid_encode_panel_id() and
2716 * drm_edid_decode_panel_id() for some details on the structure of this
2717 * ID.
2718 */
2719
drm_edid_get_panel_id(struct i2c_adapter * adapter)2720 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2721 {
2722 enum edid_block_status status;
2723 void *base_block;
2724 u32 panel_id = 0;
2725
2726 /*
2727 * There are no manufacturer IDs of 0, so if there is a problem reading
2728 * the EDID then we'll just return 0.
2729 */
2730
2731 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2732 if (!base_block)
2733 return 0;
2734
2735 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2736
2737 edid_block_status_print(status, base_block, 0);
2738
2739 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2740 panel_id = edid_extract_panel_id(base_block);
2741
2742 kfree(base_block);
2743
2744 return panel_id;
2745 }
2746 EXPORT_SYMBOL(drm_edid_get_panel_id);
2747
2748 /**
2749 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2750 * @connector: connector we're probing
2751 * @adapter: I2C adapter to use for DDC
2752 *
2753 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2754 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2755 * switch DDC to the GPU which is retrieving EDID.
2756 *
2757 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2758 */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2759 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2760 struct i2c_adapter *adapter)
2761 {
2762 struct drm_device *dev = connector->dev;
2763 struct pci_dev *pdev = to_pci_dev(dev->dev);
2764 struct edid *edid;
2765
2766 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2767 return NULL;
2768
2769 vga_switcheroo_lock_ddc(pdev);
2770 edid = drm_get_edid(connector, adapter);
2771 vga_switcheroo_unlock_ddc(pdev);
2772
2773 return edid;
2774 }
2775 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2776
2777 /**
2778 * drm_edid_duplicate - duplicate an EDID and the extensions
2779 * @edid: EDID to duplicate
2780 *
2781 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2782 */
drm_edid_duplicate(const struct edid * edid)2783 struct edid *drm_edid_duplicate(const struct edid *edid)
2784 {
2785 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2786 }
2787 EXPORT_SYMBOL(drm_edid_duplicate);
2788
2789 /*** EDID parsing ***/
2790
2791 /**
2792 * edid_get_quirks - return quirk flags for a given EDID
2793 * @drm_edid: EDID to process
2794 *
2795 * This tells subsequent routines what fixes they need to apply.
2796 */
edid_get_quirks(const struct drm_edid * drm_edid)2797 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2798 {
2799 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2800 const struct edid_quirk *quirk;
2801 int i;
2802
2803 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2804 quirk = &edid_quirk_list[i];
2805 if (quirk->panel_id == panel_id)
2806 return quirk->quirks;
2807 }
2808
2809 return 0;
2810 }
2811
2812 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2813 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2814
2815 /*
2816 * Walk the mode list for connector, clearing the preferred status on existing
2817 * modes and setting it anew for the right mode ala quirks.
2818 */
edid_fixup_preferred(struct drm_connector * connector,u32 quirks)2819 static void edid_fixup_preferred(struct drm_connector *connector,
2820 u32 quirks)
2821 {
2822 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2823 int target_refresh = 0;
2824 int cur_vrefresh, preferred_vrefresh;
2825
2826 if (list_empty(&connector->probed_modes))
2827 return;
2828
2829 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2830 target_refresh = 60;
2831 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2832 target_refresh = 75;
2833
2834 preferred_mode = list_first_entry(&connector->probed_modes,
2835 struct drm_display_mode, head);
2836
2837 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2838 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2839
2840 if (cur_mode == preferred_mode)
2841 continue;
2842
2843 /* Largest mode is preferred */
2844 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2845 preferred_mode = cur_mode;
2846
2847 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2848 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2849 /* At a given size, try to get closest to target refresh */
2850 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2851 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2852 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2853 preferred_mode = cur_mode;
2854 }
2855 }
2856
2857 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2858 }
2859
2860 static bool
mode_is_rb(const struct drm_display_mode * mode)2861 mode_is_rb(const struct drm_display_mode *mode)
2862 {
2863 return (mode->htotal - mode->hdisplay == 160) &&
2864 (mode->hsync_end - mode->hdisplay == 80) &&
2865 (mode->hsync_end - mode->hsync_start == 32) &&
2866 (mode->vsync_start - mode->vdisplay == 3);
2867 }
2868
2869 /*
2870 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2871 * @dev: Device to duplicate against
2872 * @hsize: Mode width
2873 * @vsize: Mode height
2874 * @fresh: Mode refresh rate
2875 * @rb: Mode reduced-blanking-ness
2876 *
2877 * Walk the DMT mode list looking for a match for the given parameters.
2878 *
2879 * Return: A newly allocated copy of the mode, or NULL if not found.
2880 */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)2881 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2882 int hsize, int vsize, int fresh,
2883 bool rb)
2884 {
2885 int i;
2886
2887 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2888 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2889
2890 if (hsize != ptr->hdisplay)
2891 continue;
2892 if (vsize != ptr->vdisplay)
2893 continue;
2894 if (fresh != drm_mode_vrefresh(ptr))
2895 continue;
2896 if (rb != mode_is_rb(ptr))
2897 continue;
2898
2899 return drm_mode_duplicate(dev, ptr);
2900 }
2901
2902 return NULL;
2903 }
2904 EXPORT_SYMBOL(drm_mode_find_dmt);
2905
is_display_descriptor(const struct detailed_timing * descriptor,u8 type)2906 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2907 {
2908 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2909 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2910 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2911
2912 return descriptor->pixel_clock == 0 &&
2913 descriptor->data.other_data.pad1 == 0 &&
2914 descriptor->data.other_data.type == type;
2915 }
2916
is_detailed_timing_descriptor(const struct detailed_timing * descriptor)2917 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2918 {
2919 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2920
2921 return descriptor->pixel_clock != 0;
2922 }
2923
2924 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2925
2926 static void
cea_for_each_detailed_block(const u8 * ext,detailed_cb * cb,void * closure)2927 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2928 {
2929 int i, n;
2930 u8 d = ext[0x02];
2931 const u8 *det_base = ext + d;
2932
2933 if (d < 4 || d > 127)
2934 return;
2935
2936 n = (127 - d) / 18;
2937 for (i = 0; i < n; i++)
2938 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2939 }
2940
2941 static void
vtb_for_each_detailed_block(const u8 * ext,detailed_cb * cb,void * closure)2942 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2943 {
2944 unsigned int i, n = min((int)ext[0x02], 6);
2945 const u8 *det_base = ext + 5;
2946
2947 if (ext[0x01] != 1)
2948 return; /* unknown version */
2949
2950 for (i = 0; i < n; i++)
2951 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2952 }
2953
drm_for_each_detailed_block(const struct drm_edid * drm_edid,detailed_cb * cb,void * closure)2954 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
2955 detailed_cb *cb, void *closure)
2956 {
2957 struct drm_edid_iter edid_iter;
2958 const u8 *ext;
2959 int i;
2960
2961 if (!drm_edid)
2962 return;
2963
2964 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2965 cb(&drm_edid->edid->detailed_timings[i], closure);
2966
2967 drm_edid_iter_begin(drm_edid, &edid_iter);
2968 drm_edid_iter_for_each(ext, &edid_iter) {
2969 switch (*ext) {
2970 case CEA_EXT:
2971 cea_for_each_detailed_block(ext, cb, closure);
2972 break;
2973 case VTB_EXT:
2974 vtb_for_each_detailed_block(ext, cb, closure);
2975 break;
2976 default:
2977 break;
2978 }
2979 }
2980 drm_edid_iter_end(&edid_iter);
2981 }
2982
2983 static void
is_rb(const struct detailed_timing * descriptor,void * data)2984 is_rb(const struct detailed_timing *descriptor, void *data)
2985 {
2986 bool *res = data;
2987
2988 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2989 return;
2990
2991 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2992 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2993
2994 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2995 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2996 *res = true;
2997 }
2998
2999 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3000 static bool
drm_monitor_supports_rb(const struct drm_edid * drm_edid)3001 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3002 {
3003 if (drm_edid->edid->revision >= 4) {
3004 bool ret = false;
3005
3006 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3007 return ret;
3008 }
3009
3010 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
3011 }
3012
3013 static void
find_gtf2(const struct detailed_timing * descriptor,void * data)3014 find_gtf2(const struct detailed_timing *descriptor, void *data)
3015 {
3016 const struct detailed_timing **res = data;
3017
3018 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3019 return;
3020
3021 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3022
3023 if (descriptor->data.other_data.data.range.flags == 0x02)
3024 *res = descriptor;
3025 }
3026
3027 /* Secondary GTF curve kicks in above some break frequency */
3028 static int
drm_gtf2_hbreak(const struct drm_edid * drm_edid)3029 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3030 {
3031 const struct detailed_timing *descriptor = NULL;
3032
3033 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3034
3035 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3036
3037 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3038 }
3039
3040 static int
drm_gtf2_2c(const struct drm_edid * drm_edid)3041 drm_gtf2_2c(const struct drm_edid *drm_edid)
3042 {
3043 const struct detailed_timing *descriptor = NULL;
3044
3045 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3046
3047 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3048
3049 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3050 }
3051
3052 static int
drm_gtf2_m(const struct drm_edid * drm_edid)3053 drm_gtf2_m(const struct drm_edid *drm_edid)
3054 {
3055 const struct detailed_timing *descriptor = NULL;
3056
3057 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3058
3059 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3060
3061 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3062 }
3063
3064 static int
drm_gtf2_k(const struct drm_edid * drm_edid)3065 drm_gtf2_k(const struct drm_edid *drm_edid)
3066 {
3067 const struct detailed_timing *descriptor = NULL;
3068
3069 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3070
3071 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3072
3073 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3074 }
3075
3076 static int
drm_gtf2_2j(const struct drm_edid * drm_edid)3077 drm_gtf2_2j(const struct drm_edid *drm_edid)
3078 {
3079 const struct detailed_timing *descriptor = NULL;
3080
3081 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3082
3083 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3084
3085 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3086 }
3087
3088 /* Get standard timing level (CVT/GTF/DMT). */
standard_timing_level(const struct drm_edid * drm_edid)3089 static int standard_timing_level(const struct drm_edid *drm_edid)
3090 {
3091 const struct edid *edid = drm_edid->edid;
3092
3093 if (edid->revision >= 2) {
3094 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
3095 return LEVEL_CVT;
3096 if (drm_gtf2_hbreak(drm_edid))
3097 return LEVEL_GTF2;
3098 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3099 return LEVEL_GTF;
3100 }
3101 return LEVEL_DMT;
3102 }
3103
3104 /*
3105 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3106 * monitors fill with ascii space (0x20) instead.
3107 */
3108 static int
bad_std_timing(u8 a,u8 b)3109 bad_std_timing(u8 a, u8 b)
3110 {
3111 return (a == 0x00 && b == 0x00) ||
3112 (a == 0x01 && b == 0x01) ||
3113 (a == 0x20 && b == 0x20);
3114 }
3115
drm_mode_hsync(const struct drm_display_mode * mode)3116 static int drm_mode_hsync(const struct drm_display_mode *mode)
3117 {
3118 if (mode->htotal <= 0)
3119 return 0;
3120
3121 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3122 }
3123
3124 /*
3125 * Take the standard timing params (in this case width, aspect, and refresh)
3126 * and convert them into a real mode using CVT/GTF/DMT.
3127 */
drm_mode_std(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct std_timing * t)3128 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3129 const struct drm_edid *drm_edid,
3130 const struct std_timing *t)
3131 {
3132 struct drm_device *dev = connector->dev;
3133 struct drm_display_mode *m, *mode = NULL;
3134 int hsize, vsize;
3135 int vrefresh_rate;
3136 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3137 >> EDID_TIMING_ASPECT_SHIFT;
3138 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3139 >> EDID_TIMING_VFREQ_SHIFT;
3140 int timing_level = standard_timing_level(drm_edid);
3141
3142 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3143 return NULL;
3144
3145 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3146 hsize = t->hsize * 8 + 248;
3147 /* vrefresh_rate = vfreq + 60 */
3148 vrefresh_rate = vfreq + 60;
3149 /* the vdisplay is calculated based on the aspect ratio */
3150 if (aspect_ratio == 0) {
3151 if (drm_edid->edid->revision < 3)
3152 vsize = hsize;
3153 else
3154 vsize = (hsize * 10) / 16;
3155 } else if (aspect_ratio == 1)
3156 vsize = (hsize * 3) / 4;
3157 else if (aspect_ratio == 2)
3158 vsize = (hsize * 4) / 5;
3159 else
3160 vsize = (hsize * 9) / 16;
3161
3162 /* HDTV hack, part 1 */
3163 if (vrefresh_rate == 60 &&
3164 ((hsize == 1360 && vsize == 765) ||
3165 (hsize == 1368 && vsize == 769))) {
3166 hsize = 1366;
3167 vsize = 768;
3168 }
3169
3170 /*
3171 * If this connector already has a mode for this size and refresh
3172 * rate (because it came from detailed or CVT info), use that
3173 * instead. This way we don't have to guess at interlace or
3174 * reduced blanking.
3175 */
3176 list_for_each_entry(m, &connector->probed_modes, head)
3177 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3178 drm_mode_vrefresh(m) == vrefresh_rate)
3179 return NULL;
3180
3181 /* HDTV hack, part 2 */
3182 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3183 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3184 false);
3185 if (!mode)
3186 return NULL;
3187 mode->hdisplay = 1366;
3188 mode->hsync_start = mode->hsync_start - 1;
3189 mode->hsync_end = mode->hsync_end - 1;
3190 return mode;
3191 }
3192
3193 /* check whether it can be found in default mode table */
3194 if (drm_monitor_supports_rb(drm_edid)) {
3195 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3196 true);
3197 if (mode)
3198 return mode;
3199 }
3200 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3201 if (mode)
3202 return mode;
3203
3204 /* okay, generate it */
3205 switch (timing_level) {
3206 case LEVEL_DMT:
3207 break;
3208 case LEVEL_GTF:
3209 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3210 break;
3211 case LEVEL_GTF2:
3212 /*
3213 * This is potentially wrong if there's ever a monitor with
3214 * more than one ranges section, each claiming a different
3215 * secondary GTF curve. Please don't do that.
3216 */
3217 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3218 if (!mode)
3219 return NULL;
3220 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3221 drm_mode_destroy(dev, mode);
3222 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3223 vrefresh_rate, 0, 0,
3224 drm_gtf2_m(drm_edid),
3225 drm_gtf2_2c(drm_edid),
3226 drm_gtf2_k(drm_edid),
3227 drm_gtf2_2j(drm_edid));
3228 }
3229 break;
3230 case LEVEL_CVT:
3231 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3232 false);
3233 break;
3234 }
3235 return mode;
3236 }
3237
3238 /*
3239 * EDID is delightfully ambiguous about how interlaced modes are to be
3240 * encoded. Our internal representation is of frame height, but some
3241 * HDTV detailed timings are encoded as field height.
3242 *
3243 * The format list here is from CEA, in frame size. Technically we
3244 * should be checking refresh rate too. Whatever.
3245 */
3246 static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,const struct detailed_pixel_timing * pt)3247 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3248 const struct detailed_pixel_timing *pt)
3249 {
3250 int i;
3251 static const struct {
3252 int w, h;
3253 } cea_interlaced[] = {
3254 { 1920, 1080 },
3255 { 720, 480 },
3256 { 1440, 480 },
3257 { 2880, 480 },
3258 { 720, 576 },
3259 { 1440, 576 },
3260 { 2880, 576 },
3261 };
3262
3263 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3264 return;
3265
3266 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3267 if ((mode->hdisplay == cea_interlaced[i].w) &&
3268 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3269 mode->vdisplay *= 2;
3270 mode->vsync_start *= 2;
3271 mode->vsync_end *= 2;
3272 mode->vtotal *= 2;
3273 mode->vtotal |= 1;
3274 }
3275 }
3276
3277 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3278 }
3279
3280 /*
3281 * Create a new mode from an EDID detailed timing section. An EDID detailed
3282 * timing block contains enough info for us to create and return a new struct
3283 * drm_display_mode.
3284 */
drm_mode_detailed(struct drm_device * dev,const struct drm_edid * drm_edid,const struct detailed_timing * timing,u32 quirks)3285 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
3286 const struct drm_edid *drm_edid,
3287 const struct detailed_timing *timing,
3288 u32 quirks)
3289 {
3290 struct drm_display_mode *mode;
3291 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3292 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3293 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3294 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3295 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3296 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3297 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3298 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3299 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3300
3301 /* ignore tiny modes */
3302 if (hactive < 64 || vactive < 64)
3303 return NULL;
3304
3305 if (pt->misc & DRM_EDID_PT_STEREO) {
3306 DRM_DEBUG_KMS("stereo mode not supported\n");
3307 return NULL;
3308 }
3309 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3310 DRM_DEBUG_KMS("composite sync not supported\n");
3311 }
3312
3313 /* it is incorrect if hsync/vsync width is zero */
3314 if (!hsync_pulse_width || !vsync_pulse_width) {
3315 DRM_DEBUG_KMS("Incorrect Detailed timing. "
3316 "Wrong Hsync/Vsync pulse width\n");
3317 return NULL;
3318 }
3319
3320 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3321 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3322 if (!mode)
3323 return NULL;
3324
3325 goto set_size;
3326 }
3327
3328 mode = drm_mode_create(dev);
3329 if (!mode)
3330 return NULL;
3331
3332 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3333 mode->clock = 1088 * 10;
3334 else
3335 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3336
3337 mode->hdisplay = hactive;
3338 mode->hsync_start = mode->hdisplay + hsync_offset;
3339 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3340 mode->htotal = mode->hdisplay + hblank;
3341
3342 mode->vdisplay = vactive;
3343 mode->vsync_start = mode->vdisplay + vsync_offset;
3344 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3345 mode->vtotal = mode->vdisplay + vblank;
3346
3347 /* Some EDIDs have bogus h/vtotal values */
3348 if (mode->hsync_end > mode->htotal)
3349 mode->htotal = mode->hsync_end + 1;
3350 if (mode->vsync_end > mode->vtotal)
3351 mode->vtotal = mode->vsync_end + 1;
3352
3353 drm_mode_do_interlace_quirk(mode, pt);
3354
3355 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3356 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3357 } else {
3358 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3359 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3360 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3361 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3362 }
3363
3364 set_size:
3365 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3366 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3367
3368 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3369 mode->width_mm *= 10;
3370 mode->height_mm *= 10;
3371 }
3372
3373 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3374 mode->width_mm = drm_edid->edid->width_cm * 10;
3375 mode->height_mm = drm_edid->edid->height_cm * 10;
3376 }
3377
3378 mode->type = DRM_MODE_TYPE_DRIVER;
3379 drm_mode_set_name(mode);
3380
3381 return mode;
3382 }
3383
3384 static bool
mode_in_hsync_range(const struct drm_display_mode * mode,const struct edid * edid,const u8 * t)3385 mode_in_hsync_range(const struct drm_display_mode *mode,
3386 const struct edid *edid, const u8 *t)
3387 {
3388 int hsync, hmin, hmax;
3389
3390 hmin = t[7];
3391 if (edid->revision >= 4)
3392 hmin += ((t[4] & 0x04) ? 255 : 0);
3393 hmax = t[8];
3394 if (edid->revision >= 4)
3395 hmax += ((t[4] & 0x08) ? 255 : 0);
3396 hsync = drm_mode_hsync(mode);
3397
3398 return (hsync <= hmax && hsync >= hmin);
3399 }
3400
3401 static bool
mode_in_vsync_range(const struct drm_display_mode * mode,const struct edid * edid,const u8 * t)3402 mode_in_vsync_range(const struct drm_display_mode *mode,
3403 const struct edid *edid, const u8 *t)
3404 {
3405 int vsync, vmin, vmax;
3406
3407 vmin = t[5];
3408 if (edid->revision >= 4)
3409 vmin += ((t[4] & 0x01) ? 255 : 0);
3410 vmax = t[6];
3411 if (edid->revision >= 4)
3412 vmax += ((t[4] & 0x02) ? 255 : 0);
3413 vsync = drm_mode_vrefresh(mode);
3414
3415 return (vsync <= vmax && vsync >= vmin);
3416 }
3417
3418 static u32
range_pixel_clock(const struct edid * edid,const u8 * t)3419 range_pixel_clock(const struct edid *edid, const u8 *t)
3420 {
3421 /* unspecified */
3422 if (t[9] == 0 || t[9] == 255)
3423 return 0;
3424
3425 /* 1.4 with CVT support gives us real precision, yay */
3426 if (edid->revision >= 4 && t[10] == 0x04)
3427 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3428
3429 /* 1.3 is pathetic, so fuzz up a bit */
3430 return t[9] * 10000 + 5001;
3431 }
3432
mode_in_range(const struct drm_display_mode * mode,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3433 static bool mode_in_range(const struct drm_display_mode *mode,
3434 const struct drm_edid *drm_edid,
3435 const struct detailed_timing *timing)
3436 {
3437 const struct edid *edid = drm_edid->edid;
3438 u32 max_clock;
3439 const u8 *t = (const u8 *)timing;
3440
3441 if (!mode_in_hsync_range(mode, edid, t))
3442 return false;
3443
3444 if (!mode_in_vsync_range(mode, edid, t))
3445 return false;
3446
3447 if ((max_clock = range_pixel_clock(edid, t)))
3448 if (mode->clock > max_clock)
3449 return false;
3450
3451 /* 1.4 max horizontal check */
3452 if (edid->revision >= 4 && t[10] == 0x04)
3453 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3454 return false;
3455
3456 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3457 return false;
3458
3459 return true;
3460 }
3461
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)3462 static bool valid_inferred_mode(const struct drm_connector *connector,
3463 const struct drm_display_mode *mode)
3464 {
3465 const struct drm_display_mode *m;
3466 bool ok = false;
3467
3468 list_for_each_entry(m, &connector->probed_modes, head) {
3469 if (mode->hdisplay == m->hdisplay &&
3470 mode->vdisplay == m->vdisplay &&
3471 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3472 return false; /* duplicated */
3473 if (mode->hdisplay <= m->hdisplay &&
3474 mode->vdisplay <= m->vdisplay)
3475 ok = true;
3476 }
3477 return ok;
3478 }
3479
drm_dmt_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3480 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3481 const struct drm_edid *drm_edid,
3482 const struct detailed_timing *timing)
3483 {
3484 int i, modes = 0;
3485 struct drm_display_mode *newmode;
3486 struct drm_device *dev = connector->dev;
3487
3488 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3489 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3490 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3491 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3492 if (newmode) {
3493 drm_mode_probed_add(connector, newmode);
3494 modes++;
3495 }
3496 }
3497 }
3498
3499 return modes;
3500 }
3501
3502 /* fix up 1366x768 mode from 1368x768;
3503 * GFT/CVT can't express 1366 width which isn't dividable by 8
3504 */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)3505 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3506 {
3507 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3508 mode->hdisplay = 1366;
3509 mode->hsync_start--;
3510 mode->hsync_end--;
3511 drm_mode_set_name(mode);
3512 }
3513 }
3514
drm_gtf_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3515 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3516 const struct drm_edid *drm_edid,
3517 const struct detailed_timing *timing)
3518 {
3519 int i, modes = 0;
3520 struct drm_display_mode *newmode;
3521 struct drm_device *dev = connector->dev;
3522
3523 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3524 const struct minimode *m = &extra_modes[i];
3525
3526 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3527 if (!newmode)
3528 return modes;
3529
3530 drm_mode_fixup_1366x768(newmode);
3531 if (!mode_in_range(newmode, drm_edid, timing) ||
3532 !valid_inferred_mode(connector, newmode)) {
3533 drm_mode_destroy(dev, newmode);
3534 continue;
3535 }
3536
3537 drm_mode_probed_add(connector, newmode);
3538 modes++;
3539 }
3540
3541 return modes;
3542 }
3543
drm_cvt_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3544 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3545 const struct drm_edid *drm_edid,
3546 const struct detailed_timing *timing)
3547 {
3548 int i, modes = 0;
3549 struct drm_display_mode *newmode;
3550 struct drm_device *dev = connector->dev;
3551 bool rb = drm_monitor_supports_rb(drm_edid);
3552
3553 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3554 const struct minimode *m = &extra_modes[i];
3555
3556 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3557 if (!newmode)
3558 return modes;
3559
3560 drm_mode_fixup_1366x768(newmode);
3561 if (!mode_in_range(newmode, drm_edid, timing) ||
3562 !valid_inferred_mode(connector, newmode)) {
3563 drm_mode_destroy(dev, newmode);
3564 continue;
3565 }
3566
3567 drm_mode_probed_add(connector, newmode);
3568 modes++;
3569 }
3570
3571 return modes;
3572 }
3573
3574 static void
do_inferred_modes(const struct detailed_timing * timing,void * c)3575 do_inferred_modes(const struct detailed_timing *timing, void *c)
3576 {
3577 struct detailed_mode_closure *closure = c;
3578 const struct detailed_non_pixel *data = &timing->data.other_data;
3579 const struct detailed_data_monitor_range *range = &data->data.range;
3580
3581 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3582 return;
3583
3584 closure->modes += drm_dmt_modes_for_range(closure->connector,
3585 closure->drm_edid,
3586 timing);
3587
3588 if (!version_greater(closure->drm_edid, 1, 1))
3589 return; /* GTF not defined yet */
3590
3591 switch (range->flags) {
3592 case 0x02: /* secondary gtf, XXX could do more */
3593 case 0x00: /* default gtf */
3594 closure->modes += drm_gtf_modes_for_range(closure->connector,
3595 closure->drm_edid,
3596 timing);
3597 break;
3598 case 0x04: /* cvt, only in 1.4+ */
3599 if (!version_greater(closure->drm_edid, 1, 3))
3600 break;
3601
3602 closure->modes += drm_cvt_modes_for_range(closure->connector,
3603 closure->drm_edid,
3604 timing);
3605 break;
3606 case 0x01: /* just the ranges, no formula */
3607 default:
3608 break;
3609 }
3610 }
3611
add_inferred_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3612 static int add_inferred_modes(struct drm_connector *connector,
3613 const struct drm_edid *drm_edid)
3614 {
3615 struct detailed_mode_closure closure = {
3616 .connector = connector,
3617 .drm_edid = drm_edid,
3618 };
3619
3620 if (version_greater(drm_edid, 1, 0))
3621 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3622
3623 return closure.modes;
3624 }
3625
3626 static int
drm_est3_modes(struct drm_connector * connector,const struct detailed_timing * timing)3627 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3628 {
3629 int i, j, m, modes = 0;
3630 struct drm_display_mode *mode;
3631 const u8 *est = ((const u8 *)timing) + 6;
3632
3633 for (i = 0; i < 6; i++) {
3634 for (j = 7; j >= 0; j--) {
3635 m = (i * 8) + (7 - j);
3636 if (m >= ARRAY_SIZE(est3_modes))
3637 break;
3638 if (est[i] & (1 << j)) {
3639 mode = drm_mode_find_dmt(connector->dev,
3640 est3_modes[m].w,
3641 est3_modes[m].h,
3642 est3_modes[m].r,
3643 est3_modes[m].rb);
3644 if (mode) {
3645 drm_mode_probed_add(connector, mode);
3646 modes++;
3647 }
3648 }
3649 }
3650 }
3651
3652 return modes;
3653 }
3654
3655 static void
do_established_modes(const struct detailed_timing * timing,void * c)3656 do_established_modes(const struct detailed_timing *timing, void *c)
3657 {
3658 struct detailed_mode_closure *closure = c;
3659
3660 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3661 return;
3662
3663 closure->modes += drm_est3_modes(closure->connector, timing);
3664 }
3665
3666 /*
3667 * Get established modes from EDID and add them. Each EDID block contains a
3668 * bitmap of the supported "established modes" list (defined above). Tease them
3669 * out and add them to the global modes list.
3670 */
add_established_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3671 static int add_established_modes(struct drm_connector *connector,
3672 const struct drm_edid *drm_edid)
3673 {
3674 struct drm_device *dev = connector->dev;
3675 const struct edid *edid = drm_edid->edid;
3676 unsigned long est_bits = edid->established_timings.t1 |
3677 (edid->established_timings.t2 << 8) |
3678 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3679 int i, modes = 0;
3680 struct detailed_mode_closure closure = {
3681 .connector = connector,
3682 .drm_edid = drm_edid,
3683 };
3684
3685 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3686 if (est_bits & (1<<i)) {
3687 struct drm_display_mode *newmode;
3688
3689 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3690 if (newmode) {
3691 drm_mode_probed_add(connector, newmode);
3692 modes++;
3693 }
3694 }
3695 }
3696
3697 if (version_greater(drm_edid, 1, 0))
3698 drm_for_each_detailed_block(drm_edid, do_established_modes,
3699 &closure);
3700
3701 return modes + closure.modes;
3702 }
3703
3704 static void
do_standard_modes(const struct detailed_timing * timing,void * c)3705 do_standard_modes(const struct detailed_timing *timing, void *c)
3706 {
3707 struct detailed_mode_closure *closure = c;
3708 const struct detailed_non_pixel *data = &timing->data.other_data;
3709 struct drm_connector *connector = closure->connector;
3710 int i;
3711
3712 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3713 return;
3714
3715 for (i = 0; i < 6; i++) {
3716 const struct std_timing *std = &data->data.timings[i];
3717 struct drm_display_mode *newmode;
3718
3719 newmode = drm_mode_std(connector, closure->drm_edid, std);
3720 if (newmode) {
3721 drm_mode_probed_add(connector, newmode);
3722 closure->modes++;
3723 }
3724 }
3725 }
3726
3727 /*
3728 * Get standard modes from EDID and add them. Standard modes can be calculated
3729 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3730 * add them to the list.
3731 */
add_standard_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3732 static int add_standard_modes(struct drm_connector *connector,
3733 const struct drm_edid *drm_edid)
3734 {
3735 int i, modes = 0;
3736 struct detailed_mode_closure closure = {
3737 .connector = connector,
3738 .drm_edid = drm_edid,
3739 };
3740
3741 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3742 struct drm_display_mode *newmode;
3743
3744 newmode = drm_mode_std(connector, drm_edid,
3745 &drm_edid->edid->standard_timings[i]);
3746 if (newmode) {
3747 drm_mode_probed_add(connector, newmode);
3748 modes++;
3749 }
3750 }
3751
3752 if (version_greater(drm_edid, 1, 0))
3753 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3754 &closure);
3755
3756 /* XXX should also look for standard codes in VTB blocks */
3757
3758 return modes + closure.modes;
3759 }
3760
drm_cvt_modes(struct drm_connector * connector,const struct detailed_timing * timing)3761 static int drm_cvt_modes(struct drm_connector *connector,
3762 const struct detailed_timing *timing)
3763 {
3764 int i, j, modes = 0;
3765 struct drm_display_mode *newmode;
3766 struct drm_device *dev = connector->dev;
3767 const struct cvt_timing *cvt;
3768 const int rates[] = { 60, 85, 75, 60, 50 };
3769 const u8 empty[3] = { 0, 0, 0 };
3770
3771 for (i = 0; i < 4; i++) {
3772 int width, height;
3773
3774 cvt = &(timing->data.other_data.data.cvt[i]);
3775
3776 if (!memcmp(cvt->code, empty, 3))
3777 continue;
3778
3779 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3780 switch (cvt->code[1] & 0x0c) {
3781 /* default - because compiler doesn't see that we've enumerated all cases */
3782 default:
3783 case 0x00:
3784 width = height * 4 / 3;
3785 break;
3786 case 0x04:
3787 width = height * 16 / 9;
3788 break;
3789 case 0x08:
3790 width = height * 16 / 10;
3791 break;
3792 case 0x0c:
3793 width = height * 15 / 9;
3794 break;
3795 }
3796
3797 for (j = 1; j < 5; j++) {
3798 if (cvt->code[2] & (1 << j)) {
3799 newmode = drm_cvt_mode(dev, width, height,
3800 rates[j], j == 0,
3801 false, false);
3802 if (newmode) {
3803 drm_mode_probed_add(connector, newmode);
3804 modes++;
3805 }
3806 }
3807 }
3808 }
3809
3810 return modes;
3811 }
3812
3813 static void
do_cvt_mode(const struct detailed_timing * timing,void * c)3814 do_cvt_mode(const struct detailed_timing *timing, void *c)
3815 {
3816 struct detailed_mode_closure *closure = c;
3817
3818 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3819 return;
3820
3821 closure->modes += drm_cvt_modes(closure->connector, timing);
3822 }
3823
3824 static int
add_cvt_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3825 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
3826 {
3827 struct detailed_mode_closure closure = {
3828 .connector = connector,
3829 .drm_edid = drm_edid,
3830 };
3831
3832 if (version_greater(drm_edid, 1, 2))
3833 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
3834
3835 /* XXX should also look for CVT codes in VTB blocks */
3836
3837 return closure.modes;
3838 }
3839
3840 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3841
3842 static void
do_detailed_mode(const struct detailed_timing * timing,void * c)3843 do_detailed_mode(const struct detailed_timing *timing, void *c)
3844 {
3845 struct detailed_mode_closure *closure = c;
3846 struct drm_display_mode *newmode;
3847
3848 if (!is_detailed_timing_descriptor(timing))
3849 return;
3850
3851 newmode = drm_mode_detailed(closure->connector->dev,
3852 closure->drm_edid, timing,
3853 closure->quirks);
3854 if (!newmode)
3855 return;
3856
3857 if (closure->preferred)
3858 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3859
3860 /*
3861 * Detailed modes are limited to 10kHz pixel clock resolution,
3862 * so fix up anything that looks like CEA/HDMI mode, but the clock
3863 * is just slightly off.
3864 */
3865 fixup_detailed_cea_mode_clock(newmode);
3866
3867 drm_mode_probed_add(closure->connector, newmode);
3868 closure->modes++;
3869 closure->preferred = false;
3870 }
3871
3872 /*
3873 * add_detailed_modes - Add modes from detailed timings
3874 * @connector: attached connector
3875 * @drm_edid: EDID block to scan
3876 * @quirks: quirks to apply
3877 */
add_detailed_modes(struct drm_connector * connector,const struct drm_edid * drm_edid,u32 quirks)3878 static int add_detailed_modes(struct drm_connector *connector,
3879 const struct drm_edid *drm_edid, u32 quirks)
3880 {
3881 struct detailed_mode_closure closure = {
3882 .connector = connector,
3883 .drm_edid = drm_edid,
3884 .preferred = true,
3885 .quirks = quirks,
3886 };
3887
3888 if (closure.preferred && !version_greater(drm_edid, 1, 3))
3889 closure.preferred =
3890 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3891
3892 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
3893
3894 return closure.modes;
3895 }
3896
3897 /* CTA-861-H Table 60 - CTA Tag Codes */
3898 #define CTA_DB_AUDIO 1
3899 #define CTA_DB_VIDEO 2
3900 #define CTA_DB_VENDOR 3
3901 #define CTA_DB_SPEAKER 4
3902 #define CTA_DB_EXTENDED_TAG 7
3903
3904 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
3905 #define CTA_EXT_DB_VIDEO_CAP 0
3906 #define CTA_EXT_DB_VENDOR 1
3907 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
3908 #define CTA_EXT_DB_420_VIDEO_DATA 14
3909 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
3910 #define CTA_EXT_DB_HF_EEODB 0x78
3911 #define CTA_EXT_DB_HF_SCDB 0x79
3912
3913 #define EDID_BASIC_AUDIO (1 << 6)
3914 #define EDID_CEA_YCRCB444 (1 << 5)
3915 #define EDID_CEA_YCRCB422 (1 << 4)
3916 #define EDID_CEA_VCDB_QS (1 << 6)
3917
3918 /*
3919 * Search EDID for CEA extension block.
3920 *
3921 * FIXME: Prefer not returning pointers to raw EDID data.
3922 */
drm_find_edid_extension(const struct drm_edid * drm_edid,int ext_id,int * ext_index)3923 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
3924 int ext_id, int *ext_index)
3925 {
3926 const u8 *edid_ext = NULL;
3927 int i;
3928
3929 /* No EDID or EDID extensions */
3930 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
3931 return NULL;
3932
3933 /* Find CEA extension */
3934 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
3935 edid_ext = drm_edid_extension_block_data(drm_edid, i);
3936 if (edid_block_tag(edid_ext) == ext_id)
3937 break;
3938 }
3939
3940 if (i >= drm_edid_extension_block_count(drm_edid))
3941 return NULL;
3942
3943 *ext_index = i + 1;
3944
3945 return edid_ext;
3946 }
3947
3948 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
drm_edid_has_cta_extension(const struct drm_edid * drm_edid)3949 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
3950 {
3951 const struct displayid_block *block;
3952 struct displayid_iter iter;
3953 int ext_index = 0;
3954 bool found = false;
3955
3956 /* Look for a top level CEA extension block */
3957 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
3958 return true;
3959
3960 /* CEA blocks can also be found embedded in a DisplayID block */
3961 displayid_iter_edid_begin(drm_edid, &iter);
3962 displayid_iter_for_each(block, &iter) {
3963 if (block->tag == DATA_BLOCK_CTA) {
3964 found = true;
3965 break;
3966 }
3967 }
3968 displayid_iter_end(&iter);
3969
3970 return found;
3971 }
3972
cea_mode_for_vic(u8 vic)3973 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3974 {
3975 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3976 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3977
3978 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3979 return &edid_cea_modes_1[vic - 1];
3980 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3981 return &edid_cea_modes_193[vic - 193];
3982 return NULL;
3983 }
3984
cea_num_vics(void)3985 static u8 cea_num_vics(void)
3986 {
3987 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3988 }
3989
cea_next_vic(u8 vic)3990 static u8 cea_next_vic(u8 vic)
3991 {
3992 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3993 vic = 193;
3994 return vic;
3995 }
3996
3997 /*
3998 * Calculate the alternate clock for the CEA mode
3999 * (60Hz vs. 59.94Hz etc.)
4000 */
4001 static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)4002 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4003 {
4004 unsigned int clock = cea_mode->clock;
4005
4006 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4007 return clock;
4008
4009 /*
4010 * edid_cea_modes contains the 59.94Hz
4011 * variant for 240 and 480 line modes,
4012 * and the 60Hz variant otherwise.
4013 */
4014 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4015 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4016 else
4017 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4018
4019 return clock;
4020 }
4021
4022 static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)4023 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4024 {
4025 /*
4026 * For certain VICs the spec allows the vertical
4027 * front porch to vary by one or two lines.
4028 *
4029 * cea_modes[] stores the variant with the shortest
4030 * vertical front porch. We can adjust the mode to
4031 * get the other variants by simply increasing the
4032 * vertical front porch length.
4033 */
4034 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4035 cea_mode_for_vic(9)->vtotal != 262 ||
4036 cea_mode_for_vic(12)->vtotal != 262 ||
4037 cea_mode_for_vic(13)->vtotal != 262 ||
4038 cea_mode_for_vic(23)->vtotal != 312 ||
4039 cea_mode_for_vic(24)->vtotal != 312 ||
4040 cea_mode_for_vic(27)->vtotal != 312 ||
4041 cea_mode_for_vic(28)->vtotal != 312);
4042
4043 if (((vic == 8 || vic == 9 ||
4044 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4045 ((vic == 23 || vic == 24 ||
4046 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4047 mode->vsync_start++;
4048 mode->vsync_end++;
4049 mode->vtotal++;
4050
4051 return true;
4052 }
4053
4054 return false;
4055 }
4056
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)4057 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4058 unsigned int clock_tolerance)
4059 {
4060 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4061 u8 vic;
4062
4063 if (!to_match->clock)
4064 return 0;
4065
4066 if (to_match->picture_aspect_ratio)
4067 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4068
4069 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4070 struct drm_display_mode cea_mode;
4071 unsigned int clock1, clock2;
4072
4073 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4074
4075 /* Check both 60Hz and 59.94Hz */
4076 clock1 = cea_mode.clock;
4077 clock2 = cea_mode_alternate_clock(&cea_mode);
4078
4079 if (abs(to_match->clock - clock1) > clock_tolerance &&
4080 abs(to_match->clock - clock2) > clock_tolerance)
4081 continue;
4082
4083 do {
4084 if (drm_mode_match(to_match, &cea_mode, match_flags))
4085 return vic;
4086 } while (cea_mode_alternate_timings(vic, &cea_mode));
4087 }
4088
4089 return 0;
4090 }
4091
4092 /**
4093 * drm_match_cea_mode - look for a CEA mode matching given mode
4094 * @to_match: display mode
4095 *
4096 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4097 * mode.
4098 */
drm_match_cea_mode(const struct drm_display_mode * to_match)4099 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4100 {
4101 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4102 u8 vic;
4103
4104 if (!to_match->clock)
4105 return 0;
4106
4107 if (to_match->picture_aspect_ratio)
4108 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4109
4110 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4111 struct drm_display_mode cea_mode;
4112 unsigned int clock1, clock2;
4113
4114 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4115
4116 /* Check both 60Hz and 59.94Hz */
4117 clock1 = cea_mode.clock;
4118 clock2 = cea_mode_alternate_clock(&cea_mode);
4119
4120 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4121 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4122 continue;
4123
4124 do {
4125 if (drm_mode_match(to_match, &cea_mode, match_flags))
4126 return vic;
4127 } while (cea_mode_alternate_timings(vic, &cea_mode));
4128 }
4129
4130 return 0;
4131 }
4132 EXPORT_SYMBOL(drm_match_cea_mode);
4133
drm_valid_cea_vic(u8 vic)4134 static bool drm_valid_cea_vic(u8 vic)
4135 {
4136 return cea_mode_for_vic(vic) != NULL;
4137 }
4138
drm_get_cea_aspect_ratio(const u8 video_code)4139 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4140 {
4141 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4142
4143 if (mode)
4144 return mode->picture_aspect_ratio;
4145
4146 return HDMI_PICTURE_ASPECT_NONE;
4147 }
4148
drm_get_hdmi_aspect_ratio(const u8 video_code)4149 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4150 {
4151 return edid_4k_modes[video_code].picture_aspect_ratio;
4152 }
4153
4154 /*
4155 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4156 * specific block).
4157 */
4158 static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)4159 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4160 {
4161 return cea_mode_alternate_clock(hdmi_mode);
4162 }
4163
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)4164 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4165 unsigned int clock_tolerance)
4166 {
4167 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4168 u8 vic;
4169
4170 if (!to_match->clock)
4171 return 0;
4172
4173 if (to_match->picture_aspect_ratio)
4174 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4175
4176 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4177 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4178 unsigned int clock1, clock2;
4179
4180 /* Make sure to also match alternate clocks */
4181 clock1 = hdmi_mode->clock;
4182 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4183
4184 if (abs(to_match->clock - clock1) > clock_tolerance &&
4185 abs(to_match->clock - clock2) > clock_tolerance)
4186 continue;
4187
4188 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4189 return vic;
4190 }
4191
4192 return 0;
4193 }
4194
4195 /*
4196 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4197 * @to_match: display mode
4198 *
4199 * An HDMI mode is one defined in the HDMI vendor specific block.
4200 *
4201 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4202 */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)4203 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4204 {
4205 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4206 u8 vic;
4207
4208 if (!to_match->clock)
4209 return 0;
4210
4211 if (to_match->picture_aspect_ratio)
4212 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4213
4214 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4215 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4216 unsigned int clock1, clock2;
4217
4218 /* Make sure to also match alternate clocks */
4219 clock1 = hdmi_mode->clock;
4220 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4221
4222 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4223 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4224 drm_mode_match(to_match, hdmi_mode, match_flags))
4225 return vic;
4226 }
4227 return 0;
4228 }
4229
drm_valid_hdmi_vic(u8 vic)4230 static bool drm_valid_hdmi_vic(u8 vic)
4231 {
4232 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4233 }
4234
add_alternate_cea_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4235 static int add_alternate_cea_modes(struct drm_connector *connector,
4236 const struct drm_edid *drm_edid)
4237 {
4238 struct drm_device *dev = connector->dev;
4239 struct drm_display_mode *mode, *tmp;
4240 LIST_HEAD(list);
4241 int modes = 0;
4242
4243 /* Don't add CTA modes if the CTA extension block is missing */
4244 if (!drm_edid_has_cta_extension(drm_edid))
4245 return 0;
4246
4247 /*
4248 * Go through all probed modes and create a new mode
4249 * with the alternate clock for certain CEA modes.
4250 */
4251 list_for_each_entry(mode, &connector->probed_modes, head) {
4252 const struct drm_display_mode *cea_mode = NULL;
4253 struct drm_display_mode *newmode;
4254 u8 vic = drm_match_cea_mode(mode);
4255 unsigned int clock1, clock2;
4256
4257 if (drm_valid_cea_vic(vic)) {
4258 cea_mode = cea_mode_for_vic(vic);
4259 clock2 = cea_mode_alternate_clock(cea_mode);
4260 } else {
4261 vic = drm_match_hdmi_mode(mode);
4262 if (drm_valid_hdmi_vic(vic)) {
4263 cea_mode = &edid_4k_modes[vic];
4264 clock2 = hdmi_mode_alternate_clock(cea_mode);
4265 }
4266 }
4267
4268 if (!cea_mode)
4269 continue;
4270
4271 clock1 = cea_mode->clock;
4272
4273 if (clock1 == clock2)
4274 continue;
4275
4276 if (mode->clock != clock1 && mode->clock != clock2)
4277 continue;
4278
4279 newmode = drm_mode_duplicate(dev, cea_mode);
4280 if (!newmode)
4281 continue;
4282
4283 /* Carry over the stereo flags */
4284 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4285
4286 /*
4287 * The current mode could be either variant. Make
4288 * sure to pick the "other" clock for the new mode.
4289 */
4290 if (mode->clock != clock1)
4291 newmode->clock = clock1;
4292 else
4293 newmode->clock = clock2;
4294
4295 list_add_tail(&newmode->head, &list);
4296 }
4297
4298 list_for_each_entry_safe(mode, tmp, &list, head) {
4299 list_del(&mode->head);
4300 drm_mode_probed_add(connector, mode);
4301 modes++;
4302 }
4303
4304 return modes;
4305 }
4306
svd_to_vic(u8 svd)4307 static u8 svd_to_vic(u8 svd)
4308 {
4309 /* 0-6 bit vic, 7th bit native mode indicator */
4310 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4311 return svd & 127;
4312
4313 return svd;
4314 }
4315
4316 static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,const u8 * video_db,u8 video_len,u8 video_index)4317 drm_display_mode_from_vic_index(struct drm_connector *connector,
4318 const u8 *video_db, u8 video_len,
4319 u8 video_index)
4320 {
4321 struct drm_device *dev = connector->dev;
4322 struct drm_display_mode *newmode;
4323 u8 vic;
4324
4325 if (video_db == NULL || video_index >= video_len)
4326 return NULL;
4327
4328 /* CEA modes are numbered 1..127 */
4329 vic = svd_to_vic(video_db[video_index]);
4330 if (!drm_valid_cea_vic(vic))
4331 return NULL;
4332
4333 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4334 if (!newmode)
4335 return NULL;
4336
4337 return newmode;
4338 }
4339
4340 /*
4341 * do_y420vdb_modes - Parse YCBCR 420 only modes
4342 * @connector: connector corresponding to the HDMI sink
4343 * @svds: start of the data block of CEA YCBCR 420 VDB
4344 * @len: length of the CEA YCBCR 420 VDB
4345 *
4346 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4347 * which contains modes which can be supported in YCBCR 420
4348 * output format only.
4349 */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)4350 static int do_y420vdb_modes(struct drm_connector *connector,
4351 const u8 *svds, u8 svds_len)
4352 {
4353 int modes = 0, i;
4354 struct drm_device *dev = connector->dev;
4355 struct drm_display_info *info = &connector->display_info;
4356 struct drm_hdmi_info *hdmi = &info->hdmi;
4357
4358 for (i = 0; i < svds_len; i++) {
4359 u8 vic = svd_to_vic(svds[i]);
4360 struct drm_display_mode *newmode;
4361
4362 if (!drm_valid_cea_vic(vic))
4363 continue;
4364
4365 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4366 if (!newmode)
4367 break;
4368 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4369 drm_mode_probed_add(connector, newmode);
4370 modes++;
4371 }
4372
4373 if (modes > 0)
4374 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4375 return modes;
4376 }
4377
4378 /*
4379 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4380 * @connector: connector corresponding to the HDMI sink
4381 * @vic: CEA vic for the video mode to be added in the map
4382 *
4383 * Makes an entry for a videomode in the YCBCR 420 bitmap
4384 */
4385 static void
drm_add_cmdb_modes(struct drm_connector * connector,u8 svd)4386 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4387 {
4388 u8 vic = svd_to_vic(svd);
4389 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4390
4391 if (!drm_valid_cea_vic(vic))
4392 return;
4393
4394 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4395 }
4396
4397 /**
4398 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4399 * @dev: DRM device
4400 * @video_code: CEA VIC of the mode
4401 *
4402 * Creates a new mode matching the specified CEA VIC.
4403 *
4404 * Returns: A new drm_display_mode on success or NULL on failure
4405 */
4406 struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device * dev,u8 video_code)4407 drm_display_mode_from_cea_vic(struct drm_device *dev,
4408 u8 video_code)
4409 {
4410 const struct drm_display_mode *cea_mode;
4411 struct drm_display_mode *newmode;
4412
4413 cea_mode = cea_mode_for_vic(video_code);
4414 if (!cea_mode)
4415 return NULL;
4416
4417 newmode = drm_mode_duplicate(dev, cea_mode);
4418 if (!newmode)
4419 return NULL;
4420
4421 return newmode;
4422 }
4423 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4424
4425 static int
do_cea_modes(struct drm_connector * connector,const u8 * db,u8 len)4426 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4427 {
4428 int i, modes = 0;
4429 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4430
4431 for (i = 0; i < len; i++) {
4432 struct drm_display_mode *mode;
4433
4434 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4435 if (mode) {
4436 /*
4437 * YCBCR420 capability block contains a bitmap which
4438 * gives the index of CEA modes from CEA VDB, which
4439 * can support YCBCR 420 sampling output also (apart
4440 * from RGB/YCBCR444 etc).
4441 * For example, if the bit 0 in bitmap is set,
4442 * first mode in VDB can support YCBCR420 output too.
4443 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4444 */
4445 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4446 drm_add_cmdb_modes(connector, db[i]);
4447
4448 drm_mode_probed_add(connector, mode);
4449 modes++;
4450 }
4451 }
4452
4453 return modes;
4454 }
4455
4456 struct stereo_mandatory_mode {
4457 int width, height, vrefresh;
4458 unsigned int flags;
4459 };
4460
4461 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4462 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4463 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4464 { 1920, 1080, 50,
4465 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4466 { 1920, 1080, 60,
4467 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4468 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4469 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4470 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4471 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4472 };
4473
4474 static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)4475 stereo_match_mandatory(const struct drm_display_mode *mode,
4476 const struct stereo_mandatory_mode *stereo_mode)
4477 {
4478 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4479
4480 return mode->hdisplay == stereo_mode->width &&
4481 mode->vdisplay == stereo_mode->height &&
4482 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4483 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4484 }
4485
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)4486 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4487 {
4488 struct drm_device *dev = connector->dev;
4489 const struct drm_display_mode *mode;
4490 struct list_head stereo_modes;
4491 int modes = 0, i;
4492
4493 INIT_LIST_HEAD(&stereo_modes);
4494
4495 list_for_each_entry(mode, &connector->probed_modes, head) {
4496 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4497 const struct stereo_mandatory_mode *mandatory;
4498 struct drm_display_mode *new_mode;
4499
4500 if (!stereo_match_mandatory(mode,
4501 &stereo_mandatory_modes[i]))
4502 continue;
4503
4504 mandatory = &stereo_mandatory_modes[i];
4505 new_mode = drm_mode_duplicate(dev, mode);
4506 if (!new_mode)
4507 continue;
4508
4509 new_mode->flags |= mandatory->flags;
4510 list_add_tail(&new_mode->head, &stereo_modes);
4511 modes++;
4512 }
4513 }
4514
4515 list_splice_tail(&stereo_modes, &connector->probed_modes);
4516
4517 return modes;
4518 }
4519
add_hdmi_mode(struct drm_connector * connector,u8 vic)4520 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4521 {
4522 struct drm_device *dev = connector->dev;
4523 struct drm_display_mode *newmode;
4524
4525 if (!drm_valid_hdmi_vic(vic)) {
4526 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4527 return 0;
4528 }
4529
4530 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4531 if (!newmode)
4532 return 0;
4533
4534 drm_mode_probed_add(connector, newmode);
4535
4536 return 1;
4537 }
4538
add_3d_struct_modes(struct drm_connector * connector,u16 structure,const u8 * video_db,u8 video_len,u8 video_index)4539 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4540 const u8 *video_db, u8 video_len, u8 video_index)
4541 {
4542 struct drm_display_mode *newmode;
4543 int modes = 0;
4544
4545 if (structure & (1 << 0)) {
4546 newmode = drm_display_mode_from_vic_index(connector, video_db,
4547 video_len,
4548 video_index);
4549 if (newmode) {
4550 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4551 drm_mode_probed_add(connector, newmode);
4552 modes++;
4553 }
4554 }
4555 if (structure & (1 << 6)) {
4556 newmode = drm_display_mode_from_vic_index(connector, video_db,
4557 video_len,
4558 video_index);
4559 if (newmode) {
4560 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4561 drm_mode_probed_add(connector, newmode);
4562 modes++;
4563 }
4564 }
4565 if (structure & (1 << 8)) {
4566 newmode = drm_display_mode_from_vic_index(connector, video_db,
4567 video_len,
4568 video_index);
4569 if (newmode) {
4570 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4571 drm_mode_probed_add(connector, newmode);
4572 modes++;
4573 }
4574 }
4575
4576 return modes;
4577 }
4578
4579 /*
4580 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4581 * @connector: connector corresponding to the HDMI sink
4582 * @db: start of the CEA vendor specific block
4583 * @len: length of the CEA block payload, ie. one can access up to db[len]
4584 *
4585 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4586 * also adds the stereo 3d modes when applicable.
4587 */
4588 static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len,const u8 * video_db,u8 video_len)4589 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4590 const u8 *video_db, u8 video_len)
4591 {
4592 struct drm_display_info *info = &connector->display_info;
4593 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4594 u8 vic_len, hdmi_3d_len = 0;
4595 u16 mask;
4596 u16 structure_all;
4597
4598 if (len < 8)
4599 goto out;
4600
4601 /* no HDMI_Video_Present */
4602 if (!(db[8] & (1 << 5)))
4603 goto out;
4604
4605 /* Latency_Fields_Present */
4606 if (db[8] & (1 << 7))
4607 offset += 2;
4608
4609 /* I_Latency_Fields_Present */
4610 if (db[8] & (1 << 6))
4611 offset += 2;
4612
4613 /* the declared length is not long enough for the 2 first bytes
4614 * of additional video format capabilities */
4615 if (len < (8 + offset + 2))
4616 goto out;
4617
4618 /* 3D_Present */
4619 offset++;
4620 if (db[8 + offset] & (1 << 7)) {
4621 modes += add_hdmi_mandatory_stereo_modes(connector);
4622
4623 /* 3D_Multi_present */
4624 multi_present = (db[8 + offset] & 0x60) >> 5;
4625 }
4626
4627 offset++;
4628 vic_len = db[8 + offset] >> 5;
4629 hdmi_3d_len = db[8 + offset] & 0x1f;
4630
4631 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4632 u8 vic;
4633
4634 vic = db[9 + offset + i];
4635 modes += add_hdmi_mode(connector, vic);
4636 }
4637 offset += 1 + vic_len;
4638
4639 if (multi_present == 1)
4640 multi_len = 2;
4641 else if (multi_present == 2)
4642 multi_len = 4;
4643 else
4644 multi_len = 0;
4645
4646 if (len < (8 + offset + hdmi_3d_len - 1))
4647 goto out;
4648
4649 if (hdmi_3d_len < multi_len)
4650 goto out;
4651
4652 if (multi_present == 1 || multi_present == 2) {
4653 /* 3D_Structure_ALL */
4654 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4655
4656 /* check if 3D_MASK is present */
4657 if (multi_present == 2)
4658 mask = (db[10 + offset] << 8) | db[11 + offset];
4659 else
4660 mask = 0xffff;
4661
4662 for (i = 0; i < 16; i++) {
4663 if (mask & (1 << i))
4664 modes += add_3d_struct_modes(connector,
4665 structure_all,
4666 video_db,
4667 video_len, i);
4668 }
4669 }
4670
4671 offset += multi_len;
4672
4673 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4674 int vic_index;
4675 struct drm_display_mode *newmode = NULL;
4676 unsigned int newflag = 0;
4677 bool detail_present;
4678
4679 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4680
4681 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4682 break;
4683
4684 /* 2D_VIC_order_X */
4685 vic_index = db[8 + offset + i] >> 4;
4686
4687 /* 3D_Structure_X */
4688 switch (db[8 + offset + i] & 0x0f) {
4689 case 0:
4690 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4691 break;
4692 case 6:
4693 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4694 break;
4695 case 8:
4696 /* 3D_Detail_X */
4697 if ((db[9 + offset + i] >> 4) == 1)
4698 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4699 break;
4700 }
4701
4702 if (newflag != 0) {
4703 newmode = drm_display_mode_from_vic_index(connector,
4704 video_db,
4705 video_len,
4706 vic_index);
4707
4708 if (newmode) {
4709 newmode->flags |= newflag;
4710 drm_mode_probed_add(connector, newmode);
4711 modes++;
4712 }
4713 }
4714
4715 if (detail_present)
4716 i++;
4717 }
4718
4719 out:
4720 if (modes > 0)
4721 info->has_hdmi_infoframe = true;
4722 return modes;
4723 }
4724
4725 static int
cea_revision(const u8 * cea)4726 cea_revision(const u8 *cea)
4727 {
4728 /*
4729 * FIXME is this correct for the DispID variant?
4730 * The DispID spec doesn't really specify whether
4731 * this is the revision of the CEA extension or
4732 * the DispID CEA data block. And the only value
4733 * given as an example is 0.
4734 */
4735 return cea[1];
4736 }
4737
4738 /*
4739 * CTA Data Block iterator.
4740 *
4741 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4742 * CTA Data Blocks.
4743 *
4744 * struct cea_db *db:
4745 * struct cea_db_iter iter;
4746 *
4747 * cea_db_iter_edid_begin(edid, &iter);
4748 * cea_db_iter_for_each(db, &iter) {
4749 * // do stuff with db
4750 * }
4751 * cea_db_iter_end(&iter);
4752 */
4753 struct cea_db_iter {
4754 struct drm_edid_iter edid_iter;
4755 struct displayid_iter displayid_iter;
4756
4757 /* Current Data Block Collection. */
4758 const u8 *collection;
4759
4760 /* Current Data Block index in current collection. */
4761 int index;
4762
4763 /* End index in current collection. */
4764 int end;
4765 };
4766
4767 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4768 struct cea_db {
4769 u8 tag_length;
4770 u8 data[];
4771 } __packed;
4772
cea_db_tag(const struct cea_db * db)4773 static int cea_db_tag(const struct cea_db *db)
4774 {
4775 return db->tag_length >> 5;
4776 }
4777
cea_db_payload_len(const void * _db)4778 static int cea_db_payload_len(const void *_db)
4779 {
4780 /* FIXME: Transition to passing struct cea_db * everywhere. */
4781 const struct cea_db *db = _db;
4782
4783 return db->tag_length & 0x1f;
4784 }
4785
cea_db_data(const struct cea_db * db)4786 static const void *cea_db_data(const struct cea_db *db)
4787 {
4788 return db->data;
4789 }
4790
cea_db_is_extended_tag(const struct cea_db * db,int tag)4791 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4792 {
4793 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4794 cea_db_payload_len(db) >= 1 &&
4795 db->data[0] == tag;
4796 }
4797
cea_db_is_vendor(const struct cea_db * db,int vendor_oui)4798 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4799 {
4800 const u8 *data = cea_db_data(db);
4801
4802 return cea_db_tag(db) == CTA_DB_VENDOR &&
4803 cea_db_payload_len(db) >= 3 &&
4804 oui(data[2], data[1], data[0]) == vendor_oui;
4805 }
4806
cea_db_iter_edid_begin(const struct drm_edid * drm_edid,struct cea_db_iter * iter)4807 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4808 struct cea_db_iter *iter)
4809 {
4810 memset(iter, 0, sizeof(*iter));
4811
4812 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4813 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4814 }
4815
4816 static const struct cea_db *
__cea_db_iter_current_block(const struct cea_db_iter * iter)4817 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4818 {
4819 const struct cea_db *db;
4820
4821 if (!iter->collection)
4822 return NULL;
4823
4824 db = (const struct cea_db *)&iter->collection[iter->index];
4825
4826 if (iter->index + sizeof(*db) <= iter->end &&
4827 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4828 return db;
4829
4830 return NULL;
4831 }
4832
4833 /*
4834 * References:
4835 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4836 */
cea_db_collection_size(const u8 * cta)4837 static int cea_db_collection_size(const u8 *cta)
4838 {
4839 u8 d = cta[2];
4840
4841 if (d < 4 || d > 127)
4842 return 0;
4843
4844 return d - 4;
4845 }
4846
4847 /*
4848 * References:
4849 * - VESA E-EDID v1.4
4850 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4851 */
__cea_db_iter_edid_next(struct cea_db_iter * iter)4852 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4853 {
4854 const u8 *ext;
4855
4856 drm_edid_iter_for_each(ext, &iter->edid_iter) {
4857 int size;
4858
4859 /* Only support CTA Extension revision 3+ */
4860 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4861 continue;
4862
4863 size = cea_db_collection_size(ext);
4864 if (!size)
4865 continue;
4866
4867 iter->index = 4;
4868 iter->end = iter->index + size;
4869
4870 return ext;
4871 }
4872
4873 return NULL;
4874 }
4875
4876 /*
4877 * References:
4878 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4879 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4880 *
4881 * Note that the above do not specify any connection between DisplayID Data
4882 * Block revision and CTA Extension versions.
4883 */
__cea_db_iter_displayid_next(struct cea_db_iter * iter)4884 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4885 {
4886 const struct displayid_block *block;
4887
4888 displayid_iter_for_each(block, &iter->displayid_iter) {
4889 if (block->tag != DATA_BLOCK_CTA)
4890 continue;
4891
4892 /*
4893 * The displayid iterator has already verified the block bounds
4894 * in displayid_iter_block().
4895 */
4896 iter->index = sizeof(*block);
4897 iter->end = iter->index + block->num_bytes;
4898
4899 return block;
4900 }
4901
4902 return NULL;
4903 }
4904
__cea_db_iter_next(struct cea_db_iter * iter)4905 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
4906 {
4907 const struct cea_db *db;
4908
4909 if (iter->collection) {
4910 /* Current collection should always be valid. */
4911 db = __cea_db_iter_current_block(iter);
4912 if (WARN_ON(!db)) {
4913 iter->collection = NULL;
4914 return NULL;
4915 }
4916
4917 /* Next block in CTA Data Block Collection */
4918 iter->index += sizeof(*db) + cea_db_payload_len(db);
4919
4920 db = __cea_db_iter_current_block(iter);
4921 if (db)
4922 return db;
4923 }
4924
4925 for (;;) {
4926 /*
4927 * Find the next CTA Data Block Collection. First iterate all
4928 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
4929 *
4930 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
4931 * Extension, it's recommended that DisplayID extensions are
4932 * exposed after all of the CTA Extensions.
4933 */
4934 iter->collection = __cea_db_iter_edid_next(iter);
4935 if (!iter->collection)
4936 iter->collection = __cea_db_iter_displayid_next(iter);
4937
4938 if (!iter->collection)
4939 return NULL;
4940
4941 db = __cea_db_iter_current_block(iter);
4942 if (db)
4943 return db;
4944 }
4945 }
4946
4947 #define cea_db_iter_for_each(__db, __iter) \
4948 while (((__db) = __cea_db_iter_next(__iter)))
4949
cea_db_iter_end(struct cea_db_iter * iter)4950 static void cea_db_iter_end(struct cea_db_iter *iter)
4951 {
4952 displayid_iter_end(&iter->displayid_iter);
4953 drm_edid_iter_end(&iter->edid_iter);
4954
4955 memset(iter, 0, sizeof(*iter));
4956 }
4957
cea_db_is_hdmi_vsdb(const struct cea_db * db)4958 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
4959 {
4960 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
4961 cea_db_payload_len(db) >= 5;
4962 }
4963
cea_db_is_hdmi_forum_vsdb(const struct cea_db * db)4964 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
4965 {
4966 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
4967 cea_db_payload_len(db) >= 7;
4968 }
4969
cea_db_is_hdmi_forum_eeodb(const void * db)4970 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
4971 {
4972 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
4973 cea_db_payload_len(db) >= 2;
4974 }
4975
cea_db_is_microsoft_vsdb(const struct cea_db * db)4976 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
4977 {
4978 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
4979 cea_db_payload_len(db) == 21;
4980 }
4981
cea_db_is_vcdb(const struct cea_db * db)4982 static bool cea_db_is_vcdb(const struct cea_db *db)
4983 {
4984 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
4985 cea_db_payload_len(db) == 2;
4986 }
4987
cea_db_is_hdmi_forum_scdb(const struct cea_db * db)4988 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
4989 {
4990 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
4991 cea_db_payload_len(db) >= 7;
4992 }
4993
cea_db_is_y420cmdb(const struct cea_db * db)4994 static bool cea_db_is_y420cmdb(const struct cea_db *db)
4995 {
4996 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
4997 }
4998
cea_db_is_y420vdb(const struct cea_db * db)4999 static bool cea_db_is_y420vdb(const struct cea_db *db)
5000 {
5001 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5002 }
5003
cea_db_is_hdmi_hdr_metadata_block(const struct cea_db * db)5004 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5005 {
5006 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5007 cea_db_payload_len(db) >= 3;
5008 }
5009
5010 /*
5011 * Get the HF-EEODB override extension block count from EDID.
5012 *
5013 * The passed in EDID may be partially read, as long as it has at least two
5014 * blocks (base block and one extension block) if EDID extension count is > 0.
5015 *
5016 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5017 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5018 * iterators instead.
5019 *
5020 * References:
5021 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5022 */
edid_hfeeodb_extension_block_count(const struct edid * edid)5023 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5024 {
5025 const u8 *cta;
5026
5027 /* No extensions according to base block, no HF-EEODB. */
5028 if (!edid_extension_block_count(edid))
5029 return 0;
5030
5031 /* HF-EEODB is always in the first EDID extension block only */
5032 cta = edid_extension_block_data(edid, 0);
5033 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5034 return 0;
5035
5036 /* Need to have the data block collection, and at least 3 bytes. */
5037 if (cea_db_collection_size(cta) < 3)
5038 return 0;
5039
5040 /*
5041 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5042 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5043 * through 6 of Block 1 of the E-EDID.
5044 */
5045 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5046 return 0;
5047
5048 return cta[4 + 2];
5049 }
5050
drm_parse_y420cmdb_bitmap(struct drm_connector * connector,const u8 * db)5051 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
5052 const u8 *db)
5053 {
5054 struct drm_display_info *info = &connector->display_info;
5055 struct drm_hdmi_info *hdmi = &info->hdmi;
5056 u8 map_len = cea_db_payload_len(db) - 1;
5057 u8 count;
5058 u64 map = 0;
5059
5060 if (map_len == 0) {
5061 /* All CEA modes support ycbcr420 sampling also.*/
5062 hdmi->y420_cmdb_map = U64_MAX;
5063 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5064 return;
5065 }
5066
5067 /*
5068 * This map indicates which of the existing CEA block modes
5069 * from VDB can support YCBCR420 output too. So if bit=0 is
5070 * set, first mode from VDB can support YCBCR420 output too.
5071 * We will parse and keep this map, before parsing VDB itself
5072 * to avoid going through the same block again and again.
5073 *
5074 * Spec is not clear about max possible size of this block.
5075 * Clamping max bitmap block size at 8 bytes. Every byte can
5076 * address 8 CEA modes, in this way this map can address
5077 * 8*8 = first 64 SVDs.
5078 */
5079 if (WARN_ON_ONCE(map_len > 8))
5080 map_len = 8;
5081
5082 for (count = 0; count < map_len; count++)
5083 map |= (u64)db[2 + count] << (8 * count);
5084
5085 if (map)
5086 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5087
5088 hdmi->y420_cmdb_map = map;
5089 }
5090
add_cea_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)5091 static int add_cea_modes(struct drm_connector *connector,
5092 const struct drm_edid *drm_edid)
5093 {
5094 const struct cea_db *db;
5095 struct cea_db_iter iter;
5096 int modes = 0;
5097
5098 cea_db_iter_edid_begin(drm_edid, &iter);
5099 cea_db_iter_for_each(db, &iter) {
5100 const u8 *hdmi = NULL, *video = NULL;
5101 u8 hdmi_len = 0, video_len = 0;
5102
5103 if (cea_db_tag(db) == CTA_DB_VIDEO) {
5104 video = cea_db_data(db);
5105 video_len = cea_db_payload_len(db);
5106 modes += do_cea_modes(connector, video, video_len);
5107 } else if (cea_db_is_hdmi_vsdb(db)) {
5108 /* FIXME: Switch to use cea_db_data() */
5109 hdmi = (const u8 *)db;
5110 hdmi_len = cea_db_payload_len(db);
5111 } else if (cea_db_is_y420vdb(db)) {
5112 const u8 *vdb420 = cea_db_data(db) + 1;
5113
5114 /* Add 4:2:0(only) modes present in EDID */
5115 modes += do_y420vdb_modes(connector, vdb420,
5116 cea_db_payload_len(db) - 1);
5117 }
5118
5119 /*
5120 * We parse the HDMI VSDB after having added the cea modes as we
5121 * will be patching their flags when the sink supports stereo
5122 * 3D.
5123 */
5124 if (hdmi)
5125 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
5126 video, video_len);
5127 }
5128 cea_db_iter_end(&iter);
5129
5130 return modes;
5131 }
5132
fixup_detailed_cea_mode_clock(struct drm_display_mode * mode)5133 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
5134 {
5135 const struct drm_display_mode *cea_mode;
5136 int clock1, clock2, clock;
5137 u8 vic;
5138 const char *type;
5139
5140 /*
5141 * allow 5kHz clock difference either way to account for
5142 * the 10kHz clock resolution limit of detailed timings.
5143 */
5144 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5145 if (drm_valid_cea_vic(vic)) {
5146 type = "CEA";
5147 cea_mode = cea_mode_for_vic(vic);
5148 clock1 = cea_mode->clock;
5149 clock2 = cea_mode_alternate_clock(cea_mode);
5150 } else {
5151 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5152 if (drm_valid_hdmi_vic(vic)) {
5153 type = "HDMI";
5154 cea_mode = &edid_4k_modes[vic];
5155 clock1 = cea_mode->clock;
5156 clock2 = hdmi_mode_alternate_clock(cea_mode);
5157 } else {
5158 return;
5159 }
5160 }
5161
5162 /* pick whichever is closest */
5163 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5164 clock = clock1;
5165 else
5166 clock = clock2;
5167
5168 if (mode->clock == clock)
5169 return;
5170
5171 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5172 type, vic, mode->clock, clock);
5173 mode->clock = clock;
5174 }
5175
drm_calculate_luminance_range(struct drm_connector * connector)5176 static void drm_calculate_luminance_range(struct drm_connector *connector)
5177 {
5178 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5179 struct drm_luminance_range_info *luminance_range =
5180 &connector->display_info.luminance_range;
5181 static const u8 pre_computed_values[] = {
5182 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5183 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5184 };
5185 u32 max_avg, min_cll, max, min, q, r;
5186
5187 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5188 return;
5189
5190 max_avg = hdr_metadata->max_fall;
5191 min_cll = hdr_metadata->min_cll;
5192
5193 /*
5194 * From the specification (CTA-861-G), for calculating the maximum
5195 * luminance we need to use:
5196 * Luminance = 50*2**(CV/32)
5197 * Where CV is a one-byte value.
5198 * For calculating this expression we may need float point precision;
5199 * to avoid this complexity level, we take advantage that CV is divided
5200 * by a constant. From the Euclids division algorithm, we know that CV
5201 * can be written as: CV = 32*q + r. Next, we replace CV in the
5202 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5203 * need to pre-compute the value of r/32. For pre-computing the values
5204 * We just used the following Ruby line:
5205 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5206 * The results of the above expressions can be verified at
5207 * pre_computed_values.
5208 */
5209 q = max_avg >> 5;
5210 r = max_avg % 32;
5211 max = (1 << q) * pre_computed_values[r];
5212
5213 /* min luminance: maxLum * (CV/255)^2 / 100 */
5214 q = DIV_ROUND_CLOSEST(min_cll, 255);
5215 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5216
5217 luminance_range->min_luminance = min;
5218 luminance_range->max_luminance = max;
5219 }
5220
eotf_supported(const u8 * edid_ext)5221 static uint8_t eotf_supported(const u8 *edid_ext)
5222 {
5223 return edid_ext[2] &
5224 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5225 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5226 BIT(HDMI_EOTF_SMPTE_ST2084) |
5227 BIT(HDMI_EOTF_BT_2100_HLG));
5228 }
5229
hdr_metadata_type(const u8 * edid_ext)5230 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5231 {
5232 return edid_ext[3] &
5233 BIT(HDMI_STATIC_METADATA_TYPE1);
5234 }
5235
5236 static void
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)5237 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5238 {
5239 u16 len;
5240
5241 len = cea_db_payload_len(db);
5242
5243 connector->hdr_sink_metadata.hdmi_type1.eotf =
5244 eotf_supported(db);
5245 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5246 hdr_metadata_type(db);
5247
5248 if (len >= 4)
5249 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5250 if (len >= 5)
5251 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5252 if (len >= 6) {
5253 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5254
5255 /* Calculate only when all values are available */
5256 drm_calculate_luminance_range(connector);
5257 }
5258 }
5259
5260 static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)5261 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5262 {
5263 u8 len = cea_db_payload_len(db);
5264
5265 if (len >= 6 && (db[6] & (1 << 7)))
5266 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5267 if (len >= 8) {
5268 connector->latency_present[0] = db[8] >> 7;
5269 connector->latency_present[1] = (db[8] >> 6) & 1;
5270 }
5271 if (len >= 9)
5272 connector->video_latency[0] = db[9];
5273 if (len >= 10)
5274 connector->audio_latency[0] = db[10];
5275 if (len >= 11)
5276 connector->video_latency[1] = db[11];
5277 if (len >= 12)
5278 connector->audio_latency[1] = db[12];
5279
5280 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
5281 "video latency %d %d, "
5282 "audio latency %d %d\n",
5283 connector->latency_present[0],
5284 connector->latency_present[1],
5285 connector->video_latency[0],
5286 connector->video_latency[1],
5287 connector->audio_latency[0],
5288 connector->audio_latency[1]);
5289 }
5290
5291 static void
monitor_name(const struct detailed_timing * timing,void * data)5292 monitor_name(const struct detailed_timing *timing, void *data)
5293 {
5294 const char **res = data;
5295
5296 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5297 return;
5298
5299 *res = timing->data.other_data.data.str.str;
5300 }
5301
get_monitor_name(const struct drm_edid * drm_edid,char name[13])5302 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5303 {
5304 const char *edid_name = NULL;
5305 int mnl;
5306
5307 if (!drm_edid || !name)
5308 return 0;
5309
5310 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5311 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5312 if (edid_name[mnl] == 0x0a)
5313 break;
5314
5315 name[mnl] = edid_name[mnl];
5316 }
5317
5318 return mnl;
5319 }
5320
5321 /**
5322 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5323 * @edid: monitor EDID information
5324 * @name: pointer to a character array to hold the name of the monitor
5325 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5326 *
5327 */
drm_edid_get_monitor_name(const struct edid * edid,char * name,int bufsize)5328 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5329 {
5330 int name_length = 0;
5331
5332 if (bufsize <= 0)
5333 return;
5334
5335 if (edid) {
5336 char buf[13];
5337 struct drm_edid drm_edid = {
5338 .edid = edid,
5339 .size = edid_size(edid),
5340 };
5341
5342 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5343 memcpy(name, buf, name_length);
5344 }
5345
5346 name[name_length] = '\0';
5347 }
5348 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5349
clear_eld(struct drm_connector * connector)5350 static void clear_eld(struct drm_connector *connector)
5351 {
5352 memset(connector->eld, 0, sizeof(connector->eld));
5353
5354 connector->latency_present[0] = false;
5355 connector->latency_present[1] = false;
5356 connector->video_latency[0] = 0;
5357 connector->audio_latency[0] = 0;
5358 connector->video_latency[1] = 0;
5359 connector->audio_latency[1] = 0;
5360 }
5361
5362 /*
5363 * drm_edid_to_eld - build ELD from EDID
5364 * @connector: connector corresponding to the HDMI/DP sink
5365 * @drm_edid: EDID to parse
5366 *
5367 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5368 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5369 */
drm_edid_to_eld(struct drm_connector * connector,const struct drm_edid * drm_edid)5370 static void drm_edid_to_eld(struct drm_connector *connector,
5371 const struct drm_edid *drm_edid)
5372 {
5373 const struct drm_display_info *info = &connector->display_info;
5374 const struct cea_db *db;
5375 struct cea_db_iter iter;
5376 uint8_t *eld = connector->eld;
5377 int total_sad_count = 0;
5378 int mnl;
5379
5380 clear_eld(connector);
5381
5382 if (!drm_edid)
5383 return;
5384
5385 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5386 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
5387
5388 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5389 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5390
5391 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5392
5393 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5394 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5395 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5396 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5397
5398 cea_db_iter_edid_begin(drm_edid, &iter);
5399 cea_db_iter_for_each(db, &iter) {
5400 const u8 *data = cea_db_data(db);
5401 int len = cea_db_payload_len(db);
5402 int sad_count;
5403
5404 switch (cea_db_tag(db)) {
5405 case CTA_DB_AUDIO:
5406 /* Audio Data Block, contains SADs */
5407 sad_count = min(len / 3, 15 - total_sad_count);
5408 if (sad_count >= 1)
5409 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5410 data, sad_count * 3);
5411 total_sad_count += sad_count;
5412 break;
5413 case CTA_DB_SPEAKER:
5414 /* Speaker Allocation Data Block */
5415 if (len >= 1)
5416 eld[DRM_ELD_SPEAKER] = data[0];
5417 break;
5418 case CTA_DB_VENDOR:
5419 /* HDMI Vendor-Specific Data Block */
5420 if (cea_db_is_hdmi_vsdb(db))
5421 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5422 break;
5423 default:
5424 break;
5425 }
5426 }
5427 cea_db_iter_end(&iter);
5428
5429 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5430
5431 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5432 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5433 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5434 else
5435 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5436
5437 eld[DRM_ELD_BASELINE_ELD_LEN] =
5438 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5439
5440 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
5441 drm_eld_size(eld), total_sad_count);
5442 }
5443
_drm_edid_to_sad(const struct drm_edid * drm_edid,struct cea_sad ** sads)5444 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5445 struct cea_sad **sads)
5446 {
5447 const struct cea_db *db;
5448 struct cea_db_iter iter;
5449 int count = 0;
5450
5451 cea_db_iter_edid_begin(drm_edid, &iter);
5452 cea_db_iter_for_each(db, &iter) {
5453 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5454 int j;
5455
5456 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5457 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5458 if (!*sads)
5459 return -ENOMEM;
5460 for (j = 0; j < count; j++) {
5461 const u8 *sad = &db->data[j * 3];
5462
5463 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5464 (*sads)[j].channels = sad[0] & 0x7;
5465 (*sads)[j].freq = sad[1] & 0x7F;
5466 (*sads)[j].byte2 = sad[2];
5467 }
5468 break;
5469 }
5470 }
5471 cea_db_iter_end(&iter);
5472
5473 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5474
5475 return count;
5476 }
5477
5478 /**
5479 * drm_edid_to_sad - extracts SADs from EDID
5480 * @edid: EDID to parse
5481 * @sads: pointer that will be set to the extracted SADs
5482 *
5483 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5484 *
5485 * Note: The returned pointer needs to be freed using kfree().
5486 *
5487 * Return: The number of found SADs or negative number on error.
5488 */
drm_edid_to_sad(const struct edid * edid,struct cea_sad ** sads)5489 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5490 {
5491 struct drm_edid drm_edid;
5492
5493 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5494 }
5495 EXPORT_SYMBOL(drm_edid_to_sad);
5496
_drm_edid_to_speaker_allocation(const struct drm_edid * drm_edid,u8 ** sadb)5497 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5498 u8 **sadb)
5499 {
5500 const struct cea_db *db;
5501 struct cea_db_iter iter;
5502 int count = 0;
5503
5504 cea_db_iter_edid_begin(drm_edid, &iter);
5505 cea_db_iter_for_each(db, &iter) {
5506 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5507 cea_db_payload_len(db) == 3) {
5508 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5509 GFP_KERNEL);
5510 if (!*sadb)
5511 return -ENOMEM;
5512 count = cea_db_payload_len(db);
5513 break;
5514 }
5515 }
5516 cea_db_iter_end(&iter);
5517
5518 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5519
5520 return count;
5521 }
5522
5523 /**
5524 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5525 * @edid: EDID to parse
5526 * @sadb: pointer to the speaker block
5527 *
5528 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5529 *
5530 * Note: The returned pointer needs to be freed using kfree().
5531 *
5532 * Return: The number of found Speaker Allocation Blocks or negative number on
5533 * error.
5534 */
drm_edid_to_speaker_allocation(const struct edid * edid,u8 ** sadb)5535 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5536 {
5537 struct drm_edid drm_edid;
5538
5539 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5540 sadb);
5541 }
5542 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5543
5544 /**
5545 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5546 * @connector: connector associated with the HDMI/DP sink
5547 * @mode: the display mode
5548 *
5549 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5550 * the sink doesn't support audio or video.
5551 */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)5552 int drm_av_sync_delay(struct drm_connector *connector,
5553 const struct drm_display_mode *mode)
5554 {
5555 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5556 int a, v;
5557
5558 if (!connector->latency_present[0])
5559 return 0;
5560 if (!connector->latency_present[1])
5561 i = 0;
5562
5563 a = connector->audio_latency[i];
5564 v = connector->video_latency[i];
5565
5566 /*
5567 * HDMI/DP sink doesn't support audio or video?
5568 */
5569 if (a == 255 || v == 255)
5570 return 0;
5571
5572 /*
5573 * Convert raw EDID values to millisecond.
5574 * Treat unknown latency as 0ms.
5575 */
5576 if (a)
5577 a = min(2 * (a - 1), 500);
5578 if (v)
5579 v = min(2 * (v - 1), 500);
5580
5581 return max(v - a, 0);
5582 }
5583 EXPORT_SYMBOL(drm_av_sync_delay);
5584
_drm_detect_hdmi_monitor(const struct drm_edid * drm_edid)5585 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5586 {
5587 const struct cea_db *db;
5588 struct cea_db_iter iter;
5589 bool hdmi = false;
5590
5591 /*
5592 * Because HDMI identifier is in Vendor Specific Block,
5593 * search it from all data blocks of CEA extension.
5594 */
5595 cea_db_iter_edid_begin(drm_edid, &iter);
5596 cea_db_iter_for_each(db, &iter) {
5597 if (cea_db_is_hdmi_vsdb(db)) {
5598 hdmi = true;
5599 break;
5600 }
5601 }
5602 cea_db_iter_end(&iter);
5603
5604 return hdmi;
5605 }
5606
5607 /**
5608 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5609 * @edid: monitor EDID information
5610 *
5611 * Parse the CEA extension according to CEA-861-B.
5612 *
5613 * Drivers that have added the modes parsed from EDID to drm_display_info
5614 * should use &drm_display_info.is_hdmi instead of calling this function.
5615 *
5616 * Return: True if the monitor is HDMI, false if not or unknown.
5617 */
drm_detect_hdmi_monitor(const struct edid * edid)5618 bool drm_detect_hdmi_monitor(const struct edid *edid)
5619 {
5620 struct drm_edid drm_edid;
5621
5622 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5623 }
5624 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5625
_drm_detect_monitor_audio(const struct drm_edid * drm_edid)5626 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5627 {
5628 struct drm_edid_iter edid_iter;
5629 const struct cea_db *db;
5630 struct cea_db_iter iter;
5631 const u8 *edid_ext;
5632 bool has_audio = false;
5633
5634 drm_edid_iter_begin(drm_edid, &edid_iter);
5635 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5636 if (edid_ext[0] == CEA_EXT) {
5637 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5638 if (has_audio)
5639 break;
5640 }
5641 }
5642 drm_edid_iter_end(&edid_iter);
5643
5644 if (has_audio) {
5645 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5646 goto end;
5647 }
5648
5649 cea_db_iter_edid_begin(drm_edid, &iter);
5650 cea_db_iter_for_each(db, &iter) {
5651 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5652 const u8 *data = cea_db_data(db);
5653 int i;
5654
5655 for (i = 0; i < cea_db_payload_len(db); i += 3)
5656 DRM_DEBUG_KMS("CEA audio format %d\n",
5657 (data[i] >> 3) & 0xf);
5658 has_audio = true;
5659 break;
5660 }
5661 }
5662 cea_db_iter_end(&iter);
5663
5664 end:
5665 return has_audio;
5666 }
5667
5668 /**
5669 * drm_detect_monitor_audio - check monitor audio capability
5670 * @edid: EDID block to scan
5671 *
5672 * Monitor should have CEA extension block.
5673 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5674 * audio' only. If there is any audio extension block and supported
5675 * audio format, assume at least 'basic audio' support, even if 'basic
5676 * audio' is not defined in EDID.
5677 *
5678 * Return: True if the monitor supports audio, false otherwise.
5679 */
drm_detect_monitor_audio(const struct edid * edid)5680 bool drm_detect_monitor_audio(const struct edid *edid)
5681 {
5682 struct drm_edid drm_edid;
5683
5684 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5685 }
5686 EXPORT_SYMBOL(drm_detect_monitor_audio);
5687
5688
5689 /**
5690 * drm_default_rgb_quant_range - default RGB quantization range
5691 * @mode: display mode
5692 *
5693 * Determine the default RGB quantization range for the mode,
5694 * as specified in CEA-861.
5695 *
5696 * Return: The default RGB quantization range for the mode
5697 */
5698 enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)5699 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5700 {
5701 /* All CEA modes other than VIC 1 use limited quantization range. */
5702 return drm_match_cea_mode(mode) > 1 ?
5703 HDMI_QUANTIZATION_RANGE_LIMITED :
5704 HDMI_QUANTIZATION_RANGE_FULL;
5705 }
5706 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5707
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)5708 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5709 {
5710 struct drm_display_info *info = &connector->display_info;
5711
5712 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5713
5714 if (db[2] & EDID_CEA_VCDB_QS)
5715 info->rgb_quant_range_selectable = true;
5716 }
5717
5718 static
drm_get_max_frl_rate(int max_frl_rate,u8 * max_lanes,u8 * max_rate_per_lane)5719 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5720 {
5721 switch (max_frl_rate) {
5722 case 1:
5723 *max_lanes = 3;
5724 *max_rate_per_lane = 3;
5725 break;
5726 case 2:
5727 *max_lanes = 3;
5728 *max_rate_per_lane = 6;
5729 break;
5730 case 3:
5731 *max_lanes = 4;
5732 *max_rate_per_lane = 6;
5733 break;
5734 case 4:
5735 *max_lanes = 4;
5736 *max_rate_per_lane = 8;
5737 break;
5738 case 5:
5739 *max_lanes = 4;
5740 *max_rate_per_lane = 10;
5741 break;
5742 case 6:
5743 *max_lanes = 4;
5744 *max_rate_per_lane = 12;
5745 break;
5746 case 0:
5747 default:
5748 *max_lanes = 0;
5749 *max_rate_per_lane = 0;
5750 }
5751 }
5752
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)5753 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5754 const u8 *db)
5755 {
5756 u8 dc_mask;
5757 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5758
5759 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5760 hdmi->y420_dc_modes = dc_mask;
5761 }
5762
5763 /* Sink Capability Data Structure */
drm_parse_hdmi_forum_scds(struct drm_connector * connector,const u8 * hf_scds)5764 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5765 const u8 *hf_scds)
5766 {
5767 struct drm_display_info *display = &connector->display_info;
5768 struct drm_hdmi_info *hdmi = &display->hdmi;
5769
5770 display->has_hdmi_infoframe = true;
5771
5772 if (hf_scds[6] & 0x80) {
5773 hdmi->scdc.supported = true;
5774 if (hf_scds[6] & 0x40)
5775 hdmi->scdc.read_request = true;
5776 }
5777
5778 /*
5779 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5780 * And as per the spec, three factors confirm this:
5781 * * Availability of a HF-VSDB block in EDID (check)
5782 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5783 * * SCDC support available (let's check)
5784 * Lets check it out.
5785 */
5786
5787 if (hf_scds[5]) {
5788 /* max clock is 5000 KHz times block value */
5789 u32 max_tmds_clock = hf_scds[5] * 5000;
5790 struct drm_scdc *scdc = &hdmi->scdc;
5791
5792 if (max_tmds_clock > 340000) {
5793 display->max_tmds_clock = max_tmds_clock;
5794 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5795 display->max_tmds_clock);
5796 }
5797
5798 if (scdc->supported) {
5799 scdc->scrambling.supported = true;
5800
5801 /* Few sinks support scrambling for clocks < 340M */
5802 if ((hf_scds[6] & 0x8))
5803 scdc->scrambling.low_rates = true;
5804 }
5805 }
5806
5807 if (hf_scds[7]) {
5808 u8 max_frl_rate;
5809 u8 dsc_max_frl_rate;
5810 u8 dsc_max_slices;
5811 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5812
5813 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5814 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5815 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5816 &hdmi->max_frl_rate_per_lane);
5817 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5818
5819 if (hdmi_dsc->v_1p2) {
5820 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5821 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5822
5823 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5824 hdmi_dsc->bpc_supported = 16;
5825 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5826 hdmi_dsc->bpc_supported = 12;
5827 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5828 hdmi_dsc->bpc_supported = 10;
5829 else
5830 hdmi_dsc->bpc_supported = 0;
5831
5832 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5833 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5834 &hdmi_dsc->max_frl_rate_per_lane);
5835 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5836
5837 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5838 switch (dsc_max_slices) {
5839 case 1:
5840 hdmi_dsc->max_slices = 1;
5841 hdmi_dsc->clk_per_slice = 340;
5842 break;
5843 case 2:
5844 hdmi_dsc->max_slices = 2;
5845 hdmi_dsc->clk_per_slice = 340;
5846 break;
5847 case 3:
5848 hdmi_dsc->max_slices = 4;
5849 hdmi_dsc->clk_per_slice = 340;
5850 break;
5851 case 4:
5852 hdmi_dsc->max_slices = 8;
5853 hdmi_dsc->clk_per_slice = 340;
5854 break;
5855 case 5:
5856 hdmi_dsc->max_slices = 8;
5857 hdmi_dsc->clk_per_slice = 400;
5858 break;
5859 case 6:
5860 hdmi_dsc->max_slices = 12;
5861 hdmi_dsc->clk_per_slice = 400;
5862 break;
5863 case 7:
5864 hdmi_dsc->max_slices = 16;
5865 hdmi_dsc->clk_per_slice = 400;
5866 break;
5867 case 0:
5868 default:
5869 hdmi_dsc->max_slices = 0;
5870 hdmi_dsc->clk_per_slice = 0;
5871 }
5872 }
5873 }
5874
5875 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
5876 }
5877
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)5878 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5879 const u8 *hdmi)
5880 {
5881 struct drm_display_info *info = &connector->display_info;
5882 unsigned int dc_bpc = 0;
5883
5884 /* HDMI supports at least 8 bpc */
5885 info->bpc = 8;
5886
5887 if (cea_db_payload_len(hdmi) < 6)
5888 return;
5889
5890 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5891 dc_bpc = 10;
5892 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
5893 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5894 connector->name);
5895 }
5896
5897 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5898 dc_bpc = 12;
5899 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
5900 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5901 connector->name);
5902 }
5903
5904 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5905 dc_bpc = 16;
5906 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
5907 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5908 connector->name);
5909 }
5910
5911 if (dc_bpc == 0) {
5912 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5913 connector->name);
5914 return;
5915 }
5916
5917 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5918 connector->name, dc_bpc);
5919 info->bpc = dc_bpc;
5920
5921 /* YCRCB444 is optional according to spec. */
5922 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5923 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
5924 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5925 connector->name);
5926 }
5927
5928 /*
5929 * Spec says that if any deep color mode is supported at all,
5930 * then deep color 36 bit must be supported.
5931 */
5932 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5933 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5934 connector->name);
5935 }
5936 }
5937
5938 static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)5939 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5940 {
5941 struct drm_display_info *info = &connector->display_info;
5942 u8 len = cea_db_payload_len(db);
5943
5944 info->is_hdmi = true;
5945
5946 if (len >= 6)
5947 info->dvi_dual = db[6] & 1;
5948 if (len >= 7)
5949 info->max_tmds_clock = db[7] * 5000;
5950
5951 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5952 "max TMDS clock %d kHz\n",
5953 info->dvi_dual,
5954 info->max_tmds_clock);
5955
5956 drm_parse_hdmi_deep_color_info(connector, db);
5957 }
5958
5959 /*
5960 * See EDID extension for head-mounted and specialized monitors, specified at:
5961 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5962 */
drm_parse_microsoft_vsdb(struct drm_connector * connector,const u8 * db)5963 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5964 const u8 *db)
5965 {
5966 struct drm_display_info *info = &connector->display_info;
5967 u8 version = db[4];
5968 bool desktop_usage = db[5] & BIT(6);
5969
5970 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5971 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5972 info->non_desktop = true;
5973
5974 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5975 version, db[5]);
5976 }
5977
drm_parse_cea_ext(struct drm_connector * connector,const struct drm_edid * drm_edid)5978 static void drm_parse_cea_ext(struct drm_connector *connector,
5979 const struct drm_edid *drm_edid)
5980 {
5981 struct drm_display_info *info = &connector->display_info;
5982 struct drm_edid_iter edid_iter;
5983 const struct cea_db *db;
5984 struct cea_db_iter iter;
5985 const u8 *edid_ext;
5986
5987 drm_edid_iter_begin(drm_edid, &edid_iter);
5988 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5989 if (edid_ext[0] != CEA_EXT)
5990 continue;
5991
5992 if (!info->cea_rev)
5993 info->cea_rev = edid_ext[1];
5994
5995 if (info->cea_rev != edid_ext[1])
5996 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",
5997 info->cea_rev, edid_ext[1]);
5998
5999 /* The existence of a CTA extension should imply RGB support */
6000 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6001 if (edid_ext[3] & EDID_CEA_YCRCB444)
6002 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6003 if (edid_ext[3] & EDID_CEA_YCRCB422)
6004 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6005 }
6006 drm_edid_iter_end(&edid_iter);
6007
6008 cea_db_iter_edid_begin(drm_edid, &iter);
6009 cea_db_iter_for_each(db, &iter) {
6010 /* FIXME: convert parsers to use struct cea_db */
6011 const u8 *data = (const u8 *)db;
6012
6013 if (cea_db_is_hdmi_vsdb(db))
6014 drm_parse_hdmi_vsdb_video(connector, data);
6015 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6016 cea_db_is_hdmi_forum_scdb(db))
6017 drm_parse_hdmi_forum_scds(connector, data);
6018 else if (cea_db_is_microsoft_vsdb(db))
6019 drm_parse_microsoft_vsdb(connector, data);
6020 else if (cea_db_is_y420cmdb(db))
6021 drm_parse_y420cmdb_bitmap(connector, data);
6022 else if (cea_db_is_vcdb(db))
6023 drm_parse_vcdb(connector, data);
6024 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6025 drm_parse_hdr_metadata_block(connector, data);
6026 }
6027 cea_db_iter_end(&iter);
6028 }
6029
6030 static
get_monitor_range(const struct detailed_timing * timing,void * c)6031 void get_monitor_range(const struct detailed_timing *timing, void *c)
6032 {
6033 struct detailed_mode_closure *closure = c;
6034 struct drm_display_info *info = &closure->connector->display_info;
6035 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6036 const struct detailed_non_pixel *data = &timing->data.other_data;
6037 const struct detailed_data_monitor_range *range = &data->data.range;
6038 const struct edid *edid = closure->drm_edid->edid;
6039
6040 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6041 return;
6042
6043 /*
6044 * Check for flag range limits only. If flag == 1 then
6045 * no additional timing information provided.
6046 * Default GTF, GTF Secondary curve and CVT are not
6047 * supported
6048 */
6049 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6050 return;
6051
6052 monitor_range->min_vfreq = range->min_vfreq;
6053 monitor_range->max_vfreq = range->max_vfreq;
6054
6055 if (edid->revision >= 4) {
6056 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6057 monitor_range->min_vfreq += 255;
6058 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6059 monitor_range->max_vfreq += 255;
6060 }
6061 }
6062
drm_get_monitor_range(struct drm_connector * connector,const struct drm_edid * drm_edid)6063 static void drm_get_monitor_range(struct drm_connector *connector,
6064 const struct drm_edid *drm_edid)
6065 {
6066 const struct drm_display_info *info = &connector->display_info;
6067 struct detailed_mode_closure closure = {
6068 .connector = connector,
6069 .drm_edid = drm_edid,
6070 };
6071
6072 if (!version_greater(drm_edid, 1, 1))
6073 return;
6074
6075 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6076
6077 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6078 info->monitor_range.min_vfreq,
6079 info->monitor_range.max_vfreq);
6080 }
6081
drm_parse_vesa_mso_data(struct drm_connector * connector,const struct displayid_block * block)6082 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6083 const struct displayid_block *block)
6084 {
6085 struct displayid_vesa_vendor_specific_block *vesa =
6086 (struct displayid_vesa_vendor_specific_block *)block;
6087 struct drm_display_info *info = &connector->display_info;
6088
6089 if (block->num_bytes < 3) {
6090 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
6091 block->num_bytes);
6092 return;
6093 }
6094
6095 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6096 return;
6097
6098 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6099 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
6100 return;
6101 }
6102
6103 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6104 default:
6105 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
6106 fallthrough;
6107 case 0:
6108 info->mso_stream_count = 0;
6109 break;
6110 case 1:
6111 info->mso_stream_count = 2; /* 2 or 4 links */
6112 break;
6113 case 2:
6114 info->mso_stream_count = 4; /* 4 links */
6115 break;
6116 }
6117
6118 if (!info->mso_stream_count) {
6119 info->mso_pixel_overlap = 0;
6120 return;
6121 }
6122
6123 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6124 if (info->mso_pixel_overlap > 8) {
6125 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
6126 info->mso_pixel_overlap);
6127 info->mso_pixel_overlap = 8;
6128 }
6129
6130 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
6131 info->mso_stream_count, info->mso_pixel_overlap);
6132 }
6133
drm_update_mso(struct drm_connector * connector,const struct drm_edid * drm_edid)6134 static void drm_update_mso(struct drm_connector *connector,
6135 const struct drm_edid *drm_edid)
6136 {
6137 const struct displayid_block *block;
6138 struct displayid_iter iter;
6139
6140 displayid_iter_edid_begin(drm_edid, &iter);
6141 displayid_iter_for_each(block, &iter) {
6142 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6143 drm_parse_vesa_mso_data(connector, block);
6144 }
6145 displayid_iter_end(&iter);
6146 }
6147
6148 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6149 * all of the values which would have been set from EDID
6150 */
drm_reset_display_info(struct drm_connector * connector)6151 static void drm_reset_display_info(struct drm_connector *connector)
6152 {
6153 struct drm_display_info *info = &connector->display_info;
6154
6155 info->width_mm = 0;
6156 info->height_mm = 0;
6157
6158 info->bpc = 0;
6159 info->color_formats = 0;
6160 info->cea_rev = 0;
6161 info->max_tmds_clock = 0;
6162 info->dvi_dual = false;
6163 info->is_hdmi = false;
6164 info->has_hdmi_infoframe = false;
6165 info->rgb_quant_range_selectable = false;
6166 memset(&info->hdmi, 0, sizeof(info->hdmi));
6167
6168 info->edid_hdmi_rgb444_dc_modes = 0;
6169 info->edid_hdmi_ycbcr444_dc_modes = 0;
6170
6171 info->non_desktop = 0;
6172 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6173 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6174
6175 info->mso_stream_count = 0;
6176 info->mso_pixel_overlap = 0;
6177 info->max_dsc_bpp = 0;
6178 }
6179
update_display_info(struct drm_connector * connector,const struct drm_edid * drm_edid)6180 static u32 update_display_info(struct drm_connector *connector,
6181 const struct drm_edid *drm_edid)
6182 {
6183 struct drm_display_info *info = &connector->display_info;
6184 const struct edid *edid = drm_edid->edid;
6185
6186 u32 quirks = edid_get_quirks(drm_edid);
6187
6188 drm_reset_display_info(connector);
6189
6190 info->width_mm = edid->width_cm * 10;
6191 info->height_mm = edid->height_cm * 10;
6192
6193 drm_get_monitor_range(connector, drm_edid);
6194
6195 if (edid->revision < 3)
6196 goto out;
6197
6198 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6199 goto out;
6200
6201 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6202 drm_parse_cea_ext(connector, drm_edid);
6203
6204 /*
6205 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6206 *
6207 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6208 * tells us to assume 8 bpc color depth if the EDID doesn't have
6209 * extensions which tell otherwise.
6210 */
6211 if (info->bpc == 0 && edid->revision == 3 &&
6212 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6213 info->bpc = 8;
6214 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
6215 connector->name, info->bpc);
6216 }
6217
6218 /* Only defined for 1.4 with digital displays */
6219 if (edid->revision < 4)
6220 goto out;
6221
6222 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6223 case DRM_EDID_DIGITAL_DEPTH_6:
6224 info->bpc = 6;
6225 break;
6226 case DRM_EDID_DIGITAL_DEPTH_8:
6227 info->bpc = 8;
6228 break;
6229 case DRM_EDID_DIGITAL_DEPTH_10:
6230 info->bpc = 10;
6231 break;
6232 case DRM_EDID_DIGITAL_DEPTH_12:
6233 info->bpc = 12;
6234 break;
6235 case DRM_EDID_DIGITAL_DEPTH_14:
6236 info->bpc = 14;
6237 break;
6238 case DRM_EDID_DIGITAL_DEPTH_16:
6239 info->bpc = 16;
6240 break;
6241 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6242 default:
6243 info->bpc = 0;
6244 break;
6245 }
6246
6247 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6248 connector->name, info->bpc);
6249
6250 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6251 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6252 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6253 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6254
6255 drm_update_mso(connector, drm_edid);
6256
6257 out:
6258 if (quirks & EDID_QUIRK_NON_DESKTOP) {
6259 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
6260 info->non_desktop ? " (redundant quirk)" : "");
6261 info->non_desktop = true;
6262 }
6263
6264 if (quirks & EDID_QUIRK_CAP_DSC_15BPP)
6265 info->max_dsc_bpp = 15;
6266
6267 return quirks;
6268 }
6269
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings,bool type_7)6270 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6271 struct displayid_detailed_timings_1 *timings,
6272 bool type_7)
6273 {
6274 struct drm_display_mode *mode;
6275 unsigned pixel_clock = (timings->pixel_clock[0] |
6276 (timings->pixel_clock[1] << 8) |
6277 (timings->pixel_clock[2] << 16)) + 1;
6278 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6279 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6280 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6281 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6282 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6283 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6284 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6285 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6286 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6287 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6288
6289 mode = drm_mode_create(dev);
6290 if (!mode)
6291 return NULL;
6292
6293 /* resolution is kHz for type VII, and 10 kHz for type I */
6294 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6295 mode->hdisplay = hactive;
6296 mode->hsync_start = mode->hdisplay + hsync;
6297 mode->hsync_end = mode->hsync_start + hsync_width;
6298 mode->htotal = mode->hdisplay + hblank;
6299
6300 mode->vdisplay = vactive;
6301 mode->vsync_start = mode->vdisplay + vsync;
6302 mode->vsync_end = mode->vsync_start + vsync_width;
6303 mode->vtotal = mode->vdisplay + vblank;
6304
6305 mode->flags = 0;
6306 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6307 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6308 mode->type = DRM_MODE_TYPE_DRIVER;
6309
6310 if (timings->flags & 0x80)
6311 mode->type |= DRM_MODE_TYPE_PREFERRED;
6312 drm_mode_set_name(mode);
6313
6314 return mode;
6315 }
6316
add_displayid_detailed_1_modes(struct drm_connector * connector,const struct displayid_block * block)6317 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6318 const struct displayid_block *block)
6319 {
6320 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6321 int i;
6322 int num_timings;
6323 struct drm_display_mode *newmode;
6324 int num_modes = 0;
6325 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6326 /* blocks must be multiple of 20 bytes length */
6327 if (block->num_bytes % 20)
6328 return 0;
6329
6330 num_timings = block->num_bytes / 20;
6331 for (i = 0; i < num_timings; i++) {
6332 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6333
6334 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6335 if (!newmode)
6336 continue;
6337
6338 drm_mode_probed_add(connector, newmode);
6339 num_modes++;
6340 }
6341 return num_modes;
6342 }
6343
add_displayid_detailed_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)6344 static int add_displayid_detailed_modes(struct drm_connector *connector,
6345 const struct drm_edid *drm_edid)
6346 {
6347 const struct displayid_block *block;
6348 struct displayid_iter iter;
6349 int num_modes = 0;
6350
6351 displayid_iter_edid_begin(drm_edid, &iter);
6352 displayid_iter_for_each(block, &iter) {
6353 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6354 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6355 num_modes += add_displayid_detailed_1_modes(connector, block);
6356 }
6357 displayid_iter_end(&iter);
6358
6359 return num_modes;
6360 }
6361
_drm_edid_connector_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6362 static int _drm_edid_connector_update(struct drm_connector *connector,
6363 const struct drm_edid *drm_edid)
6364 {
6365 int num_modes = 0;
6366 u32 quirks;
6367
6368 if (!drm_edid) {
6369 drm_reset_display_info(connector);
6370 clear_eld(connector);
6371 return 0;
6372 }
6373
6374 /*
6375 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6376 * To avoid multiple parsing of same block, lets parse that map
6377 * from sink info, before parsing CEA modes.
6378 */
6379 quirks = update_display_info(connector, drm_edid);
6380
6381 /* Depends on info->cea_rev set by update_display_info() above */
6382 drm_edid_to_eld(connector, drm_edid);
6383
6384 /*
6385 * EDID spec says modes should be preferred in this order:
6386 * - preferred detailed mode
6387 * - other detailed modes from base block
6388 * - detailed modes from extension blocks
6389 * - CVT 3-byte code modes
6390 * - standard timing codes
6391 * - established timing codes
6392 * - modes inferred from GTF or CVT range information
6393 *
6394 * We get this pretty much right.
6395 *
6396 * XXX order for additional mode types in extension blocks?
6397 */
6398 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6399 num_modes += add_cvt_modes(connector, drm_edid);
6400 num_modes += add_standard_modes(connector, drm_edid);
6401 num_modes += add_established_modes(connector, drm_edid);
6402 num_modes += add_cea_modes(connector, drm_edid);
6403 num_modes += add_alternate_cea_modes(connector, drm_edid);
6404 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6405 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
6406 num_modes += add_inferred_modes(connector, drm_edid);
6407
6408 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6409 edid_fixup_preferred(connector, quirks);
6410
6411 if (quirks & EDID_QUIRK_FORCE_6BPC)
6412 connector->display_info.bpc = 6;
6413
6414 if (quirks & EDID_QUIRK_FORCE_8BPC)
6415 connector->display_info.bpc = 8;
6416
6417 if (quirks & EDID_QUIRK_FORCE_10BPC)
6418 connector->display_info.bpc = 10;
6419
6420 if (quirks & EDID_QUIRK_FORCE_12BPC)
6421 connector->display_info.bpc = 12;
6422
6423 return num_modes;
6424 }
6425
6426 static void _drm_update_tile_info(struct drm_connector *connector,
6427 const struct drm_edid *drm_edid);
6428
_drm_edid_connector_property_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6429 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6430 const struct drm_edid *drm_edid)
6431 {
6432 struct drm_device *dev = connector->dev;
6433 int ret;
6434
6435 if (connector->edid_blob_ptr) {
6436 const struct edid *old_edid = connector->edid_blob_ptr->data;
6437
6438 if (old_edid) {
6439 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6440 connector->epoch_counter++;
6441 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6442 connector->base.id, connector->name,
6443 connector->epoch_counter);
6444 }
6445 }
6446 }
6447
6448 ret = drm_property_replace_global_blob(dev,
6449 &connector->edid_blob_ptr,
6450 drm_edid ? drm_edid->size : 0,
6451 drm_edid ? drm_edid->edid : NULL,
6452 &connector->base,
6453 dev->mode_config.edid_property);
6454 if (ret) {
6455 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6456 connector->base.id, connector->name, ret);
6457 goto out;
6458 }
6459
6460 ret = drm_object_property_set_value(&connector->base,
6461 dev->mode_config.non_desktop_property,
6462 connector->display_info.non_desktop);
6463 if (ret) {
6464 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6465 connector->base.id, connector->name, ret);
6466 goto out;
6467 }
6468
6469 ret = drm_connector_set_tile_property(connector);
6470 if (ret) {
6471 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6472 connector->base.id, connector->name, ret);
6473 goto out;
6474 }
6475
6476 out:
6477 return ret;
6478 }
6479
6480 /**
6481 * drm_edid_connector_update - Update connector information from EDID
6482 * @connector: Connector
6483 * @drm_edid: EDID
6484 *
6485 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6486 * properties, etc. from the passed in EDID.
6487 *
6488 * If EDID is NULL, reset the information.
6489 *
6490 * Return: The number of modes added or 0 if we couldn't find any.
6491 */
drm_edid_connector_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6492 int drm_edid_connector_update(struct drm_connector *connector,
6493 const struct drm_edid *drm_edid)
6494 {
6495 int count;
6496
6497 /*
6498 * FIXME: Reconcile the differences in override_edid handling between
6499 * this and drm_connector_update_edid_property().
6500 *
6501 * If override_edid is set, and the EDID passed in here originates from
6502 * drm_edid_read() and friends, it will be the override EDID, and there
6503 * are no issues. drm_connector_update_edid_property() ignoring requests
6504 * to set the EDID dates back to a time when override EDID was not
6505 * handled at the low level EDID read.
6506 *
6507 * The only way the EDID passed in here can be different from the
6508 * override EDID is when a driver passes in an EDID that does *not*
6509 * originate from drm_edid_read() and friends, or passes in a stale
6510 * cached version. This, in turn, is a question of when an override EDID
6511 * set via debugfs should take effect.
6512 */
6513
6514 count = _drm_edid_connector_update(connector, drm_edid);
6515
6516 _drm_update_tile_info(connector, drm_edid);
6517
6518 /* Note: Ignore errors for now. */
6519 _drm_edid_connector_property_update(connector, drm_edid);
6520
6521 return count;
6522 }
6523 EXPORT_SYMBOL(drm_edid_connector_update);
6524
_drm_connector_update_edid_property(struct drm_connector * connector,const struct drm_edid * drm_edid)6525 static int _drm_connector_update_edid_property(struct drm_connector *connector,
6526 const struct drm_edid *drm_edid)
6527 {
6528 /* ignore requests to set edid when overridden */
6529 if (connector->override_edid)
6530 return 0;
6531
6532 /*
6533 * Set the display info, using edid if available, otherwise resetting
6534 * the values to defaults. This duplicates the work done in
6535 * drm_add_edid_modes, but that function is not consistently called
6536 * before this one in all drivers and the computation is cheap enough
6537 * that it seems better to duplicate it rather than attempt to ensure
6538 * some arbitrary ordering of calls.
6539 */
6540 if (drm_edid)
6541 update_display_info(connector, drm_edid);
6542 else
6543 drm_reset_display_info(connector);
6544
6545 _drm_update_tile_info(connector, drm_edid);
6546
6547 return _drm_edid_connector_property_update(connector, drm_edid);
6548 }
6549
6550 /**
6551 * drm_connector_update_edid_property - update the edid property of a connector
6552 * @connector: drm connector
6553 * @edid: new value of the edid property
6554 *
6555 * This function creates a new blob modeset object and assigns its id to the
6556 * connector's edid property.
6557 * Since we also parse tile information from EDID's displayID block, we also
6558 * set the connector's tile property here. See drm_connector_set_tile_property()
6559 * for more details.
6560 *
6561 * This function is deprecated. Use drm_edid_connector_update() instead.
6562 *
6563 * Returns:
6564 * Zero on success, negative errno on failure.
6565 */
drm_connector_update_edid_property(struct drm_connector * connector,const struct edid * edid)6566 int drm_connector_update_edid_property(struct drm_connector *connector,
6567 const struct edid *edid)
6568 {
6569 struct drm_edid drm_edid;
6570
6571 return _drm_connector_update_edid_property(connector,
6572 drm_edid_legacy_init(&drm_edid, edid));
6573 }
6574 EXPORT_SYMBOL(drm_connector_update_edid_property);
6575
6576 /**
6577 * drm_add_edid_modes - add modes from EDID data, if available
6578 * @connector: connector we're probing
6579 * @edid: EDID data
6580 *
6581 * Add the specified modes to the connector's mode list. Also fills out the
6582 * &drm_display_info structure and ELD in @connector with any information which
6583 * can be derived from the edid.
6584 *
6585 * This function is deprecated. Use drm_edid_connector_update() instead.
6586 *
6587 * Return: The number of modes added or 0 if we couldn't find any.
6588 */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)6589 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6590 {
6591 struct drm_edid drm_edid;
6592
6593 if (edid && !drm_edid_is_valid(edid)) {
6594 drm_warn(connector->dev, "%s: EDID invalid.\n",
6595 connector->name);
6596 edid = NULL;
6597 }
6598
6599 return _drm_edid_connector_update(connector,
6600 drm_edid_legacy_init(&drm_edid, edid));
6601 }
6602 EXPORT_SYMBOL(drm_add_edid_modes);
6603
6604 /**
6605 * drm_add_modes_noedid - add modes for the connectors without EDID
6606 * @connector: connector we're probing
6607 * @hdisplay: the horizontal display limit
6608 * @vdisplay: the vertical display limit
6609 *
6610 * Add the specified modes to the connector's mode list. Only when the
6611 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6612 *
6613 * Return: The number of modes added or 0 if we couldn't find any.
6614 */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)6615 int drm_add_modes_noedid(struct drm_connector *connector,
6616 int hdisplay, int vdisplay)
6617 {
6618 int i, count, num_modes = 0;
6619 struct drm_display_mode *mode;
6620 struct drm_device *dev = connector->dev;
6621
6622 count = ARRAY_SIZE(drm_dmt_modes);
6623 if (hdisplay < 0)
6624 hdisplay = 0;
6625 if (vdisplay < 0)
6626 vdisplay = 0;
6627
6628 for (i = 0; i < count; i++) {
6629 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6630
6631 if (hdisplay && vdisplay) {
6632 /*
6633 * Only when two are valid, they will be used to check
6634 * whether the mode should be added to the mode list of
6635 * the connector.
6636 */
6637 if (ptr->hdisplay > hdisplay ||
6638 ptr->vdisplay > vdisplay)
6639 continue;
6640 }
6641 if (drm_mode_vrefresh(ptr) > 61)
6642 continue;
6643 mode = drm_mode_duplicate(dev, ptr);
6644 if (mode) {
6645 drm_mode_probed_add(connector, mode);
6646 num_modes++;
6647 }
6648 }
6649 return num_modes;
6650 }
6651 EXPORT_SYMBOL(drm_add_modes_noedid);
6652
6653 /**
6654 * drm_set_preferred_mode - Sets the preferred mode of a connector
6655 * @connector: connector whose mode list should be processed
6656 * @hpref: horizontal resolution of preferred mode
6657 * @vpref: vertical resolution of preferred mode
6658 *
6659 * Marks a mode as preferred if it matches the resolution specified by @hpref
6660 * and @vpref.
6661 */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)6662 void drm_set_preferred_mode(struct drm_connector *connector,
6663 int hpref, int vpref)
6664 {
6665 struct drm_display_mode *mode;
6666
6667 list_for_each_entry(mode, &connector->probed_modes, head) {
6668 if (mode->hdisplay == hpref &&
6669 mode->vdisplay == vpref)
6670 mode->type |= DRM_MODE_TYPE_PREFERRED;
6671 }
6672 }
6673 EXPORT_SYMBOL(drm_set_preferred_mode);
6674
is_hdmi2_sink(const struct drm_connector * connector)6675 static bool is_hdmi2_sink(const struct drm_connector *connector)
6676 {
6677 /*
6678 * FIXME: sil-sii8620 doesn't have a connector around when
6679 * we need one, so we have to be prepared for a NULL connector.
6680 */
6681 if (!connector)
6682 return true;
6683
6684 return connector->display_info.hdmi.scdc.supported ||
6685 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6686 }
6687
drm_mode_hdmi_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)6688 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6689 const struct drm_display_mode *mode)
6690 {
6691 bool has_hdmi_infoframe = connector ?
6692 connector->display_info.has_hdmi_infoframe : false;
6693
6694 if (!has_hdmi_infoframe)
6695 return 0;
6696
6697 /* No HDMI VIC when signalling 3D video format */
6698 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6699 return 0;
6700
6701 return drm_match_hdmi_mode(mode);
6702 }
6703
drm_mode_cea_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)6704 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
6705 const struct drm_display_mode *mode)
6706 {
6707 u8 vic;
6708
6709 /*
6710 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6711 * we should send its VIC in vendor infoframes, else send the
6712 * VIC in AVI infoframes. Lets check if this mode is present in
6713 * HDMI 1.4b 4K modes
6714 */
6715 if (drm_mode_hdmi_vic(connector, mode))
6716 return 0;
6717
6718 vic = drm_match_cea_mode(mode);
6719
6720 /*
6721 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6722 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6723 * have to make sure we dont break HDMI 1.4 sinks.
6724 */
6725 if (!is_hdmi2_sink(connector) && vic > 64)
6726 return 0;
6727
6728 return vic;
6729 }
6730
6731 /**
6732 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6733 * data from a DRM display mode
6734 * @frame: HDMI AVI infoframe
6735 * @connector: the connector
6736 * @mode: DRM display mode
6737 *
6738 * Return: 0 on success or a negative error code on failure.
6739 */
6740 int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)6741 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
6742 const struct drm_connector *connector,
6743 const struct drm_display_mode *mode)
6744 {
6745 enum hdmi_picture_aspect picture_aspect;
6746 u8 vic, hdmi_vic;
6747
6748 if (!frame || !mode)
6749 return -EINVAL;
6750
6751 hdmi_avi_infoframe_init(frame);
6752
6753 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6754 frame->pixel_repeat = 1;
6755
6756 vic = drm_mode_cea_vic(connector, mode);
6757 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
6758
6759 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6760
6761 /*
6762 * As some drivers don't support atomic, we can't use connector state.
6763 * So just initialize the frame with default values, just the same way
6764 * as it's done with other properties here.
6765 */
6766 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6767 frame->itc = 0;
6768
6769 /*
6770 * Populate picture aspect ratio from either
6771 * user input (if specified) or from the CEA/HDMI mode lists.
6772 */
6773 picture_aspect = mode->picture_aspect_ratio;
6774 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6775 if (vic)
6776 picture_aspect = drm_get_cea_aspect_ratio(vic);
6777 else if (hdmi_vic)
6778 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6779 }
6780
6781 /*
6782 * The infoframe can't convey anything but none, 4:3
6783 * and 16:9, so if the user has asked for anything else
6784 * we can only satisfy it by specifying the right VIC.
6785 */
6786 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
6787 if (vic) {
6788 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6789 return -EINVAL;
6790 } else if (hdmi_vic) {
6791 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6792 return -EINVAL;
6793 } else {
6794 return -EINVAL;
6795 }
6796
6797 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6798 }
6799
6800 frame->video_code = vic;
6801 frame->picture_aspect = picture_aspect;
6802 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
6803 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
6804
6805 return 0;
6806 }
6807 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
6808
6809 /**
6810 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6811 * quantization range information
6812 * @frame: HDMI AVI infoframe
6813 * @connector: the connector
6814 * @mode: DRM display mode
6815 * @rgb_quant_range: RGB quantization range (Q)
6816 */
6817 void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)6818 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6819 const struct drm_connector *connector,
6820 const struct drm_display_mode *mode,
6821 enum hdmi_quantization_range rgb_quant_range)
6822 {
6823 const struct drm_display_info *info = &connector->display_info;
6824
6825 /*
6826 * CEA-861:
6827 * "A Source shall not send a non-zero Q value that does not correspond
6828 * to the default RGB Quantization Range for the transmitted Picture
6829 * unless the Sink indicates support for the Q bit in a Video
6830 * Capabilities Data Block."
6831 *
6832 * HDMI 2.0 recommends sending non-zero Q when it does match the
6833 * default RGB quantization range for the mode, even when QS=0.
6834 */
6835 if (info->rgb_quant_range_selectable ||
6836 rgb_quant_range == drm_default_rgb_quant_range(mode))
6837 frame->quantization_range = rgb_quant_range;
6838 else
6839 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
6840
6841 /*
6842 * CEA-861-F:
6843 * "When transmitting any RGB colorimetry, the Source should set the
6844 * YQ-field to match the RGB Quantization Range being transmitted
6845 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6846 * set YQ=1) and the Sink shall ignore the YQ-field."
6847 *
6848 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6849 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6850 * good way to tell which version of CEA-861 the sink supports, so
6851 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6852 * on on CEA-861-F.
6853 */
6854 if (!is_hdmi2_sink(connector) ||
6855 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
6856 frame->ycc_quantization_range =
6857 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6858 else
6859 frame->ycc_quantization_range =
6860 HDMI_YCC_QUANTIZATION_RANGE_FULL;
6861 }
6862 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6863
6864 static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)6865 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6866 {
6867 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6868
6869 switch (layout) {
6870 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6871 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6872 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6873 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6874 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6875 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6876 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6877 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6878 case DRM_MODE_FLAG_3D_L_DEPTH:
6879 return HDMI_3D_STRUCTURE_L_DEPTH;
6880 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6881 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6882 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6883 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6884 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6885 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6886 default:
6887 return HDMI_3D_STRUCTURE_INVALID;
6888 }
6889 }
6890
6891 /**
6892 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6893 * data from a DRM display mode
6894 * @frame: HDMI vendor infoframe
6895 * @connector: the connector
6896 * @mode: DRM display mode
6897 *
6898 * Note that there's is a need to send HDMI vendor infoframes only when using a
6899 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6900 * function will return -EINVAL, error that can be safely ignored.
6901 *
6902 * Return: 0 on success or a negative error code on failure.
6903 */
6904 int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)6905 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6906 const struct drm_connector *connector,
6907 const struct drm_display_mode *mode)
6908 {
6909 /*
6910 * FIXME: sil-sii8620 doesn't have a connector around when
6911 * we need one, so we have to be prepared for a NULL connector.
6912 */
6913 bool has_hdmi_infoframe = connector ?
6914 connector->display_info.has_hdmi_infoframe : false;
6915 int err;
6916
6917 if (!frame || !mode)
6918 return -EINVAL;
6919
6920 if (!has_hdmi_infoframe)
6921 return -EINVAL;
6922
6923 err = hdmi_vendor_infoframe_init(frame);
6924 if (err < 0)
6925 return err;
6926
6927 /*
6928 * Even if it's not absolutely necessary to send the infoframe
6929 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6930 * know that the sink can handle it. This is based on a
6931 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6932 * have trouble realizing that they should switch from 3D to 2D
6933 * mode if the source simply stops sending the infoframe when
6934 * it wants to switch from 3D to 2D.
6935 */
6936 frame->vic = drm_mode_hdmi_vic(connector, mode);
6937 frame->s3d_struct = s3d_structure_from_display_mode(mode);
6938
6939 return 0;
6940 }
6941 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6942
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)6943 static void drm_parse_tiled_block(struct drm_connector *connector,
6944 const struct displayid_block *block)
6945 {
6946 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6947 u16 w, h;
6948 u8 tile_v_loc, tile_h_loc;
6949 u8 num_v_tile, num_h_tile;
6950 struct drm_tile_group *tg;
6951
6952 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6953 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6954
6955 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6956 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6957 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6958 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6959
6960 connector->has_tile = true;
6961 if (tile->tile_cap & 0x80)
6962 connector->tile_is_single_monitor = true;
6963
6964 connector->num_h_tile = num_h_tile + 1;
6965 connector->num_v_tile = num_v_tile + 1;
6966 connector->tile_h_loc = tile_h_loc;
6967 connector->tile_v_loc = tile_v_loc;
6968 connector->tile_h_size = w + 1;
6969 connector->tile_v_size = h + 1;
6970
6971 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6972 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6973 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6974 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6975 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6976
6977 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6978 if (!tg)
6979 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6980 if (!tg)
6981 return;
6982
6983 if (connector->tile_group != tg) {
6984 /* if we haven't got a pointer,
6985 take the reference, drop ref to old tile group */
6986 if (connector->tile_group)
6987 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6988 connector->tile_group = tg;
6989 } else {
6990 /* if same tile group, then release the ref we just took. */
6991 drm_mode_put_tile_group(connector->dev, tg);
6992 }
6993 }
6994
_drm_update_tile_info(struct drm_connector * connector,const struct drm_edid * drm_edid)6995 static void _drm_update_tile_info(struct drm_connector *connector,
6996 const struct drm_edid *drm_edid)
6997 {
6998 const struct displayid_block *block;
6999 struct displayid_iter iter;
7000
7001 connector->has_tile = false;
7002
7003 displayid_iter_edid_begin(drm_edid, &iter);
7004 displayid_iter_for_each(block, &iter) {
7005 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
7006 drm_parse_tiled_block(connector, block);
7007 }
7008 displayid_iter_end(&iter);
7009
7010 if (!connector->has_tile && connector->tile_group) {
7011 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7012 connector->tile_group = NULL;
7013 }
7014 }
7015