1 /*
2  * Copyright © 2009 Keith Packard
3  *
4  * Permission to use, copy, modify, distribute, and sell this software and its
5  * documentation for any purpose is hereby granted without fee, provided that
6  * the above copyright notice appear in all copies and that both that copyright
7  * notice and this permission notice appear in supporting documentation, and
8  * that the name of the copyright holders not be used in advertising or
9  * publicity pertaining to distribution of the software without specific,
10  * written prior permission.  The copyright holders make no representations
11  * about the suitability of this software for any purpose.  It is provided "as
12  * is" without express or implied warranty.
13  *
14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20  * OF THIS SOFTWARE.
21  */
22 
23 #include <linux/backlight.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/sched.h>
31 #include <linux/seq_file.h>
32 #include <linux/string_helpers.h>
33 #include <linux/dynamic_debug.h>
34 
35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/display/drm_dp_mst_helper.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_print.h>
39 #include <drm/drm_vblank.h>
40 #include <drm/drm_panel.h>
41 
42 #include "drm_dp_helper_internal.h"
43 
44 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
45 			"DRM_UT_CORE",
46 			"DRM_UT_DRIVER",
47 			"DRM_UT_KMS",
48 			"DRM_UT_PRIME",
49 			"DRM_UT_ATOMIC",
50 			"DRM_UT_VBL",
51 			"DRM_UT_STATE",
52 			"DRM_UT_LEASE",
53 			"DRM_UT_DP",
54 			"DRM_UT_DRMRES");
55 
56 struct dp_aux_backlight {
57 	struct backlight_device *base;
58 	struct drm_dp_aux *aux;
59 	struct drm_edp_backlight_info info;
60 	bool enabled;
61 };
62 
63 /**
64  * DOC: dp helpers
65  *
66  * These functions contain some common logic and helpers at various abstraction
67  * levels to deal with Display Port sink devices and related things like DP aux
68  * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
69  * blocks, ...
70  */
71 
72 /* Helpers for DP link training */
dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE],int r)73 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
74 {
75 	return link_status[r - DP_LANE0_1_STATUS];
76 }
77 
dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)78 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
79 			     int lane)
80 {
81 	int i = DP_LANE0_1_STATUS + (lane >> 1);
82 	int s = (lane & 1) * 4;
83 	u8 l = dp_link_status(link_status, i);
84 
85 	return (l >> s) & 0xf;
86 }
87 
drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)88 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
89 			  int lane_count)
90 {
91 	u8 lane_align;
92 	u8 lane_status;
93 	int lane;
94 
95 	lane_align = dp_link_status(link_status,
96 				    DP_LANE_ALIGN_STATUS_UPDATED);
97 	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
98 		return false;
99 	for (lane = 0; lane < lane_count; lane++) {
100 		lane_status = dp_get_lane_status(link_status, lane);
101 		if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
102 			return false;
103 	}
104 	return true;
105 }
106 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
107 
drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)108 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
109 			      int lane_count)
110 {
111 	int lane;
112 	u8 lane_status;
113 
114 	for (lane = 0; lane < lane_count; lane++) {
115 		lane_status = dp_get_lane_status(link_status, lane);
116 		if ((lane_status & DP_LANE_CR_DONE) == 0)
117 			return false;
118 	}
119 	return true;
120 }
121 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
122 
drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)123 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
124 				     int lane)
125 {
126 	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
127 	int s = ((lane & 1) ?
128 		 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
129 		 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
130 	u8 l = dp_link_status(link_status, i);
131 
132 	return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
133 }
134 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
135 
drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)136 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
137 					  int lane)
138 {
139 	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
140 	int s = ((lane & 1) ?
141 		 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
142 		 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
143 	u8 l = dp_link_status(link_status, i);
144 
145 	return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
146 }
147 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
148 
149 /* DP 2.0 128b/132b */
drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)150 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
151 				   int lane)
152 {
153 	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
154 	int s = ((lane & 1) ?
155 		 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
156 		 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
157 	u8 l = dp_link_status(link_status, i);
158 
159 	return (l >> s) & 0xf;
160 }
161 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
162 
163 /* DP 2.0 errata for 128b/132b */
drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)164 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
165 					  int lane_count)
166 {
167 	u8 lane_align, lane_status;
168 	int lane;
169 
170 	lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
171 	if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
172 		return false;
173 
174 	for (lane = 0; lane < lane_count; lane++) {
175 		lane_status = dp_get_lane_status(link_status, lane);
176 		if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE))
177 			return false;
178 	}
179 	return true;
180 }
181 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done);
182 
183 /* DP 2.0 errata for 128b/132b */
drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)184 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
185 					int lane_count)
186 {
187 	u8 lane_status;
188 	int lane;
189 
190 	for (lane = 0; lane < lane_count; lane++) {
191 		lane_status = dp_get_lane_status(link_status, lane);
192 		if (!(lane_status & DP_LANE_SYMBOL_LOCKED))
193 			return false;
194 	}
195 	return true;
196 }
197 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked);
198 
199 /* DP 2.0 errata for 128b/132b */
drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])200 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
201 {
202 	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
203 
204 	return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE;
205 }
206 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done);
207 
208 /* DP 2.0 errata for 128b/132b */
drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])209 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
210 {
211 	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
212 
213 	return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE;
214 }
215 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done);
216 
217 /* DP 2.0 errata for 128b/132b */
drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])218 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])
219 {
220 	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
221 
222 	return status & DP_128B132B_LT_FAILED;
223 }
224 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed);
225 
__8b10b_clock_recovery_delay_us(const struct drm_dp_aux * aux,u8 rd_interval)226 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
227 {
228 	if (rd_interval > 4)
229 		drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
230 			    aux->name, rd_interval);
231 
232 	if (rd_interval == 0)
233 		return 100;
234 
235 	return rd_interval * 4 * USEC_PER_MSEC;
236 }
237 
__8b10b_channel_eq_delay_us(const struct drm_dp_aux * aux,u8 rd_interval)238 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
239 {
240 	if (rd_interval > 4)
241 		drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
242 			    aux->name, rd_interval);
243 
244 	if (rd_interval == 0)
245 		return 400;
246 
247 	return rd_interval * 4 * USEC_PER_MSEC;
248 }
249 
__128b132b_channel_eq_delay_us(const struct drm_dp_aux * aux,u8 rd_interval)250 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
251 {
252 	switch (rd_interval) {
253 	default:
254 		drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n",
255 			    aux->name, rd_interval);
256 		fallthrough;
257 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US:
258 		return 400;
259 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS:
260 		return 4000;
261 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS:
262 		return 8000;
263 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS:
264 		return 12000;
265 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS:
266 		return 16000;
267 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS:
268 		return 32000;
269 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS:
270 		return 64000;
271 	}
272 }
273 
274 /*
275  * The link training delays are different for:
276  *
277  *  - Clock recovery vs. channel equalization
278  *  - DPRX vs. LTTPR
279  *  - 128b/132b vs. 8b/10b
280  *  - DPCD rev 1.3 vs. later
281  *
282  * Get the correct delay in us, reading DPCD if necessary.
283  */
__read_delay(struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE],enum drm_dp_phy dp_phy,bool uhbr,bool cr)284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
285 			enum drm_dp_phy dp_phy, bool uhbr, bool cr)
286 {
287 	int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);
288 	unsigned int offset;
289 	u8 rd_interval, mask;
290 
291 	if (dp_phy == DP_PHY_DPRX) {
292 		if (uhbr) {
293 			if (cr)
294 				return 100;
295 
296 			offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL;
297 			mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
298 			parse = __128b132b_channel_eq_delay_us;
299 		} else {
300 			if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
301 				return 100;
302 
303 			offset = DP_TRAINING_AUX_RD_INTERVAL;
304 			mask = DP_TRAINING_AUX_RD_MASK;
305 			if (cr)
306 				parse = __8b10b_clock_recovery_delay_us;
307 			else
308 				parse = __8b10b_channel_eq_delay_us;
309 		}
310 	} else {
311 		if (uhbr) {
312 			offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
313 			mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
314 			parse = __128b132b_channel_eq_delay_us;
315 		} else {
316 			if (cr)
317 				return 100;
318 
319 			offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
320 			mask = DP_TRAINING_AUX_RD_MASK;
321 			parse = __8b10b_channel_eq_delay_us;
322 		}
323 	}
324 
325 	if (offset < DP_RECEIVER_CAP_SIZE) {
326 		rd_interval = dpcd[offset];
327 	} else {
328 		if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) {
329 			drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n",
330 				    aux->name);
331 			/* arbitrary default delay */
332 			return 400;
333 		}
334 	}
335 
336 	return parse(aux, rd_interval & mask);
337 }
338 
drm_dp_read_clock_recovery_delay(struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE],enum drm_dp_phy dp_phy,bool uhbr)339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
340 				     enum drm_dp_phy dp_phy, bool uhbr)
341 {
342 	return __read_delay(aux, dpcd, dp_phy, uhbr, true);
343 }
344 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay);
345 
drm_dp_read_channel_eq_delay(struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE],enum drm_dp_phy dp_phy,bool uhbr)346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
347 				 enum drm_dp_phy dp_phy, bool uhbr)
348 {
349 	return __read_delay(aux, dpcd, dp_phy, uhbr, false);
350 }
351 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
352 
353 /* Per DP 2.0 Errata */
drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux * aux)354 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
355 {
356 	int unit;
357 	u8 val;
358 
359 	if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) {
360 		drm_err(aux->drm_dev, "%s: failed rd interval read\n",
361 			aux->name);
362 		/* default to max */
363 		val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
364 	}
365 
366 	unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
367 	val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
368 
369 	return (val + 1) * unit * 1000;
370 }
371 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
372 
drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE])373 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
374 					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])
375 {
376 	u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
377 		DP_TRAINING_AUX_RD_MASK;
378 	int delay_us;
379 
380 	if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
381 		delay_us = 100;
382 	else
383 		delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
384 
385 	usleep_range(delay_us, delay_us * 2);
386 }
387 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
388 
__drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux * aux,u8 rd_interval)389 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
390 						 u8 rd_interval)
391 {
392 	int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
393 
394 	usleep_range(delay_us, delay_us * 2);
395 }
396 
drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE])397 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
398 					const u8 dpcd[DP_RECEIVER_CAP_SIZE])
399 {
400 	__drm_dp_link_train_channel_eq_delay(aux,
401 					     dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
402 					     DP_TRAINING_AUX_RD_MASK);
403 }
404 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
405 
406 /**
407  * drm_dp_phy_name() - Get the name of the given DP PHY
408  * @dp_phy: The DP PHY identifier
409  *
410  * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
411  * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always
412  * non-NULL and valid.
413  *
414  * Returns: Name of the DP PHY.
415  */
drm_dp_phy_name(enum drm_dp_phy dp_phy)416 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
417 {
418 	static const char * const phy_names[] = {
419 		[DP_PHY_DPRX] = "DPRX",
420 		[DP_PHY_LTTPR1] = "LTTPR 1",
421 		[DP_PHY_LTTPR2] = "LTTPR 2",
422 		[DP_PHY_LTTPR3] = "LTTPR 3",
423 		[DP_PHY_LTTPR4] = "LTTPR 4",
424 		[DP_PHY_LTTPR5] = "LTTPR 5",
425 		[DP_PHY_LTTPR6] = "LTTPR 6",
426 		[DP_PHY_LTTPR7] = "LTTPR 7",
427 		[DP_PHY_LTTPR8] = "LTTPR 8",
428 	};
429 
430 	if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) ||
431 	    WARN_ON(!phy_names[dp_phy]))
432 		return "<INVALID DP PHY>";
433 
434 	return phy_names[dp_phy];
435 }
436 EXPORT_SYMBOL(drm_dp_phy_name);
437 
drm_dp_lttpr_link_train_clock_recovery_delay(void)438 void drm_dp_lttpr_link_train_clock_recovery_delay(void)
439 {
440 	usleep_range(100, 200);
441 }
442 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
443 
dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE],int r)444 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
445 {
446 	return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
447 }
448 
drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux * aux,const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])449 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
450 					      const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
451 {
452 	u8 interval = dp_lttpr_phy_cap(phy_cap,
453 				       DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
454 		      DP_TRAINING_AUX_RD_MASK;
455 
456 	__drm_dp_link_train_channel_eq_delay(aux, interval);
457 }
458 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
459 
drm_dp_link_rate_to_bw_code(int link_rate)460 u8 drm_dp_link_rate_to_bw_code(int link_rate)
461 {
462 	switch (link_rate) {
463 	case 1000000:
464 		return DP_LINK_BW_10;
465 	case 1350000:
466 		return DP_LINK_BW_13_5;
467 	case 2000000:
468 		return DP_LINK_BW_20;
469 	default:
470 		/* Spec says link_bw = link_rate / 0.27Gbps */
471 		return link_rate / 27000;
472 	}
473 }
474 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
475 
drm_dp_bw_code_to_link_rate(u8 link_bw)476 int drm_dp_bw_code_to_link_rate(u8 link_bw)
477 {
478 	switch (link_bw) {
479 	case DP_LINK_BW_10:
480 		return 1000000;
481 	case DP_LINK_BW_13_5:
482 		return 1350000;
483 	case DP_LINK_BW_20:
484 		return 2000000;
485 	default:
486 		/* Spec says link_rate = link_bw * 0.27Gbps */
487 		return link_bw * 27000;
488 	}
489 }
490 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
491 
492 #define AUX_RETRY_INTERVAL 500 /* us */
493 
494 static inline void
drm_dp_dump_access(const struct drm_dp_aux * aux,u8 request,uint offset,void * buffer,int ret)495 drm_dp_dump_access(const struct drm_dp_aux *aux,
496 		   u8 request, uint offset, void *buffer, int ret)
497 {
498 	const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
499 
500 	if (ret > 0)
501 		drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
502 			   aux->name, offset, arrow, ret, min(ret, 20), buffer);
503 	else
504 		drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
505 			   aux->name, offset, arrow, ret);
506 }
507 
508 /**
509  * DOC: dp helpers
510  *
511  * The DisplayPort AUX channel is an abstraction to allow generic, driver-
512  * independent access to AUX functionality. Drivers can take advantage of
513  * this by filling in the fields of the drm_dp_aux structure.
514  *
515  * Transactions are described using a hardware-independent drm_dp_aux_msg
516  * structure, which is passed into a driver's .transfer() implementation.
517  * Both native and I2C-over-AUX transactions are supported.
518  */
519 
drm_dp_dpcd_access(struct drm_dp_aux * aux,u8 request,unsigned int offset,void * buffer,size_t size)520 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
521 			      unsigned int offset, void *buffer, size_t size)
522 {
523 	struct drm_dp_aux_msg msg;
524 	unsigned int retry, native_reply;
525 	int err = 0, ret = 0;
526 
527 	memset(&msg, 0, sizeof(msg));
528 	msg.address = offset;
529 	msg.request = request;
530 	msg.buffer = buffer;
531 	msg.size = size;
532 
533 	mutex_lock(&aux->hw_mutex);
534 
535 	/*
536 	 * The specification doesn't give any recommendation on how often to
537 	 * retry native transactions. We used to retry 7 times like for
538 	 * aux i2c transactions but real world devices this wasn't
539 	 * sufficient, bump to 32 which makes Dell 4k monitors happier.
540 	 */
541 	for (retry = 0; retry < 32; retry++) {
542 		if (ret != 0 && ret != -ETIMEDOUT) {
543 			usleep_range(AUX_RETRY_INTERVAL,
544 				     AUX_RETRY_INTERVAL + 100);
545 		}
546 
547 		ret = aux->transfer(aux, &msg);
548 		if (ret >= 0) {
549 			native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
550 			if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
551 				if (ret == size)
552 					goto unlock;
553 
554 				ret = -EPROTO;
555 			} else
556 				ret = -EIO;
557 		}
558 
559 		/*
560 		 * We want the error we return to be the error we received on
561 		 * the first transaction, since we may get a different error the
562 		 * next time we retry
563 		 */
564 		if (!err)
565 			err = ret;
566 	}
567 
568 	drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
569 		    aux->name, err);
570 	ret = err;
571 
572 unlock:
573 	mutex_unlock(&aux->hw_mutex);
574 	return ret;
575 }
576 
577 /**
578  * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
579  * @aux: DisplayPort AUX channel (SST)
580  * @offset: address of the register to probe
581  *
582  * Probe the provided DPCD address by reading 1 byte from it. The function can
583  * be used to trigger some side-effect the read access has, like waking up the
584  * sink, without the need for the read-out value.
585  *
586  * Returns 0 if the read access suceeded, or a negative error code on failure.
587  */
drm_dp_dpcd_probe(struct drm_dp_aux * aux,unsigned int offset)588 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset)
589 {
590 	u8 buffer;
591 	int ret;
592 
593 	ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1);
594 	WARN_ON(ret == 0);
595 
596 	drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret);
597 
598 	return ret < 0 ? ret : 0;
599 }
600 EXPORT_SYMBOL(drm_dp_dpcd_probe);
601 
602 /**
603  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
604  * @aux: DisplayPort AUX channel (SST or MST)
605  * @offset: address of the (first) register to read
606  * @buffer: buffer to store the register values
607  * @size: number of bytes in @buffer
608  *
609  * Returns the number of bytes transferred on success, or a negative error
610  * code on failure. -EIO is returned if the request was NAKed by the sink or
611  * if the retry count was exceeded. If not all bytes were transferred, this
612  * function returns -EPROTO. Errors from the underlying AUX channel transfer
613  * function, with the exception of -EBUSY (which causes the transaction to
614  * be retried), are propagated to the caller.
615  */
drm_dp_dpcd_read(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)616 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
617 			 void *buffer, size_t size)
618 {
619 	int ret;
620 
621 	/*
622 	 * HP ZR24w corrupts the first DPCD access after entering power save
623 	 * mode. Eg. on a read, the entire buffer will be filled with the same
624 	 * byte. Do a throw away read to avoid corrupting anything we care
625 	 * about. Afterwards things will work correctly until the monitor
626 	 * gets woken up and subsequently re-enters power save mode.
627 	 *
628 	 * The user pressing any button on the monitor is enough to wake it
629 	 * up, so there is no particularly good place to do the workaround.
630 	 * We just have to do it before any DPCD access and hope that the
631 	 * monitor doesn't power down exactly after the throw away read.
632 	 */
633 	if (!aux->is_remote) {
634 		ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV);
635 		if (ret < 0)
636 			return ret;
637 	}
638 
639 	if (aux->is_remote)
640 		ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
641 	else
642 		ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
643 					 buffer, size);
644 
645 	drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
646 	return ret;
647 }
648 EXPORT_SYMBOL(drm_dp_dpcd_read);
649 
650 /**
651  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
652  * @aux: DisplayPort AUX channel (SST or MST)
653  * @offset: address of the (first) register to write
654  * @buffer: buffer containing the values to write
655  * @size: number of bytes in @buffer
656  *
657  * Returns the number of bytes transferred on success, or a negative error
658  * code on failure. -EIO is returned if the request was NAKed by the sink or
659  * if the retry count was exceeded. If not all bytes were transferred, this
660  * function returns -EPROTO. Errors from the underlying AUX channel transfer
661  * function, with the exception of -EBUSY (which causes the transaction to
662  * be retried), are propagated to the caller.
663  */
drm_dp_dpcd_write(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)664 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
665 			  void *buffer, size_t size)
666 {
667 	int ret;
668 
669 	if (aux->is_remote)
670 		ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
671 	else
672 		ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
673 					 buffer, size);
674 
675 	drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
676 	return ret;
677 }
678 EXPORT_SYMBOL(drm_dp_dpcd_write);
679 
680 /**
681  * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
682  * @aux: DisplayPort AUX channel
683  * @status: buffer to store the link status in (must be at least 6 bytes)
684  *
685  * Returns the number of bytes transferred on success or a negative error
686  * code on failure.
687  */
drm_dp_dpcd_read_link_status(struct drm_dp_aux * aux,u8 status[DP_LINK_STATUS_SIZE])688 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
689 				 u8 status[DP_LINK_STATUS_SIZE])
690 {
691 	return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
692 				DP_LINK_STATUS_SIZE);
693 }
694 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
695 
696 /**
697  * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
698  * @aux: DisplayPort AUX channel
699  * @dp_phy: the DP PHY to get the link status for
700  * @link_status: buffer to return the status in
701  *
702  * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
703  * layout of the returned @link_status matches the DPCD register layout of the
704  * DPRX PHY link status.
705  *
706  * Returns 0 if the information was read successfully or a negative error code
707  * on failure.
708  */
drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux * aux,enum drm_dp_phy dp_phy,u8 link_status[DP_LINK_STATUS_SIZE])709 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
710 				     enum drm_dp_phy dp_phy,
711 				     u8 link_status[DP_LINK_STATUS_SIZE])
712 {
713 	int ret;
714 
715 	if (dp_phy == DP_PHY_DPRX) {
716 		ret = drm_dp_dpcd_read(aux,
717 				       DP_LANE0_1_STATUS,
718 				       link_status,
719 				       DP_LINK_STATUS_SIZE);
720 
721 		if (ret < 0)
722 			return ret;
723 
724 		WARN_ON(ret != DP_LINK_STATUS_SIZE);
725 
726 		return 0;
727 	}
728 
729 	ret = drm_dp_dpcd_read(aux,
730 			       DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
731 			       link_status,
732 			       DP_LINK_STATUS_SIZE - 1);
733 
734 	if (ret < 0)
735 		return ret;
736 
737 	WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
738 
739 	/* Convert the LTTPR to the sink PHY link status layout */
740 	memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
741 		&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
742 		DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
743 	link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
744 
745 	return 0;
746 }
747 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
748 
is_edid_digital_input_dp(const struct edid * edid)749 static bool is_edid_digital_input_dp(const struct edid *edid)
750 {
751 	return edid && edid->revision >= 4 &&
752 		edid->input & DRM_EDID_INPUT_DIGITAL &&
753 		(edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
754 }
755 
756 /**
757  * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
758  * @dpcd: DisplayPort configuration data
759  * @port_cap: port capabilities
760  * @type: port type to be checked. Can be:
761  * 	  %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
762  * 	  %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
763  *	  %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
764  *
765  * Caveat: Only works with DPCD 1.1+ port caps.
766  *
767  * Returns: whether the downstream facing port matches the type.
768  */
drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],u8 type)769 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
770 			       const u8 port_cap[4], u8 type)
771 {
772 	return drm_dp_is_branch(dpcd) &&
773 		dpcd[DP_DPCD_REV] >= 0x11 &&
774 		(port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
775 }
776 EXPORT_SYMBOL(drm_dp_downstream_is_type);
777 
778 /**
779  * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
780  * @dpcd: DisplayPort configuration data
781  * @port_cap: port capabilities
782  * @edid: EDID
783  *
784  * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
785  */
drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],const struct edid * edid)786 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
787 			       const u8 port_cap[4],
788 			       const struct edid *edid)
789 {
790 	if (dpcd[DP_DPCD_REV] < 0x11) {
791 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
792 		case DP_DWN_STRM_PORT_TYPE_TMDS:
793 			return true;
794 		default:
795 			return false;
796 		}
797 	}
798 
799 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
800 	case DP_DS_PORT_TYPE_DP_DUALMODE:
801 		if (is_edid_digital_input_dp(edid))
802 			return false;
803 		fallthrough;
804 	case DP_DS_PORT_TYPE_DVI:
805 	case DP_DS_PORT_TYPE_HDMI:
806 		return true;
807 	default:
808 		return false;
809 	}
810 }
811 EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
812 
813 /**
814  * drm_dp_send_real_edid_checksum() - send back real edid checksum value
815  * @aux: DisplayPort AUX channel
816  * @real_edid_checksum: real edid checksum for the last block
817  *
818  * Returns:
819  * True on success
820  */
drm_dp_send_real_edid_checksum(struct drm_dp_aux * aux,u8 real_edid_checksum)821 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
822 				    u8 real_edid_checksum)
823 {
824 	u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
825 
826 	if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
827 			     &auto_test_req, 1) < 1) {
828 		drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
829 			aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
830 		return false;
831 	}
832 	auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
833 
834 	if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
835 		drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
836 			aux->name, DP_TEST_REQUEST);
837 		return false;
838 	}
839 	link_edid_read &= DP_TEST_LINK_EDID_READ;
840 
841 	if (!auto_test_req || !link_edid_read) {
842 		drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
843 			    aux->name);
844 		return false;
845 	}
846 
847 	if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
848 			      &auto_test_req, 1) < 1) {
849 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
850 			aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
851 		return false;
852 	}
853 
854 	/* send back checksum for the last edid extension block data */
855 	if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
856 			      &real_edid_checksum, 1) < 1) {
857 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
858 			aux->name, DP_TEST_EDID_CHECKSUM);
859 		return false;
860 	}
861 
862 	test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
863 	if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
864 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
865 			aux->name, DP_TEST_RESPONSE);
866 		return false;
867 	}
868 
869 	return true;
870 }
871 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
872 
drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])873 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
874 {
875 	u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
876 
877 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
878 		port_count = 4;
879 
880 	return port_count;
881 }
882 
drm_dp_read_extended_dpcd_caps(struct drm_dp_aux * aux,u8 dpcd[DP_RECEIVER_CAP_SIZE])883 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
884 					  u8 dpcd[DP_RECEIVER_CAP_SIZE])
885 {
886 	u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
887 	int ret;
888 
889 	/*
890 	 * Prior to DP1.3 the bit represented by
891 	 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
892 	 * If it is set DP_DPCD_REV at 0000h could be at a value less than
893 	 * the true capability of the panel. The only way to check is to
894 	 * then compare 0000h and 2200h.
895 	 */
896 	if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
897 	      DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
898 		return 0;
899 
900 	ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
901 			       sizeof(dpcd_ext));
902 	if (ret < 0)
903 		return ret;
904 	if (ret != sizeof(dpcd_ext))
905 		return -EIO;
906 
907 	if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
908 		drm_dbg_kms(aux->drm_dev,
909 			    "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
910 			    aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
911 		return 0;
912 	}
913 
914 	if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
915 		return 0;
916 
917 	drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
918 
919 	memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
920 
921 	return 0;
922 }
923 
924 /**
925  * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
926  * available
927  * @aux: DisplayPort AUX channel
928  * @dpcd: Buffer to store the resulting DPCD in
929  *
930  * Attempts to read the base DPCD caps for @aux. Additionally, this function
931  * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
932  * present.
933  *
934  * Returns: %0 if the DPCD was read successfully, negative error code
935  * otherwise.
936  */
drm_dp_read_dpcd_caps(struct drm_dp_aux * aux,u8 dpcd[DP_RECEIVER_CAP_SIZE])937 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
938 			  u8 dpcd[DP_RECEIVER_CAP_SIZE])
939 {
940 	int ret;
941 
942 	ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
943 	if (ret < 0)
944 		return ret;
945 	if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
946 		return -EIO;
947 
948 	ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
949 	if (ret < 0)
950 		return ret;
951 
952 	drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
953 
954 	return ret;
955 }
956 EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
957 
958 /**
959  * drm_dp_read_downstream_info() - read DPCD downstream port info if available
960  * @aux: DisplayPort AUX channel
961  * @dpcd: A cached copy of the port's DPCD
962  * @downstream_ports: buffer to store the downstream port info in
963  *
964  * See also:
965  * drm_dp_downstream_max_clock()
966  * drm_dp_downstream_max_bpc()
967  *
968  * Returns: 0 if either the downstream port info was read successfully or
969  * there was no downstream info to read, or a negative error code otherwise.
970  */
drm_dp_read_downstream_info(struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE],u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])971 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
972 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
973 				u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
974 {
975 	int ret;
976 	u8 len;
977 
978 	memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
979 
980 	/* No downstream info to read */
981 	if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
982 		return 0;
983 
984 	/* Some branches advertise having 0 downstream ports, despite also advertising they have a
985 	 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since
986 	 * some branches do it we need to handle it regardless.
987 	 */
988 	len = drm_dp_downstream_port_count(dpcd);
989 	if (!len)
990 		return 0;
991 
992 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
993 		len *= 4;
994 
995 	ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
996 	if (ret < 0)
997 		return ret;
998 	if (ret != len)
999 		return -EIO;
1000 
1001 	drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
1002 
1003 	return 0;
1004 }
1005 EXPORT_SYMBOL(drm_dp_read_downstream_info);
1006 
1007 /**
1008  * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1009  * @dpcd: DisplayPort configuration data
1010  * @port_cap: port capabilities
1011  *
1012  * Returns: Downstream facing port max dot clock in kHz on success,
1013  * or 0 if max clock not defined
1014  */
drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])1015 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1016 				   const u8 port_cap[4])
1017 {
1018 	if (!drm_dp_is_branch(dpcd))
1019 		return 0;
1020 
1021 	if (dpcd[DP_DPCD_REV] < 0x11)
1022 		return 0;
1023 
1024 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1025 	case DP_DS_PORT_TYPE_VGA:
1026 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1027 			return 0;
1028 		return port_cap[1] * 8000;
1029 	default:
1030 		return 0;
1031 	}
1032 }
1033 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
1034 
1035 /**
1036  * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1037  * @dpcd: DisplayPort configuration data
1038  * @port_cap: port capabilities
1039  * @edid: EDID
1040  *
1041  * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
1042  * or 0 if max TMDS clock not defined
1043  */
drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],const struct edid * edid)1044 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1045 				     const u8 port_cap[4],
1046 				     const struct edid *edid)
1047 {
1048 	if (!drm_dp_is_branch(dpcd))
1049 		return 0;
1050 
1051 	if (dpcd[DP_DPCD_REV] < 0x11) {
1052 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1053 		case DP_DWN_STRM_PORT_TYPE_TMDS:
1054 			return 165000;
1055 		default:
1056 			return 0;
1057 		}
1058 	}
1059 
1060 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1061 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1062 		if (is_edid_digital_input_dp(edid))
1063 			return 0;
1064 		/*
1065 		 * It's left up to the driver to check the
1066 		 * DP dual mode adapter's max TMDS clock.
1067 		 *
1068 		 * Unfortunately it looks like branch devices
1069 		 * may not fordward that the DP dual mode i2c
1070 		 * access so we just usually get i2c nak :(
1071 		 */
1072 		fallthrough;
1073 	case DP_DS_PORT_TYPE_HDMI:
1074 		 /*
1075 		  * We should perhaps assume 165 MHz when detailed cap
1076 		  * info is not available. But looks like many typical
1077 		  * branch devices fall into that category and so we'd
1078 		  * probably end up with users complaining that they can't
1079 		  * get high resolution modes with their favorite dongle.
1080 		  *
1081 		  * So let's limit to 300 MHz instead since DPCD 1.4
1082 		  * HDMI 2.0 DFPs are required to have the detailed cap
1083 		  * info. So it's more likely we're dealing with a HDMI 1.4
1084 		  * compatible* device here.
1085 		  */
1086 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1087 			return 300000;
1088 		return port_cap[1] * 2500;
1089 	case DP_DS_PORT_TYPE_DVI:
1090 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1091 			return 165000;
1092 		/* FIXME what to do about DVI dual link? */
1093 		return port_cap[1] * 2500;
1094 	default:
1095 		return 0;
1096 	}
1097 }
1098 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
1099 
1100 /**
1101  * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1102  * @dpcd: DisplayPort configuration data
1103  * @port_cap: port capabilities
1104  * @edid: EDID
1105  *
1106  * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
1107  * or 0 if max TMDS clock not defined
1108  */
drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],const struct edid * edid)1109 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1110 				     const u8 port_cap[4],
1111 				     const struct edid *edid)
1112 {
1113 	if (!drm_dp_is_branch(dpcd))
1114 		return 0;
1115 
1116 	if (dpcd[DP_DPCD_REV] < 0x11) {
1117 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1118 		case DP_DWN_STRM_PORT_TYPE_TMDS:
1119 			return 25000;
1120 		default:
1121 			return 0;
1122 		}
1123 	}
1124 
1125 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1126 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1127 		if (is_edid_digital_input_dp(edid))
1128 			return 0;
1129 		fallthrough;
1130 	case DP_DS_PORT_TYPE_DVI:
1131 	case DP_DS_PORT_TYPE_HDMI:
1132 		/*
1133 		 * Unclear whether the protocol converter could
1134 		 * utilize pixel replication. Assume it won't.
1135 		 */
1136 		return 25000;
1137 	default:
1138 		return 0;
1139 	}
1140 }
1141 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
1142 
1143 /**
1144  * drm_dp_downstream_max_bpc() - extract downstream facing port max
1145  *                               bits per component
1146  * @dpcd: DisplayPort configuration data
1147  * @port_cap: downstream facing port capabilities
1148  * @edid: EDID
1149  *
1150  * Returns: Max bpc on success or 0 if max bpc not defined
1151  */
drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],const struct edid * edid)1152 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1153 			      const u8 port_cap[4],
1154 			      const struct edid *edid)
1155 {
1156 	if (!drm_dp_is_branch(dpcd))
1157 		return 0;
1158 
1159 	if (dpcd[DP_DPCD_REV] < 0x11) {
1160 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1161 		case DP_DWN_STRM_PORT_TYPE_DP:
1162 			return 0;
1163 		default:
1164 			return 8;
1165 		}
1166 	}
1167 
1168 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1169 	case DP_DS_PORT_TYPE_DP:
1170 		return 0;
1171 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1172 		if (is_edid_digital_input_dp(edid))
1173 			return 0;
1174 		fallthrough;
1175 	case DP_DS_PORT_TYPE_HDMI:
1176 	case DP_DS_PORT_TYPE_DVI:
1177 	case DP_DS_PORT_TYPE_VGA:
1178 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1179 			return 8;
1180 
1181 		switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
1182 		case DP_DS_8BPC:
1183 			return 8;
1184 		case DP_DS_10BPC:
1185 			return 10;
1186 		case DP_DS_12BPC:
1187 			return 12;
1188 		case DP_DS_16BPC:
1189 			return 16;
1190 		default:
1191 			return 8;
1192 		}
1193 		break;
1194 	default:
1195 		return 8;
1196 	}
1197 }
1198 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
1199 
1200 /**
1201  * drm_dp_downstream_420_passthrough() - determine downstream facing port
1202  *                                       YCbCr 4:2:0 pass-through capability
1203  * @dpcd: DisplayPort configuration data
1204  * @port_cap: downstream facing port capabilities
1205  *
1206  * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
1207  */
drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])1208 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1209 				       const u8 port_cap[4])
1210 {
1211 	if (!drm_dp_is_branch(dpcd))
1212 		return false;
1213 
1214 	if (dpcd[DP_DPCD_REV] < 0x13)
1215 		return false;
1216 
1217 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1218 	case DP_DS_PORT_TYPE_DP:
1219 		return true;
1220 	case DP_DS_PORT_TYPE_HDMI:
1221 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1222 			return false;
1223 
1224 		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
1225 	default:
1226 		return false;
1227 	}
1228 }
1229 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
1230 
1231 /**
1232  * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1233  *                                             YCbCr 4:4:4->4:2:0 conversion capability
1234  * @dpcd: DisplayPort configuration data
1235  * @port_cap: downstream facing port capabilities
1236  *
1237  * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
1238  */
drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])1239 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1240 					     const u8 port_cap[4])
1241 {
1242 	if (!drm_dp_is_branch(dpcd))
1243 		return false;
1244 
1245 	if (dpcd[DP_DPCD_REV] < 0x13)
1246 		return false;
1247 
1248 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1249 	case DP_DS_PORT_TYPE_HDMI:
1250 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1251 			return false;
1252 
1253 		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
1254 	default:
1255 		return false;
1256 	}
1257 }
1258 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
1259 
1260 /**
1261  * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1262  *                                               RGB->YCbCr conversion capability
1263  * @dpcd: DisplayPort configuration data
1264  * @port_cap: downstream facing port capabilities
1265  * @color_spc: Colorspace for which conversion cap is sought
1266  *
1267  * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1268  * colorspace.
1269  */
drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],u8 color_spc)1270 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1271 					       const u8 port_cap[4],
1272 					       u8 color_spc)
1273 {
1274 	if (!drm_dp_is_branch(dpcd))
1275 		return false;
1276 
1277 	if (dpcd[DP_DPCD_REV] < 0x13)
1278 		return false;
1279 
1280 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1281 	case DP_DS_PORT_TYPE_HDMI:
1282 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1283 			return false;
1284 
1285 		return port_cap[3] & color_spc;
1286 	default:
1287 		return false;
1288 	}
1289 }
1290 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
1291 
1292 /**
1293  * drm_dp_downstream_mode() - return a mode for downstream facing port
1294  * @dev: DRM device
1295  * @dpcd: DisplayPort configuration data
1296  * @port_cap: port capabilities
1297  *
1298  * Provides a suitable mode for downstream facing ports without EDID.
1299  *
1300  * Returns: A new drm_display_mode on success or NULL on failure
1301  */
1302 struct drm_display_mode *
drm_dp_downstream_mode(struct drm_device * dev,const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])1303 drm_dp_downstream_mode(struct drm_device *dev,
1304 		       const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1305 		       const u8 port_cap[4])
1306 
1307 {
1308 	u8 vic;
1309 
1310 	if (!drm_dp_is_branch(dpcd))
1311 		return NULL;
1312 
1313 	if (dpcd[DP_DPCD_REV] < 0x11)
1314 		return NULL;
1315 
1316 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1317 	case DP_DS_PORT_TYPE_NON_EDID:
1318 		switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1319 		case DP_DS_NON_EDID_720x480i_60:
1320 			vic = 6;
1321 			break;
1322 		case DP_DS_NON_EDID_720x480i_50:
1323 			vic = 21;
1324 			break;
1325 		case DP_DS_NON_EDID_1920x1080i_60:
1326 			vic = 5;
1327 			break;
1328 		case DP_DS_NON_EDID_1920x1080i_50:
1329 			vic = 20;
1330 			break;
1331 		case DP_DS_NON_EDID_1280x720_60:
1332 			vic = 4;
1333 			break;
1334 		case DP_DS_NON_EDID_1280x720_50:
1335 			vic = 19;
1336 			break;
1337 		default:
1338 			return NULL;
1339 		}
1340 		return drm_display_mode_from_cea_vic(dev, vic);
1341 	default:
1342 		return NULL;
1343 	}
1344 }
1345 EXPORT_SYMBOL(drm_dp_downstream_mode);
1346 
1347 /**
1348  * drm_dp_downstream_id() - identify branch device
1349  * @aux: DisplayPort AUX channel
1350  * @id: DisplayPort branch device id
1351  *
1352  * Returns branch device id on success or NULL on failure
1353  */
drm_dp_downstream_id(struct drm_dp_aux * aux,char id[6])1354 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1355 {
1356 	return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1357 }
1358 EXPORT_SYMBOL(drm_dp_downstream_id);
1359 
1360 /**
1361  * drm_dp_downstream_debug() - debug DP branch devices
1362  * @m: pointer for debugfs file
1363  * @dpcd: DisplayPort configuration data
1364  * @port_cap: port capabilities
1365  * @edid: EDID
1366  * @aux: DisplayPort AUX channel
1367  *
1368  */
drm_dp_downstream_debug(struct seq_file * m,const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],const struct edid * edid,struct drm_dp_aux * aux)1369 void drm_dp_downstream_debug(struct seq_file *m,
1370 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1371 			     const u8 port_cap[4],
1372 			     const struct edid *edid,
1373 			     struct drm_dp_aux *aux)
1374 {
1375 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1376 				 DP_DETAILED_CAP_INFO_AVAILABLE;
1377 	int clk;
1378 	int bpc;
1379 	char id[7];
1380 	int len;
1381 	uint8_t rev[2];
1382 	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1383 	bool branch_device = drm_dp_is_branch(dpcd);
1384 
1385 	seq_printf(m, "\tDP branch device present: %s\n",
1386 		   str_yes_no(branch_device));
1387 
1388 	if (!branch_device)
1389 		return;
1390 
1391 	switch (type) {
1392 	case DP_DS_PORT_TYPE_DP:
1393 		seq_puts(m, "\t\tType: DisplayPort\n");
1394 		break;
1395 	case DP_DS_PORT_TYPE_VGA:
1396 		seq_puts(m, "\t\tType: VGA\n");
1397 		break;
1398 	case DP_DS_PORT_TYPE_DVI:
1399 		seq_puts(m, "\t\tType: DVI\n");
1400 		break;
1401 	case DP_DS_PORT_TYPE_HDMI:
1402 		seq_puts(m, "\t\tType: HDMI\n");
1403 		break;
1404 	case DP_DS_PORT_TYPE_NON_EDID:
1405 		seq_puts(m, "\t\tType: others without EDID support\n");
1406 		break;
1407 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1408 		seq_puts(m, "\t\tType: DP++\n");
1409 		break;
1410 	case DP_DS_PORT_TYPE_WIRELESS:
1411 		seq_puts(m, "\t\tType: Wireless\n");
1412 		break;
1413 	default:
1414 		seq_puts(m, "\t\tType: N/A\n");
1415 	}
1416 
1417 	memset(id, 0, sizeof(id));
1418 	drm_dp_downstream_id(aux, id);
1419 	seq_printf(m, "\t\tID: %s\n", id);
1420 
1421 	len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1422 	if (len > 0)
1423 		seq_printf(m, "\t\tHW: %d.%d\n",
1424 			   (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1425 
1426 	len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1427 	if (len > 0)
1428 		seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1429 
1430 	if (detailed_cap_info) {
1431 		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1432 		if (clk > 0)
1433 			seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1434 
1435 		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);
1436 		if (clk > 0)
1437 			seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1438 
1439 		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);
1440 		if (clk > 0)
1441 			seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1442 
1443 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
1444 
1445 		if (bpc > 0)
1446 			seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1447 	}
1448 }
1449 EXPORT_SYMBOL(drm_dp_downstream_debug);
1450 
1451 /**
1452  * drm_dp_subconnector_type() - get DP branch device type
1453  * @dpcd: DisplayPort configuration data
1454  * @port_cap: port capabilities
1455  */
1456 enum drm_mode_subconnector
drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])1457 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1458 			 const u8 port_cap[4])
1459 {
1460 	int type;
1461 	if (!drm_dp_is_branch(dpcd))
1462 		return DRM_MODE_SUBCONNECTOR_Native;
1463 	/* DP 1.0 approach */
1464 	if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1465 		type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1466 		       DP_DWN_STRM_PORT_TYPE_MASK;
1467 
1468 		switch (type) {
1469 		case DP_DWN_STRM_PORT_TYPE_TMDS:
1470 			/* Can be HDMI or DVI-D, DVI-D is a safer option */
1471 			return DRM_MODE_SUBCONNECTOR_DVID;
1472 		case DP_DWN_STRM_PORT_TYPE_ANALOG:
1473 			/* Can be VGA or DVI-A, VGA is more popular */
1474 			return DRM_MODE_SUBCONNECTOR_VGA;
1475 		case DP_DWN_STRM_PORT_TYPE_DP:
1476 			return DRM_MODE_SUBCONNECTOR_DisplayPort;
1477 		case DP_DWN_STRM_PORT_TYPE_OTHER:
1478 		default:
1479 			return DRM_MODE_SUBCONNECTOR_Unknown;
1480 		}
1481 	}
1482 	type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1483 
1484 	switch (type) {
1485 	case DP_DS_PORT_TYPE_DP:
1486 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1487 		return DRM_MODE_SUBCONNECTOR_DisplayPort;
1488 	case DP_DS_PORT_TYPE_VGA:
1489 		return DRM_MODE_SUBCONNECTOR_VGA;
1490 	case DP_DS_PORT_TYPE_DVI:
1491 		return DRM_MODE_SUBCONNECTOR_DVID;
1492 	case DP_DS_PORT_TYPE_HDMI:
1493 		return DRM_MODE_SUBCONNECTOR_HDMIA;
1494 	case DP_DS_PORT_TYPE_WIRELESS:
1495 		return DRM_MODE_SUBCONNECTOR_Wireless;
1496 	case DP_DS_PORT_TYPE_NON_EDID:
1497 	default:
1498 		return DRM_MODE_SUBCONNECTOR_Unknown;
1499 	}
1500 }
1501 EXPORT_SYMBOL(drm_dp_subconnector_type);
1502 
1503 /**
1504  * drm_dp_set_subconnector_property - set subconnector for DP connector
1505  * @connector: connector to set property on
1506  * @status: connector status
1507  * @dpcd: DisplayPort configuration data
1508  * @port_cap: port capabilities
1509  *
1510  * Called by a driver on every detect event.
1511  */
drm_dp_set_subconnector_property(struct drm_connector * connector,enum drm_connector_status status,const u8 * dpcd,const u8 port_cap[4])1512 void drm_dp_set_subconnector_property(struct drm_connector *connector,
1513 				      enum drm_connector_status status,
1514 				      const u8 *dpcd,
1515 				      const u8 port_cap[4])
1516 {
1517 	enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1518 
1519 	if (status == connector_status_connected)
1520 		subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1521 	drm_object_property_set_value(&connector->base,
1522 			connector->dev->mode_config.dp_subconnector_property,
1523 			subconnector);
1524 }
1525 EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1526 
1527 /**
1528  * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1529  * count
1530  * @connector: The DRM connector to check
1531  * @dpcd: A cached copy of the connector's DPCD RX capabilities
1532  * @desc: A cached copy of the connector's DP descriptor
1533  *
1534  * See also: drm_dp_read_sink_count()
1535  *
1536  * Returns: %True if the (e)DP connector has a valid sink count that should
1537  * be probed, %false otherwise.
1538  */
drm_dp_read_sink_count_cap(struct drm_connector * connector,const u8 dpcd[DP_RECEIVER_CAP_SIZE],const struct drm_dp_desc * desc)1539 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1540 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1541 				const struct drm_dp_desc *desc)
1542 {
1543 	/* Some eDP panels don't set a valid value for the sink count */
1544 	return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1545 		dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1546 		dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1547 		!drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1548 }
1549 EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1550 
1551 /**
1552  * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1553  * @aux: The DP AUX channel to use
1554  *
1555  * See also: drm_dp_read_sink_count_cap()
1556  *
1557  * Returns: The current sink count reported by @aux, or a negative error code
1558  * otherwise.
1559  */
drm_dp_read_sink_count(struct drm_dp_aux * aux)1560 int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1561 {
1562 	u8 count;
1563 	int ret;
1564 
1565 	ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1566 	if (ret < 0)
1567 		return ret;
1568 	if (ret != 1)
1569 		return -EIO;
1570 
1571 	return DP_GET_SINK_COUNT(count);
1572 }
1573 EXPORT_SYMBOL(drm_dp_read_sink_count);
1574 
1575 /*
1576  * I2C-over-AUX implementation
1577  */
1578 
drm_dp_i2c_functionality(struct i2c_adapter * adapter)1579 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1580 {
1581 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1582 	       I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1583 	       I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1584 	       I2C_FUNC_10BIT_ADDR;
1585 }
1586 
drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg * msg)1587 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1588 {
1589 	/*
1590 	 * In case of i2c defer or short i2c ack reply to a write,
1591 	 * we need to switch to WRITE_STATUS_UPDATE to drain the
1592 	 * rest of the message
1593 	 */
1594 	if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1595 		msg->request &= DP_AUX_I2C_MOT;
1596 		msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1597 	}
1598 }
1599 
1600 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1601 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1602 #define AUX_STOP_LEN 4
1603 #define AUX_CMD_LEN 4
1604 #define AUX_ADDRESS_LEN 20
1605 #define AUX_REPLY_PAD_LEN 4
1606 #define AUX_LENGTH_LEN 8
1607 
1608 /*
1609  * Calculate the duration of the AUX request/reply in usec. Gives the
1610  * "best" case estimate, ie. successful while as short as possible.
1611  */
drm_dp_aux_req_duration(const struct drm_dp_aux_msg * msg)1612 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1613 {
1614 	int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1615 		AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1616 
1617 	if ((msg->request & DP_AUX_I2C_READ) == 0)
1618 		len += msg->size * 8;
1619 
1620 	return len;
1621 }
1622 
drm_dp_aux_reply_duration(const struct drm_dp_aux_msg * msg)1623 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1624 {
1625 	int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1626 		AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1627 
1628 	/*
1629 	 * For read we expect what was asked. For writes there will
1630 	 * be 0 or 1 data bytes. Assume 0 for the "best" case.
1631 	 */
1632 	if (msg->request & DP_AUX_I2C_READ)
1633 		len += msg->size * 8;
1634 
1635 	return len;
1636 }
1637 
1638 #define I2C_START_LEN 1
1639 #define I2C_STOP_LEN 1
1640 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1641 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1642 
1643 /*
1644  * Calculate the length of the i2c transfer in usec, assuming
1645  * the i2c bus speed is as specified. Gives the "worst"
1646  * case estimate, ie. successful while as long as possible.
1647  * Doesn't account the "MOT" bit, and instead assumes each
1648  * message includes a START, ADDRESS and STOP. Neither does it
1649  * account for additional random variables such as clock stretching.
1650  */
drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg * msg,int i2c_speed_khz)1651 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1652 				   int i2c_speed_khz)
1653 {
1654 	/* AUX bitrate is 1MHz, i2c bitrate as specified */
1655 	return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1656 			     msg->size * I2C_DATA_LEN +
1657 			     I2C_STOP_LEN) * 1000, i2c_speed_khz);
1658 }
1659 
1660 /*
1661  * Determine how many retries should be attempted to successfully transfer
1662  * the specified message, based on the estimated durations of the
1663  * i2c and AUX transfers.
1664  */
drm_dp_i2c_retry_count(const struct drm_dp_aux_msg * msg,int i2c_speed_khz)1665 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1666 			      int i2c_speed_khz)
1667 {
1668 	int aux_time_us = drm_dp_aux_req_duration(msg) +
1669 		drm_dp_aux_reply_duration(msg);
1670 	int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1671 
1672 	return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1673 }
1674 
1675 /*
1676  * FIXME currently assumes 10 kHz as some real world devices seem
1677  * to require it. We should query/set the speed via DPCD if supported.
1678  */
1679 static int dp_aux_i2c_speed_khz __read_mostly = 10;
1680 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1681 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1682 		 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1683 
1684 /*
1685  * Transfer a single I2C-over-AUX message and handle various error conditions,
1686  * retrying the transaction as appropriate.  It is assumed that the
1687  * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1688  * reply field.
1689  *
1690  * Returns bytes transferred on success, or a negative error code on failure.
1691  */
drm_dp_i2c_do_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1692 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1693 {
1694 	unsigned int retry, defer_i2c;
1695 	int ret;
1696 	/*
1697 	 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1698 	 * is required to retry at least seven times upon receiving AUX_DEFER
1699 	 * before giving up the AUX transaction.
1700 	 *
1701 	 * We also try to account for the i2c bus speed.
1702 	 */
1703 	int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1704 
1705 	for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1706 		ret = aux->transfer(aux, msg);
1707 		if (ret < 0) {
1708 			if (ret == -EBUSY)
1709 				continue;
1710 
1711 			/*
1712 			 * While timeouts can be errors, they're usually normal
1713 			 * behavior (for instance, when a driver tries to
1714 			 * communicate with a non-existent DisplayPort device).
1715 			 * Avoid spamming the kernel log with timeout errors.
1716 			 */
1717 			if (ret == -ETIMEDOUT)
1718 				drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
1719 							aux->name);
1720 			else
1721 				drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
1722 					    aux->name, ret);
1723 			return ret;
1724 		}
1725 
1726 
1727 		switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1728 		case DP_AUX_NATIVE_REPLY_ACK:
1729 			/*
1730 			 * For I2C-over-AUX transactions this isn't enough, we
1731 			 * need to check for the I2C ACK reply.
1732 			 */
1733 			break;
1734 
1735 		case DP_AUX_NATIVE_REPLY_NACK:
1736 			drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
1737 				    aux->name, ret, msg->size);
1738 			return -EREMOTEIO;
1739 
1740 		case DP_AUX_NATIVE_REPLY_DEFER:
1741 			drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
1742 			/*
1743 			 * We could check for I2C bit rate capabilities and if
1744 			 * available adjust this interval. We could also be
1745 			 * more careful with DP-to-legacy adapters where a
1746 			 * long legacy cable may force very low I2C bit rates.
1747 			 *
1748 			 * For now just defer for long enough to hopefully be
1749 			 * safe for all use-cases.
1750 			 */
1751 			usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1752 			continue;
1753 
1754 		default:
1755 			drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
1756 				aux->name, msg->reply);
1757 			return -EREMOTEIO;
1758 		}
1759 
1760 		switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1761 		case DP_AUX_I2C_REPLY_ACK:
1762 			/*
1763 			 * Both native ACK and I2C ACK replies received. We
1764 			 * can assume the transfer was successful.
1765 			 */
1766 			if (ret != msg->size)
1767 				drm_dp_i2c_msg_write_status_update(msg);
1768 			return ret;
1769 
1770 		case DP_AUX_I2C_REPLY_NACK:
1771 			drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
1772 				    aux->name, ret, msg->size);
1773 			aux->i2c_nack_count++;
1774 			return -EREMOTEIO;
1775 
1776 		case DP_AUX_I2C_REPLY_DEFER:
1777 			drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
1778 			/* DP Compliance Test 4.2.2.5 Requirement:
1779 			 * Must have at least 7 retries for I2C defers on the
1780 			 * transaction to pass this test
1781 			 */
1782 			aux->i2c_defer_count++;
1783 			if (defer_i2c < 7)
1784 				defer_i2c++;
1785 			usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1786 			drm_dp_i2c_msg_write_status_update(msg);
1787 
1788 			continue;
1789 
1790 		default:
1791 			drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
1792 				aux->name, msg->reply);
1793 			return -EREMOTEIO;
1794 		}
1795 	}
1796 
1797 	drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
1798 	return -EREMOTEIO;
1799 }
1800 
drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg * msg,const struct i2c_msg * i2c_msg)1801 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1802 				       const struct i2c_msg *i2c_msg)
1803 {
1804 	msg->request = (i2c_msg->flags & I2C_M_RD) ?
1805 		DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1806 	if (!(i2c_msg->flags & I2C_M_STOP))
1807 		msg->request |= DP_AUX_I2C_MOT;
1808 }
1809 
1810 /*
1811  * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
1812  *
1813  * Returns an error code on failure, or a recommended transfer size on success.
1814  */
drm_dp_i2c_drain_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * orig_msg)1815 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1816 {
1817 	int err, ret = orig_msg->size;
1818 	struct drm_dp_aux_msg msg = *orig_msg;
1819 
1820 	while (msg.size > 0) {
1821 		err = drm_dp_i2c_do_msg(aux, &msg);
1822 		if (err <= 0)
1823 			return err == 0 ? -EPROTO : err;
1824 
1825 		if (err < msg.size && err < ret) {
1826 			drm_dbg_kms(aux->drm_dev,
1827 				    "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1828 				    aux->name, msg.size, err);
1829 			ret = err;
1830 		}
1831 
1832 		msg.size -= err;
1833 		msg.buffer += err;
1834 	}
1835 
1836 	return ret;
1837 }
1838 
1839 /*
1840  * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1841  * packets to be as large as possible. If not, the I2C transactions never
1842  * succeed. Hence the default is maximum.
1843  */
1844 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1845 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1846 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1847 		 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1848 
drm_dp_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1849 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1850 			   int num)
1851 {
1852 	struct drm_dp_aux *aux = adapter->algo_data;
1853 	unsigned int i, j;
1854 	unsigned transfer_size;
1855 	struct drm_dp_aux_msg msg;
1856 	int err = 0;
1857 
1858 	dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1859 
1860 	memset(&msg, 0, sizeof(msg));
1861 
1862 	for (i = 0; i < num; i++) {
1863 		msg.address = msgs[i].addr;
1864 		drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1865 		/* Send a bare address packet to start the transaction.
1866 		 * Zero sized messages specify an address only (bare
1867 		 * address) transaction.
1868 		 */
1869 		msg.buffer = NULL;
1870 		msg.size = 0;
1871 		err = drm_dp_i2c_do_msg(aux, &msg);
1872 
1873 		/*
1874 		 * Reset msg.request in case in case it got
1875 		 * changed into a WRITE_STATUS_UPDATE.
1876 		 */
1877 		drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1878 
1879 		if (err < 0)
1880 			break;
1881 		/* We want each transaction to be as large as possible, but
1882 		 * we'll go to smaller sizes if the hardware gives us a
1883 		 * short reply.
1884 		 */
1885 		transfer_size = dp_aux_i2c_transfer_size;
1886 		for (j = 0; j < msgs[i].len; j += msg.size) {
1887 			msg.buffer = msgs[i].buf + j;
1888 			msg.size = min(transfer_size, msgs[i].len - j);
1889 
1890 			err = drm_dp_i2c_drain_msg(aux, &msg);
1891 
1892 			/*
1893 			 * Reset msg.request in case in case it got
1894 			 * changed into a WRITE_STATUS_UPDATE.
1895 			 */
1896 			drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1897 
1898 			if (err < 0)
1899 				break;
1900 			transfer_size = err;
1901 		}
1902 		if (err < 0)
1903 			break;
1904 	}
1905 	if (err >= 0)
1906 		err = num;
1907 	/* Send a bare address packet to close out the transaction.
1908 	 * Zero sized messages specify an address only (bare
1909 	 * address) transaction.
1910 	 */
1911 	msg.request &= ~DP_AUX_I2C_MOT;
1912 	msg.buffer = NULL;
1913 	msg.size = 0;
1914 	(void)drm_dp_i2c_do_msg(aux, &msg);
1915 
1916 	return err;
1917 }
1918 
1919 static const struct i2c_algorithm drm_dp_i2c_algo = {
1920 	.functionality = drm_dp_i2c_functionality,
1921 	.master_xfer = drm_dp_i2c_xfer,
1922 };
1923 
i2c_to_aux(struct i2c_adapter * i2c)1924 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1925 {
1926 	return container_of(i2c, struct drm_dp_aux, ddc);
1927 }
1928 
lock_bus(struct i2c_adapter * i2c,unsigned int flags)1929 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1930 {
1931 	mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1932 }
1933 
trylock_bus(struct i2c_adapter * i2c,unsigned int flags)1934 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1935 {
1936 	return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1937 }
1938 
unlock_bus(struct i2c_adapter * i2c,unsigned int flags)1939 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1940 {
1941 	mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1942 }
1943 
1944 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1945 	.lock_bus = lock_bus,
1946 	.trylock_bus = trylock_bus,
1947 	.unlock_bus = unlock_bus,
1948 };
1949 
drm_dp_aux_get_crc(struct drm_dp_aux * aux,u8 * crc)1950 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1951 {
1952 	u8 buf, count;
1953 	int ret;
1954 
1955 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1956 	if (ret < 0)
1957 		return ret;
1958 
1959 	WARN_ON(!(buf & DP_TEST_SINK_START));
1960 
1961 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1962 	if (ret < 0)
1963 		return ret;
1964 
1965 	count = buf & DP_TEST_COUNT_MASK;
1966 	if (count == aux->crc_count)
1967 		return -EAGAIN; /* No CRC yet */
1968 
1969 	aux->crc_count = count;
1970 
1971 	/*
1972 	 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1973 	 * per component (RGB or CrYCb).
1974 	 */
1975 	ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1976 	if (ret < 0)
1977 		return ret;
1978 
1979 	return 0;
1980 }
1981 
drm_dp_aux_crc_work(struct work_struct * work)1982 static void drm_dp_aux_crc_work(struct work_struct *work)
1983 {
1984 	struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1985 					      crc_work);
1986 	struct drm_crtc *crtc;
1987 	u8 crc_bytes[6];
1988 	uint32_t crcs[3];
1989 	int ret;
1990 
1991 	if (WARN_ON(!aux->crtc))
1992 		return;
1993 
1994 	crtc = aux->crtc;
1995 	while (crtc->crc.opened) {
1996 		drm_crtc_wait_one_vblank(crtc);
1997 		if (!crtc->crc.opened)
1998 			break;
1999 
2000 		ret = drm_dp_aux_get_crc(aux, crc_bytes);
2001 		if (ret == -EAGAIN) {
2002 			usleep_range(1000, 2000);
2003 			ret = drm_dp_aux_get_crc(aux, crc_bytes);
2004 		}
2005 
2006 		if (ret == -EAGAIN) {
2007 			drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
2008 				    aux->name, ret);
2009 			continue;
2010 		} else if (ret) {
2011 			drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
2012 			continue;
2013 		}
2014 
2015 		crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
2016 		crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
2017 		crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
2018 		drm_crtc_add_crc_entry(crtc, false, 0, crcs);
2019 	}
2020 }
2021 
2022 /**
2023  * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2024  * @aux: DisplayPort AUX channel
2025  *
2026  * Used for remote aux channel in general. Merely initialize the crc work
2027  * struct.
2028  */
drm_dp_remote_aux_init(struct drm_dp_aux * aux)2029 void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
2030 {
2031 	INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2032 }
2033 EXPORT_SYMBOL(drm_dp_remote_aux_init);
2034 
2035 /**
2036  * drm_dp_aux_init() - minimally initialise an aux channel
2037  * @aux: DisplayPort AUX channel
2038  *
2039  * If you need to use the drm_dp_aux's i2c adapter prior to registering it with
2040  * the outside world, call drm_dp_aux_init() first. For drivers which are
2041  * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
2042  * &drm_connector), you must still call drm_dp_aux_register() once the connector
2043  * has been registered to allow userspace access to the auxiliary DP channel.
2044  * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
2045  * early as possible so that the &drm_device that corresponds to the AUX adapter
2046  * may be mentioned in debugging output from the DRM DP helpers.
2047  *
2048  * For devices which use a separate platform device for their AUX adapters, this
2049  * may be called as early as required by the driver.
2050  *
2051  */
drm_dp_aux_init(struct drm_dp_aux * aux)2052 void drm_dp_aux_init(struct drm_dp_aux *aux)
2053 {
2054 	mutex_init(&aux->hw_mutex);
2055 	mutex_init(&aux->cec.lock);
2056 	INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2057 
2058 	aux->ddc.algo = &drm_dp_i2c_algo;
2059 	aux->ddc.algo_data = aux;
2060 	aux->ddc.retries = 3;
2061 
2062 	aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
2063 }
2064 EXPORT_SYMBOL(drm_dp_aux_init);
2065 
2066 /**
2067  * drm_dp_aux_register() - initialise and register aux channel
2068  * @aux: DisplayPort AUX channel
2069  *
2070  * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
2071  * should only be called once the parent of @aux, &drm_dp_aux.dev, is
2072  * initialized. For devices which are grandparents of their AUX channels,
2073  * &drm_dp_aux.dev will typically be the &drm_connector &device which
2074  * corresponds to @aux. For these devices, it's advised to call
2075  * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
2076  * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
2077  * Functions which don't follow this will likely Oops when
2078  * %CONFIG_DRM_DP_AUX_CHARDEV is enabled.
2079  *
2080  * For devices where the AUX channel is a device that exists independently of
2081  * the &drm_device that uses it, such as SoCs and bridge devices, it is
2082  * recommended to call drm_dp_aux_register() after a &drm_device has been
2083  * assigned to &drm_dp_aux.drm_dev, and likewise to call
2084  * drm_dp_aux_unregister() once the &drm_device should no longer be associated
2085  * with the AUX channel (e.g. on bridge detach).
2086  *
2087  * Drivers which need to use the aux channel before either of the two points
2088  * mentioned above need to call drm_dp_aux_init() in order to use the AUX
2089  * channel before registration.
2090  *
2091  * Returns 0 on success or a negative error code on failure.
2092  */
drm_dp_aux_register(struct drm_dp_aux * aux)2093 int drm_dp_aux_register(struct drm_dp_aux *aux)
2094 {
2095 	int ret;
2096 
2097 	WARN_ON_ONCE(!aux->drm_dev);
2098 
2099 	if (!aux->ddc.algo)
2100 		drm_dp_aux_init(aux);
2101 
2102 	aux->ddc.class = I2C_CLASS_DDC;
2103 	aux->ddc.owner = THIS_MODULE;
2104 	aux->ddc.dev.parent = aux->dev;
2105 
2106 	strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
2107 		sizeof(aux->ddc.name));
2108 
2109 	ret = drm_dp_aux_register_devnode(aux);
2110 	if (ret)
2111 		return ret;
2112 
2113 	ret = i2c_add_adapter(&aux->ddc);
2114 	if (ret) {
2115 		drm_dp_aux_unregister_devnode(aux);
2116 		return ret;
2117 	}
2118 
2119 	return 0;
2120 }
2121 EXPORT_SYMBOL(drm_dp_aux_register);
2122 
2123 /**
2124  * drm_dp_aux_unregister() - unregister an AUX adapter
2125  * @aux: DisplayPort AUX channel
2126  */
drm_dp_aux_unregister(struct drm_dp_aux * aux)2127 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
2128 {
2129 	drm_dp_aux_unregister_devnode(aux);
2130 	i2c_del_adapter(&aux->ddc);
2131 }
2132 EXPORT_SYMBOL(drm_dp_aux_unregister);
2133 
2134 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
2135 
2136 /**
2137  * drm_dp_psr_setup_time() - PSR setup in time usec
2138  * @psr_cap: PSR capabilities from DPCD
2139  *
2140  * Returns:
2141  * PSR setup time for the panel in microseconds,  negative
2142  * error code on failure.
2143  */
drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])2144 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
2145 {
2146 	static const u16 psr_setup_time_us[] = {
2147 		PSR_SETUP_TIME(330),
2148 		PSR_SETUP_TIME(275),
2149 		PSR_SETUP_TIME(220),
2150 		PSR_SETUP_TIME(165),
2151 		PSR_SETUP_TIME(110),
2152 		PSR_SETUP_TIME(55),
2153 		PSR_SETUP_TIME(0),
2154 	};
2155 	int i;
2156 
2157 	i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
2158 	if (i >= ARRAY_SIZE(psr_setup_time_us))
2159 		return -EINVAL;
2160 
2161 	return psr_setup_time_us[i];
2162 }
2163 EXPORT_SYMBOL(drm_dp_psr_setup_time);
2164 
2165 #undef PSR_SETUP_TIME
2166 
2167 /**
2168  * drm_dp_start_crc() - start capture of frame CRCs
2169  * @aux: DisplayPort AUX channel
2170  * @crtc: CRTC displaying the frames whose CRCs are to be captured
2171  *
2172  * Returns 0 on success or a negative error code on failure.
2173  */
drm_dp_start_crc(struct drm_dp_aux * aux,struct drm_crtc * crtc)2174 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
2175 {
2176 	u8 buf;
2177 	int ret;
2178 
2179 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2180 	if (ret < 0)
2181 		return ret;
2182 
2183 	ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
2184 	if (ret < 0)
2185 		return ret;
2186 
2187 	aux->crc_count = 0;
2188 	aux->crtc = crtc;
2189 	schedule_work(&aux->crc_work);
2190 
2191 	return 0;
2192 }
2193 EXPORT_SYMBOL(drm_dp_start_crc);
2194 
2195 /**
2196  * drm_dp_stop_crc() - stop capture of frame CRCs
2197  * @aux: DisplayPort AUX channel
2198  *
2199  * Returns 0 on success or a negative error code on failure.
2200  */
drm_dp_stop_crc(struct drm_dp_aux * aux)2201 int drm_dp_stop_crc(struct drm_dp_aux *aux)
2202 {
2203 	u8 buf;
2204 	int ret;
2205 
2206 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2207 	if (ret < 0)
2208 		return ret;
2209 
2210 	ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
2211 	if (ret < 0)
2212 		return ret;
2213 
2214 	flush_work(&aux->crc_work);
2215 	aux->crtc = NULL;
2216 
2217 	return 0;
2218 }
2219 EXPORT_SYMBOL(drm_dp_stop_crc);
2220 
2221 struct dpcd_quirk {
2222 	u8 oui[3];
2223 	u8 device_id[6];
2224 	bool is_branch;
2225 	u32 quirks;
2226 };
2227 
2228 #define OUI(first, second, third) { (first), (second), (third) }
2229 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
2230 	{ (first), (second), (third), (fourth), (fifth), (sixth) }
2231 
2232 #define DEVICE_ID_ANY	DEVICE_ID(0, 0, 0, 0, 0, 0)
2233 
2234 static const struct dpcd_quirk dpcd_quirk_list[] = {
2235 	/* Analogix 7737 needs reduced M and N at HBR2 link rates */
2236 	{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2237 	/* LG LP140WF6-SPM1 eDP panel */
2238 	{ OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2239 	/* Apple panels need some additional handling to support PSR */
2240 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
2241 	/* CH7511 seems to leave SINK_COUNT zeroed */
2242 	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
2243 	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
2244 	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
2245 	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
2246 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
2247 };
2248 
2249 #undef OUI
2250 
2251 /*
2252  * Get a bit mask of DPCD quirks for the sink/branch device identified by
2253  * ident. The quirk data is shared but it's up to the drivers to act on the
2254  * data.
2255  *
2256  * For now, only the OUI (first three bytes) is used, but this may be extended
2257  * to device identification string and hardware/firmware revisions later.
2258  */
2259 static u32
drm_dp_get_quirks(const struct drm_dp_dpcd_ident * ident,bool is_branch)2260 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
2261 {
2262 	const struct dpcd_quirk *quirk;
2263 	u32 quirks = 0;
2264 	int i;
2265 	u8 any_device[] = DEVICE_ID_ANY;
2266 
2267 	for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
2268 		quirk = &dpcd_quirk_list[i];
2269 
2270 		if (quirk->is_branch != is_branch)
2271 			continue;
2272 
2273 		if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
2274 			continue;
2275 
2276 		if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
2277 		    memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
2278 			continue;
2279 
2280 		quirks |= quirk->quirks;
2281 	}
2282 
2283 	return quirks;
2284 }
2285 
2286 #undef DEVICE_ID_ANY
2287 #undef DEVICE_ID
2288 
2289 /**
2290  * drm_dp_read_desc - read sink/branch descriptor from DPCD
2291  * @aux: DisplayPort AUX channel
2292  * @desc: Device descriptor to fill from DPCD
2293  * @is_branch: true for branch devices, false for sink devices
2294  *
2295  * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
2296  * identification.
2297  *
2298  * Returns 0 on success or a negative error code on failure.
2299  */
drm_dp_read_desc(struct drm_dp_aux * aux,struct drm_dp_desc * desc,bool is_branch)2300 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2301 		     bool is_branch)
2302 {
2303 	struct drm_dp_dpcd_ident *ident = &desc->ident;
2304 	unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2305 	int ret, dev_id_len;
2306 
2307 	ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
2308 	if (ret < 0)
2309 		return ret;
2310 
2311 	desc->quirks = drm_dp_get_quirks(ident, is_branch);
2312 
2313 	dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
2314 
2315 	drm_dbg_kms(aux->drm_dev,
2316 		    "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2317 		    aux->name, is_branch ? "branch" : "sink",
2318 		    (int)sizeof(ident->oui), ident->oui, dev_id_len,
2319 		    ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf,
2320 		    ident->sw_major_rev, ident->sw_minor_rev, desc->quirks);
2321 
2322 	return 0;
2323 }
2324 EXPORT_SYMBOL(drm_dp_read_desc);
2325 
2326 /**
2327  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2328  * supported by the DSC sink.
2329  * @dsc_dpcd: DSC capabilities from DPCD
2330  * @is_edp: true if its eDP, false for DP
2331  *
2332  * Read the slice capabilities DPCD register from DSC sink to get
2333  * the maximum slice count supported. This is used to populate
2334  * the DSC parameters in the &struct drm_dsc_config by the driver.
2335  * Driver creates an infoframe using these parameters to populate
2336  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2337  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2338  *
2339  * Returns:
2340  * Maximum slice count supported by DSC sink or 0 its invalid
2341  */
drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],bool is_edp)2342 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2343 				   bool is_edp)
2344 {
2345 	u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2346 
2347 	if (is_edp) {
2348 		/* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2349 		if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2350 			return 4;
2351 		if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2352 			return 2;
2353 		if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2354 			return 1;
2355 	} else {
2356 		/* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2357 		u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2358 
2359 		if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2360 			return 24;
2361 		if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2362 			return 20;
2363 		if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2364 			return 16;
2365 		if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2366 			return 12;
2367 		if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2368 			return 10;
2369 		if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2370 			return 8;
2371 		if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2372 			return 6;
2373 		if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2374 			return 4;
2375 		if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2376 			return 2;
2377 		if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2378 			return 1;
2379 	}
2380 
2381 	return 0;
2382 }
2383 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2384 
2385 /**
2386  * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2387  * @dsc_dpcd: DSC capabilities from DPCD
2388  *
2389  * Read the DSC DPCD register to parse the line buffer depth in bits which is
2390  * number of bits of precision within the decoder line buffer supported by
2391  * the DSC sink. This is used to populate the DSC parameters in the
2392  * &struct drm_dsc_config by the driver.
2393  * Driver creates an infoframe using these parameters to populate
2394  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2395  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2396  *
2397  * Returns:
2398  * Line buffer depth supported by DSC panel or 0 its invalid
2399  */
drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])2400 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2401 {
2402 	u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2403 
2404 	switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2405 	case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2406 		return 9;
2407 	case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2408 		return 10;
2409 	case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2410 		return 11;
2411 	case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2412 		return 12;
2413 	case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2414 		return 13;
2415 	case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2416 		return 14;
2417 	case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2418 		return 15;
2419 	case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2420 		return 16;
2421 	case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2422 		return 8;
2423 	}
2424 
2425 	return 0;
2426 }
2427 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2428 
2429 /**
2430  * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2431  * values supported by the DSC sink.
2432  * @dsc_dpcd: DSC capabilities from DPCD
2433  * @dsc_bpc: An array to be filled by this helper with supported
2434  *           input bpcs.
2435  *
2436  * Read the DSC DPCD from the sink device to parse the supported bits per
2437  * component values. This is used to populate the DSC parameters
2438  * in the &struct drm_dsc_config by the driver.
2439  * Driver creates an infoframe using these parameters to populate
2440  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2441  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2442  *
2443  * Returns:
2444  * Number of input BPC values parsed from the DPCD
2445  */
drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],u8 dsc_bpc[3])2446 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2447 					 u8 dsc_bpc[3])
2448 {
2449 	int num_bpc = 0;
2450 	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2451 
2452 	if (color_depth & DP_DSC_12_BPC)
2453 		dsc_bpc[num_bpc++] = 12;
2454 	if (color_depth & DP_DSC_10_BPC)
2455 		dsc_bpc[num_bpc++] = 10;
2456 	if (color_depth & DP_DSC_8_BPC)
2457 		dsc_bpc[num_bpc++] = 8;
2458 
2459 	return num_bpc;
2460 }
2461 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2462 
drm_dp_read_lttpr_regs(struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE],int address,u8 * buf,int buf_size)2463 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
2464 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
2465 				  u8 *buf, int buf_size)
2466 {
2467 	/*
2468 	 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
2469 	 * corrupted values when reading from the 0xF0000- range with a block
2470 	 * size bigger than 1.
2471 	 */
2472 	int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
2473 	int offset;
2474 	int ret;
2475 
2476 	for (offset = 0; offset < buf_size; offset += block_size) {
2477 		ret = drm_dp_dpcd_read(aux,
2478 				       address + offset,
2479 				       &buf[offset], block_size);
2480 		if (ret < 0)
2481 			return ret;
2482 
2483 		WARN_ON(ret != block_size);
2484 	}
2485 
2486 	return 0;
2487 }
2488 
2489 /**
2490  * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2491  * @aux: DisplayPort AUX channel
2492  * @dpcd: DisplayPort configuration data
2493  * @caps: buffer to return the capability info in
2494  *
2495  * Read capabilities common to all LTTPRs.
2496  *
2497  * Returns 0 on success or a negative error code on failure.
2498  */
drm_dp_read_lttpr_common_caps(struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE],u8 caps[DP_LTTPR_COMMON_CAP_SIZE])2499 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2500 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2501 				  u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2502 {
2503 	return drm_dp_read_lttpr_regs(aux, dpcd,
2504 				      DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2505 				      caps, DP_LTTPR_COMMON_CAP_SIZE);
2506 }
2507 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2508 
2509 /**
2510  * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2511  * @aux: DisplayPort AUX channel
2512  * @dpcd: DisplayPort configuration data
2513  * @dp_phy: LTTPR PHY to read the capabilities for
2514  * @caps: buffer to return the capability info in
2515  *
2516  * Read the capabilities for the given LTTPR PHY.
2517  *
2518  * Returns 0 on success or a negative error code on failure.
2519  */
drm_dp_read_lttpr_phy_caps(struct drm_dp_aux * aux,const u8 dpcd[DP_RECEIVER_CAP_SIZE],enum drm_dp_phy dp_phy,u8 caps[DP_LTTPR_PHY_CAP_SIZE])2520 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2521 			       const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2522 			       enum drm_dp_phy dp_phy,
2523 			       u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2524 {
2525 	return drm_dp_read_lttpr_regs(aux, dpcd,
2526 				      DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2527 				      caps, DP_LTTPR_PHY_CAP_SIZE);
2528 }
2529 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2530 
dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE],int r)2531 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2532 {
2533 	return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2534 }
2535 
2536 /**
2537  * drm_dp_lttpr_count - get the number of detected LTTPRs
2538  * @caps: LTTPR common capabilities
2539  *
2540  * Get the number of detected LTTPRs from the LTTPR common capabilities info.
2541  *
2542  * Returns:
2543  *   -ERANGE if more than supported number (8) of LTTPRs are detected
2544  *   -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2545  *   otherwise the number of detected LTTPRs
2546  */
drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])2547 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2548 {
2549 	u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2550 
2551 	switch (hweight8(count)) {
2552 	case 0:
2553 		return 0;
2554 	case 1:
2555 		return 8 - ilog2(count);
2556 	case 8:
2557 		return -ERANGE;
2558 	default:
2559 		return -EINVAL;
2560 	}
2561 }
2562 EXPORT_SYMBOL(drm_dp_lttpr_count);
2563 
2564 /**
2565  * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2566  * @caps: LTTPR common capabilities
2567  *
2568  * Returns the maximum link rate supported by all detected LTTPRs.
2569  */
drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])2570 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2571 {
2572 	u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2573 
2574 	return drm_dp_bw_code_to_link_rate(rate);
2575 }
2576 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2577 
2578 /**
2579  * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2580  * @caps: LTTPR common capabilities
2581  *
2582  * Returns the maximum lane count supported by all detected LTTPRs.
2583  */
drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])2584 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2585 {
2586 	u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2587 
2588 	return max_lanes & DP_MAX_LANE_COUNT_MASK;
2589 }
2590 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2591 
2592 /**
2593  * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2594  * @caps: LTTPR PHY capabilities
2595  *
2596  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2597  * voltage swing level 3.
2598  */
2599 bool
drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])2600 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2601 {
2602 	u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2603 
2604 	return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2605 }
2606 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2607 
2608 /**
2609  * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2610  * @caps: LTTPR PHY capabilities
2611  *
2612  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2613  * pre-emphasis level 3.
2614  */
2615 bool
drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])2616 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2617 {
2618 	u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2619 
2620 	return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2621 }
2622 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2623 
2624 /**
2625  * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2626  * @aux: DisplayPort AUX channel
2627  * @data: DP phy compliance test parameters.
2628  *
2629  * Returns 0 on success or a negative error code on failure.
2630  */
drm_dp_get_phy_test_pattern(struct drm_dp_aux * aux,struct drm_dp_phy_test_params * data)2631 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2632 				struct drm_dp_phy_test_params *data)
2633 {
2634 	int err;
2635 	u8 rate, lanes;
2636 
2637 	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2638 	if (err < 0)
2639 		return err;
2640 	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2641 
2642 	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2643 	if (err < 0)
2644 		return err;
2645 	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2646 
2647 	if (lanes & DP_ENHANCED_FRAME_CAP)
2648 		data->enhanced_frame_cap = true;
2649 
2650 	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2651 	if (err < 0)
2652 		return err;
2653 
2654 	switch (data->phy_pattern) {
2655 	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2656 		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2657 				       &data->custom80, sizeof(data->custom80));
2658 		if (err < 0)
2659 			return err;
2660 
2661 		break;
2662 	case DP_PHY_TEST_PATTERN_CP2520:
2663 		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2664 				       &data->hbr2_reset,
2665 				       sizeof(data->hbr2_reset));
2666 		if (err < 0)
2667 			return err;
2668 	}
2669 
2670 	return 0;
2671 }
2672 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2673 
2674 /**
2675  * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2676  * @aux: DisplayPort AUX channel
2677  * @data: DP phy compliance test parameters.
2678  * @dp_rev: DP revision to use for compliance testing
2679  *
2680  * Returns 0 on success or a negative error code on failure.
2681  */
drm_dp_set_phy_test_pattern(struct drm_dp_aux * aux,struct drm_dp_phy_test_params * data,u8 dp_rev)2682 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2683 				struct drm_dp_phy_test_params *data, u8 dp_rev)
2684 {
2685 	int err, i;
2686 	u8 test_pattern;
2687 
2688 	test_pattern = data->phy_pattern;
2689 	if (dp_rev < 0x12) {
2690 		test_pattern = (test_pattern << 2) &
2691 			       DP_LINK_QUAL_PATTERN_11_MASK;
2692 		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2693 					 test_pattern);
2694 		if (err < 0)
2695 			return err;
2696 	} else {
2697 		for (i = 0; i < data->num_lanes; i++) {
2698 			err = drm_dp_dpcd_writeb(aux,
2699 						 DP_LINK_QUAL_LANE0_SET + i,
2700 						 test_pattern);
2701 			if (err < 0)
2702 				return err;
2703 		}
2704 	}
2705 
2706 	return 0;
2707 }
2708 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2709 
dp_pixelformat_get_name(enum dp_pixelformat pixelformat)2710 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2711 {
2712 	if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2713 		return "Invalid";
2714 
2715 	switch (pixelformat) {
2716 	case DP_PIXELFORMAT_RGB:
2717 		return "RGB";
2718 	case DP_PIXELFORMAT_YUV444:
2719 		return "YUV444";
2720 	case DP_PIXELFORMAT_YUV422:
2721 		return "YUV422";
2722 	case DP_PIXELFORMAT_YUV420:
2723 		return "YUV420";
2724 	case DP_PIXELFORMAT_Y_ONLY:
2725 		return "Y_ONLY";
2726 	case DP_PIXELFORMAT_RAW:
2727 		return "RAW";
2728 	default:
2729 		return "Reserved";
2730 	}
2731 }
2732 
dp_colorimetry_get_name(enum dp_pixelformat pixelformat,enum dp_colorimetry colorimetry)2733 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2734 					   enum dp_colorimetry colorimetry)
2735 {
2736 	if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2737 		return "Invalid";
2738 
2739 	switch (colorimetry) {
2740 	case DP_COLORIMETRY_DEFAULT:
2741 		switch (pixelformat) {
2742 		case DP_PIXELFORMAT_RGB:
2743 			return "sRGB";
2744 		case DP_PIXELFORMAT_YUV444:
2745 		case DP_PIXELFORMAT_YUV422:
2746 		case DP_PIXELFORMAT_YUV420:
2747 			return "BT.601";
2748 		case DP_PIXELFORMAT_Y_ONLY:
2749 			return "DICOM PS3.14";
2750 		case DP_PIXELFORMAT_RAW:
2751 			return "Custom Color Profile";
2752 		default:
2753 			return "Reserved";
2754 		}
2755 	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
2756 		switch (pixelformat) {
2757 		case DP_PIXELFORMAT_RGB:
2758 			return "Wide Fixed";
2759 		case DP_PIXELFORMAT_YUV444:
2760 		case DP_PIXELFORMAT_YUV422:
2761 		case DP_PIXELFORMAT_YUV420:
2762 			return "BT.709";
2763 		default:
2764 			return "Reserved";
2765 		}
2766 	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
2767 		switch (pixelformat) {
2768 		case DP_PIXELFORMAT_RGB:
2769 			return "Wide Float";
2770 		case DP_PIXELFORMAT_YUV444:
2771 		case DP_PIXELFORMAT_YUV422:
2772 		case DP_PIXELFORMAT_YUV420:
2773 			return "xvYCC 601";
2774 		default:
2775 			return "Reserved";
2776 		}
2777 	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
2778 		switch (pixelformat) {
2779 		case DP_PIXELFORMAT_RGB:
2780 			return "OpRGB";
2781 		case DP_PIXELFORMAT_YUV444:
2782 		case DP_PIXELFORMAT_YUV422:
2783 		case DP_PIXELFORMAT_YUV420:
2784 			return "xvYCC 709";
2785 		default:
2786 			return "Reserved";
2787 		}
2788 	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
2789 		switch (pixelformat) {
2790 		case DP_PIXELFORMAT_RGB:
2791 			return "DCI-P3";
2792 		case DP_PIXELFORMAT_YUV444:
2793 		case DP_PIXELFORMAT_YUV422:
2794 		case DP_PIXELFORMAT_YUV420:
2795 			return "sYCC 601";
2796 		default:
2797 			return "Reserved";
2798 		}
2799 	case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
2800 		switch (pixelformat) {
2801 		case DP_PIXELFORMAT_RGB:
2802 			return "Custom Profile";
2803 		case DP_PIXELFORMAT_YUV444:
2804 		case DP_PIXELFORMAT_YUV422:
2805 		case DP_PIXELFORMAT_YUV420:
2806 			return "OpYCC 601";
2807 		default:
2808 			return "Reserved";
2809 		}
2810 	case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
2811 		switch (pixelformat) {
2812 		case DP_PIXELFORMAT_RGB:
2813 			return "BT.2020 RGB";
2814 		case DP_PIXELFORMAT_YUV444:
2815 		case DP_PIXELFORMAT_YUV422:
2816 		case DP_PIXELFORMAT_YUV420:
2817 			return "BT.2020 CYCC";
2818 		default:
2819 			return "Reserved";
2820 		}
2821 	case DP_COLORIMETRY_BT2020_YCC:
2822 		switch (pixelformat) {
2823 		case DP_PIXELFORMAT_YUV444:
2824 		case DP_PIXELFORMAT_YUV422:
2825 		case DP_PIXELFORMAT_YUV420:
2826 			return "BT.2020 YCC";
2827 		default:
2828 			return "Reserved";
2829 		}
2830 	default:
2831 		return "Invalid";
2832 	}
2833 }
2834 
dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)2835 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2836 {
2837 	switch (dynamic_range) {
2838 	case DP_DYNAMIC_RANGE_VESA:
2839 		return "VESA range";
2840 	case DP_DYNAMIC_RANGE_CTA:
2841 		return "CTA range";
2842 	default:
2843 		return "Invalid";
2844 	}
2845 }
2846 
dp_content_type_get_name(enum dp_content_type content_type)2847 static const char *dp_content_type_get_name(enum dp_content_type content_type)
2848 {
2849 	switch (content_type) {
2850 	case DP_CONTENT_TYPE_NOT_DEFINED:
2851 		return "Not defined";
2852 	case DP_CONTENT_TYPE_GRAPHICS:
2853 		return "Graphics";
2854 	case DP_CONTENT_TYPE_PHOTO:
2855 		return "Photo";
2856 	case DP_CONTENT_TYPE_VIDEO:
2857 		return "Video";
2858 	case DP_CONTENT_TYPE_GAME:
2859 		return "Game";
2860 	default:
2861 		return "Reserved";
2862 	}
2863 }
2864 
drm_dp_vsc_sdp_log(const char * level,struct device * dev,const struct drm_dp_vsc_sdp * vsc)2865 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
2866 			const struct drm_dp_vsc_sdp *vsc)
2867 {
2868 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
2869 	DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
2870 		   vsc->revision, vsc->length);
2871 	DP_SDP_LOG("    pixelformat: %s\n",
2872 		   dp_pixelformat_get_name(vsc->pixelformat));
2873 	DP_SDP_LOG("    colorimetry: %s\n",
2874 		   dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2875 	DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
2876 	DP_SDP_LOG("    dynamic range: %s\n",
2877 		   dp_dynamic_range_get_name(vsc->dynamic_range));
2878 	DP_SDP_LOG("    content type: %s\n",
2879 		   dp_content_type_get_name(vsc->content_type));
2880 #undef DP_SDP_LOG
2881 }
2882 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
2883 
2884 /**
2885  * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
2886  * @dpcd: DisplayPort configuration data
2887  * @port_cap: port capabilities
2888  *
2889  * Returns maximum frl bandwidth supported by PCON in GBPS,
2890  * returns 0 if not supported.
2891  */
drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])2892 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2893 			       const u8 port_cap[4])
2894 {
2895 	int bw;
2896 	u8 buf;
2897 
2898 	buf = port_cap[2];
2899 	bw = buf & DP_PCON_MAX_FRL_BW;
2900 
2901 	switch (bw) {
2902 	case DP_PCON_MAX_9GBPS:
2903 		return 9;
2904 	case DP_PCON_MAX_18GBPS:
2905 		return 18;
2906 	case DP_PCON_MAX_24GBPS:
2907 		return 24;
2908 	case DP_PCON_MAX_32GBPS:
2909 		return 32;
2910 	case DP_PCON_MAX_40GBPS:
2911 		return 40;
2912 	case DP_PCON_MAX_48GBPS:
2913 		return 48;
2914 	case DP_PCON_MAX_0GBPS:
2915 	default:
2916 		return 0;
2917 	}
2918 
2919 	return 0;
2920 }
2921 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
2922 
2923 /**
2924  * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
2925  * @aux: DisplayPort AUX channel
2926  * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
2927  *
2928  * Returns 0 if success, else returns negative error code.
2929  */
drm_dp_pcon_frl_prepare(struct drm_dp_aux * aux,bool enable_frl_ready_hpd)2930 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
2931 {
2932 	int ret;
2933 	u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
2934 		 DP_PCON_ENABLE_LINK_FRL_MODE;
2935 
2936 	if (enable_frl_ready_hpd)
2937 		buf |= DP_PCON_ENABLE_HPD_READY;
2938 
2939 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2940 
2941 	return ret;
2942 }
2943 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
2944 
2945 /**
2946  * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
2947  * @aux: DisplayPort AUX channel
2948  *
2949  * Returns true if success, else returns false.
2950  */
drm_dp_pcon_is_frl_ready(struct drm_dp_aux * aux)2951 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
2952 {
2953 	int ret;
2954 	u8 buf;
2955 
2956 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2957 	if (ret < 0)
2958 		return false;
2959 
2960 	if (buf & DP_PCON_FRL_READY)
2961 		return true;
2962 
2963 	return false;
2964 }
2965 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
2966 
2967 /**
2968  * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
2969  * @aux: DisplayPort AUX channel
2970  * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
2971  * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
2972  * In Concurrent Mode, the FRL link bring up can be done along with
2973  * DP Link training. In Sequential mode, the FRL link bring up is done prior to
2974  * the DP Link training.
2975  *
2976  * Returns 0 if success, else returns negative error code.
2977  */
2978 
drm_dp_pcon_frl_configure_1(struct drm_dp_aux * aux,int max_frl_gbps,u8 frl_mode)2979 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2980 				u8 frl_mode)
2981 {
2982 	int ret;
2983 	u8 buf;
2984 
2985 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
2986 	if (ret < 0)
2987 		return ret;
2988 
2989 	if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
2990 		buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
2991 	else
2992 		buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
2993 
2994 	switch (max_frl_gbps) {
2995 	case 9:
2996 		buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS;
2997 		break;
2998 	case 18:
2999 		buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS;
3000 		break;
3001 	case 24:
3002 		buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS;
3003 		break;
3004 	case 32:
3005 		buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS;
3006 		break;
3007 	case 40:
3008 		buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS;
3009 		break;
3010 	case 48:
3011 		buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS;
3012 		break;
3013 	case 0:
3014 		buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS;
3015 		break;
3016 	default:
3017 		return -EINVAL;
3018 	}
3019 
3020 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3021 	if (ret < 0)
3022 		return ret;
3023 
3024 	return 0;
3025 }
3026 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
3027 
3028 /**
3029  * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3030  * @aux: DisplayPort AUX channel
3031  * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
3032  * @frl_type : FRL training type, can be Extended, or Normal.
3033  * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
3034  * starting from min, and stops when link training is successful. In Extended
3035  * FRL training, all frl bw selected in the mask are trained by the PCON.
3036  *
3037  * Returns 0 if success, else returns negative error code.
3038  */
drm_dp_pcon_frl_configure_2(struct drm_dp_aux * aux,int max_frl_mask,u8 frl_type)3039 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
3040 				u8 frl_type)
3041 {
3042 	int ret;
3043 	u8 buf = max_frl_mask;
3044 
3045 	if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
3046 		buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3047 	else
3048 		buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3049 
3050 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
3051 	if (ret < 0)
3052 		return ret;
3053 
3054 	return 0;
3055 }
3056 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
3057 
3058 /**
3059  * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3060  * @aux: DisplayPort AUX channel
3061  *
3062  * Returns 0 if success, else returns negative error code.
3063  */
drm_dp_pcon_reset_frl_config(struct drm_dp_aux * aux)3064 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
3065 {
3066 	int ret;
3067 
3068 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
3069 	if (ret < 0)
3070 		return ret;
3071 
3072 	return 0;
3073 }
3074 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
3075 
3076 /**
3077  * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3078  * @aux: DisplayPort AUX channel
3079  *
3080  * Returns 0 if success, else returns negative error code.
3081  */
drm_dp_pcon_frl_enable(struct drm_dp_aux * aux)3082 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
3083 {
3084 	int ret;
3085 	u8 buf = 0;
3086 
3087 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
3088 	if (ret < 0)
3089 		return ret;
3090 	if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
3091 		drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
3092 			    aux->name);
3093 		return -EINVAL;
3094 	}
3095 	buf |= DP_PCON_ENABLE_HDMI_LINK;
3096 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3097 	if (ret < 0)
3098 		return ret;
3099 
3100 	return 0;
3101 }
3102 EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
3103 
3104 /**
3105  * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3106  * @aux: DisplayPort AUX channel
3107  *
3108  * Returns true if link is active else returns false.
3109  */
drm_dp_pcon_hdmi_link_active(struct drm_dp_aux * aux)3110 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
3111 {
3112 	u8 buf;
3113 	int ret;
3114 
3115 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
3116 	if (ret < 0)
3117 		return false;
3118 
3119 	return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
3120 }
3121 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
3122 
3123 /**
3124  * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3125  * @aux: DisplayPort AUX channel
3126  * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
3127  * Valid only if the MODE returned is FRL. For Normal Link training mode
3128  * only 1 of the bits will be set, but in case of Extended mode, more than
3129  * one bits can be set.
3130  *
3131  * Returns the link mode : TMDS or FRL on success, else returns negative error
3132  * code.
3133  */
drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux * aux,u8 * frl_trained_mask)3134 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
3135 {
3136 	u8 buf;
3137 	int mode;
3138 	int ret;
3139 
3140 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
3141 	if (ret < 0)
3142 		return ret;
3143 
3144 	mode = buf & DP_PCON_HDMI_LINK_MODE;
3145 
3146 	if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
3147 		*frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
3148 
3149 	return mode;
3150 }
3151 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
3152 
3153 /**
3154  * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3155  * during link failure between PCON and HDMI sink
3156  * @aux: DisplayPort AUX channel
3157  * @connector: DRM connector
3158  * code.
3159  **/
3160 
drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux * aux,struct drm_connector * connector)3161 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
3162 					   struct drm_connector *connector)
3163 {
3164 	u8 buf, error_count;
3165 	int i, num_error;
3166 	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3167 
3168 	for (i = 0; i < hdmi->max_lanes; i++) {
3169 		if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)
3170 			return;
3171 
3172 		error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
3173 		switch (error_count) {
3174 		case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
3175 			num_error = 100;
3176 			break;
3177 		case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
3178 			num_error = 10;
3179 			break;
3180 		case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
3181 			num_error = 3;
3182 			break;
3183 		default:
3184 			num_error = 0;
3185 		}
3186 
3187 		drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
3188 			aux->name, num_error, i);
3189 	}
3190 }
3191 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
3192 
3193 /*
3194  * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3195  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3196  *
3197  * Returns true is PCON encoder is DSC 1.2 else returns false.
3198  */
drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])3199 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3200 {
3201 	u8 buf;
3202 	u8 major_v, minor_v;
3203 
3204 	buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
3205 	major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
3206 	minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
3207 
3208 	if (major_v == 1 && minor_v == 2)
3209 		return true;
3210 
3211 	return false;
3212 }
3213 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
3214 
3215 /*
3216  * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3217  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3218  *
3219  * Returns maximum no. of slices supported by the PCON DSC Encoder.
3220  */
drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])3221 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3222 {
3223 	u8 slice_cap1, slice_cap2;
3224 
3225 	slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
3226 	slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
3227 
3228 	if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
3229 		return 24;
3230 	if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
3231 		return 20;
3232 	if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
3233 		return 16;
3234 	if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
3235 		return 12;
3236 	if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
3237 		return 10;
3238 	if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
3239 		return 8;
3240 	if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
3241 		return 6;
3242 	if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
3243 		return 4;
3244 	if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
3245 		return 2;
3246 	if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
3247 		return 1;
3248 
3249 	return 0;
3250 }
3251 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
3252 
3253 /*
3254  * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3255  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3256  *
3257  * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
3258  */
drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])3259 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3260 {
3261 	u8 buf;
3262 
3263 	buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
3264 
3265 	return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
3266 }
3267 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
3268 
3269 /*
3270  * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3271  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3272  *
3273  * Returns the bpp precision supported by the PCON encoder.
3274  */
drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])3275 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3276 {
3277 	u8 buf;
3278 
3279 	buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
3280 
3281 	switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
3282 	case DP_PCON_DSC_ONE_16TH_BPP:
3283 		return 16;
3284 	case DP_PCON_DSC_ONE_8TH_BPP:
3285 		return 8;
3286 	case DP_PCON_DSC_ONE_4TH_BPP:
3287 		return 4;
3288 	case DP_PCON_DSC_ONE_HALF_BPP:
3289 		return 2;
3290 	case DP_PCON_DSC_ONE_BPP:
3291 		return 1;
3292 	}
3293 
3294 	return 0;
3295 }
3296 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
3297 
3298 static
drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux * aux,u8 pps_buf_config)3299 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
3300 {
3301 	u8 buf;
3302 	int ret;
3303 
3304 	ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3305 	if (ret < 0)
3306 		return ret;
3307 
3308 	buf |= DP_PCON_ENABLE_DSC_ENCODER;
3309 
3310 	if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
3311 		buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
3312 		buf |= pps_buf_config << 2;
3313 	}
3314 
3315 	ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3316 	if (ret < 0)
3317 		return ret;
3318 
3319 	return 0;
3320 }
3321 
3322 /**
3323  * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3324  * for DSC1.2 between PCON & HDMI2.1 sink
3325  * @aux: DisplayPort AUX channel
3326  *
3327  * Returns 0 on success, else returns negative error code.
3328  */
drm_dp_pcon_pps_default(struct drm_dp_aux * aux)3329 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3330 {
3331 	int ret;
3332 
3333 	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
3334 	if (ret < 0)
3335 		return ret;
3336 
3337 	return 0;
3338 }
3339 EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3340 
3341 /**
3342  * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3343  * HDMI sink
3344  * @aux: DisplayPort AUX channel
3345  * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
3346  *
3347  * Returns 0 on success, else returns negative error code.
3348  */
drm_dp_pcon_pps_override_buf(struct drm_dp_aux * aux,u8 pps_buf[128])3349 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3350 {
3351 	int ret;
3352 
3353 	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
3354 	if (ret < 0)
3355 		return ret;
3356 
3357 	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3358 	if (ret < 0)
3359 		return ret;
3360 
3361 	return 0;
3362 }
3363 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3364 
3365 /*
3366  * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3367  * override registers
3368  * @aux: DisplayPort AUX channel
3369  * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
3370  * bits_per_pixel.
3371  *
3372  * Returns 0 on success, else returns negative error code.
3373  */
drm_dp_pcon_pps_override_param(struct drm_dp_aux * aux,u8 pps_param[6])3374 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3375 {
3376 	int ret;
3377 
3378 	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
3379 	if (ret < 0)
3380 		return ret;
3381 	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
3382 	if (ret < 0)
3383 		return ret;
3384 	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
3385 	if (ret < 0)
3386 		return ret;
3387 
3388 	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3389 	if (ret < 0)
3390 		return ret;
3391 
3392 	return 0;
3393 }
3394 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3395 
3396 /*
3397  * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3398  * @aux: displayPort AUX channel
3399  * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3400  *
3401  * Returns 0 on success, else returns negative error code.
3402  */
drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux * aux,u8 color_spc)3403 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3404 {
3405 	int ret;
3406 	u8 buf;
3407 
3408 	ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3409 	if (ret < 0)
3410 		return ret;
3411 
3412 	if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3413 		buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3414 	else
3415 		buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3416 
3417 	ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3418 	if (ret < 0)
3419 		return ret;
3420 
3421 	return 0;
3422 }
3423 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
3424 
3425 /**
3426  * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3427  * @aux: The DP AUX channel to use
3428  * @bl: Backlight capability info from drm_edp_backlight_init()
3429  * @level: The brightness level to set
3430  *
3431  * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
3432  * already have been enabled by the driver by calling drm_edp_backlight_enable().
3433  *
3434  * Returns: %0 on success, negative error code on failure
3435  */
drm_edp_backlight_set_level(struct drm_dp_aux * aux,const struct drm_edp_backlight_info * bl,u16 level)3436 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3437 				u16 level)
3438 {
3439 	int ret;
3440 	u8 buf[2] = { 0 };
3441 
3442 	/* The panel uses the PWM for controlling brightness levels */
3443 	if (!bl->aux_set)
3444 		return 0;
3445 
3446 	if (bl->lsb_reg_used) {
3447 		buf[0] = (level & 0xff00) >> 8;
3448 		buf[1] = (level & 0x00ff);
3449 	} else {
3450 		buf[0] = level;
3451 	}
3452 
3453 	ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
3454 	if (ret != sizeof(buf)) {
3455 		drm_err(aux->drm_dev,
3456 			"%s: Failed to write aux backlight level: %d\n",
3457 			aux->name, ret);
3458 		return ret < 0 ? ret : -EIO;
3459 	}
3460 
3461 	return 0;
3462 }
3463 EXPORT_SYMBOL(drm_edp_backlight_set_level);
3464 
3465 static int
drm_edp_backlight_set_enable(struct drm_dp_aux * aux,const struct drm_edp_backlight_info * bl,bool enable)3466 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3467 			     bool enable)
3468 {
3469 	int ret;
3470 	u8 buf;
3471 
3472 	/* This panel uses the EDP_BL_PWR GPIO for enablement */
3473 	if (!bl->aux_enable)
3474 		return 0;
3475 
3476 	ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
3477 	if (ret != 1) {
3478 		drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
3479 			aux->name, ret);
3480 		return ret < 0 ? ret : -EIO;
3481 	}
3482 	if (enable)
3483 		buf |= DP_EDP_BACKLIGHT_ENABLE;
3484 	else
3485 		buf &= ~DP_EDP_BACKLIGHT_ENABLE;
3486 
3487 	ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
3488 	if (ret != 1) {
3489 		drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
3490 			aux->name, ret);
3491 		return ret < 0 ? ret : -EIO;
3492 	}
3493 
3494 	return 0;
3495 }
3496 
3497 /**
3498  * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
3499  * @aux: The DP AUX channel to use
3500  * @bl: Backlight capability info from drm_edp_backlight_init()
3501  * @level: The initial backlight level to set via AUX, if there is one
3502  *
3503  * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
3504  * restoring any important backlight state such as the given backlight level, the brightness byte
3505  * count, backlight frequency, etc.
3506  *
3507  * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3508  * that the driver handle enabling/disabling the panel through implementation-specific means using
3509  * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3510  * this function becomes a no-op, and the driver is expected to handle powering the panel on using
3511  * the EDP_BL_PWR GPIO.
3512  *
3513  * Returns: %0 on success, negative error code on failure.
3514  */
drm_edp_backlight_enable(struct drm_dp_aux * aux,const struct drm_edp_backlight_info * bl,const u16 level)3515 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3516 			     const u16 level)
3517 {
3518 	int ret;
3519 	u8 dpcd_buf;
3520 
3521 	if (bl->aux_set)
3522 		dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
3523 	else
3524 		dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
3525 
3526 	if (bl->pwmgen_bit_count) {
3527 		ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
3528 		if (ret != 1)
3529 			drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3530 				    aux->name, ret);
3531 	}
3532 
3533 	if (bl->pwm_freq_pre_divider) {
3534 		ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
3535 		if (ret != 1)
3536 			drm_dbg_kms(aux->drm_dev,
3537 				    "%s: Failed to write aux backlight frequency: %d\n",
3538 				    aux->name, ret);
3539 		else
3540 			dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
3541 	}
3542 
3543 	ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf);
3544 	if (ret != 1) {
3545 		drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
3546 			    aux->name, ret);
3547 		return ret < 0 ? ret : -EIO;
3548 	}
3549 
3550 	ret = drm_edp_backlight_set_level(aux, bl, level);
3551 	if (ret < 0)
3552 		return ret;
3553 	ret = drm_edp_backlight_set_enable(aux, bl, true);
3554 	if (ret < 0)
3555 		return ret;
3556 
3557 	return 0;
3558 }
3559 EXPORT_SYMBOL(drm_edp_backlight_enable);
3560 
3561 /**
3562  * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
3563  * @aux: The DP AUX channel to use
3564  * @bl: Backlight capability info from drm_edp_backlight_init()
3565  *
3566  * This function handles disabling DPCD backlight controls on a panel over AUX.
3567  *
3568  * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3569  * that the driver handle enabling/disabling the panel through implementation-specific means using
3570  * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3571  * this function becomes a no-op, and the driver is expected to handle powering the panel off using
3572  * the EDP_BL_PWR GPIO.
3573  *
3574  * Returns: %0 on success or no-op, negative error code on failure.
3575  */
drm_edp_backlight_disable(struct drm_dp_aux * aux,const struct drm_edp_backlight_info * bl)3576 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
3577 {
3578 	int ret;
3579 
3580 	ret = drm_edp_backlight_set_enable(aux, bl, false);
3581 	if (ret < 0)
3582 		return ret;
3583 
3584 	return 0;
3585 }
3586 EXPORT_SYMBOL(drm_edp_backlight_disable);
3587 
3588 static inline int
drm_edp_backlight_probe_max(struct drm_dp_aux * aux,struct drm_edp_backlight_info * bl,u16 driver_pwm_freq_hz,const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])3589 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3590 			    u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
3591 {
3592 	int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
3593 	int ret;
3594 	u8 pn, pn_min, pn_max;
3595 
3596 	if (!bl->aux_set)
3597 		return 0;
3598 
3599 	ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
3600 	if (ret != 1) {
3601 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
3602 			    aux->name, ret);
3603 		return -ENODEV;
3604 	}
3605 
3606 	pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3607 	bl->max = (1 << pn) - 1;
3608 	if (!driver_pwm_freq_hz)
3609 		return 0;
3610 
3611 	/*
3612 	 * Set PWM Frequency divider to match desired frequency provided by the driver.
3613 	 * The PWM Frequency is calculated as 27Mhz / (F x P).
3614 	 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
3615 	 *             EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
3616 	 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
3617 	 *             EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
3618 	 */
3619 
3620 	/* Find desired value of (F x P)
3621 	 * Note that, if F x P is out of supported range, the maximum value or minimum value will
3622 	 * applied automatically. So no need to check that.
3623 	 */
3624 	fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
3625 
3626 	/* Use highest possible value of Pn for more granularity of brightness adjustment while
3627 	 * satisfying the conditions below.
3628 	 * - Pn is in the range of Pn_min and Pn_max
3629 	 * - F is in the range of 1 and 255
3630 	 * - FxP is within 25% of desired value.
3631 	 *   Note: 25% is arbitrary value and may need some tweak.
3632 	 */
3633 	ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
3634 	if (ret != 1) {
3635 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
3636 			    aux->name, ret);
3637 		return 0;
3638 	}
3639 	ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
3640 	if (ret != 1) {
3641 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
3642 			    aux->name, ret);
3643 		return 0;
3644 	}
3645 	pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3646 	pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3647 
3648 	/* Ensure frequency is within 25% of desired value */
3649 	fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
3650 	fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
3651 	if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
3652 		drm_dbg_kms(aux->drm_dev,
3653 			    "%s: Driver defined backlight frequency (%d) out of range\n",
3654 			    aux->name, driver_pwm_freq_hz);
3655 		return 0;
3656 	}
3657 
3658 	for (pn = pn_max; pn >= pn_min; pn--) {
3659 		f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
3660 		fxp_actual = f << pn;
3661 		if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
3662 			break;
3663 	}
3664 
3665 	ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
3666 	if (ret != 1) {
3667 		drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3668 			    aux->name, ret);
3669 		return 0;
3670 	}
3671 	bl->pwmgen_bit_count = pn;
3672 	bl->max = (1 << pn) - 1;
3673 
3674 	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
3675 		bl->pwm_freq_pre_divider = f;
3676 		drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
3677 			    aux->name, driver_pwm_freq_hz);
3678 	}
3679 
3680 	return 0;
3681 }
3682 
3683 static inline int
drm_edp_backlight_probe_state(struct drm_dp_aux * aux,struct drm_edp_backlight_info * bl,u8 * current_mode)3684 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3685 			      u8 *current_mode)
3686 {
3687 	int ret;
3688 	u8 buf[2];
3689 	u8 mode_reg;
3690 
3691 	ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
3692 	if (ret != 1) {
3693 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
3694 			    aux->name, ret);
3695 		return ret < 0 ? ret : -EIO;
3696 	}
3697 
3698 	*current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
3699 	if (!bl->aux_set)
3700 		return 0;
3701 
3702 	if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
3703 		int size = 1 + bl->lsb_reg_used;
3704 
3705 		ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
3706 		if (ret != size) {
3707 			drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
3708 				    aux->name, ret);
3709 			return ret < 0 ? ret : -EIO;
3710 		}
3711 
3712 		if (bl->lsb_reg_used)
3713 			return (buf[0] << 8) | buf[1];
3714 		else
3715 			return buf[0];
3716 	}
3717 
3718 	/*
3719 	 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
3720 	 * the driver should assume max brightness
3721 	 */
3722 	return bl->max;
3723 }
3724 
3725 /**
3726  * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
3727  * interface.
3728  * @aux: The DP aux device to use for probing
3729  * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
3730  * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
3731  * @edp_dpcd: A cached copy of the eDP DPCD
3732  * @current_level: Where to store the probed brightness level, if any
3733  * @current_mode: Where to store the currently set backlight control mode
3734  *
3735  * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
3736  * along with also probing the current and maximum supported brightness levels.
3737  *
3738  * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
3739  * default frequency from the panel is used.
3740  *
3741  * Returns: %0 on success, negative error code on failure.
3742  */
3743 int
drm_edp_backlight_init(struct drm_dp_aux * aux,struct drm_edp_backlight_info * bl,u16 driver_pwm_freq_hz,const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],u16 * current_level,u8 * current_mode)3744 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3745 		       u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
3746 		       u16 *current_level, u8 *current_mode)
3747 {
3748 	int ret;
3749 
3750 	if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
3751 		bl->aux_enable = true;
3752 	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
3753 		bl->aux_set = true;
3754 	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
3755 		bl->lsb_reg_used = true;
3756 
3757 	/* Sanity check caps */
3758 	if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
3759 		drm_dbg_kms(aux->drm_dev,
3760 			    "%s: Panel supports neither AUX or PWM brightness control? Aborting\n",
3761 			    aux->name);
3762 		return -EINVAL;
3763 	}
3764 
3765 	ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
3766 	if (ret < 0)
3767 		return ret;
3768 
3769 	ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
3770 	if (ret < 0)
3771 		return ret;
3772 	*current_level = ret;
3773 
3774 	drm_dbg_kms(aux->drm_dev,
3775 		    "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",
3776 		    aux->name, bl->aux_set, bl->aux_enable, *current_mode);
3777 	if (bl->aux_set) {
3778 		drm_dbg_kms(aux->drm_dev,
3779 			    "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",
3780 			    aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,
3781 			    bl->lsb_reg_used);
3782 	}
3783 
3784 	return 0;
3785 }
3786 EXPORT_SYMBOL(drm_edp_backlight_init);
3787 
3788 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
3789 	(IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))
3790 
dp_aux_backlight_update_status(struct backlight_device * bd)3791 static int dp_aux_backlight_update_status(struct backlight_device *bd)
3792 {
3793 	struct dp_aux_backlight *bl = bl_get_data(bd);
3794 	u16 brightness = backlight_get_brightness(bd);
3795 	int ret = 0;
3796 
3797 	if (!backlight_is_blank(bd)) {
3798 		if (!bl->enabled) {
3799 			drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
3800 			bl->enabled = true;
3801 			return 0;
3802 		}
3803 		ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
3804 	} else {
3805 		if (bl->enabled) {
3806 			drm_edp_backlight_disable(bl->aux, &bl->info);
3807 			bl->enabled = false;
3808 		}
3809 	}
3810 
3811 	return ret;
3812 }
3813 
3814 static const struct backlight_ops dp_aux_bl_ops = {
3815 	.update_status = dp_aux_backlight_update_status,
3816 };
3817 
3818 /**
3819  * drm_panel_dp_aux_backlight - create and use DP AUX backlight
3820  * @panel: DRM panel
3821  * @aux: The DP AUX channel to use
3822  *
3823  * Use this function to create and handle backlight if your panel
3824  * supports backlight control over DP AUX channel using DPCD
3825  * registers as per VESA's standard backlight control interface.
3826  *
3827  * When the panel is enabled backlight will be enabled after a
3828  * successful call to &drm_panel_funcs.enable()
3829  *
3830  * When the panel is disabled backlight will be disabled before the
3831  * call to &drm_panel_funcs.disable().
3832  *
3833  * A typical implementation for a panel driver supporting backlight
3834  * control over DP AUX will call this function at probe time.
3835  * Backlight will then be handled transparently without requiring
3836  * any intervention from the driver.
3837  *
3838  * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init().
3839  *
3840  * Return: 0 on success or a negative error code on failure.
3841  */
drm_panel_dp_aux_backlight(struct drm_panel * panel,struct drm_dp_aux * aux)3842 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
3843 {
3844 	struct dp_aux_backlight *bl;
3845 	struct backlight_properties props = { 0 };
3846 	u16 current_level;
3847 	u8 current_mode;
3848 	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
3849 	int ret;
3850 
3851 	if (!panel || !panel->dev || !aux)
3852 		return -EINVAL;
3853 
3854 	ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd,
3855 			       EDP_DISPLAY_CTL_CAP_SIZE);
3856 	if (ret < 0)
3857 		return ret;
3858 
3859 	if (!drm_edp_backlight_supported(edp_dpcd)) {
3860 		DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n");
3861 		return 0;
3862 	}
3863 
3864 	bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL);
3865 	if (!bl)
3866 		return -ENOMEM;
3867 
3868 	bl->aux = aux;
3869 
3870 	ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
3871 				     &current_level, &current_mode);
3872 	if (ret < 0)
3873 		return ret;
3874 
3875 	props.type = BACKLIGHT_RAW;
3876 	props.brightness = current_level;
3877 	props.max_brightness = bl->info.max;
3878 
3879 	bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight",
3880 						  panel->dev, bl,
3881 						  &dp_aux_bl_ops, &props);
3882 	if (IS_ERR(bl->base))
3883 		return PTR_ERR(bl->base);
3884 
3885 	backlight_disable(bl->base);
3886 
3887 	panel->backlight = bl->base;
3888 
3889 	return 0;
3890 }
3891 EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
3892 
3893 #endif
3894