1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
9 
10 #include <linux/debugfs.h>
11 #include <linux/dma-buf.h>
12 
13 #include <drm/drm_atomic.h>
14 #include <drm/drm_atomic_uapi.h>
15 #include <drm/drm_blend.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_framebuffer.h>
18 #include <drm/drm_gem_atomic_helper.h>
19 
20 #include "msm_drv.h"
21 #include "dpu_kms.h"
22 #include "dpu_formats.h"
23 #include "dpu_hw_sspp.h"
24 #include "dpu_trace.h"
25 #include "dpu_crtc.h"
26 #include "dpu_vbif.h"
27 #include "dpu_plane.h"
28 
29 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
30 		(pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
31 
32 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
33 		(pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
34 
35 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
36 #define PHASE_STEP_SHIFT	21
37 #define PHASE_STEP_UNIT_SCALE   ((int) (1 << PHASE_STEP_SHIFT))
38 #define PHASE_RESIDUAL		15
39 
40 #define SHARP_STRENGTH_DEFAULT	32
41 #define SHARP_EDGE_THR_DEFAULT	112
42 #define SHARP_SMOOTH_THR_DEFAULT	8
43 #define SHARP_NOISE_THR_DEFAULT	2
44 
45 #define DPU_NAME_SIZE  12
46 
47 #define DPU_PLANE_COLOR_FILL_FLAG	BIT(31)
48 #define DPU_ZPOS_MAX 255
49 
50 /* multirect rect index */
51 enum {
52 	R0,
53 	R1,
54 	R_MAX
55 };
56 
57 /*
58  * Default Preload Values
59  */
60 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
61 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
62 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2
63 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4
64 
65 #define DEFAULT_REFRESH_RATE	60
66 
67 static const uint32_t qcom_compressed_supported_formats[] = {
68 	DRM_FORMAT_ABGR8888,
69 	DRM_FORMAT_ARGB8888,
70 	DRM_FORMAT_XBGR8888,
71 	DRM_FORMAT_XRGB8888,
72 	DRM_FORMAT_BGR565,
73 
74 	DRM_FORMAT_NV12,
75 };
76 
77 /**
78  * enum dpu_plane_qos - Different qos configurations for each pipe
79  *
80  * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
81  * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
82  *	this configuration is mutually exclusive from VBLANK_CTRL.
83  * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
84  */
85 enum dpu_plane_qos {
86 	DPU_PLANE_QOS_VBLANK_CTRL = BIT(0),
87 	DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
88 	DPU_PLANE_QOS_PANIC_CTRL = BIT(2),
89 };
90 
91 /*
92  * struct dpu_plane - local dpu plane structure
93  * @aspace: address space pointer
94  * @csc_ptr: Points to dpu_csc_cfg structure to use for current
95  * @catalog: Points to dpu catalog structure
96  * @revalidate: force revalidation of all the plane properties
97  */
98 struct dpu_plane {
99 	struct drm_plane base;
100 
101 	struct mutex lock;
102 
103 	enum dpu_sspp pipe;
104 
105 	struct dpu_hw_pipe *pipe_hw;
106 	uint32_t color_fill;
107 	bool is_error;
108 	bool is_rt_pipe;
109 	const struct dpu_mdss_cfg *catalog;
110 };
111 
112 static const uint64_t supported_format_modifiers[] = {
113 	DRM_FORMAT_MOD_QCOM_COMPRESSED,
114 	DRM_FORMAT_MOD_LINEAR,
115 	DRM_FORMAT_MOD_INVALID
116 };
117 
118 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
119 
_dpu_plane_get_kms(struct drm_plane * plane)120 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
121 {
122 	struct msm_drm_private *priv = plane->dev->dev_private;
123 
124 	return to_dpu_kms(priv->kms);
125 }
126 
127 /**
128  * _dpu_plane_calc_bw - calculate bandwidth required for a plane
129  * @plane: Pointer to drm plane.
130  * @fb:   Pointer to framebuffer associated with the given plane
131  * @pipe_cfg: Pointer to pipe configuration
132  * Result: Updates calculated bandwidth in the plane state.
133  * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
134  * Prefill BW Equation: line src bytes * line_time
135  */
_dpu_plane_calc_bw(struct drm_plane * plane,struct drm_framebuffer * fb,struct dpu_hw_pipe_cfg * pipe_cfg)136 static void _dpu_plane_calc_bw(struct drm_plane *plane,
137 	struct drm_framebuffer *fb,
138 	struct dpu_hw_pipe_cfg *pipe_cfg)
139 {
140 	struct dpu_plane_state *pstate;
141 	struct drm_display_mode *mode;
142 	const struct dpu_format *fmt = NULL;
143 	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
144 	int src_width, src_height, dst_height, fps;
145 	u64 plane_prefill_bw;
146 	u64 plane_bw;
147 	u32 hw_latency_lines;
148 	u64 scale_factor;
149 	int vbp, vpw, vfp;
150 
151 	pstate = to_dpu_plane_state(plane->state);
152 	mode = &plane->state->crtc->mode;
153 
154 	fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
155 
156 	src_width = drm_rect_width(&pipe_cfg->src_rect);
157 	src_height = drm_rect_height(&pipe_cfg->src_rect);
158 	dst_height = drm_rect_height(&pipe_cfg->dst_rect);
159 	fps = drm_mode_vrefresh(mode);
160 	vbp = mode->vtotal - mode->vsync_end;
161 	vpw = mode->vsync_end - mode->vsync_start;
162 	vfp = mode->vsync_start - mode->vdisplay;
163 	hw_latency_lines =  dpu_kms->catalog->perf->min_prefill_lines;
164 	scale_factor = src_height > dst_height ?
165 		mult_frac(src_height, 1, dst_height) : 1;
166 
167 	plane_bw =
168 		src_width * mode->vtotal * fps * fmt->bpp *
169 		scale_factor;
170 
171 	plane_prefill_bw =
172 		src_width * hw_latency_lines * fps * fmt->bpp *
173 		scale_factor * mode->vtotal;
174 
175 	if ((vbp+vpw) > hw_latency_lines)
176 		do_div(plane_prefill_bw, (vbp+vpw));
177 	else if ((vbp+vpw+vfp) < hw_latency_lines)
178 		do_div(plane_prefill_bw, (vbp+vpw+vfp));
179 	else
180 		do_div(plane_prefill_bw, hw_latency_lines);
181 
182 
183 	pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
184 }
185 
186 /**
187  * _dpu_plane_calc_clk - calculate clock required for a plane
188  * @plane: Pointer to drm plane.
189  * @pipe_cfg: Pointer to pipe configuration
190  * Result: Updates calculated clock in the plane state.
191  * Clock equation: dst_w * v_total * fps * (src_h / dst_h)
192  */
_dpu_plane_calc_clk(struct drm_plane * plane,struct dpu_hw_pipe_cfg * pipe_cfg)193 static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg)
194 {
195 	struct dpu_plane_state *pstate;
196 	struct drm_display_mode *mode;
197 	int dst_width, src_height, dst_height, fps;
198 
199 	pstate = to_dpu_plane_state(plane->state);
200 	mode = &plane->state->crtc->mode;
201 
202 	src_height = drm_rect_height(&pipe_cfg->src_rect);
203 	dst_width = drm_rect_width(&pipe_cfg->dst_rect);
204 	dst_height = drm_rect_height(&pipe_cfg->dst_rect);
205 	fps = drm_mode_vrefresh(mode);
206 
207 	pstate->plane_clk =
208 		dst_width * mode->vtotal * fps;
209 
210 	if (src_height > dst_height) {
211 		pstate->plane_clk *= src_height;
212 		do_div(pstate->plane_clk, dst_height);
213 	}
214 }
215 
216 /**
217  * _dpu_plane_calc_fill_level - calculate fill level of the given source format
218  * @plane:		Pointer to drm plane
219  * @fmt:		Pointer to source buffer format
220  * @src_width:		width of source buffer
221  * Return: fill level corresponding to the source buffer/format or 0 if error
222  */
_dpu_plane_calc_fill_level(struct drm_plane * plane,const struct dpu_format * fmt,u32 src_width)223 static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
224 		const struct dpu_format *fmt, u32 src_width)
225 {
226 	struct dpu_plane *pdpu;
227 	struct dpu_plane_state *pstate;
228 	u32 fixed_buff_size;
229 	u32 total_fl;
230 
231 	if (!fmt || !plane->state || !src_width || !fmt->bpp) {
232 		DPU_ERROR("invalid arguments\n");
233 		return 0;
234 	}
235 
236 	pdpu = to_dpu_plane(plane);
237 	pstate = to_dpu_plane_state(plane->state);
238 	fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
239 
240 	/* FIXME: in multirect case account for the src_width of all the planes */
241 
242 	if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
243 		if (fmt->chroma_sample == DPU_CHROMA_420) {
244 			/* NV12 */
245 			total_fl = (fixed_buff_size / 2) /
246 				((src_width + 32) * fmt->bpp);
247 		} else {
248 			/* non NV12 */
249 			total_fl = (fixed_buff_size / 2) * 2 /
250 				((src_width + 32) * fmt->bpp);
251 		}
252 	} else {
253 		if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
254 			total_fl = (fixed_buff_size / 2) * 2 /
255 				((src_width + 32) * fmt->bpp);
256 		} else {
257 			total_fl = (fixed_buff_size) * 2 /
258 				((src_width + 32) * fmt->bpp);
259 		}
260 	}
261 
262 	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
263 			pdpu->pipe - SSPP_VIG0,
264 			(char *)&fmt->base.pixel_format,
265 			src_width, total_fl);
266 
267 	return total_fl;
268 }
269 
270 /**
271  * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
272  * @plane:		Pointer to drm plane
273  * @fb:			Pointer to framebuffer associated with the given plane
274  * @pipe_cfg:		Pointer to pipe configuration
275  */
_dpu_plane_set_qos_lut(struct drm_plane * plane,struct drm_framebuffer * fb,struct dpu_hw_pipe_cfg * pipe_cfg)276 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
277 		struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
278 {
279 	struct dpu_plane *pdpu = to_dpu_plane(plane);
280 	const struct dpu_format *fmt = NULL;
281 	u64 qos_lut;
282 	u32 total_fl = 0, lut_usage;
283 
284 	if (!pdpu->is_rt_pipe) {
285 		lut_usage = DPU_QOS_LUT_USAGE_NRT;
286 	} else {
287 		fmt = dpu_get_dpu_format_ext(
288 				fb->format->format,
289 				fb->modifier);
290 		total_fl = _dpu_plane_calc_fill_level(plane, fmt,
291 				drm_rect_width(&pipe_cfg->src_rect));
292 
293 		if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
294 			lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
295 		else
296 			lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
297 	}
298 
299 	qos_lut = _dpu_hw_get_qos_lut(
300 			&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
301 
302 	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
303 			(fmt) ? fmt->base.pixel_format : 0,
304 			pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
305 
306 	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
307 			pdpu->pipe - SSPP_VIG0,
308 			fmt ? (char *)&fmt->base.pixel_format : NULL,
309 			pdpu->is_rt_pipe, total_fl, qos_lut);
310 
311 	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
312 }
313 
314 /**
315  * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane
316  * @plane:		Pointer to drm plane
317  * @fb:			Pointer to framebuffer associated with the given plane
318  */
_dpu_plane_set_danger_lut(struct drm_plane * plane,struct drm_framebuffer * fb)319 static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
320 		struct drm_framebuffer *fb)
321 {
322 	struct dpu_plane *pdpu = to_dpu_plane(plane);
323 	const struct dpu_format *fmt = NULL;
324 	u32 danger_lut, safe_lut;
325 
326 	if (!pdpu->is_rt_pipe) {
327 		danger_lut = pdpu->catalog->perf->danger_lut_tbl
328 				[DPU_QOS_LUT_USAGE_NRT];
329 		safe_lut = pdpu->catalog->perf->safe_lut_tbl
330 				[DPU_QOS_LUT_USAGE_NRT];
331 	} else {
332 		fmt = dpu_get_dpu_format_ext(
333 				fb->format->format,
334 				fb->modifier);
335 
336 		if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
337 			danger_lut = pdpu->catalog->perf->danger_lut_tbl
338 					[DPU_QOS_LUT_USAGE_LINEAR];
339 			safe_lut = pdpu->catalog->perf->safe_lut_tbl
340 					[DPU_QOS_LUT_USAGE_LINEAR];
341 		} else {
342 			danger_lut = pdpu->catalog->perf->danger_lut_tbl
343 					[DPU_QOS_LUT_USAGE_MACROTILE];
344 			safe_lut = pdpu->catalog->perf->safe_lut_tbl
345 					[DPU_QOS_LUT_USAGE_MACROTILE];
346 		}
347 	}
348 
349 	trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
350 			(fmt) ? fmt->base.pixel_format : 0,
351 			(fmt) ? fmt->fetch_mode : 0,
352 			danger_lut,
353 			safe_lut);
354 
355 	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
356 		pdpu->pipe - SSPP_VIG0,
357 		fmt ? (char *)&fmt->base.pixel_format : NULL,
358 		fmt ? fmt->fetch_mode : -1,
359 		danger_lut,
360 		safe_lut);
361 
362 	pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
363 			danger_lut, safe_lut);
364 }
365 
366 /**
367  * _dpu_plane_set_qos_ctrl - set QoS control of the given plane
368  * @plane:		Pointer to drm plane
369  * @enable:		true to enable QoS control
370  * @flags:		QoS control mode (enum dpu_plane_qos)
371  */
_dpu_plane_set_qos_ctrl(struct drm_plane * plane,bool enable,u32 flags)372 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
373 	bool enable, u32 flags)
374 {
375 	struct dpu_plane *pdpu = to_dpu_plane(plane);
376 	struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
377 
378 	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
379 
380 	if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
381 		pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
382 		pipe_qos_cfg.danger_vblank =
383 				pdpu->pipe_hw->cap->sblk->danger_vblank;
384 		pipe_qos_cfg.vblank_en = enable;
385 	}
386 
387 	if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
388 		/* this feature overrules previous VBLANK_CTRL */
389 		pipe_qos_cfg.vblank_en = false;
390 		pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
391 	}
392 
393 	if (flags & DPU_PLANE_QOS_PANIC_CTRL)
394 		pipe_qos_cfg.danger_safe_en = enable;
395 
396 	if (!pdpu->is_rt_pipe) {
397 		pipe_qos_cfg.vblank_en = false;
398 		pipe_qos_cfg.danger_safe_en = false;
399 	}
400 
401 	DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
402 		pdpu->pipe - SSPP_VIG0,
403 		pipe_qos_cfg.danger_safe_en,
404 		pipe_qos_cfg.vblank_en,
405 		pipe_qos_cfg.creq_vblank,
406 		pipe_qos_cfg.danger_vblank,
407 		pdpu->is_rt_pipe);
408 
409 	pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
410 			&pipe_qos_cfg);
411 }
412 
413 /**
414  * _dpu_plane_set_ot_limit - set OT limit for the given plane
415  * @plane:		Pointer to drm plane
416  * @crtc:		Pointer to drm crtc
417  * @pipe_cfg:		Pointer to pipe configuration
418  */
_dpu_plane_set_ot_limit(struct drm_plane * plane,struct drm_crtc * crtc,struct dpu_hw_pipe_cfg * pipe_cfg)419 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
420 		struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
421 {
422 	struct dpu_plane *pdpu = to_dpu_plane(plane);
423 	struct dpu_vbif_set_ot_params ot_params;
424 	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
425 
426 	memset(&ot_params, 0, sizeof(ot_params));
427 	ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
428 	ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
429 	ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
430 	ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
431 	ot_params.is_wfd = !pdpu->is_rt_pipe;
432 	ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
433 	ot_params.vbif_idx = VBIF_RT;
434 	ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
435 	ot_params.rd = true;
436 
437 	dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
438 }
439 
440 /**
441  * _dpu_plane_set_qos_remap - set vbif QoS for the given plane
442  * @plane:		Pointer to drm plane
443  */
_dpu_plane_set_qos_remap(struct drm_plane * plane)444 static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
445 {
446 	struct dpu_plane *pdpu = to_dpu_plane(plane);
447 	struct dpu_vbif_set_qos_params qos_params;
448 	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
449 
450 	memset(&qos_params, 0, sizeof(qos_params));
451 	qos_params.vbif_idx = VBIF_RT;
452 	qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
453 	qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
454 	qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
455 	qos_params.is_rt = pdpu->is_rt_pipe;
456 
457 	DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
458 			qos_params.num,
459 			qos_params.vbif_idx,
460 			qos_params.xin_id, qos_params.is_rt,
461 			qos_params.clk_ctrl);
462 
463 	dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
464 }
465 
_dpu_plane_set_scanout(struct drm_plane * plane,struct dpu_plane_state * pstate,struct dpu_hw_pipe_cfg * pipe_cfg,struct drm_framebuffer * fb)466 static void _dpu_plane_set_scanout(struct drm_plane *plane,
467 		struct dpu_plane_state *pstate,
468 		struct dpu_hw_pipe_cfg *pipe_cfg,
469 		struct drm_framebuffer *fb)
470 {
471 	struct dpu_plane *pdpu = to_dpu_plane(plane);
472 	struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
473 	struct msm_gem_address_space *aspace = kms->base.aspace;
474 	int ret;
475 
476 	ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
477 	if (ret == -EAGAIN)
478 		DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
479 	else if (ret)
480 		DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
481 	else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
482 		trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
483 					    &pipe_cfg->layout,
484 					    pstate->multirect_index);
485 		pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
486 						pstate->multirect_index);
487 	}
488 }
489 
_dpu_plane_setup_scaler3(struct dpu_plane * pdpu,struct dpu_plane_state * pstate,uint32_t src_w,uint32_t src_h,uint32_t dst_w,uint32_t dst_h,struct dpu_hw_scaler3_cfg * scale_cfg,const struct dpu_format * fmt,uint32_t chroma_subsmpl_h,uint32_t chroma_subsmpl_v)490 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
491 		struct dpu_plane_state *pstate,
492 		uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
493 		struct dpu_hw_scaler3_cfg *scale_cfg,
494 		const struct dpu_format *fmt,
495 		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
496 {
497 	uint32_t i;
498 	bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90;
499 
500 	/*
501 	 * For inline rotation cases, scaler config is post-rotation,
502 	 * so swap the dimensions here. However, pixel extension will
503 	 * need pre-rotation settings.
504 	 */
505 	if (inline_rotation)
506 		swap(src_w, src_h);
507 
508 	scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
509 		mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
510 	scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
511 		mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
512 
513 
514 	scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
515 		scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v;
516 	scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] =
517 		scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h;
518 
519 	scale_cfg->phase_step_x[DPU_SSPP_COMP_2] =
520 		scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2];
521 	scale_cfg->phase_step_y[DPU_SSPP_COMP_2] =
522 		scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2];
523 
524 	scale_cfg->phase_step_x[DPU_SSPP_COMP_3] =
525 		scale_cfg->phase_step_x[DPU_SSPP_COMP_0];
526 	scale_cfg->phase_step_y[DPU_SSPP_COMP_3] =
527 		scale_cfg->phase_step_y[DPU_SSPP_COMP_0];
528 
529 	for (i = 0; i < DPU_MAX_PLANES; i++) {
530 		scale_cfg->src_width[i] = src_w;
531 		scale_cfg->src_height[i] = src_h;
532 		if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
533 			scale_cfg->src_width[i] /= chroma_subsmpl_h;
534 			scale_cfg->src_height[i] /= chroma_subsmpl_v;
535 		}
536 
537 		if (pdpu->pipe_hw->cap->features &
538 			BIT(DPU_SSPP_SCALER_QSEED4)) {
539 			scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
540 			scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
541 		} else {
542 			scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
543 			scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
544 		}
545 	}
546 	if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
547 		&& (src_w == dst_w))
548 		return;
549 
550 	scale_cfg->dst_width = dst_w;
551 	scale_cfg->dst_height = dst_h;
552 	scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL;
553 	scale_cfg->uv_filter_cfg = DPU_SCALE_BIL;
554 	scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL;
555 	scale_cfg->lut_flag = 0;
556 	scale_cfg->blend_cfg = 1;
557 	scale_cfg->enable = 1;
558 }
559 
_dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg * scale_cfg,struct dpu_hw_pixel_ext * pixel_ext,uint32_t src_w,uint32_t src_h,uint32_t chroma_subsmpl_h,uint32_t chroma_subsmpl_v)560 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,
561 				struct dpu_hw_pixel_ext *pixel_ext,
562 				uint32_t src_w, uint32_t src_h,
563 				uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
564 {
565 	int i;
566 
567 	for (i = 0; i < DPU_MAX_PLANES; i++) {
568 		if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
569 			src_w /= chroma_subsmpl_h;
570 			src_h /= chroma_subsmpl_v;
571 		}
572 
573 		pixel_ext->num_ext_pxls_top[i] = src_h;
574 		pixel_ext->num_ext_pxls_left[i] = src_w;
575 	}
576 }
577 
578 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
579 	{
580 		/* S15.16 format */
581 		0x00012A00, 0x00000000, 0x00019880,
582 		0x00012A00, 0xFFFF9B80, 0xFFFF3000,
583 		0x00012A00, 0x00020480, 0x00000000,
584 	},
585 	/* signed bias */
586 	{ 0xfff0, 0xff80, 0xff80,},
587 	{ 0x0, 0x0, 0x0,},
588 	/* unsigned clamp */
589 	{ 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
590 	{ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
591 };
592 
593 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
594 	{
595 		/* S15.16 format */
596 		0x00012A00, 0x00000000, 0x00019880,
597 		0x00012A00, 0xFFFF9B80, 0xFFFF3000,
598 		0x00012A00, 0x00020480, 0x00000000,
599 		},
600 	/* signed bias */
601 	{ 0xffc0, 0xfe00, 0xfe00,},
602 	{ 0x0, 0x0, 0x0,},
603 	/* unsigned clamp */
604 	{ 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
605 	{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
606 };
607 
_dpu_plane_get_csc(struct dpu_plane * pdpu,const struct dpu_format * fmt)608 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
609 {
610 	const struct dpu_csc_cfg *csc_ptr;
611 
612 	if (!pdpu) {
613 		DPU_ERROR("invalid plane\n");
614 		return NULL;
615 	}
616 
617 	if (!DPU_FORMAT_IS_YUV(fmt))
618 		return NULL;
619 
620 	if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features)
621 		csc_ptr = &dpu_csc10_YUV2RGB_601L;
622 	else
623 		csc_ptr = &dpu_csc_YUV2RGB_601L;
624 
625 	DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
626 			csc_ptr->csc_mv[0],
627 			csc_ptr->csc_mv[1],
628 			csc_ptr->csc_mv[2]);
629 
630 	return csc_ptr;
631 }
632 
_dpu_plane_setup_scaler(struct dpu_plane * pdpu,struct dpu_plane_state * pstate,const struct dpu_format * fmt,bool color_fill,struct dpu_hw_pipe_cfg * pipe_cfg)633 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
634 		struct dpu_plane_state *pstate,
635 		const struct dpu_format *fmt, bool color_fill,
636 		struct dpu_hw_pipe_cfg *pipe_cfg)
637 {
638 	const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
639 	struct dpu_hw_scaler3_cfg scaler3_cfg;
640 	struct dpu_hw_pixel_ext pixel_ext;
641 	u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
642 	u32 src_height = drm_rect_height(&pipe_cfg->src_rect);
643 	u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect);
644 	u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect);
645 
646 	memset(&scaler3_cfg, 0, sizeof(scaler3_cfg));
647 	memset(&pixel_ext, 0, sizeof(pixel_ext));
648 
649 	/* don't chroma subsample if decimating */
650 	/* update scaler. calculate default config for QSEED3 */
651 	_dpu_plane_setup_scaler3(pdpu, pstate,
652 			src_width,
653 			src_height,
654 			dst_width,
655 			dst_height,
656 			&scaler3_cfg, fmt,
657 			info->hsub, info->vsub);
658 
659 	/* configure pixel extension based on scalar config */
660 	_dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
661 			src_width, src_height, info->hsub, info->vsub);
662 
663 	if (pdpu->pipe_hw->ops.setup_pe)
664 		pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
665 				&pixel_ext);
666 
667 	/**
668 	 * when programmed in multirect mode, scalar block will be
669 	 * bypassed. Still we need to update alpha and bitwidth
670 	 * ONLY for RECT0
671 	 */
672 	if (pdpu->pipe_hw->ops.setup_scaler &&
673 			pstate->multirect_index != DPU_SSPP_RECT_1)
674 		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
675 				pipe_cfg,
676 				&scaler3_cfg);
677 }
678 
679 /**
680  * _dpu_plane_color_fill - enables color fill on plane
681  * @pdpu:   Pointer to DPU plane object
682  * @color:  RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
683  * @alpha:  8-bit fill alpha value, 255 selects 100% alpha
684  * Returns: 0 on success
685  */
_dpu_plane_color_fill(struct dpu_plane * pdpu,uint32_t color,uint32_t alpha)686 static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
687 		uint32_t color, uint32_t alpha)
688 {
689 	const struct dpu_format *fmt;
690 	const struct drm_plane *plane = &pdpu->base;
691 	struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
692 	struct dpu_hw_pipe_cfg pipe_cfg;
693 
694 	DPU_DEBUG_PLANE(pdpu, "\n");
695 
696 	/*
697 	 * select fill format to match user property expectation,
698 	 * h/w only supports RGB variants
699 	 */
700 	fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
701 
702 	/* update sspp */
703 	if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
704 		pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
705 				(color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
706 				pstate->multirect_index);
707 
708 		/* override scaler/decimation if solid fill */
709 		pipe_cfg.dst_rect = pstate->base.dst;
710 
711 		pipe_cfg.src_rect.x1 = 0;
712 		pipe_cfg.src_rect.y1 = 0;
713 		pipe_cfg.src_rect.x2 =
714 			drm_rect_width(&pipe_cfg.dst_rect);
715 		pipe_cfg.src_rect.y2 =
716 			drm_rect_height(&pipe_cfg.dst_rect);
717 
718 		if (pdpu->pipe_hw->ops.setup_format)
719 			pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
720 					fmt, DPU_SSPP_SOLID_FILL,
721 					pstate->multirect_index);
722 
723 		if (pdpu->pipe_hw->ops.setup_rects)
724 			pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
725 					&pipe_cfg,
726 					pstate->multirect_index);
727 
728 		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
729 	}
730 
731 	return 0;
732 }
733 
dpu_plane_clear_multirect(const struct drm_plane_state * drm_state)734 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
735 {
736 	struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
737 
738 	pstate->multirect_index = DPU_SSPP_RECT_SOLO;
739 	pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
740 }
741 
dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states * plane)742 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
743 {
744 	struct dpu_plane_state *pstate[R_MAX];
745 	const struct drm_plane_state *drm_state[R_MAX];
746 	struct drm_rect src[R_MAX], dst[R_MAX];
747 	struct dpu_plane *dpu_plane[R_MAX];
748 	const struct dpu_format *fmt[R_MAX];
749 	int i, buffer_lines;
750 	unsigned int max_tile_height = 1;
751 	bool parallel_fetch_qualified = true;
752 	bool has_tiled_rect = false;
753 
754 	for (i = 0; i < R_MAX; i++) {
755 		const struct msm_format *msm_fmt;
756 
757 		drm_state[i] = i ? plane->r1 : plane->r0;
758 		msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
759 		fmt[i] = to_dpu_format(msm_fmt);
760 
761 		if (DPU_FORMAT_IS_UBWC(fmt[i])) {
762 			has_tiled_rect = true;
763 			if (fmt[i]->tile_height > max_tile_height)
764 				max_tile_height = fmt[i]->tile_height;
765 		}
766 	}
767 
768 	for (i = 0; i < R_MAX; i++) {
769 		int width_threshold;
770 
771 		pstate[i] = to_dpu_plane_state(drm_state[i]);
772 		dpu_plane[i] = to_dpu_plane(drm_state[i]->plane);
773 
774 		if (pstate[i] == NULL) {
775 			DPU_ERROR("DPU plane state of plane id %d is NULL\n",
776 				drm_state[i]->plane->base.id);
777 			return -EINVAL;
778 		}
779 
780 		src[i].x1 = drm_state[i]->src_x >> 16;
781 		src[i].y1 = drm_state[i]->src_y >> 16;
782 		src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16);
783 		src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16);
784 
785 		dst[i] = drm_plane_state_dest(drm_state[i]);
786 
787 		if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 ||
788 		    drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) {
789 			DPU_ERROR_PLANE(dpu_plane[i],
790 				"scaling is not supported in multirect mode\n");
791 			return -EINVAL;
792 		}
793 
794 		if (DPU_FORMAT_IS_YUV(fmt[i])) {
795 			DPU_ERROR_PLANE(dpu_plane[i],
796 				"Unsupported format for multirect mode\n");
797 			return -EINVAL;
798 		}
799 
800 		/**
801 		 * SSPP PD_MEM is split half - one for each RECT.
802 		 * Tiled formats need 5 lines of buffering while fetching
803 		 * whereas linear formats need only 2 lines.
804 		 * So we cannot support more than half of the supported SSPP
805 		 * width for tiled formats.
806 		 */
807 		width_threshold = dpu_plane[i]->catalog->caps->max_linewidth;
808 		if (has_tiled_rect)
809 			width_threshold /= 2;
810 
811 		if (parallel_fetch_qualified &&
812 		    drm_rect_width(&src[i]) > width_threshold)
813 			parallel_fetch_qualified = false;
814 
815 	}
816 
817 	/* Validate RECT's and set the mode */
818 
819 	/* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
820 	if (parallel_fetch_qualified) {
821 		pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
822 		pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
823 
824 		goto done;
825 	}
826 
827 	/* TIME_MX Mode */
828 	buffer_lines = 2 * max_tile_height;
829 
830 	if (dst[R1].y1 >= dst[R0].y2 + buffer_lines ||
831 	    dst[R0].y1 >= dst[R1].y2 + buffer_lines) {
832 		pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
833 		pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
834 	} else {
835 		DPU_ERROR(
836 			"No multirect mode possible for the planes (%d - %d)\n",
837 			drm_state[R0]->plane->base.id,
838 			drm_state[R1]->plane->base.id);
839 		return -EINVAL;
840 	}
841 
842 done:
843 	pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
844 	pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
845 
846 	DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
847 		pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
848 	DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
849 		pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
850 	return 0;
851 }
852 
dpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)853 static int dpu_plane_prepare_fb(struct drm_plane *plane,
854 		struct drm_plane_state *new_state)
855 {
856 	struct drm_framebuffer *fb = new_state->fb;
857 	struct dpu_plane *pdpu = to_dpu_plane(plane);
858 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
859 	struct dpu_hw_fmt_layout layout;
860 	struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
861 	int ret;
862 
863 	if (!new_state->fb)
864 		return 0;
865 
866 	DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
867 
868 	/* cache aspace */
869 	pstate->aspace = kms->base.aspace;
870 
871 	/*
872 	 * TODO: Need to sort out the msm_framebuffer_prepare() call below so
873 	 *       we can use msm_atomic_prepare_fb() instead of doing the
874 	 *       implicit fence and fb prepare by hand here.
875 	 */
876 	drm_gem_plane_helper_prepare_fb(plane, new_state);
877 
878 	if (pstate->aspace) {
879 		ret = msm_framebuffer_prepare(new_state->fb,
880 				pstate->aspace, pstate->needs_dirtyfb);
881 		if (ret) {
882 			DPU_ERROR("failed to prepare framebuffer\n");
883 			return ret;
884 		}
885 	}
886 
887 	/* validate framebuffer layout before commit */
888 	ret = dpu_format_populate_layout(pstate->aspace,
889 			new_state->fb, &layout);
890 	if (ret) {
891 		DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
892 		return ret;
893 	}
894 
895 	return 0;
896 }
897 
dpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)898 static void dpu_plane_cleanup_fb(struct drm_plane *plane,
899 		struct drm_plane_state *old_state)
900 {
901 	struct dpu_plane *pdpu = to_dpu_plane(plane);
902 	struct dpu_plane_state *old_pstate;
903 
904 	if (!old_state || !old_state->fb)
905 		return;
906 
907 	old_pstate = to_dpu_plane_state(old_state);
908 
909 	DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
910 
911 	msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace,
912 				old_pstate->needs_dirtyfb);
913 }
914 
dpu_plane_validate_src(struct drm_rect * src,struct drm_rect * fb_rect,uint32_t min_src_size)915 static bool dpu_plane_validate_src(struct drm_rect *src,
916 				   struct drm_rect *fb_rect,
917 				   uint32_t min_src_size)
918 {
919 	/* Ensure fb size is supported */
920 	if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH ||
921 	    drm_rect_height(fb_rect) > MAX_IMG_HEIGHT)
922 		return false;
923 
924 	/* Ensure src rect is above the minimum size */
925 	if (drm_rect_width(src) < min_src_size ||
926 	    drm_rect_height(src) < min_src_size)
927 		return false;
928 
929 	/* Ensure src is fully encapsulated in fb */
930 	return drm_rect_intersect(fb_rect, src) &&
931 		drm_rect_equals(fb_rect, src);
932 }
933 
dpu_plane_check_inline_rotation(struct dpu_plane * pdpu,const struct dpu_sspp_sub_blks * sblk,struct drm_rect src,const struct dpu_format * fmt)934 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
935 						const struct dpu_sspp_sub_blks *sblk,
936 						struct drm_rect src, const struct dpu_format *fmt)
937 {
938 	size_t num_formats;
939 	const u32 *supported_formats;
940 
941 	if (!sblk->rotation_cfg) {
942 		DPU_ERROR("invalid rotation cfg\n");
943 		return -EINVAL;
944 	}
945 
946 	if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) {
947 		DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n",
948 				src.y2, sblk->rotation_cfg->rot_maxheight);
949 		return -EINVAL;
950 	}
951 
952 	supported_formats = sblk->rotation_cfg->rot_format_list;
953 	num_formats = sblk->rotation_cfg->rot_num_formats;
954 
955 	if (!DPU_FORMAT_IS_UBWC(fmt) ||
956 		!dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats))
957 		return -EINVAL;
958 
959 	return 0;
960 }
961 
dpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)962 static int dpu_plane_atomic_check(struct drm_plane *plane,
963 				  struct drm_atomic_state *state)
964 {
965 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
966 										 plane);
967 	int ret = 0, min_scale;
968 	struct dpu_plane *pdpu = to_dpu_plane(plane);
969 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
970 	const struct drm_crtc_state *crtc_state = NULL;
971 	const struct dpu_format *fmt;
972 	struct drm_rect src, dst, fb_rect = { 0 };
973 	uint32_t min_src_size, max_linewidth;
974 	unsigned int rotation;
975 	uint32_t supported_rotations;
976 	const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap;
977 	const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk;
978 
979 	if (new_plane_state->crtc)
980 		crtc_state = drm_atomic_get_new_crtc_state(state,
981 							   new_plane_state->crtc);
982 
983 	min_scale = FRAC_16_16(1, sblk->maxupscale);
984 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
985 						  min_scale,
986 						  sblk->maxdwnscale << 16,
987 						  true, true);
988 	if (ret) {
989 		DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
990 		return ret;
991 	}
992 	if (!new_plane_state->visible)
993 		return 0;
994 
995 	src.x1 = new_plane_state->src_x >> 16;
996 	src.y1 = new_plane_state->src_y >> 16;
997 	src.x2 = src.x1 + (new_plane_state->src_w >> 16);
998 	src.y2 = src.y1 + (new_plane_state->src_h >> 16);
999 
1000 	dst = drm_plane_state_dest(new_plane_state);
1001 
1002 	fb_rect.x2 = new_plane_state->fb->width;
1003 	fb_rect.y2 = new_plane_state->fb->height;
1004 
1005 	max_linewidth = pdpu->catalog->caps->max_linewidth;
1006 
1007 	fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
1008 
1009 	min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
1010 
1011 	if (DPU_FORMAT_IS_YUV(fmt) &&
1012 		(!(pipe_hw_caps->features & DPU_SSPP_SCALER) ||
1013 		 !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) {
1014 		DPU_DEBUG_PLANE(pdpu,
1015 				"plane doesn't have scaler/csc for yuv\n");
1016 		return -EINVAL;
1017 
1018 	/* check src bounds */
1019 	} else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
1020 		DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
1021 				DRM_RECT_ARG(&src));
1022 		return -E2BIG;
1023 
1024 	/* valid yuv image */
1025 	} else if (DPU_FORMAT_IS_YUV(fmt) &&
1026 		   (src.x1 & 0x1 || src.y1 & 0x1 ||
1027 		    drm_rect_width(&src) & 0x1 ||
1028 		    drm_rect_height(&src) & 0x1)) {
1029 		DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
1030 				DRM_RECT_ARG(&src));
1031 		return -EINVAL;
1032 
1033 	/* min dst support */
1034 	} else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
1035 		DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
1036 				DRM_RECT_ARG(&dst));
1037 		return -EINVAL;
1038 
1039 	/* check decimated source width */
1040 	} else if (drm_rect_width(&src) > max_linewidth) {
1041 		DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
1042 				DRM_RECT_ARG(&src), max_linewidth);
1043 		return -E2BIG;
1044 	}
1045 
1046 	supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
1047 
1048 	if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION))
1049 		supported_rotations |= DRM_MODE_ROTATE_90;
1050 
1051 	rotation = drm_rotation_simplify(new_plane_state->rotation,
1052 					supported_rotations);
1053 
1054 	if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) &&
1055 		(rotation & DRM_MODE_ROTATE_90)) {
1056 		ret = dpu_plane_check_inline_rotation(pdpu, sblk, src, fmt);
1057 		if (ret)
1058 			return ret;
1059 	}
1060 
1061 	pstate->rotation = rotation;
1062 	pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);
1063 
1064 	return 0;
1065 }
1066 
dpu_plane_flush(struct drm_plane * plane)1067 void dpu_plane_flush(struct drm_plane *plane)
1068 {
1069 	struct dpu_plane *pdpu;
1070 	struct dpu_plane_state *pstate;
1071 
1072 	if (!plane || !plane->state) {
1073 		DPU_ERROR("invalid plane\n");
1074 		return;
1075 	}
1076 
1077 	pdpu = to_dpu_plane(plane);
1078 	pstate = to_dpu_plane_state(plane->state);
1079 
1080 	/*
1081 	 * These updates have to be done immediately before the plane flush
1082 	 * timing, and may not be moved to the atomic_update/mode_set functions.
1083 	 */
1084 	if (pdpu->is_error)
1085 		/* force white frame with 100% alpha pipe output on error */
1086 		_dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
1087 	else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
1088 		/* force 100% alpha */
1089 		_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
1090 	else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) {
1091 		const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
1092 		const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
1093 
1094 		if (csc_ptr)
1095 			pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr);
1096 	}
1097 
1098 	/* flag h/w flush complete */
1099 	if (plane->state)
1100 		pstate->pending = false;
1101 }
1102 
1103 /**
1104  * dpu_plane_set_error: enable/disable error condition
1105  * @plane: pointer to drm_plane structure
1106  * @error: error value to set
1107  */
dpu_plane_set_error(struct drm_plane * plane,bool error)1108 void dpu_plane_set_error(struct drm_plane *plane, bool error)
1109 {
1110 	struct dpu_plane *pdpu;
1111 
1112 	if (!plane)
1113 		return;
1114 
1115 	pdpu = to_dpu_plane(plane);
1116 	pdpu->is_error = error;
1117 }
1118 
dpu_plane_sspp_atomic_update(struct drm_plane * plane)1119 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
1120 {
1121 	uint32_t src_flags;
1122 	struct dpu_plane *pdpu = to_dpu_plane(plane);
1123 	struct drm_plane_state *state = plane->state;
1124 	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1125 	struct drm_crtc *crtc = state->crtc;
1126 	struct drm_framebuffer *fb = state->fb;
1127 	bool is_rt_pipe, update_qos_remap;
1128 	const struct dpu_format *fmt =
1129 		to_dpu_format(msm_framebuffer_format(fb));
1130 	struct dpu_hw_pipe_cfg pipe_cfg;
1131 
1132 	memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
1133 
1134 	_dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
1135 
1136 	pstate->pending = true;
1137 
1138 	is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
1139 	_dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1140 
1141 	DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1142 			", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1143 			crtc->base.id, DRM_RECT_ARG(&state->dst),
1144 			(char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
1145 
1146 	pipe_cfg.src_rect = state->src;
1147 
1148 	/* state->src is 16.16, src_rect is not */
1149 	pipe_cfg.src_rect.x1 >>= 16;
1150 	pipe_cfg.src_rect.x2 >>= 16;
1151 	pipe_cfg.src_rect.y1 >>= 16;
1152 	pipe_cfg.src_rect.y2 >>= 16;
1153 
1154 	pipe_cfg.dst_rect = state->dst;
1155 
1156 	/* override for color fill */
1157 	if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1158 		/* skip remaining processing on color fill */
1159 		return;
1160 	}
1161 
1162 	if (pdpu->pipe_hw->ops.setup_rects) {
1163 		pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
1164 				&pipe_cfg,
1165 				pstate->multirect_index);
1166 	}
1167 
1168 	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
1169 
1170 	if (pdpu->pipe_hw->ops.setup_multirect)
1171 		pdpu->pipe_hw->ops.setup_multirect(
1172 				pdpu->pipe_hw,
1173 				pstate->multirect_index,
1174 				pstate->multirect_mode);
1175 
1176 	if (pdpu->pipe_hw->ops.setup_format) {
1177 		unsigned int rotation = pstate->rotation;
1178 
1179 		src_flags = 0x0;
1180 
1181 		if (rotation & DRM_MODE_REFLECT_X)
1182 			src_flags |= DPU_SSPP_FLIP_LR;
1183 
1184 		if (rotation & DRM_MODE_REFLECT_Y)
1185 			src_flags |= DPU_SSPP_FLIP_UD;
1186 
1187 		if (rotation & DRM_MODE_ROTATE_90)
1188 			src_flags |= DPU_SSPP_ROT_90;
1189 
1190 		/* update format */
1191 		pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
1192 				pstate->multirect_index);
1193 
1194 		if (pdpu->pipe_hw->ops.setup_cdp) {
1195 			struct dpu_hw_cdp_cfg cdp_cfg;
1196 
1197 			memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
1198 
1199 			cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg
1200 					[DPU_PERF_CDP_USAGE_RT].rd_enable;
1201 			cdp_cfg.ubwc_meta_enable =
1202 					DPU_FORMAT_IS_UBWC(fmt);
1203 			cdp_cfg.tile_amortize_enable =
1204 					DPU_FORMAT_IS_UBWC(fmt) ||
1205 					DPU_FORMAT_IS_TILE(fmt);
1206 			cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
1207 
1208 			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index);
1209 		}
1210 	}
1211 
1212 	_dpu_plane_set_qos_lut(plane, fb, &pipe_cfg);
1213 	_dpu_plane_set_danger_lut(plane, fb);
1214 
1215 	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
1216 		_dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
1217 		_dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
1218 	}
1219 
1220 	update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) ||
1221 			pstate->needs_qos_remap;
1222 
1223 	if (update_qos_remap) {
1224 		if (is_rt_pipe != pdpu->is_rt_pipe)
1225 			pdpu->is_rt_pipe = is_rt_pipe;
1226 		else if (pstate->needs_qos_remap)
1227 			pstate->needs_qos_remap = false;
1228 		_dpu_plane_set_qos_remap(plane);
1229 	}
1230 
1231 	_dpu_plane_calc_bw(plane, fb, &pipe_cfg);
1232 
1233 	_dpu_plane_calc_clk(plane, &pipe_cfg);
1234 }
1235 
_dpu_plane_atomic_disable(struct drm_plane * plane)1236 static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1237 {
1238 	struct drm_plane_state *state = plane->state;
1239 	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1240 
1241 	trace_dpu_plane_disable(DRMID(plane), false,
1242 				pstate->multirect_mode);
1243 
1244 	pstate->pending = true;
1245 }
1246 
dpu_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)1247 static void dpu_plane_atomic_update(struct drm_plane *plane,
1248 				struct drm_atomic_state *state)
1249 {
1250 	struct dpu_plane *pdpu = to_dpu_plane(plane);
1251 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1252 									   plane);
1253 
1254 	pdpu->is_error = false;
1255 
1256 	DPU_DEBUG_PLANE(pdpu, "\n");
1257 
1258 	if (!new_state->visible) {
1259 		_dpu_plane_atomic_disable(plane);
1260 	} else {
1261 		dpu_plane_sspp_atomic_update(plane);
1262 	}
1263 }
1264 
dpu_plane_destroy(struct drm_plane * plane)1265 static void dpu_plane_destroy(struct drm_plane *plane)
1266 {
1267 	struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
1268 
1269 	DPU_DEBUG_PLANE(pdpu, "\n");
1270 
1271 	if (pdpu) {
1272 		_dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1273 
1274 		mutex_destroy(&pdpu->lock);
1275 
1276 		/* this will destroy the states as well */
1277 		drm_plane_cleanup(plane);
1278 
1279 		dpu_hw_sspp_destroy(pdpu->pipe_hw);
1280 
1281 		kfree(pdpu);
1282 	}
1283 }
1284 
dpu_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)1285 static void dpu_plane_destroy_state(struct drm_plane *plane,
1286 		struct drm_plane_state *state)
1287 {
1288 	__drm_atomic_helper_plane_destroy_state(state);
1289 	kfree(to_dpu_plane_state(state));
1290 }
1291 
1292 static struct drm_plane_state *
dpu_plane_duplicate_state(struct drm_plane * plane)1293 dpu_plane_duplicate_state(struct drm_plane *plane)
1294 {
1295 	struct dpu_plane *pdpu;
1296 	struct dpu_plane_state *pstate;
1297 	struct dpu_plane_state *old_state;
1298 
1299 	if (!plane) {
1300 		DPU_ERROR("invalid plane\n");
1301 		return NULL;
1302 	} else if (!plane->state) {
1303 		DPU_ERROR("invalid plane state\n");
1304 		return NULL;
1305 	}
1306 
1307 	old_state = to_dpu_plane_state(plane->state);
1308 	pdpu = to_dpu_plane(plane);
1309 	pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1310 	if (!pstate) {
1311 		DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1312 		return NULL;
1313 	}
1314 
1315 	DPU_DEBUG_PLANE(pdpu, "\n");
1316 
1317 	pstate->pending = false;
1318 
1319 	__drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1320 
1321 	return &pstate->base;
1322 }
1323 
1324 static const char * const multirect_mode_name[] = {
1325 	[DPU_SSPP_MULTIRECT_NONE] = "none",
1326 	[DPU_SSPP_MULTIRECT_PARALLEL] = "parallel",
1327 	[DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx",
1328 };
1329 
1330 static const char * const multirect_index_name[] = {
1331 	[DPU_SSPP_RECT_SOLO] = "solo",
1332 	[DPU_SSPP_RECT_0] = "rect_0",
1333 	[DPU_SSPP_RECT_1] = "rect_1",
1334 };
1335 
dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode)1336 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode)
1337 {
1338 	if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name)))
1339 		return "unknown";
1340 
1341 	return multirect_mode_name[mode];
1342 }
1343 
dpu_get_multirect_index(enum dpu_sspp_multirect_index index)1344 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index)
1345 {
1346 	if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name)))
1347 		return "unknown";
1348 
1349 	return multirect_index_name[index];
1350 }
1351 
dpu_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)1352 static void dpu_plane_atomic_print_state(struct drm_printer *p,
1353 		const struct drm_plane_state *state)
1354 {
1355 	const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1356 	const struct dpu_plane *pdpu = to_dpu_plane(state->plane);
1357 
1358 	drm_printf(p, "\tstage=%d\n", pstate->stage);
1359 	drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name);
1360 	drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode));
1361 	drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index));
1362 }
1363 
dpu_plane_reset(struct drm_plane * plane)1364 static void dpu_plane_reset(struct drm_plane *plane)
1365 {
1366 	struct dpu_plane *pdpu;
1367 	struct dpu_plane_state *pstate;
1368 
1369 	if (!plane) {
1370 		DPU_ERROR("invalid plane\n");
1371 		return;
1372 	}
1373 
1374 	pdpu = to_dpu_plane(plane);
1375 	DPU_DEBUG_PLANE(pdpu, "\n");
1376 
1377 	/* remove previous state, if present */
1378 	if (plane->state) {
1379 		dpu_plane_destroy_state(plane, plane->state);
1380 		plane->state = NULL;
1381 	}
1382 
1383 	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1384 	if (!pstate) {
1385 		DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1386 		return;
1387 	}
1388 
1389 	__drm_atomic_helper_plane_reset(plane, &pstate->base);
1390 }
1391 
1392 #ifdef CONFIG_DEBUG_FS
dpu_plane_danger_signal_ctrl(struct drm_plane * plane,bool enable)1393 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1394 {
1395 	struct dpu_plane *pdpu = to_dpu_plane(plane);
1396 	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1397 
1398 	if (!pdpu->is_rt_pipe)
1399 		return;
1400 
1401 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
1402 	_dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
1403 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1404 }
1405 
1406 /* SSPP live inside dpu_plane private data only. Enumerate them here. */
dpu_debugfs_sspp_init(struct dpu_kms * dpu_kms,struct dentry * debugfs_root)1407 void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
1408 {
1409 	struct drm_plane *plane;
1410 	struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
1411 
1412 	if (IS_ERR(entry))
1413 		return;
1414 
1415 	drm_for_each_plane(plane, dpu_kms->dev) {
1416 		struct dpu_plane *pdpu = to_dpu_plane(plane);
1417 
1418 		_dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry);
1419 	}
1420 }
1421 #endif
1422 
dpu_plane_format_mod_supported(struct drm_plane * plane,uint32_t format,uint64_t modifier)1423 static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
1424 		uint32_t format, uint64_t modifier)
1425 {
1426 	if (modifier == DRM_FORMAT_MOD_LINEAR)
1427 		return true;
1428 
1429 	if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED)
1430 		return dpu_find_format(format, qcom_compressed_supported_formats,
1431 				ARRAY_SIZE(qcom_compressed_supported_formats));
1432 
1433 	return false;
1434 }
1435 
1436 static const struct drm_plane_funcs dpu_plane_funcs = {
1437 		.update_plane = drm_atomic_helper_update_plane,
1438 		.disable_plane = drm_atomic_helper_disable_plane,
1439 		.destroy = dpu_plane_destroy,
1440 		.reset = dpu_plane_reset,
1441 		.atomic_duplicate_state = dpu_plane_duplicate_state,
1442 		.atomic_destroy_state = dpu_plane_destroy_state,
1443 		.atomic_print_state = dpu_plane_atomic_print_state,
1444 		.format_mod_supported = dpu_plane_format_mod_supported,
1445 };
1446 
1447 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
1448 		.prepare_fb = dpu_plane_prepare_fb,
1449 		.cleanup_fb = dpu_plane_cleanup_fb,
1450 		.atomic_check = dpu_plane_atomic_check,
1451 		.atomic_update = dpu_plane_atomic_update,
1452 };
1453 
dpu_plane_pipe(struct drm_plane * plane)1454 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
1455 {
1456 	return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
1457 }
1458 
1459 /* initialize plane */
dpu_plane_init(struct drm_device * dev,uint32_t pipe,enum drm_plane_type type,unsigned long possible_crtcs)1460 struct drm_plane *dpu_plane_init(struct drm_device *dev,
1461 		uint32_t pipe, enum drm_plane_type type,
1462 		unsigned long possible_crtcs)
1463 {
1464 	struct drm_plane *plane = NULL;
1465 	const uint32_t *format_list;
1466 	struct dpu_plane *pdpu;
1467 	struct msm_drm_private *priv = dev->dev_private;
1468 	struct dpu_kms *kms = to_dpu_kms(priv->kms);
1469 	uint32_t num_formats;
1470 	uint32_t supported_rotations;
1471 	int ret = -EINVAL;
1472 
1473 	/* create and zero local structure */
1474 	pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);
1475 	if (!pdpu) {
1476 		DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe);
1477 		ret = -ENOMEM;
1478 		return ERR_PTR(ret);
1479 	}
1480 
1481 	/* cache local stuff for later */
1482 	plane = &pdpu->base;
1483 	pdpu->pipe = pipe;
1484 
1485 	/* initialize underlying h/w driver */
1486 	pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
1487 	if (IS_ERR(pdpu->pipe_hw)) {
1488 		DPU_ERROR("[%u]SSPP init failed\n", pipe);
1489 		ret = PTR_ERR(pdpu->pipe_hw);
1490 		goto clean_plane;
1491 	} else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
1492 		DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
1493 		goto clean_sspp;
1494 	}
1495 
1496 	format_list = pdpu->pipe_hw->cap->sblk->format_list;
1497 	num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
1498 
1499 	ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
1500 				format_list, num_formats,
1501 				supported_format_modifiers, type, NULL);
1502 	if (ret)
1503 		goto clean_sspp;
1504 
1505 	pdpu->catalog = kms->catalog;
1506 
1507 	ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX);
1508 	if (ret)
1509 		DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1510 
1511 	drm_plane_create_alpha_property(plane);
1512 	drm_plane_create_blend_mode_property(plane,
1513 			BIT(DRM_MODE_BLEND_PIXEL_NONE) |
1514 			BIT(DRM_MODE_BLEND_PREMULTI) |
1515 			BIT(DRM_MODE_BLEND_COVERAGE));
1516 
1517 	supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1518 
1519 	if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
1520 		supported_rotations |= DRM_MODE_ROTATE_MASK;
1521 
1522 	drm_plane_create_rotation_property(plane,
1523 		    DRM_MODE_ROTATE_0, supported_rotations);
1524 
1525 	drm_plane_enable_fb_damage_clips(plane);
1526 
1527 	/* success! finalize initialization */
1528 	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
1529 
1530 	mutex_init(&pdpu->lock);
1531 
1532 	DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name,
1533 					pipe, plane->base.id);
1534 	return plane;
1535 
1536 clean_sspp:
1537 	if (pdpu && pdpu->pipe_hw)
1538 		dpu_hw_sspp_destroy(pdpu->pipe_hw);
1539 clean_plane:
1540 	kfree(pdpu);
1541 	return ERR_PTR(ret);
1542 }
1543