1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
6  *
7  * Author: Rob Clark <robdclark@gmail.com>
8  */
9 
10 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
11 #include <linux/debugfs.h>
12 #include <linux/kthread.h>
13 #include <linux/seq_file.h>
14 
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_file.h>
17 #include <drm/drm_probe_helper.h>
18 
19 #include "msm_drv.h"
20 #include "dpu_kms.h"
21 #include "dpu_hwio.h"
22 #include "dpu_hw_catalog.h"
23 #include "dpu_hw_intf.h"
24 #include "dpu_hw_ctl.h"
25 #include "dpu_hw_dspp.h"
26 #include "dpu_hw_dsc.h"
27 #include "dpu_hw_merge3d.h"
28 #include "dpu_formats.h"
29 #include "dpu_encoder_phys.h"
30 #include "dpu_crtc.h"
31 #include "dpu_trace.h"
32 #include "dpu_core_irq.h"
33 #include "disp/msm_disp_snapshot.h"
34 
35 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
36 		(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
37 
38 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
39 		(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
40 
41 /*
42  * Two to anticipate panels that can do cmd/vid dynamic switching
43  * plan is to create all possible physical encoder types, and switch between
44  * them at runtime
45  */
46 #define NUM_PHYS_ENCODER_TYPES 2
47 
48 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
49 	(MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
50 
51 #define MAX_CHANNELS_PER_ENC 2
52 
53 #define IDLE_SHORT_TIMEOUT	1
54 
55 #define MAX_HDISPLAY_SPLIT 1080
56 
57 /* timeout in frames waiting for frame done */
58 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
59 
60 /**
61  * enum dpu_enc_rc_events - events for resource control state machine
62  * @DPU_ENC_RC_EVENT_KICKOFF:
63  *	This event happens at NORMAL priority.
64  *	Event that signals the start of the transfer. When this event is
65  *	received, enable MDP/DSI core clocks. Regardless of the previous
66  *	state, the resource should be in ON state at the end of this event.
67  * @DPU_ENC_RC_EVENT_FRAME_DONE:
68  *	This event happens at INTERRUPT level.
69  *	Event signals the end of the data transfer after the PP FRAME_DONE
70  *	event. At the end of this event, a delayed work is scheduled to go to
71  *	IDLE_PC state after IDLE_TIMEOUT time.
72  * @DPU_ENC_RC_EVENT_PRE_STOP:
73  *	This event happens at NORMAL priority.
74  *	This event, when received during the ON state, leave the RC STATE
75  *	in the PRE_OFF state. It should be followed by the STOP event as
76  *	part of encoder disable.
77  *	If received during IDLE or OFF states, it will do nothing.
78  * @DPU_ENC_RC_EVENT_STOP:
79  *	This event happens at NORMAL priority.
80  *	When this event is received, disable all the MDP/DSI core clocks, and
81  *	disable IRQs. It should be called from the PRE_OFF or IDLE states.
82  *	IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
83  *	PRE_OFF is expected when PRE_STOP was executed during the ON state.
84  *	Resource state should be in OFF at the end of the event.
85  * @DPU_ENC_RC_EVENT_ENTER_IDLE:
86  *	This event happens at NORMAL priority from a work item.
87  *	Event signals that there were no frame updates for IDLE_TIMEOUT time.
88  *	This would disable MDP/DSI core clocks and change the resource state
89  *	to IDLE.
90  */
91 enum dpu_enc_rc_events {
92 	DPU_ENC_RC_EVENT_KICKOFF = 1,
93 	DPU_ENC_RC_EVENT_FRAME_DONE,
94 	DPU_ENC_RC_EVENT_PRE_STOP,
95 	DPU_ENC_RC_EVENT_STOP,
96 	DPU_ENC_RC_EVENT_ENTER_IDLE
97 };
98 
99 /*
100  * enum dpu_enc_rc_states - states that the resource control maintains
101  * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
102  * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
103  * @DPU_ENC_RC_STATE_ON: Resource is in ON state
104  * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
105  * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
106  */
107 enum dpu_enc_rc_states {
108 	DPU_ENC_RC_STATE_OFF,
109 	DPU_ENC_RC_STATE_PRE_OFF,
110 	DPU_ENC_RC_STATE_ON,
111 	DPU_ENC_RC_STATE_IDLE
112 };
113 
114 /**
115  * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
116  *	encoders. Virtual encoder manages one "logical" display. Physical
117  *	encoders manage one intf block, tied to a specific panel/sub-panel.
118  *	Virtual encoder defers as much as possible to the physical encoders.
119  *	Virtual encoder registers itself with the DRM Framework as the encoder.
120  * @base:		drm_encoder base class for registration with DRM
121  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
122  * @enabled:		True if the encoder is active, protected by enc_lock
123  * @num_phys_encs:	Actual number of physical encoders contained.
124  * @phys_encs:		Container of physical encoders managed.
125  * @cur_master:		Pointer to the current master in this mode. Optimization
126  *			Only valid after enable. Cleared as disable.
127  * @cur_slave:		As above but for the slave encoder.
128  * @hw_pp:		Handle to the pingpong blocks used for the display. No.
129  *			pingpong blocks can be different than num_phys_encs.
130  * @hw_dsc:		Handle to the DSC blocks used for the display.
131  * @dsc_mask:		Bitmask of used DSC blocks.
132  * @intfs_swapped:	Whether or not the phys_enc interfaces have been swapped
133  *			for partial update right-only cases, such as pingpong
134  *			split where virtual pingpong does not generate IRQs
135  * @crtc:		Pointer to the currently assigned crtc. Normally you
136  *			would use crtc->state->encoder_mask to determine the
137  *			link between encoder/crtc. However in this case we need
138  *			to track crtc in the disable() hook which is called
139  *			_after_ encoder_mask is cleared.
140  * @connector:		If a mode is set, cached pointer to the active connector
141  * @crtc_kickoff_cb:		Callback into CRTC that will flush & start
142  *				all CTL paths
143  * @crtc_kickoff_cb_data:	Opaque user data given to crtc_kickoff_cb
144  * @debugfs_root:		Debug file system root file node
145  * @enc_lock:			Lock around physical encoder
146  *				create/destroy/enable/disable
147  * @frame_busy_mask:		Bitmask tracking which phys_enc we are still
148  *				busy processing current command.
149  *				Bit0 = phys_encs[0] etc.
150  * @crtc_frame_event_cb:	callback handler for frame event
151  * @crtc_frame_event_cb_data:	callback handler private data
152  * @frame_done_timeout_ms:	frame done timeout in ms
153  * @frame_done_timer:		watchdog timer for frame done event
154  * @vsync_event_timer:		vsync timer
155  * @disp_info:			local copy of msm_display_info struct
156  * @idle_pc_supported:		indicate if idle power collaps is supported
157  * @rc_lock:			resource control mutex lock to protect
158  *				virt encoder over various state changes
159  * @rc_state:			resource controller state
160  * @delayed_off_work:		delayed worker to schedule disabling of
161  *				clks and resources after IDLE_TIMEOUT time.
162  * @vsync_event_work:		worker to handle vsync event for autorefresh
163  * @topology:                   topology of the display
164  * @idle_timeout:		idle timeout duration in milliseconds
165  * @dsc:			drm_dsc_config pointer, for DSC-enabled encoders
166  */
167 struct dpu_encoder_virt {
168 	struct drm_encoder base;
169 	spinlock_t enc_spinlock;
170 
171 	bool enabled;
172 
173 	unsigned int num_phys_encs;
174 	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
175 	struct dpu_encoder_phys *cur_master;
176 	struct dpu_encoder_phys *cur_slave;
177 	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
178 	struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
179 
180 	unsigned int dsc_mask;
181 
182 	bool intfs_swapped;
183 
184 	struct drm_crtc *crtc;
185 	struct drm_connector *connector;
186 
187 	struct dentry *debugfs_root;
188 	struct mutex enc_lock;
189 	DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
190 	void (*crtc_frame_event_cb)(void *, u32 event);
191 	void *crtc_frame_event_cb_data;
192 
193 	atomic_t frame_done_timeout_ms;
194 	struct timer_list frame_done_timer;
195 	struct timer_list vsync_event_timer;
196 
197 	struct msm_display_info disp_info;
198 
199 	bool idle_pc_supported;
200 	struct mutex rc_lock;
201 	enum dpu_enc_rc_states rc_state;
202 	struct delayed_work delayed_off_work;
203 	struct kthread_work vsync_event_work;
204 	struct msm_display_topology topology;
205 
206 	u32 idle_timeout;
207 
208 	bool wide_bus_en;
209 
210 	/* DSC configuration */
211 	struct drm_dsc_config *dsc;
212 };
213 
214 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
215 
216 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
217 	15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
218 };
219 
220 
dpu_encoder_is_widebus_enabled(const struct drm_encoder * drm_enc)221 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
222 {
223 	const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
224 
225 	return dpu_enc->wide_bus_en;
226 }
227 
dpu_encoder_get_crc_values_cnt(const struct drm_encoder * drm_enc)228 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
229 {
230 	struct dpu_encoder_virt *dpu_enc;
231 	int i, num_intf = 0;
232 
233 	dpu_enc = to_dpu_encoder_virt(drm_enc);
234 
235 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
236 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
237 
238 		if (phys->hw_intf && phys->hw_intf->ops.setup_misr
239 				&& phys->hw_intf->ops.collect_misr)
240 			num_intf++;
241 	}
242 
243 	return num_intf;
244 }
245 
dpu_encoder_setup_misr(const struct drm_encoder * drm_enc)246 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
247 {
248 	struct dpu_encoder_virt *dpu_enc;
249 
250 	int i;
251 
252 	dpu_enc = to_dpu_encoder_virt(drm_enc);
253 
254 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
255 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
256 
257 		if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
258 			continue;
259 
260 		phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1);
261 	}
262 }
263 
dpu_encoder_get_crc(const struct drm_encoder * drm_enc,u32 * crcs,int pos)264 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos)
265 {
266 	struct dpu_encoder_virt *dpu_enc;
267 
268 	int i, rc = 0, entries_added = 0;
269 
270 	if (!drm_enc->crtc) {
271 		DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index);
272 		return -EINVAL;
273 	}
274 
275 	dpu_enc = to_dpu_encoder_virt(drm_enc);
276 
277 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
278 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
279 
280 		if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr)
281 			continue;
282 
283 		rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]);
284 		if (rc)
285 			return rc;
286 		entries_added++;
287 	}
288 
289 	return entries_added;
290 }
291 
_dpu_encoder_setup_dither(struct dpu_hw_pingpong * hw_pp,unsigned bpc)292 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
293 {
294 	struct dpu_hw_dither_cfg dither_cfg = { 0 };
295 
296 	if (!hw_pp->ops.setup_dither)
297 		return;
298 
299 	switch (bpc) {
300 	case 6:
301 		dither_cfg.c0_bitdepth = 6;
302 		dither_cfg.c1_bitdepth = 6;
303 		dither_cfg.c2_bitdepth = 6;
304 		dither_cfg.c3_bitdepth = 6;
305 		dither_cfg.temporal_en = 0;
306 		break;
307 	default:
308 		hw_pp->ops.setup_dither(hw_pp, NULL);
309 		return;
310 	}
311 
312 	memcpy(&dither_cfg.matrix, dither_matrix,
313 			sizeof(u32) * DITHER_MATRIX_SZ);
314 
315 	hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
316 }
317 
dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)318 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
319 {
320 	switch (intf_mode) {
321 	case INTF_MODE_VIDEO:
322 		return "INTF_MODE_VIDEO";
323 	case INTF_MODE_CMD:
324 		return "INTF_MODE_CMD";
325 	case INTF_MODE_WB_BLOCK:
326 		return "INTF_MODE_WB_BLOCK";
327 	case INTF_MODE_WB_LINE:
328 		return "INTF_MODE_WB_LINE";
329 	default:
330 		return "INTF_MODE_UNKNOWN";
331 	}
332 }
333 
dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys * phys_enc,enum dpu_intr_idx intr_idx)334 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
335 		enum dpu_intr_idx intr_idx)
336 {
337 	DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",
338 			DRMID(phys_enc->parent),
339 			dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
340 			phys_enc->intf_idx - INTF_0, phys_enc->wb_idx - WB_0,
341 			phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
342 
343 	if (phys_enc->parent_ops->handle_frame_done)
344 		phys_enc->parent_ops->handle_frame_done(
345 				phys_enc->parent, phys_enc,
346 				DPU_ENCODER_FRAME_EVENT_ERROR);
347 }
348 
349 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
350 		u32 irq_idx, struct dpu_encoder_wait_info *info);
351 
dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys * phys_enc,int irq,void (* func)(void * arg,int irq_idx),struct dpu_encoder_wait_info * wait_info)352 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
353 		int irq,
354 		void (*func)(void *arg, int irq_idx),
355 		struct dpu_encoder_wait_info *wait_info)
356 {
357 	u32 irq_status;
358 	int ret;
359 
360 	if (!wait_info) {
361 		DPU_ERROR("invalid params\n");
362 		return -EINVAL;
363 	}
364 	/* note: do master / slave checking outside */
365 
366 	/* return EWOULDBLOCK since we know the wait isn't necessary */
367 	if (phys_enc->enable_state == DPU_ENC_DISABLED) {
368 		DRM_ERROR("encoder is disabled id=%u, callback=%ps, irq=%d\n",
369 			  DRMID(phys_enc->parent), func,
370 			  irq);
371 		return -EWOULDBLOCK;
372 	}
373 
374 	if (irq < 0) {
375 		DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
376 			      DRMID(phys_enc->parent), func);
377 		return 0;
378 	}
379 
380 	DRM_DEBUG_KMS("id=%u, callback=%ps, irq=%d, pp=%d, pending_cnt=%d\n",
381 		      DRMID(phys_enc->parent), func,
382 		      irq, phys_enc->hw_pp->idx - PINGPONG_0,
383 		      atomic_read(wait_info->atomic_cnt));
384 
385 	ret = dpu_encoder_helper_wait_event_timeout(
386 			DRMID(phys_enc->parent),
387 			irq,
388 			wait_info);
389 
390 	if (ret <= 0) {
391 		irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq);
392 		if (irq_status) {
393 			unsigned long flags;
394 
395 			DRM_DEBUG_KMS("irq not triggered id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d\n",
396 				      DRMID(phys_enc->parent), func,
397 				      irq,
398 				      phys_enc->hw_pp->idx - PINGPONG_0,
399 				      atomic_read(wait_info->atomic_cnt));
400 			local_irq_save(flags);
401 			func(phys_enc, irq);
402 			local_irq_restore(flags);
403 			ret = 0;
404 		} else {
405 			ret = -ETIMEDOUT;
406 			DRM_DEBUG_KMS("irq timeout id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d\n",
407 				      DRMID(phys_enc->parent), func,
408 				      irq,
409 				      phys_enc->hw_pp->idx - PINGPONG_0,
410 				      atomic_read(wait_info->atomic_cnt));
411 		}
412 	} else {
413 		ret = 0;
414 		trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
415 			func, irq,
416 			phys_enc->hw_pp->idx - PINGPONG_0,
417 			atomic_read(wait_info->atomic_cnt));
418 	}
419 
420 	return ret;
421 }
422 
dpu_encoder_get_vsync_count(struct drm_encoder * drm_enc)423 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc)
424 {
425 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
426 	struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL;
427 	return phys ? atomic_read(&phys->vsync_cnt) : 0;
428 }
429 
dpu_encoder_get_linecount(struct drm_encoder * drm_enc)430 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
431 {
432 	struct dpu_encoder_virt *dpu_enc;
433 	struct dpu_encoder_phys *phys;
434 	int linecount = 0;
435 
436 	dpu_enc = to_dpu_encoder_virt(drm_enc);
437 	phys = dpu_enc ? dpu_enc->cur_master : NULL;
438 
439 	if (phys && phys->ops.get_line_count)
440 		linecount = phys->ops.get_line_count(phys);
441 
442 	return linecount;
443 }
444 
dpu_encoder_destroy(struct drm_encoder * drm_enc)445 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
446 {
447 	struct dpu_encoder_virt *dpu_enc = NULL;
448 	int i = 0;
449 
450 	if (!drm_enc) {
451 		DPU_ERROR("invalid encoder\n");
452 		return;
453 	}
454 
455 	dpu_enc = to_dpu_encoder_virt(drm_enc);
456 	DPU_DEBUG_ENC(dpu_enc, "\n");
457 
458 	mutex_lock(&dpu_enc->enc_lock);
459 
460 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
461 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
462 
463 		if (phys->ops.destroy) {
464 			phys->ops.destroy(phys);
465 			--dpu_enc->num_phys_encs;
466 			dpu_enc->phys_encs[i] = NULL;
467 		}
468 	}
469 
470 	if (dpu_enc->num_phys_encs)
471 		DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
472 				dpu_enc->num_phys_encs);
473 	dpu_enc->num_phys_encs = 0;
474 	mutex_unlock(&dpu_enc->enc_lock);
475 
476 	drm_encoder_cleanup(drm_enc);
477 	mutex_destroy(&dpu_enc->enc_lock);
478 }
479 
dpu_encoder_helper_split_config(struct dpu_encoder_phys * phys_enc,enum dpu_intf interface)480 void dpu_encoder_helper_split_config(
481 		struct dpu_encoder_phys *phys_enc,
482 		enum dpu_intf interface)
483 {
484 	struct dpu_encoder_virt *dpu_enc;
485 	struct split_pipe_cfg cfg = { 0 };
486 	struct dpu_hw_mdp *hw_mdptop;
487 	struct msm_display_info *disp_info;
488 
489 	if (!phys_enc->hw_mdptop || !phys_enc->parent) {
490 		DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
491 		return;
492 	}
493 
494 	dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
495 	hw_mdptop = phys_enc->hw_mdptop;
496 	disp_info = &dpu_enc->disp_info;
497 
498 	if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
499 		return;
500 
501 	/**
502 	 * disable split modes since encoder will be operating in as the only
503 	 * encoder, either for the entire use case in the case of, for example,
504 	 * single DSI, or for this frame in the case of left/right only partial
505 	 * update.
506 	 */
507 	if (phys_enc->split_role == ENC_ROLE_SOLO) {
508 		if (hw_mdptop->ops.setup_split_pipe)
509 			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
510 		return;
511 	}
512 
513 	cfg.en = true;
514 	cfg.mode = phys_enc->intf_mode;
515 	cfg.intf = interface;
516 
517 	if (cfg.en && phys_enc->ops.needs_single_flush &&
518 			phys_enc->ops.needs_single_flush(phys_enc))
519 		cfg.split_flush_en = true;
520 
521 	if (phys_enc->split_role == ENC_ROLE_MASTER) {
522 		DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
523 
524 		if (hw_mdptop->ops.setup_split_pipe)
525 			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
526 	}
527 }
528 
dpu_encoder_use_dsc_merge(struct drm_encoder * drm_enc)529 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
530 {
531 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
532 	int i, intf_count = 0, num_dsc = 0;
533 
534 	for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
535 		if (dpu_enc->phys_encs[i])
536 			intf_count++;
537 
538 	/* See dpu_encoder_get_topology, we only support 2:2:1 topology */
539 	if (dpu_enc->dsc)
540 		num_dsc = 2;
541 
542 	return (num_dsc > 0) && (num_dsc > intf_count);
543 }
544 
dpu_encoder_get_topology(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct drm_display_mode * mode)545 static struct msm_display_topology dpu_encoder_get_topology(
546 			struct dpu_encoder_virt *dpu_enc,
547 			struct dpu_kms *dpu_kms,
548 			struct drm_display_mode *mode)
549 {
550 	struct msm_display_topology topology = {0};
551 	int i, intf_count = 0;
552 
553 	for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
554 		if (dpu_enc->phys_encs[i])
555 			intf_count++;
556 
557 	/* Datapath topology selection
558 	 *
559 	 * Dual display
560 	 * 2 LM, 2 INTF ( Split display using 2 interfaces)
561 	 *
562 	 * Single display
563 	 * 1 LM, 1 INTF
564 	 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
565 	 *
566 	 * Adding color blocks only to primary interface if available in
567 	 * sufficient number
568 	 */
569 	if (intf_count == 2)
570 		topology.num_lm = 2;
571 	else if (!dpu_kms->catalog->caps->has_3d_merge)
572 		topology.num_lm = 1;
573 	else
574 		topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
575 
576 	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
577 		if (dpu_kms->catalog->dspp &&
578 			(dpu_kms->catalog->dspp_count >= topology.num_lm))
579 			topology.num_dspp = topology.num_lm;
580 	}
581 
582 	topology.num_enc = 0;
583 	topology.num_intf = intf_count;
584 
585 	if (dpu_enc->dsc) {
586 		/* In case of Display Stream Compression (DSC), we would use
587 		 * 2 encoders, 2 layer mixers and 1 interface
588 		 * this is power optimal and can drive up to (including) 4k
589 		 * screens
590 		 */
591 		topology.num_enc = 2;
592 		topology.num_dsc = 2;
593 		topology.num_intf = 1;
594 		topology.num_lm = 2;
595 	}
596 
597 	return topology;
598 }
599 
dpu_encoder_virt_atomic_check(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)600 static int dpu_encoder_virt_atomic_check(
601 		struct drm_encoder *drm_enc,
602 		struct drm_crtc_state *crtc_state,
603 		struct drm_connector_state *conn_state)
604 {
605 	struct dpu_encoder_virt *dpu_enc;
606 	struct msm_drm_private *priv;
607 	struct dpu_kms *dpu_kms;
608 	struct drm_display_mode *adj_mode;
609 	struct msm_display_topology topology;
610 	struct dpu_global_state *global_state;
611 	int i = 0;
612 	int ret = 0;
613 
614 	if (!drm_enc || !crtc_state || !conn_state) {
615 		DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
616 				drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
617 		return -EINVAL;
618 	}
619 
620 	dpu_enc = to_dpu_encoder_virt(drm_enc);
621 	DPU_DEBUG_ENC(dpu_enc, "\n");
622 
623 	priv = drm_enc->dev->dev_private;
624 	dpu_kms = to_dpu_kms(priv->kms);
625 	adj_mode = &crtc_state->adjusted_mode;
626 	global_state = dpu_kms_get_global_state(crtc_state->state);
627 	if (IS_ERR(global_state))
628 		return PTR_ERR(global_state);
629 
630 	trace_dpu_enc_atomic_check(DRMID(drm_enc));
631 
632 	/* perform atomic check on the first physical encoder (master) */
633 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
634 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
635 
636 		if (phys->ops.atomic_check)
637 			ret = phys->ops.atomic_check(phys, crtc_state,
638 					conn_state);
639 		if (ret) {
640 			DPU_ERROR_ENC(dpu_enc,
641 					"mode unsupported, phys idx %d\n", i);
642 			break;
643 		}
644 	}
645 
646 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
647 
648 	/* Reserve dynamic resources now. */
649 	if (!ret) {
650 		/*
651 		 * Release and Allocate resources on every modeset
652 		 * Dont allocate when active is false.
653 		 */
654 		if (drm_atomic_crtc_needs_modeset(crtc_state)) {
655 			dpu_rm_release(global_state, drm_enc);
656 
657 			if (!crtc_state->active_changed || crtc_state->active)
658 				ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
659 						drm_enc, crtc_state, topology);
660 		}
661 	}
662 
663 	trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
664 
665 	return ret;
666 }
667 
_dpu_encoder_update_vsync_source(struct dpu_encoder_virt * dpu_enc,struct msm_display_info * disp_info)668 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
669 			struct msm_display_info *disp_info)
670 {
671 	struct dpu_vsync_source_cfg vsync_cfg = { 0 };
672 	struct msm_drm_private *priv;
673 	struct dpu_kms *dpu_kms;
674 	struct dpu_hw_mdp *hw_mdptop;
675 	struct drm_encoder *drm_enc;
676 	int i;
677 
678 	if (!dpu_enc || !disp_info) {
679 		DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
680 					dpu_enc != NULL, disp_info != NULL);
681 		return;
682 	} else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
683 		DPU_ERROR("invalid num phys enc %d/%d\n",
684 				dpu_enc->num_phys_encs,
685 				(int) ARRAY_SIZE(dpu_enc->hw_pp));
686 		return;
687 	}
688 
689 	drm_enc = &dpu_enc->base;
690 	/* this pointers are checked in virt_enable_helper */
691 	priv = drm_enc->dev->dev_private;
692 
693 	dpu_kms = to_dpu_kms(priv->kms);
694 	hw_mdptop = dpu_kms->hw_mdp;
695 	if (!hw_mdptop) {
696 		DPU_ERROR("invalid mdptop\n");
697 		return;
698 	}
699 
700 	if (hw_mdptop->ops.setup_vsync_source &&
701 			disp_info->is_cmd_mode) {
702 		for (i = 0; i < dpu_enc->num_phys_encs; i++)
703 			vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
704 
705 		vsync_cfg.pp_count = dpu_enc->num_phys_encs;
706 		if (disp_info->is_te_using_watchdog_timer)
707 			vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
708 		else
709 			vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
710 
711 		hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
712 	}
713 }
714 
_dpu_encoder_irq_control(struct drm_encoder * drm_enc,bool enable)715 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
716 {
717 	struct dpu_encoder_virt *dpu_enc;
718 	int i;
719 
720 	if (!drm_enc) {
721 		DPU_ERROR("invalid encoder\n");
722 		return;
723 	}
724 
725 	dpu_enc = to_dpu_encoder_virt(drm_enc);
726 
727 	DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
728 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
729 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
730 
731 		if (phys->ops.irq_control)
732 			phys->ops.irq_control(phys, enable);
733 	}
734 
735 }
736 
_dpu_encoder_resource_control_helper(struct drm_encoder * drm_enc,bool enable)737 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
738 		bool enable)
739 {
740 	struct msm_drm_private *priv;
741 	struct dpu_kms *dpu_kms;
742 	struct dpu_encoder_virt *dpu_enc;
743 
744 	dpu_enc = to_dpu_encoder_virt(drm_enc);
745 	priv = drm_enc->dev->dev_private;
746 	dpu_kms = to_dpu_kms(priv->kms);
747 
748 	trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
749 
750 	if (!dpu_enc->cur_master) {
751 		DPU_ERROR("encoder master not set\n");
752 		return;
753 	}
754 
755 	if (enable) {
756 		/* enable DPU core clks */
757 		pm_runtime_get_sync(&dpu_kms->pdev->dev);
758 
759 		/* enable all the irq */
760 		_dpu_encoder_irq_control(drm_enc, true);
761 
762 	} else {
763 		/* disable all the irq */
764 		_dpu_encoder_irq_control(drm_enc, false);
765 
766 		/* disable DPU core clks */
767 		pm_runtime_put_sync(&dpu_kms->pdev->dev);
768 	}
769 
770 }
771 
dpu_encoder_resource_control(struct drm_encoder * drm_enc,u32 sw_event)772 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
773 		u32 sw_event)
774 {
775 	struct dpu_encoder_virt *dpu_enc;
776 	struct msm_drm_private *priv;
777 	bool is_vid_mode = false;
778 
779 	if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
780 		DPU_ERROR("invalid parameters\n");
781 		return -EINVAL;
782 	}
783 	dpu_enc = to_dpu_encoder_virt(drm_enc);
784 	priv = drm_enc->dev->dev_private;
785 	is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
786 
787 	/*
788 	 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
789 	 * events and return early for other events (ie wb display).
790 	 */
791 	if (!dpu_enc->idle_pc_supported &&
792 			(sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
793 			sw_event != DPU_ENC_RC_EVENT_STOP &&
794 			sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
795 		return 0;
796 
797 	trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
798 			 dpu_enc->rc_state, "begin");
799 
800 	switch (sw_event) {
801 	case DPU_ENC_RC_EVENT_KICKOFF:
802 		/* cancel delayed off work, if any */
803 		if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
804 			DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
805 					sw_event);
806 
807 		mutex_lock(&dpu_enc->rc_lock);
808 
809 		/* return if the resource control is already in ON state */
810 		if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
811 			DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
812 				      DRMID(drm_enc), sw_event);
813 			mutex_unlock(&dpu_enc->rc_lock);
814 			return 0;
815 		} else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
816 				dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
817 			DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
818 				      DRMID(drm_enc), sw_event,
819 				      dpu_enc->rc_state);
820 			mutex_unlock(&dpu_enc->rc_lock);
821 			return -EINVAL;
822 		}
823 
824 		if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
825 			_dpu_encoder_irq_control(drm_enc, true);
826 		else
827 			_dpu_encoder_resource_control_helper(drm_enc, true);
828 
829 		dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
830 
831 		trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
832 				 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
833 				 "kickoff");
834 
835 		mutex_unlock(&dpu_enc->rc_lock);
836 		break;
837 
838 	case DPU_ENC_RC_EVENT_FRAME_DONE:
839 		/*
840 		 * mutex lock is not used as this event happens at interrupt
841 		 * context. And locking is not required as, the other events
842 		 * like KICKOFF and STOP does a wait-for-idle before executing
843 		 * the resource_control
844 		 */
845 		if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
846 			DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
847 				      DRMID(drm_enc), sw_event,
848 				      dpu_enc->rc_state);
849 			return -EINVAL;
850 		}
851 
852 		/*
853 		 * schedule off work item only when there are no
854 		 * frames pending
855 		 */
856 		if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
857 			DRM_DEBUG_KMS("id:%d skip schedule work\n",
858 				      DRMID(drm_enc));
859 			return 0;
860 		}
861 
862 		queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
863 				   msecs_to_jiffies(dpu_enc->idle_timeout));
864 
865 		trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
866 				 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
867 				 "frame done");
868 		break;
869 
870 	case DPU_ENC_RC_EVENT_PRE_STOP:
871 		/* cancel delayed off work, if any */
872 		if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
873 			DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
874 					sw_event);
875 
876 		mutex_lock(&dpu_enc->rc_lock);
877 
878 		if (is_vid_mode &&
879 			  dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
880 			_dpu_encoder_irq_control(drm_enc, true);
881 		}
882 		/* skip if is already OFF or IDLE, resources are off already */
883 		else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
884 				dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
885 			DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
886 				      DRMID(drm_enc), sw_event,
887 				      dpu_enc->rc_state);
888 			mutex_unlock(&dpu_enc->rc_lock);
889 			return 0;
890 		}
891 
892 		dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
893 
894 		trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
895 				 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
896 				 "pre stop");
897 
898 		mutex_unlock(&dpu_enc->rc_lock);
899 		break;
900 
901 	case DPU_ENC_RC_EVENT_STOP:
902 		mutex_lock(&dpu_enc->rc_lock);
903 
904 		/* return if the resource control is already in OFF state */
905 		if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
906 			DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
907 				      DRMID(drm_enc), sw_event);
908 			mutex_unlock(&dpu_enc->rc_lock);
909 			return 0;
910 		} else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
911 			DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
912 				  DRMID(drm_enc), sw_event, dpu_enc->rc_state);
913 			mutex_unlock(&dpu_enc->rc_lock);
914 			return -EINVAL;
915 		}
916 
917 		/**
918 		 * expect to arrive here only if in either idle state or pre-off
919 		 * and in IDLE state the resources are already disabled
920 		 */
921 		if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
922 			_dpu_encoder_resource_control_helper(drm_enc, false);
923 
924 		dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
925 
926 		trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
927 				 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
928 				 "stop");
929 
930 		mutex_unlock(&dpu_enc->rc_lock);
931 		break;
932 
933 	case DPU_ENC_RC_EVENT_ENTER_IDLE:
934 		mutex_lock(&dpu_enc->rc_lock);
935 
936 		if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
937 			DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
938 				  DRMID(drm_enc), sw_event, dpu_enc->rc_state);
939 			mutex_unlock(&dpu_enc->rc_lock);
940 			return 0;
941 		}
942 
943 		/*
944 		 * if we are in ON but a frame was just kicked off,
945 		 * ignore the IDLE event, it's probably a stale timer event
946 		 */
947 		if (dpu_enc->frame_busy_mask[0]) {
948 			DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
949 				  DRMID(drm_enc), sw_event, dpu_enc->rc_state);
950 			mutex_unlock(&dpu_enc->rc_lock);
951 			return 0;
952 		}
953 
954 		if (is_vid_mode)
955 			_dpu_encoder_irq_control(drm_enc, false);
956 		else
957 			_dpu_encoder_resource_control_helper(drm_enc, false);
958 
959 		dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
960 
961 		trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
962 				 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
963 				 "idle");
964 
965 		mutex_unlock(&dpu_enc->rc_lock);
966 		break;
967 
968 	default:
969 		DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
970 			  sw_event);
971 		trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
972 				 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
973 				 "error");
974 		break;
975 	}
976 
977 	trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
978 			 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
979 			 "end");
980 	return 0;
981 }
982 
dpu_encoder_prepare_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)983 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
984 		struct drm_writeback_job *job)
985 {
986 	struct dpu_encoder_virt *dpu_enc;
987 	int i;
988 
989 	dpu_enc = to_dpu_encoder_virt(drm_enc);
990 
991 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
992 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
993 
994 		if (phys->ops.prepare_wb_job)
995 			phys->ops.prepare_wb_job(phys, job);
996 
997 	}
998 }
999 
dpu_encoder_cleanup_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1000 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
1001 		struct drm_writeback_job *job)
1002 {
1003 	struct dpu_encoder_virt *dpu_enc;
1004 	int i;
1005 
1006 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1007 
1008 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1009 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1010 
1011 		if (phys->ops.cleanup_wb_job)
1012 			phys->ops.cleanup_wb_job(phys, job);
1013 
1014 	}
1015 }
1016 
dpu_encoder_virt_atomic_mode_set(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1017 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
1018 					     struct drm_crtc_state *crtc_state,
1019 					     struct drm_connector_state *conn_state)
1020 {
1021 	struct dpu_encoder_virt *dpu_enc;
1022 	struct msm_drm_private *priv;
1023 	struct dpu_kms *dpu_kms;
1024 	struct dpu_crtc_state *cstate;
1025 	struct dpu_global_state *global_state;
1026 	struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
1027 	struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
1028 	struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
1029 	struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
1030 	struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
1031 	int num_lm, num_ctl, num_pp, num_dsc;
1032 	unsigned int dsc_mask = 0;
1033 	int i;
1034 
1035 	if (!drm_enc) {
1036 		DPU_ERROR("invalid encoder\n");
1037 		return;
1038 	}
1039 
1040 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1041 	DPU_DEBUG_ENC(dpu_enc, "\n");
1042 
1043 	priv = drm_enc->dev->dev_private;
1044 	dpu_kms = to_dpu_kms(priv->kms);
1045 
1046 	global_state = dpu_kms_get_existing_global_state(dpu_kms);
1047 	if (IS_ERR_OR_NULL(global_state)) {
1048 		DPU_ERROR("Failed to get global state");
1049 		return;
1050 	}
1051 
1052 	trace_dpu_enc_mode_set(DRMID(drm_enc));
1053 
1054 	/* Query resource that have been reserved in atomic check step. */
1055 	num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1056 		drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1057 		ARRAY_SIZE(hw_pp));
1058 	num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1059 		drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1060 	num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1061 		drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1062 	dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1063 		drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
1064 		ARRAY_SIZE(hw_dspp));
1065 
1066 	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1067 		dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1068 						: NULL;
1069 
1070 	if (dpu_enc->dsc) {
1071 		num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1072 							drm_enc->base.id, DPU_HW_BLK_DSC,
1073 							hw_dsc, ARRAY_SIZE(hw_dsc));
1074 		for (i = 0; i < num_dsc; i++) {
1075 			dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
1076 			dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
1077 		}
1078 	}
1079 
1080 	dpu_enc->dsc_mask = dsc_mask;
1081 
1082 	cstate = to_dpu_crtc_state(crtc_state);
1083 
1084 	for (i = 0; i < num_lm; i++) {
1085 		int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1086 
1087 		cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1088 		cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1089 		cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1090 	}
1091 
1092 	cstate->num_mixers = num_lm;
1093 
1094 	dpu_enc->connector = conn_state->connector;
1095 
1096 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1097 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1098 
1099 		if (!dpu_enc->hw_pp[i]) {
1100 			DPU_ERROR_ENC(dpu_enc,
1101 				"no pp block assigned at idx: %d\n", i);
1102 			return;
1103 		}
1104 
1105 		if (!hw_ctl[i]) {
1106 			DPU_ERROR_ENC(dpu_enc,
1107 				"no ctl block assigned at idx: %d\n", i);
1108 			return;
1109 		}
1110 
1111 		phys->hw_pp = dpu_enc->hw_pp[i];
1112 		phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
1113 
1114 		phys->cached_mode = crtc_state->adjusted_mode;
1115 		if (phys->ops.atomic_mode_set)
1116 			phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
1117 	}
1118 }
1119 
_dpu_encoder_virt_enable_helper(struct drm_encoder * drm_enc)1120 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1121 {
1122 	struct dpu_encoder_virt *dpu_enc = NULL;
1123 	int i;
1124 
1125 	if (!drm_enc || !drm_enc->dev) {
1126 		DPU_ERROR("invalid parameters\n");
1127 		return;
1128 	}
1129 
1130 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1131 	if (!dpu_enc || !dpu_enc->cur_master) {
1132 		DPU_ERROR("invalid dpu encoder/master\n");
1133 		return;
1134 	}
1135 
1136 
1137 	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
1138 		dpu_enc->cur_master->hw_mdptop &&
1139 		dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1140 		dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1141 			dpu_enc->cur_master->hw_mdptop);
1142 
1143 	_dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1144 
1145 	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1146 			!WARN_ON(dpu_enc->num_phys_encs == 0)) {
1147 		unsigned bpc = dpu_enc->connector->display_info.bpc;
1148 		for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1149 			if (!dpu_enc->hw_pp[i])
1150 				continue;
1151 			_dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1152 		}
1153 	}
1154 }
1155 
dpu_encoder_virt_runtime_resume(struct drm_encoder * drm_enc)1156 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1157 {
1158 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1159 
1160 	mutex_lock(&dpu_enc->enc_lock);
1161 
1162 	if (!dpu_enc->enabled)
1163 		goto out;
1164 
1165 	if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1166 		dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1167 	if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1168 		dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1169 
1170 	_dpu_encoder_virt_enable_helper(drm_enc);
1171 
1172 out:
1173 	mutex_unlock(&dpu_enc->enc_lock);
1174 }
1175 
dpu_encoder_virt_enable(struct drm_encoder * drm_enc)1176 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1177 {
1178 	struct dpu_encoder_virt *dpu_enc = NULL;
1179 	int ret = 0;
1180 	struct drm_display_mode *cur_mode = NULL;
1181 
1182 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1183 
1184 	mutex_lock(&dpu_enc->enc_lock);
1185 	cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1186 
1187 	trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1188 			     cur_mode->vdisplay);
1189 
1190 	/* always enable slave encoder before master */
1191 	if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1192 		dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1193 
1194 	if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1195 		dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1196 
1197 	ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1198 	if (ret) {
1199 		DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1200 				ret);
1201 		goto out;
1202 	}
1203 
1204 	_dpu_encoder_virt_enable_helper(drm_enc);
1205 
1206 	dpu_enc->enabled = true;
1207 
1208 out:
1209 	mutex_unlock(&dpu_enc->enc_lock);
1210 }
1211 
dpu_encoder_virt_disable(struct drm_encoder * drm_enc)1212 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1213 {
1214 	struct dpu_encoder_virt *dpu_enc = NULL;
1215 	int i = 0;
1216 
1217 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1218 	DPU_DEBUG_ENC(dpu_enc, "\n");
1219 
1220 	mutex_lock(&dpu_enc->enc_lock);
1221 	dpu_enc->enabled = false;
1222 
1223 	trace_dpu_enc_disable(DRMID(drm_enc));
1224 
1225 	/* wait for idle */
1226 	dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1227 
1228 	dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1229 
1230 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1231 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1232 
1233 		if (phys->ops.disable)
1234 			phys->ops.disable(phys);
1235 	}
1236 
1237 
1238 	/* after phys waits for frame-done, should be no more frames pending */
1239 	if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1240 		DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1241 		del_timer_sync(&dpu_enc->frame_done_timer);
1242 	}
1243 
1244 	dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1245 
1246 	dpu_enc->connector = NULL;
1247 
1248 	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1249 
1250 	mutex_unlock(&dpu_enc->enc_lock);
1251 }
1252 
dpu_encoder_get_intf(const struct dpu_mdss_cfg * catalog,enum dpu_intf_type type,u32 controller_id)1253 static enum dpu_intf dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
1254 		enum dpu_intf_type type, u32 controller_id)
1255 {
1256 	int i = 0;
1257 
1258 	if (type == INTF_WB)
1259 		return INTF_MAX;
1260 
1261 	for (i = 0; i < catalog->intf_count; i++) {
1262 		if (catalog->intf[i].type == type
1263 		    && catalog->intf[i].controller_id == controller_id) {
1264 			return catalog->intf[i].id;
1265 		}
1266 	}
1267 
1268 	return INTF_MAX;
1269 }
1270 
dpu_encoder_get_wb(const struct dpu_mdss_cfg * catalog,enum dpu_intf_type type,u32 controller_id)1271 static enum dpu_wb dpu_encoder_get_wb(const struct dpu_mdss_cfg *catalog,
1272 		enum dpu_intf_type type, u32 controller_id)
1273 {
1274 	int i = 0;
1275 
1276 	if (type != INTF_WB)
1277 		return WB_MAX;
1278 
1279 	for (i = 0; i < catalog->wb_count; i++) {
1280 		if (catalog->wb[i].id == controller_id)
1281 			return catalog->wb[i].id;
1282 	}
1283 
1284 	return WB_MAX;
1285 }
1286 
dpu_encoder_vblank_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1287 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1288 		struct dpu_encoder_phys *phy_enc)
1289 {
1290 	struct dpu_encoder_virt *dpu_enc = NULL;
1291 	unsigned long lock_flags;
1292 
1293 	if (!drm_enc || !phy_enc)
1294 		return;
1295 
1296 	DPU_ATRACE_BEGIN("encoder_vblank_callback");
1297 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1298 
1299 	atomic_inc(&phy_enc->vsync_cnt);
1300 
1301 	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1302 	if (dpu_enc->crtc)
1303 		dpu_crtc_vblank_callback(dpu_enc->crtc);
1304 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1305 
1306 	DPU_ATRACE_END("encoder_vblank_callback");
1307 }
1308 
dpu_encoder_underrun_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1309 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1310 		struct dpu_encoder_phys *phy_enc)
1311 {
1312 	if (!phy_enc)
1313 		return;
1314 
1315 	DPU_ATRACE_BEGIN("encoder_underrun_callback");
1316 	atomic_inc(&phy_enc->underrun_cnt);
1317 
1318 	/* trigger dump only on the first underrun */
1319 	if (atomic_read(&phy_enc->underrun_cnt) == 1)
1320 		msm_disp_snapshot_state(drm_enc->dev);
1321 
1322 	trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1323 				  atomic_read(&phy_enc->underrun_cnt));
1324 	DPU_ATRACE_END("encoder_underrun_callback");
1325 }
1326 
dpu_encoder_assign_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc)1327 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1328 {
1329 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1330 	unsigned long lock_flags;
1331 
1332 	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1333 	/* crtc should always be cleared before re-assigning */
1334 	WARN_ON(crtc && dpu_enc->crtc);
1335 	dpu_enc->crtc = crtc;
1336 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1337 }
1338 
dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc,bool enable)1339 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1340 					struct drm_crtc *crtc, bool enable)
1341 {
1342 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1343 	unsigned long lock_flags;
1344 	int i;
1345 
1346 	trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1347 
1348 	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1349 	if (dpu_enc->crtc != crtc) {
1350 		spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1351 		return;
1352 	}
1353 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1354 
1355 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1356 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1357 
1358 		if (phys->ops.control_vblank_irq)
1359 			phys->ops.control_vblank_irq(phys, enable);
1360 	}
1361 }
1362 
dpu_encoder_register_frame_event_callback(struct drm_encoder * drm_enc,void (* frame_event_cb)(void *,u32 event),void * frame_event_cb_data)1363 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1364 		void (*frame_event_cb)(void *, u32 event),
1365 		void *frame_event_cb_data)
1366 {
1367 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1368 	unsigned long lock_flags;
1369 	bool enable;
1370 
1371 	enable = frame_event_cb ? true : false;
1372 
1373 	if (!drm_enc) {
1374 		DPU_ERROR("invalid encoder\n");
1375 		return;
1376 	}
1377 	trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1378 
1379 	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1380 	dpu_enc->crtc_frame_event_cb = frame_event_cb;
1381 	dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1382 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1383 }
1384 
dpu_encoder_frame_done_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * ready_phys,u32 event)1385 static void dpu_encoder_frame_done_callback(
1386 		struct drm_encoder *drm_enc,
1387 		struct dpu_encoder_phys *ready_phys, u32 event)
1388 {
1389 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1390 	unsigned int i;
1391 
1392 	if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1393 			| DPU_ENCODER_FRAME_EVENT_ERROR
1394 			| DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1395 
1396 		if (!dpu_enc->frame_busy_mask[0]) {
1397 			/**
1398 			 * suppress frame_done without waiter,
1399 			 * likely autorefresh
1400 			 */
1401 			trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
1402 					dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
1403 					ready_phys->intf_idx, ready_phys->wb_idx);
1404 			return;
1405 		}
1406 
1407 		/* One of the physical encoders has become idle */
1408 		for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1409 			if (dpu_enc->phys_encs[i] == ready_phys) {
1410 				trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1411 						dpu_enc->frame_busy_mask[0]);
1412 				clear_bit(i, dpu_enc->frame_busy_mask);
1413 			}
1414 		}
1415 
1416 		if (!dpu_enc->frame_busy_mask[0]) {
1417 			atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1418 			del_timer(&dpu_enc->frame_done_timer);
1419 
1420 			dpu_encoder_resource_control(drm_enc,
1421 					DPU_ENC_RC_EVENT_FRAME_DONE);
1422 
1423 			if (dpu_enc->crtc_frame_event_cb)
1424 				dpu_enc->crtc_frame_event_cb(
1425 					dpu_enc->crtc_frame_event_cb_data,
1426 					event);
1427 		}
1428 	} else {
1429 		if (dpu_enc->crtc_frame_event_cb)
1430 			dpu_enc->crtc_frame_event_cb(
1431 				dpu_enc->crtc_frame_event_cb_data, event);
1432 	}
1433 }
1434 
dpu_encoder_off_work(struct work_struct * work)1435 static void dpu_encoder_off_work(struct work_struct *work)
1436 {
1437 	struct dpu_encoder_virt *dpu_enc = container_of(work,
1438 			struct dpu_encoder_virt, delayed_off_work.work);
1439 
1440 	dpu_encoder_resource_control(&dpu_enc->base,
1441 						DPU_ENC_RC_EVENT_ENTER_IDLE);
1442 
1443 	dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1444 				DPU_ENCODER_FRAME_EVENT_IDLE);
1445 }
1446 
1447 /**
1448  * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1449  * @drm_enc: Pointer to drm encoder structure
1450  * @phys: Pointer to physical encoder structure
1451  * @extra_flush_bits: Additional bit mask to include in flush trigger
1452  */
_dpu_encoder_trigger_flush(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phys,uint32_t extra_flush_bits)1453 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1454 		struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1455 {
1456 	struct dpu_hw_ctl *ctl;
1457 	int pending_kickoff_cnt;
1458 	u32 ret = UINT_MAX;
1459 
1460 	if (!phys->hw_pp) {
1461 		DPU_ERROR("invalid pingpong hw\n");
1462 		return;
1463 	}
1464 
1465 	ctl = phys->hw_ctl;
1466 	if (!ctl->ops.trigger_flush) {
1467 		DPU_ERROR("missing trigger cb\n");
1468 		return;
1469 	}
1470 
1471 	pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1472 
1473 	if (extra_flush_bits && ctl->ops.update_pending_flush)
1474 		ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1475 
1476 	ctl->ops.trigger_flush(ctl);
1477 
1478 	if (ctl->ops.get_pending_flush)
1479 		ret = ctl->ops.get_pending_flush(ctl);
1480 
1481 	trace_dpu_enc_trigger_flush(DRMID(drm_enc),
1482 			dpu_encoder_helper_get_intf_type(phys->intf_mode),
1483 			phys->intf_idx, phys->wb_idx,
1484 			pending_kickoff_cnt, ctl->idx,
1485 			extra_flush_bits, ret);
1486 }
1487 
1488 /**
1489  * _dpu_encoder_trigger_start - trigger start for a physical encoder
1490  * @phys: Pointer to physical encoder structure
1491  */
_dpu_encoder_trigger_start(struct dpu_encoder_phys * phys)1492 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1493 {
1494 	if (!phys) {
1495 		DPU_ERROR("invalid argument(s)\n");
1496 		return;
1497 	}
1498 
1499 	if (!phys->hw_pp) {
1500 		DPU_ERROR("invalid pingpong hw\n");
1501 		return;
1502 	}
1503 
1504 	if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1505 		phys->ops.trigger_start(phys);
1506 }
1507 
dpu_encoder_helper_trigger_start(struct dpu_encoder_phys * phys_enc)1508 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1509 {
1510 	struct dpu_hw_ctl *ctl;
1511 
1512 	ctl = phys_enc->hw_ctl;
1513 	if (ctl->ops.trigger_start) {
1514 		ctl->ops.trigger_start(ctl);
1515 		trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1516 	}
1517 }
1518 
dpu_encoder_helper_wait_event_timeout(int32_t drm_id,u32 irq_idx,struct dpu_encoder_wait_info * info)1519 static int dpu_encoder_helper_wait_event_timeout(
1520 		int32_t drm_id,
1521 		u32 irq_idx,
1522 		struct dpu_encoder_wait_info *info)
1523 {
1524 	int rc = 0;
1525 	s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1526 	s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1527 	s64 time;
1528 
1529 	do {
1530 		rc = wait_event_timeout(*(info->wq),
1531 				atomic_read(info->atomic_cnt) == 0, jiffies);
1532 		time = ktime_to_ms(ktime_get());
1533 
1534 		trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
1535 						 expected_time,
1536 						 atomic_read(info->atomic_cnt));
1537 	/* If we timed out, counter is valid and time is less, wait again */
1538 	} while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1539 			(time < expected_time));
1540 
1541 	return rc;
1542 }
1543 
dpu_encoder_helper_hw_reset(struct dpu_encoder_phys * phys_enc)1544 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1545 {
1546 	struct dpu_encoder_virt *dpu_enc;
1547 	struct dpu_hw_ctl *ctl;
1548 	int rc;
1549 	struct drm_encoder *drm_enc;
1550 
1551 	dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1552 	ctl = phys_enc->hw_ctl;
1553 	drm_enc = phys_enc->parent;
1554 
1555 	if (!ctl->ops.reset)
1556 		return;
1557 
1558 	DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1559 		      ctl->idx);
1560 
1561 	rc = ctl->ops.reset(ctl);
1562 	if (rc) {
1563 		DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1564 		msm_disp_snapshot_state(drm_enc->dev);
1565 	}
1566 
1567 	phys_enc->enable_state = DPU_ENC_ENABLED;
1568 }
1569 
1570 /**
1571  * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1572  *	Iterate through the physical encoders and perform consolidated flush
1573  *	and/or control start triggering as needed. This is done in the virtual
1574  *	encoder rather than the individual physical ones in order to handle
1575  *	use cases that require visibility into multiple physical encoders at
1576  *	a time.
1577  * @dpu_enc: Pointer to virtual encoder structure
1578  */
_dpu_encoder_kickoff_phys(struct dpu_encoder_virt * dpu_enc)1579 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1580 {
1581 	struct dpu_hw_ctl *ctl;
1582 	uint32_t i, pending_flush;
1583 	unsigned long lock_flags;
1584 
1585 	pending_flush = 0x0;
1586 
1587 	/* update pending counts and trigger kickoff ctl flush atomically */
1588 	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1589 
1590 	/* don't perform flush/start operations for slave encoders */
1591 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1592 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1593 
1594 		if (phys->enable_state == DPU_ENC_DISABLED)
1595 			continue;
1596 
1597 		ctl = phys->hw_ctl;
1598 
1599 		/*
1600 		 * This is cleared in frame_done worker, which isn't invoked
1601 		 * for async commits. So don't set this for async, since it'll
1602 		 * roll over to the next commit.
1603 		 */
1604 		if (phys->split_role != ENC_ROLE_SLAVE)
1605 			set_bit(i, dpu_enc->frame_busy_mask);
1606 
1607 		if (!phys->ops.needs_single_flush ||
1608 				!phys->ops.needs_single_flush(phys))
1609 			_dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1610 		else if (ctl->ops.get_pending_flush)
1611 			pending_flush |= ctl->ops.get_pending_flush(ctl);
1612 	}
1613 
1614 	/* for split flush, combine pending flush masks and send to master */
1615 	if (pending_flush && dpu_enc->cur_master) {
1616 		_dpu_encoder_trigger_flush(
1617 				&dpu_enc->base,
1618 				dpu_enc->cur_master,
1619 				pending_flush);
1620 	}
1621 
1622 	_dpu_encoder_trigger_start(dpu_enc->cur_master);
1623 
1624 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1625 }
1626 
dpu_encoder_trigger_kickoff_pending(struct drm_encoder * drm_enc)1627 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1628 {
1629 	struct dpu_encoder_virt *dpu_enc;
1630 	struct dpu_encoder_phys *phys;
1631 	unsigned int i;
1632 	struct dpu_hw_ctl *ctl;
1633 	struct msm_display_info *disp_info;
1634 
1635 	if (!drm_enc) {
1636 		DPU_ERROR("invalid encoder\n");
1637 		return;
1638 	}
1639 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1640 	disp_info = &dpu_enc->disp_info;
1641 
1642 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1643 		phys = dpu_enc->phys_encs[i];
1644 
1645 		ctl = phys->hw_ctl;
1646 		if (ctl->ops.clear_pending_flush)
1647 			ctl->ops.clear_pending_flush(ctl);
1648 
1649 		/* update only for command mode primary ctl */
1650 		if ((phys == dpu_enc->cur_master) &&
1651 		    disp_info->is_cmd_mode
1652 		    && ctl->ops.trigger_pending)
1653 			ctl->ops.trigger_pending(ctl);
1654 	}
1655 }
1656 
_dpu_encoder_calculate_linetime(struct dpu_encoder_virt * dpu_enc,struct drm_display_mode * mode)1657 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1658 		struct drm_display_mode *mode)
1659 {
1660 	u64 pclk_rate;
1661 	u32 pclk_period;
1662 	u32 line_time;
1663 
1664 	/*
1665 	 * For linetime calculation, only operate on master encoder.
1666 	 */
1667 	if (!dpu_enc->cur_master)
1668 		return 0;
1669 
1670 	if (!dpu_enc->cur_master->ops.get_line_count) {
1671 		DPU_ERROR("get_line_count function not defined\n");
1672 		return 0;
1673 	}
1674 
1675 	pclk_rate = mode->clock; /* pixel clock in kHz */
1676 	if (pclk_rate == 0) {
1677 		DPU_ERROR("pclk is 0, cannot calculate line time\n");
1678 		return 0;
1679 	}
1680 
1681 	pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1682 	if (pclk_period == 0) {
1683 		DPU_ERROR("pclk period is 0\n");
1684 		return 0;
1685 	}
1686 
1687 	/*
1688 	 * Line time calculation based on Pixel clock and HTOTAL.
1689 	 * Final unit is in ns.
1690 	 */
1691 	line_time = (pclk_period * mode->htotal) / 1000;
1692 	if (line_time == 0) {
1693 		DPU_ERROR("line time calculation is 0\n");
1694 		return 0;
1695 	}
1696 
1697 	DPU_DEBUG_ENC(dpu_enc,
1698 			"clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1699 			pclk_rate, pclk_period, line_time);
1700 
1701 	return line_time;
1702 }
1703 
dpu_encoder_vsync_time(struct drm_encoder * drm_enc,ktime_t * wakeup_time)1704 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1705 {
1706 	struct drm_display_mode *mode;
1707 	struct dpu_encoder_virt *dpu_enc;
1708 	u32 cur_line;
1709 	u32 line_time;
1710 	u32 vtotal, time_to_vsync;
1711 	ktime_t cur_time;
1712 
1713 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1714 
1715 	if (!drm_enc->crtc || !drm_enc->crtc->state) {
1716 		DPU_ERROR("crtc/crtc state object is NULL\n");
1717 		return -EINVAL;
1718 	}
1719 	mode = &drm_enc->crtc->state->adjusted_mode;
1720 
1721 	line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1722 	if (!line_time)
1723 		return -EINVAL;
1724 
1725 	cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1726 
1727 	vtotal = mode->vtotal;
1728 	if (cur_line >= vtotal)
1729 		time_to_vsync = line_time * vtotal;
1730 	else
1731 		time_to_vsync = line_time * (vtotal - cur_line);
1732 
1733 	if (time_to_vsync == 0) {
1734 		DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1735 				vtotal);
1736 		return -EINVAL;
1737 	}
1738 
1739 	cur_time = ktime_get();
1740 	*wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1741 
1742 	DPU_DEBUG_ENC(dpu_enc,
1743 			"cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1744 			cur_line, vtotal, time_to_vsync,
1745 			ktime_to_ms(cur_time),
1746 			ktime_to_ms(*wakeup_time));
1747 	return 0;
1748 }
1749 
dpu_encoder_vsync_event_handler(struct timer_list * t)1750 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1751 {
1752 	struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1753 			vsync_event_timer);
1754 	struct drm_encoder *drm_enc = &dpu_enc->base;
1755 	struct msm_drm_private *priv;
1756 	struct msm_drm_thread *event_thread;
1757 
1758 	if (!drm_enc->dev || !drm_enc->crtc) {
1759 		DPU_ERROR("invalid parameters\n");
1760 		return;
1761 	}
1762 
1763 	priv = drm_enc->dev->dev_private;
1764 
1765 	if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1766 		DPU_ERROR("invalid crtc index\n");
1767 		return;
1768 	}
1769 	event_thread = &priv->event_thread[drm_enc->crtc->index];
1770 	if (!event_thread) {
1771 		DPU_ERROR("event_thread not found for crtc:%d\n",
1772 				drm_enc->crtc->index);
1773 		return;
1774 	}
1775 
1776 	del_timer(&dpu_enc->vsync_event_timer);
1777 }
1778 
dpu_encoder_vsync_event_work_handler(struct kthread_work * work)1779 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1780 {
1781 	struct dpu_encoder_virt *dpu_enc = container_of(work,
1782 			struct dpu_encoder_virt, vsync_event_work);
1783 	ktime_t wakeup_time;
1784 
1785 	if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1786 		return;
1787 
1788 	trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1789 	mod_timer(&dpu_enc->vsync_event_timer,
1790 			nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1791 }
1792 
1793 static u32
dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config * dsc,u32 enc_ip_width)1794 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
1795 				  u32 enc_ip_width)
1796 {
1797 	int ssm_delay, total_pixels, soft_slice_per_enc;
1798 
1799 	soft_slice_per_enc = enc_ip_width / dsc->slice_width;
1800 
1801 	/*
1802 	 * minimum number of initial line pixels is a sum of:
1803 	 * 1. sub-stream multiplexer delay (83 groups for 8bpc,
1804 	 *    91 for 10 bpc) * 3
1805 	 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
1806 	 * 3. the initial xmit delay
1807 	 * 4. total pipeline delay through the "lock step" of encoder (47)
1808 	 * 5. 6 additional pixels as the output of the rate buffer is
1809 	 *    48 bits wide
1810 	 */
1811 	ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
1812 	total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
1813 	if (soft_slice_per_enc > 1)
1814 		total_pixels += (ssm_delay * 3);
1815 	return DIV_ROUND_UP(total_pixels, dsc->slice_width);
1816 }
1817 
dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp,struct drm_dsc_config * dsc,u32 common_mode,u32 initial_lines)1818 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
1819 				     struct dpu_hw_pingpong *hw_pp,
1820 				     struct drm_dsc_config *dsc,
1821 				     u32 common_mode,
1822 				     u32 initial_lines)
1823 {
1824 	if (hw_dsc->ops.dsc_config)
1825 		hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);
1826 
1827 	if (hw_dsc->ops.dsc_config_thresh)
1828 		hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
1829 
1830 	if (hw_pp->ops.setup_dsc)
1831 		hw_pp->ops.setup_dsc(hw_pp);
1832 
1833 	if (hw_pp->ops.enable_dsc)
1834 		hw_pp->ops.enable_dsc(hw_pp);
1835 }
1836 
dpu_encoder_prep_dsc(struct dpu_encoder_virt * dpu_enc,struct drm_dsc_config * dsc)1837 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
1838 				 struct drm_dsc_config *dsc)
1839 {
1840 	/* coding only for 2LM, 2enc, 1 dsc config */
1841 	struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
1842 	struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
1843 	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
1844 	int this_frame_slices;
1845 	int intf_ip_w, enc_ip_w;
1846 	int dsc_common_mode;
1847 	int pic_width;
1848 	u32 initial_lines;
1849 	int i;
1850 
1851 	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1852 		hw_pp[i] = dpu_enc->hw_pp[i];
1853 		hw_dsc[i] = dpu_enc->hw_dsc[i];
1854 
1855 		if (!hw_pp[i] || !hw_dsc[i]) {
1856 			DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
1857 			return;
1858 		}
1859 	}
1860 
1861 	dsc_common_mode = 0;
1862 	pic_width = dsc->pic_width;
1863 
1864 	dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
1865 	if (enc_master->intf_mode == INTF_MODE_VIDEO)
1866 		dsc_common_mode |= DSC_MODE_VIDEO;
1867 
1868 	this_frame_slices = pic_width / dsc->slice_width;
1869 	intf_ip_w = this_frame_slices * dsc->slice_width;
1870 
1871 	/*
1872 	 * dsc merge case: when using 2 encoders for the same stream,
1873 	 * no. of slices need to be same on both the encoders.
1874 	 */
1875 	enc_ip_w = intf_ip_w / 2;
1876 	initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
1877 
1878 	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1879 		dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines);
1880 }
1881 
dpu_encoder_prepare_for_kickoff(struct drm_encoder * drm_enc)1882 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1883 {
1884 	struct dpu_encoder_virt *dpu_enc;
1885 	struct dpu_encoder_phys *phys;
1886 	bool needs_hw_reset = false;
1887 	unsigned int i;
1888 
1889 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1890 
1891 	trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1892 
1893 	/* prepare for next kickoff, may include waiting on previous kickoff */
1894 	DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1895 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1896 		phys = dpu_enc->phys_encs[i];
1897 		if (phys->ops.prepare_for_kickoff)
1898 			phys->ops.prepare_for_kickoff(phys);
1899 		if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1900 			needs_hw_reset = true;
1901 	}
1902 	DPU_ATRACE_END("enc_prepare_for_kickoff");
1903 
1904 	dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1905 
1906 	/* if any phys needs reset, reset all phys, in-order */
1907 	if (needs_hw_reset) {
1908 		trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1909 		for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1910 			dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1911 		}
1912 	}
1913 
1914 	if (dpu_enc->dsc)
1915 		dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
1916 }
1917 
dpu_encoder_is_valid_for_commit(struct drm_encoder * drm_enc)1918 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc)
1919 {
1920 	struct dpu_encoder_virt *dpu_enc;
1921 	unsigned int i;
1922 	struct dpu_encoder_phys *phys;
1923 
1924 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1925 
1926 	if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1927 		for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1928 			phys = dpu_enc->phys_encs[i];
1929 			if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) {
1930 				DPU_DEBUG("invalid FB not kicking off\n");
1931 				return false;
1932 			}
1933 		}
1934 	}
1935 
1936 	return true;
1937 }
1938 
dpu_encoder_kickoff(struct drm_encoder * drm_enc)1939 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1940 {
1941 	struct dpu_encoder_virt *dpu_enc;
1942 	struct dpu_encoder_phys *phys;
1943 	ktime_t wakeup_time;
1944 	unsigned long timeout_ms;
1945 	unsigned int i;
1946 
1947 	DPU_ATRACE_BEGIN("encoder_kickoff");
1948 	dpu_enc = to_dpu_encoder_virt(drm_enc);
1949 
1950 	trace_dpu_enc_kickoff(DRMID(drm_enc));
1951 
1952 	timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1953 			drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1954 
1955 	atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1956 	mod_timer(&dpu_enc->frame_done_timer,
1957 			jiffies + msecs_to_jiffies(timeout_ms));
1958 
1959 	/* All phys encs are ready to go, trigger the kickoff */
1960 	_dpu_encoder_kickoff_phys(dpu_enc);
1961 
1962 	/* allow phys encs to handle any post-kickoff business */
1963 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1964 		phys = dpu_enc->phys_encs[i];
1965 		if (phys->ops.handle_post_kickoff)
1966 			phys->ops.handle_post_kickoff(phys);
1967 	}
1968 
1969 	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1970 			!dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1971 		trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1972 					    ktime_to_ms(wakeup_time));
1973 		mod_timer(&dpu_enc->vsync_event_timer,
1974 				nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1975 	}
1976 
1977 	DPU_ATRACE_END("encoder_kickoff");
1978 }
1979 
dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys * phys_enc)1980 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
1981 {
1982 	struct dpu_hw_mixer_cfg mixer;
1983 	int i, num_lm;
1984 	struct dpu_global_state *global_state;
1985 	struct dpu_hw_blk *hw_lm[2];
1986 	struct dpu_hw_mixer *hw_mixer[2];
1987 	struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
1988 
1989 	memset(&mixer, 0, sizeof(mixer));
1990 
1991 	/* reset all mixers for this encoder */
1992 	if (phys_enc->hw_ctl->ops.clear_all_blendstages)
1993 		phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
1994 
1995 	global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);
1996 
1997 	num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state,
1998 		phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1999 
2000 	for (i = 0; i < num_lm; i++) {
2001 		hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);
2002 		if (phys_enc->hw_ctl->ops.update_pending_flush_mixer)
2003 			phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx);
2004 
2005 		/* clear all blendstages */
2006 		if (phys_enc->hw_ctl->ops.setup_blendstage)
2007 			phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL);
2008 	}
2009 }
2010 
dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys * phys_enc)2011 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
2012 {
2013 	struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2014 	struct dpu_hw_intf_cfg intf_cfg = { 0 };
2015 	int i;
2016 	struct dpu_encoder_virt *dpu_enc;
2017 
2018 	dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2019 
2020 	phys_enc->hw_ctl->ops.reset(ctl);
2021 
2022 	dpu_encoder_helper_reset_mixers(phys_enc);
2023 
2024 	/*
2025 	 * TODO: move the once-only operation like CTL flush/trigger
2026 	 * into dpu_encoder_virt_disable() and all operations which need
2027 	 * to be done per phys encoder into the phys_disable() op.
2028 	 */
2029 	if (phys_enc->hw_wb) {
2030 		/* disable the PP block */
2031 		if (phys_enc->hw_wb->ops.bind_pingpong_blk)
2032 			phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, false,
2033 					phys_enc->hw_pp->idx);
2034 
2035 		/* mark WB flush as pending */
2036 		if (phys_enc->hw_ctl->ops.update_pending_flush_wb)
2037 			phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx);
2038 	} else {
2039 		for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2040 			if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
2041 				phys_enc->hw_intf->ops.bind_pingpong_blk(
2042 						dpu_enc->phys_encs[i]->hw_intf, false,
2043 						dpu_enc->phys_encs[i]->hw_pp->idx);
2044 
2045 			/* mark INTF flush as pending */
2046 			if (phys_enc->hw_ctl->ops.update_pending_flush_intf)
2047 				phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl,
2048 						dpu_enc->phys_encs[i]->hw_intf->idx);
2049 		}
2050 	}
2051 
2052 	/* reset the merge 3D HW block */
2053 	if (phys_enc->hw_pp->merge_3d) {
2054 		phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
2055 				BLEND_3D_NONE);
2056 		if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d)
2057 			phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl,
2058 					phys_enc->hw_pp->merge_3d->idx);
2059 	}
2060 
2061 	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
2062 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
2063 
2064 	if (phys_enc->hw_intf)
2065 		intf_cfg.intf = phys_enc->hw_intf->idx;
2066 	if (phys_enc->hw_wb)
2067 		intf_cfg.wb = phys_enc->hw_wb->idx;
2068 
2069 	if (phys_enc->hw_pp->merge_3d)
2070 		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
2071 
2072 	if (ctl->ops.reset_intf_cfg)
2073 		ctl->ops.reset_intf_cfg(ctl, &intf_cfg);
2074 
2075 	ctl->ops.trigger_flush(ctl);
2076 	ctl->ops.trigger_start(ctl);
2077 	ctl->ops.clear_pending_flush(ctl);
2078 }
2079 
dpu_encoder_prepare_commit(struct drm_encoder * drm_enc)2080 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
2081 {
2082 	struct dpu_encoder_virt *dpu_enc;
2083 	struct dpu_encoder_phys *phys;
2084 	int i;
2085 
2086 	if (!drm_enc) {
2087 		DPU_ERROR("invalid encoder\n");
2088 		return;
2089 	}
2090 	dpu_enc = to_dpu_encoder_virt(drm_enc);
2091 
2092 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2093 		phys = dpu_enc->phys_encs[i];
2094 		if (phys->ops.prepare_commit)
2095 			phys->ops.prepare_commit(phys);
2096 	}
2097 }
2098 
2099 #ifdef CONFIG_DEBUG_FS
_dpu_encoder_status_show(struct seq_file * s,void * data)2100 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
2101 {
2102 	struct dpu_encoder_virt *dpu_enc = s->private;
2103 	int i;
2104 
2105 	mutex_lock(&dpu_enc->enc_lock);
2106 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2107 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2108 
2109 		seq_printf(s, "intf:%d  wb:%d  vsync:%8d     underrun:%8d    ",
2110 				phys->intf_idx - INTF_0, phys->wb_idx - WB_0,
2111 				atomic_read(&phys->vsync_cnt),
2112 				atomic_read(&phys->underrun_cnt));
2113 
2114 		seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode));
2115 	}
2116 	mutex_unlock(&dpu_enc->enc_lock);
2117 
2118 	return 0;
2119 }
2120 
2121 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
2122 
_dpu_encoder_init_debugfs(struct drm_encoder * drm_enc)2123 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
2124 {
2125 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2126 	int i;
2127 
2128 	char name[DPU_NAME_SIZE];
2129 
2130 	if (!drm_enc->dev) {
2131 		DPU_ERROR("invalid encoder or kms\n");
2132 		return -EINVAL;
2133 	}
2134 
2135 	snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
2136 
2137 	/* create overall sub-directory for the encoder */
2138 	dpu_enc->debugfs_root = debugfs_create_dir(name,
2139 			drm_enc->dev->primary->debugfs_root);
2140 
2141 	/* don't error check these */
2142 	debugfs_create_file("status", 0600,
2143 		dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops);
2144 
2145 	for (i = 0; i < dpu_enc->num_phys_encs; i++)
2146 		if (dpu_enc->phys_encs[i]->ops.late_register)
2147 			dpu_enc->phys_encs[i]->ops.late_register(
2148 					dpu_enc->phys_encs[i],
2149 					dpu_enc->debugfs_root);
2150 
2151 	return 0;
2152 }
2153 #else
_dpu_encoder_init_debugfs(struct drm_encoder * drm_enc)2154 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
2155 {
2156 	return 0;
2157 }
2158 #endif
2159 
dpu_encoder_late_register(struct drm_encoder * encoder)2160 static int dpu_encoder_late_register(struct drm_encoder *encoder)
2161 {
2162 	return _dpu_encoder_init_debugfs(encoder);
2163 }
2164 
dpu_encoder_early_unregister(struct drm_encoder * encoder)2165 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
2166 {
2167 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2168 
2169 	debugfs_remove_recursive(dpu_enc->debugfs_root);
2170 }
2171 
dpu_encoder_virt_add_phys_encs(struct msm_display_info * disp_info,struct dpu_encoder_virt * dpu_enc,struct dpu_enc_phys_init_params * params)2172 static int dpu_encoder_virt_add_phys_encs(
2173 		struct msm_display_info *disp_info,
2174 		struct dpu_encoder_virt *dpu_enc,
2175 		struct dpu_enc_phys_init_params *params)
2176 {
2177 	struct dpu_encoder_phys *enc = NULL;
2178 
2179 	DPU_DEBUG_ENC(dpu_enc, "\n");
2180 
2181 	/*
2182 	 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
2183 	 * in this function, check up-front.
2184 	 */
2185 	if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2186 			ARRAY_SIZE(dpu_enc->phys_encs)) {
2187 		DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2188 			  dpu_enc->num_phys_encs);
2189 		return -EINVAL;
2190 	}
2191 
2192 
2193 	if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
2194 		enc = dpu_encoder_phys_wb_init(params);
2195 
2196 		if (IS_ERR(enc)) {
2197 			DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
2198 				PTR_ERR(enc));
2199 			return PTR_ERR(enc);
2200 		}
2201 
2202 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2203 		++dpu_enc->num_phys_encs;
2204 	} else if (disp_info->is_cmd_mode) {
2205 		enc = dpu_encoder_phys_cmd_init(params);
2206 
2207 		if (IS_ERR(enc)) {
2208 			DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2209 				PTR_ERR(enc));
2210 			return PTR_ERR(enc);
2211 		}
2212 
2213 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2214 		++dpu_enc->num_phys_encs;
2215 	} else {
2216 		enc = dpu_encoder_phys_vid_init(params);
2217 
2218 		if (IS_ERR(enc)) {
2219 			DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2220 				PTR_ERR(enc));
2221 			return PTR_ERR(enc);
2222 		}
2223 
2224 		dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2225 		++dpu_enc->num_phys_encs;
2226 	}
2227 
2228 	if (params->split_role == ENC_ROLE_SLAVE)
2229 		dpu_enc->cur_slave = enc;
2230 	else
2231 		dpu_enc->cur_master = enc;
2232 
2233 	return 0;
2234 }
2235 
2236 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
2237 	.handle_vblank_virt = dpu_encoder_vblank_callback,
2238 	.handle_underrun_virt = dpu_encoder_underrun_callback,
2239 	.handle_frame_done = dpu_encoder_frame_done_callback,
2240 };
2241 
dpu_encoder_setup_display(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct msm_display_info * disp_info)2242 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2243 				 struct dpu_kms *dpu_kms,
2244 				 struct msm_display_info *disp_info)
2245 {
2246 	int ret = 0;
2247 	int i = 0;
2248 	enum dpu_intf_type intf_type = INTF_NONE;
2249 	struct dpu_enc_phys_init_params phys_params;
2250 
2251 	if (!dpu_enc) {
2252 		DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2253 		return -EINVAL;
2254 	}
2255 
2256 	dpu_enc->cur_master = NULL;
2257 
2258 	memset(&phys_params, 0, sizeof(phys_params));
2259 	phys_params.dpu_kms = dpu_kms;
2260 	phys_params.parent = &dpu_enc->base;
2261 	phys_params.parent_ops = &dpu_encoder_parent_ops;
2262 	phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2263 
2264 	switch (disp_info->intf_type) {
2265 	case DRM_MODE_ENCODER_DSI:
2266 		intf_type = INTF_DSI;
2267 		break;
2268 	case DRM_MODE_ENCODER_TMDS:
2269 		intf_type = INTF_DP;
2270 		break;
2271 	case DRM_MODE_ENCODER_VIRTUAL:
2272 		intf_type = INTF_WB;
2273 		break;
2274 	}
2275 
2276 	WARN_ON(disp_info->num_of_h_tiles < 1);
2277 
2278 	DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2279 
2280 	if (disp_info->intf_type != DRM_MODE_ENCODER_VIRTUAL)
2281 		dpu_enc->idle_pc_supported =
2282 				dpu_kms->catalog->caps->has_idle_pc;
2283 
2284 	dpu_enc->dsc = disp_info->dsc;
2285 
2286 	mutex_lock(&dpu_enc->enc_lock);
2287 	for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2288 		/*
2289 		 * Left-most tile is at index 0, content is controller id
2290 		 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2291 		 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2292 		 */
2293 		u32 controller_id = disp_info->h_tile_instance[i];
2294 
2295 		if (disp_info->num_of_h_tiles > 1) {
2296 			if (i == 0)
2297 				phys_params.split_role = ENC_ROLE_MASTER;
2298 			else
2299 				phys_params.split_role = ENC_ROLE_SLAVE;
2300 		} else {
2301 			phys_params.split_role = ENC_ROLE_SOLO;
2302 		}
2303 
2304 		DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2305 				i, controller_id, phys_params.split_role);
2306 
2307 		phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2308 													intf_type,
2309 													controller_id);
2310 
2311 		phys_params.wb_idx = dpu_encoder_get_wb(dpu_kms->catalog,
2312 				intf_type, controller_id);
2313 		/*
2314 		 * The phys_params might represent either an INTF or a WB unit, but not
2315 		 * both of them at the same time.
2316 		 */
2317 		if ((phys_params.intf_idx == INTF_MAX) &&
2318 				(phys_params.wb_idx == WB_MAX)) {
2319 			DPU_ERROR_ENC(dpu_enc, "could not get intf or wb: type %d, id %d\n",
2320 						  intf_type, controller_id);
2321 			ret = -EINVAL;
2322 		}
2323 
2324 		if ((phys_params.intf_idx != INTF_MAX) &&
2325 				(phys_params.wb_idx != WB_MAX)) {
2326 			DPU_ERROR_ENC(dpu_enc, "both intf and wb present: type %d, id %d\n",
2327 						  intf_type, controller_id);
2328 			ret = -EINVAL;
2329 		}
2330 
2331 		if (!ret) {
2332 			ret = dpu_encoder_virt_add_phys_encs(disp_info,
2333 					dpu_enc, &phys_params);
2334 			if (ret)
2335 				DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2336 		}
2337 	}
2338 
2339 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2340 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2341 		atomic_set(&phys->vsync_cnt, 0);
2342 		atomic_set(&phys->underrun_cnt, 0);
2343 
2344 		if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
2345 			phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
2346 
2347 		if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
2348 			phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
2349 
2350 		if (!phys->hw_intf && !phys->hw_wb) {
2351 			DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
2352 			ret = -EINVAL;
2353 		}
2354 
2355 		if (phys->hw_intf && phys->hw_wb) {
2356 			DPU_ERROR_ENC(dpu_enc,
2357 					"invalid phys both intf and wb block at idx: %d\n", i);
2358 			ret = -EINVAL;
2359 		}
2360 	}
2361 
2362 	mutex_unlock(&dpu_enc->enc_lock);
2363 
2364 	return ret;
2365 }
2366 
dpu_encoder_frame_done_timeout(struct timer_list * t)2367 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2368 {
2369 	struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2370 			frame_done_timer);
2371 	struct drm_encoder *drm_enc = &dpu_enc->base;
2372 	u32 event;
2373 
2374 	if (!drm_enc->dev) {
2375 		DPU_ERROR("invalid parameters\n");
2376 		return;
2377 	}
2378 
2379 	if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2380 		DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2381 			      DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2382 		return;
2383 	} else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2384 		DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2385 		return;
2386 	}
2387 
2388 	DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2389 
2390 	event = DPU_ENCODER_FRAME_EVENT_ERROR;
2391 	trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2392 	dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2393 }
2394 
2395 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2396 	.atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
2397 	.disable = dpu_encoder_virt_disable,
2398 	.enable = dpu_encoder_virt_enable,
2399 	.atomic_check = dpu_encoder_virt_atomic_check,
2400 };
2401 
2402 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2403 		.destroy = dpu_encoder_destroy,
2404 		.late_register = dpu_encoder_late_register,
2405 		.early_unregister = dpu_encoder_early_unregister,
2406 };
2407 
dpu_encoder_setup(struct drm_device * dev,struct drm_encoder * enc,struct msm_display_info * disp_info)2408 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2409 		struct msm_display_info *disp_info)
2410 {
2411 	struct msm_drm_private *priv = dev->dev_private;
2412 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2413 	struct drm_encoder *drm_enc = NULL;
2414 	struct dpu_encoder_virt *dpu_enc = NULL;
2415 	int ret = 0;
2416 
2417 	dpu_enc = to_dpu_encoder_virt(enc);
2418 
2419 	ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2420 	if (ret)
2421 		goto fail;
2422 
2423 	atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2424 	timer_setup(&dpu_enc->frame_done_timer,
2425 			dpu_encoder_frame_done_timeout, 0);
2426 
2427 	if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2428 		timer_setup(&dpu_enc->vsync_event_timer,
2429 				dpu_encoder_vsync_event_handler,
2430 				0);
2431 	else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)
2432 		dpu_enc->wide_bus_en = msm_dp_wide_bus_available(
2433 				priv->dp[disp_info->h_tile_instance[0]]);
2434 
2435 	INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2436 			dpu_encoder_off_work);
2437 	dpu_enc->idle_timeout = IDLE_TIMEOUT;
2438 
2439 	kthread_init_work(&dpu_enc->vsync_event_work,
2440 			dpu_encoder_vsync_event_work_handler);
2441 
2442 	memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2443 
2444 	DPU_DEBUG_ENC(dpu_enc, "created\n");
2445 
2446 	return ret;
2447 
2448 fail:
2449 	DPU_ERROR("failed to create encoder\n");
2450 	if (drm_enc)
2451 		dpu_encoder_destroy(drm_enc);
2452 
2453 	return ret;
2454 
2455 
2456 }
2457 
dpu_encoder_init(struct drm_device * dev,int drm_enc_mode)2458 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2459 		int drm_enc_mode)
2460 {
2461 	struct dpu_encoder_virt *dpu_enc = NULL;
2462 	int rc = 0;
2463 
2464 	dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2465 	if (!dpu_enc)
2466 		return ERR_PTR(-ENOMEM);
2467 
2468 
2469 	rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2470 							  drm_enc_mode, NULL);
2471 	if (rc) {
2472 		devm_kfree(dev->dev, dpu_enc);
2473 		return ERR_PTR(rc);
2474 	}
2475 
2476 	drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2477 
2478 	spin_lock_init(&dpu_enc->enc_spinlock);
2479 	dpu_enc->enabled = false;
2480 	mutex_init(&dpu_enc->enc_lock);
2481 	mutex_init(&dpu_enc->rc_lock);
2482 
2483 	return &dpu_enc->base;
2484 }
2485 
dpu_encoder_wait_for_event(struct drm_encoder * drm_enc,enum msm_event_wait event)2486 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2487 	enum msm_event_wait event)
2488 {
2489 	int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2490 	struct dpu_encoder_virt *dpu_enc = NULL;
2491 	int i, ret = 0;
2492 
2493 	if (!drm_enc) {
2494 		DPU_ERROR("invalid encoder\n");
2495 		return -EINVAL;
2496 	}
2497 	dpu_enc = to_dpu_encoder_virt(drm_enc);
2498 	DPU_DEBUG_ENC(dpu_enc, "\n");
2499 
2500 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2501 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2502 
2503 		switch (event) {
2504 		case MSM_ENC_COMMIT_DONE:
2505 			fn_wait = phys->ops.wait_for_commit_done;
2506 			break;
2507 		case MSM_ENC_TX_COMPLETE:
2508 			fn_wait = phys->ops.wait_for_tx_complete;
2509 			break;
2510 		case MSM_ENC_VBLANK:
2511 			fn_wait = phys->ops.wait_for_vblank;
2512 			break;
2513 		default:
2514 			DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2515 					event);
2516 			return -EINVAL;
2517 		}
2518 
2519 		if (fn_wait) {
2520 			DPU_ATRACE_BEGIN("wait_for_completion_event");
2521 			ret = fn_wait(phys);
2522 			DPU_ATRACE_END("wait_for_completion_event");
2523 			if (ret)
2524 				return ret;
2525 		}
2526 	}
2527 
2528 	return ret;
2529 }
2530 
dpu_encoder_get_intf_mode(struct drm_encoder * encoder)2531 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2532 {
2533 	struct dpu_encoder_virt *dpu_enc = NULL;
2534 
2535 	if (!encoder) {
2536 		DPU_ERROR("invalid encoder\n");
2537 		return INTF_MODE_NONE;
2538 	}
2539 	dpu_enc = to_dpu_encoder_virt(encoder);
2540 
2541 	if (dpu_enc->cur_master)
2542 		return dpu_enc->cur_master->intf_mode;
2543 
2544 	if (dpu_enc->num_phys_encs)
2545 		return dpu_enc->phys_encs[0]->intf_mode;
2546 
2547 	return INTF_MODE_NONE;
2548 }
2549 
dpu_encoder_helper_get_dsc(struct dpu_encoder_phys * phys_enc)2550 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
2551 {
2552 	struct drm_encoder *encoder = phys_enc->parent;
2553 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2554 
2555 	return dpu_enc->dsc_mask;
2556 }
2557