1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "reg_helper.h"
29 #include "dcn30_dpp.h"
30 #include "basics/conversion.h"
31 #include "dcn30_cm_common.h"
32
33 #define REG(reg)\
34 dpp->tf_regs->reg
35
36 #define CTX \
37 dpp->base.ctx
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
43
dpp30_read_state(struct dpp * dpp_base,struct dcn_dpp_state * s)44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
45 {
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
47
48 REG_GET(DPP_CONTROL,
49 DPP_CLOCK_ENABLE, &s->is_enabled);
50
51 // TODO: Implement for DCN3
52 }
53 /*program post scaler scs block in dpp CM*/
dpp3_program_post_csc(struct dpp * dpp_base,enum dc_color_space color_space,enum dcn10_input_csc_select input_select,const struct out_csc_color_matrix * tbl_entry)54 void dpp3_program_post_csc(
55 struct dpp *dpp_base,
56 enum dc_color_space color_space,
57 enum dcn10_input_csc_select input_select,
58 const struct out_csc_color_matrix *tbl_entry)
59 {
60 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
61 int i;
62 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
63 const uint16_t *regval = NULL;
64 uint32_t cur_select = 0;
65 enum dcn10_input_csc_select select;
66 struct color_matrices_reg gam_regs;
67
68 if (input_select == INPUT_CSC_SELECT_BYPASS) {
69 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
70 return;
71 }
72
73 if (tbl_entry == NULL) {
74 for (i = 0; i < arr_size; i++)
75 if (dpp_input_csc_matrix[i].color_space == color_space) {
76 regval = dpp_input_csc_matrix[i].regval;
77 break;
78 }
79
80 if (regval == NULL) {
81 BREAK_TO_DEBUGGER();
82 return;
83 }
84 } else {
85 regval = tbl_entry->regval;
86 }
87
88 /* determine which CSC matrix (icsc or coma) we are using
89 * currently. select the alternate set to double buffer
90 * the CSC update so CSC is updated on frame boundary
91 */
92 REG_GET(CM_POST_CSC_CONTROL,
93 CM_POST_CSC_MODE_CURRENT, &cur_select);
94
95 if (cur_select != INPUT_CSC_SELECT_ICSC)
96 select = INPUT_CSC_SELECT_ICSC;
97 else
98 select = INPUT_CSC_SELECT_COMA;
99
100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
104
105 if (select == INPUT_CSC_SELECT_ICSC) {
106
107 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
108 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
109
110 } else {
111
112 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
113 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
114
115 }
116
117 cm_helper_program_color_matrices(
118 dpp->base.ctx,
119 regval,
120 &gam_regs);
121
122 REG_SET(CM_POST_CSC_CONTROL, 0,
123 CM_POST_CSC_MODE, select);
124 }
125
126
127 /*CNVC degam unit has read only LUTs*/
dpp3_set_pre_degam(struct dpp * dpp_base,enum dc_transfer_func_predefined tr)128 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
129 {
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
131 int pre_degam_en = 1;
132 int degamma_lut_selection = 0;
133
134 switch (tr) {
135 case TRANSFER_FUNCTION_LINEAR:
136 case TRANSFER_FUNCTION_UNITY:
137 pre_degam_en = 0; //bypass
138 break;
139 case TRANSFER_FUNCTION_SRGB:
140 degamma_lut_selection = 0;
141 break;
142 case TRANSFER_FUNCTION_BT709:
143 degamma_lut_selection = 4;
144 break;
145 case TRANSFER_FUNCTION_PQ:
146 degamma_lut_selection = 5;
147 break;
148 case TRANSFER_FUNCTION_HLG:
149 degamma_lut_selection = 6;
150 break;
151 case TRANSFER_FUNCTION_GAMMA22:
152 degamma_lut_selection = 1;
153 break;
154 case TRANSFER_FUNCTION_GAMMA24:
155 degamma_lut_selection = 2;
156 break;
157 case TRANSFER_FUNCTION_GAMMA26:
158 degamma_lut_selection = 3;
159 break;
160 default:
161 pre_degam_en = 0;
162 break;
163 }
164
165 REG_SET_2(PRE_DEGAM, 0,
166 PRE_DEGAM_MODE, pre_degam_en,
167 PRE_DEGAM_SELECT, degamma_lut_selection);
168 }
169
dpp3_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut)170 void dpp3_cnv_setup (
171 struct dpp *dpp_base,
172 enum surface_pixel_format format,
173 enum expansion_mode mode,
174 struct dc_csc_transform input_csc_color_matrix,
175 enum dc_color_space input_color_space,
176 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
177 {
178 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
179 uint32_t pixel_format = 0;
180 uint32_t alpha_en = 1;
181 enum dc_color_space color_space = COLOR_SPACE_SRGB;
182 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
183 bool force_disable_cursor = false;
184 uint32_t is_2bit = 0;
185 uint32_t alpha_plane_enable = 0;
186 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
187 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
188 uint32_t program_prealpha_dealpha = 0;
189 struct out_csc_color_matrix tbl_entry;
190 int i;
191
192 REG_SET_2(FORMAT_CONTROL, 0,
193 CNVC_BYPASS, 0,
194 FORMAT_EXPANSION_MODE, mode);
195
196 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
197 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
198 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
200
201 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
204
205 switch (format) {
206 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
207 pixel_format = 1;
208 break;
209 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
210 pixel_format = 3;
211 alpha_en = 0;
212 break;
213 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
214 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
215 pixel_format = 8;
216 break;
217 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
218 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
219 pixel_format = 10;
220 is_2bit = 1;
221 break;
222 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
223 force_disable_cursor = false;
224 pixel_format = 65;
225 color_space = COLOR_SPACE_YCBCR709;
226 select = INPUT_CSC_SELECT_ICSC;
227 break;
228 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
229 force_disable_cursor = true;
230 pixel_format = 64;
231 color_space = COLOR_SPACE_YCBCR709;
232 select = INPUT_CSC_SELECT_ICSC;
233 break;
234 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
235 force_disable_cursor = true;
236 pixel_format = 67;
237 color_space = COLOR_SPACE_YCBCR709;
238 select = INPUT_CSC_SELECT_ICSC;
239 break;
240 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
241 force_disable_cursor = true;
242 pixel_format = 66;
243 color_space = COLOR_SPACE_YCBCR709;
244 select = INPUT_CSC_SELECT_ICSC;
245 break;
246 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
247 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
248 pixel_format = 26; /* ARGB16161616_UNORM */
249 break;
250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
251 pixel_format = 24;
252 break;
253 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
254 pixel_format = 25;
255 break;
256 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
257 pixel_format = 12;
258 color_space = COLOR_SPACE_YCBCR709;
259 select = INPUT_CSC_SELECT_ICSC;
260 break;
261 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
262 pixel_format = 112;
263 break;
264 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
265 pixel_format = 113;
266 break;
267 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
268 pixel_format = 114;
269 color_space = COLOR_SPACE_YCBCR709;
270 select = INPUT_CSC_SELECT_ICSC;
271 is_2bit = 1;
272 break;
273 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
274 pixel_format = 115;
275 color_space = COLOR_SPACE_YCBCR709;
276 select = INPUT_CSC_SELECT_ICSC;
277 is_2bit = 1;
278 break;
279 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
280 pixel_format = 116;
281 alpha_plane_enable = 0;
282 break;
283 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
284 pixel_format = 116;
285 alpha_plane_enable = 1;
286 break;
287 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
288 pixel_format = 118;
289 break;
290 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
291 pixel_format = 119;
292 break;
293 default:
294 break;
295 }
296
297 /* Set default color space based on format if none is given. */
298 color_space = input_color_space ? input_color_space : color_space;
299
300 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
302 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
303 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
304 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
305 }
306
307 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
308 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
309 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
310 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
311
312 if (program_prealpha_dealpha) {
313 dealpha_en = 1;
314 realpha_en = 1;
315 }
316 REG_SET_2(PRE_DEALPHA, 0,
317 PRE_DEALPHA_EN, dealpha_en,
318 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
319 REG_SET_2(PRE_REALPHA, 0,
320 PRE_REALPHA_EN, realpha_en,
321 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
322
323 /* If input adjustment exists, program the ICSC with those values. */
324 if (input_csc_color_matrix.enable_adjustment == true) {
325 for (i = 0; i < 12; i++)
326 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
327
328 tbl_entry.color_space = input_color_space;
329
330 if (color_space >= COLOR_SPACE_YCBCR601)
331 select = INPUT_CSC_SELECT_ICSC;
332 else
333 select = INPUT_CSC_SELECT_BYPASS;
334
335 dpp3_program_post_csc(dpp_base, color_space, select,
336 &tbl_entry);
337 } else {
338 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
339 }
340
341 if (force_disable_cursor) {
342 REG_UPDATE(CURSOR_CONTROL,
343 CURSOR_ENABLE, 0);
344 REG_UPDATE(CURSOR0_CONTROL,
345 CUR0_ENABLE, 0);
346 }
347 }
348
349 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
350
dpp3_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes)351 void dpp3_set_cursor_attributes(
352 struct dpp *dpp_base,
353 struct dc_cursor_attributes *cursor_attributes)
354 {
355 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
356 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
357 int cur_rom_en = 0;
358
359 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
360 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
361 cur_rom_en = 1;
362
363 REG_UPDATE_3(CURSOR0_CONTROL,
364 CUR0_MODE, color_format,
365 CUR0_EXPANSION_MODE, 0,
366 CUR0_ROM_EN, cur_rom_en);
367
368 if (color_format == CURSOR_MODE_MONO) {
369 /* todo: clarify what to program these to */
370 REG_UPDATE(CURSOR0_COLOR0,
371 CUR0_COLOR0, 0x00000000);
372 REG_UPDATE(CURSOR0_COLOR1,
373 CUR0_COLOR1, 0xFFFFFFFF);
374 }
375
376 dpp_base->att.cur0_ctl.bits.expansion_mode = 0;
377 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;
378 dpp_base->att.cur0_ctl.bits.mode = color_format;
379 }
380
381
dpp3_get_optimal_number_of_taps(struct dpp * dpp,struct scaler_data * scl_data,const struct scaling_taps * in_taps)382 bool dpp3_get_optimal_number_of_taps(
383 struct dpp *dpp,
384 struct scaler_data *scl_data,
385 const struct scaling_taps *in_taps)
386 {
387 int num_part_y, num_part_c;
388 int max_taps_y, max_taps_c;
389 int min_taps_y, min_taps_c;
390 enum lb_memory_config lb_config;
391
392 if (scl_data->viewport.width > scl_data->h_active &&
393 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
394 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
395 return false;
396
397 /*
398 * Set default taps if none are provided
399 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
400 * taps = 4 for upscaling
401 */
402 if (in_taps->h_taps == 0) {
403 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
404 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
405 else
406 scl_data->taps.h_taps = 4;
407 } else
408 scl_data->taps.h_taps = in_taps->h_taps;
409 if (in_taps->v_taps == 0) {
410 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
411 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
412 else
413 scl_data->taps.v_taps = 4;
414 } else
415 scl_data->taps.v_taps = in_taps->v_taps;
416 if (in_taps->v_taps_c == 0) {
417 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
418 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
419 else
420 scl_data->taps.v_taps_c = 4;
421 } else
422 scl_data->taps.v_taps_c = in_taps->v_taps_c;
423 if (in_taps->h_taps_c == 0) {
424 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
425 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
426 else
427 scl_data->taps.h_taps_c = 4;
428 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
429 /* Only 1 and even h_taps_c are supported by hw */
430 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
431 else
432 scl_data->taps.h_taps_c = in_taps->h_taps_c;
433
434 /*Ensure we can support the requested number of vtaps*/
435 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
436 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
437
438 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
439 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
440 lb_config = LB_MEMORY_CONFIG_3;
441 else
442 lb_config = LB_MEMORY_CONFIG_0;
443
444 dpp->caps->dscl_calc_lb_num_partitions(
445 scl_data, lb_config, &num_part_y, &num_part_c);
446
447 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
448 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
449 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
450 else
451 max_taps_y = num_part_y;
452
453 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
454 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
455 else
456 max_taps_c = num_part_c;
457
458 if (max_taps_y < min_taps_y)
459 return false;
460 else if (max_taps_c < min_taps_c)
461 return false;
462
463 if (scl_data->taps.v_taps > max_taps_y)
464 scl_data->taps.v_taps = max_taps_y;
465
466 if (scl_data->taps.v_taps_c > max_taps_c)
467 scl_data->taps.v_taps_c = max_taps_c;
468
469 if (!dpp->ctx->dc->debug.always_scale) {
470 if (IDENTITY_RATIO(scl_data->ratios.horz))
471 scl_data->taps.h_taps = 1;
472 if (IDENTITY_RATIO(scl_data->ratios.vert))
473 scl_data->taps.v_taps = 1;
474 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
475 scl_data->taps.h_taps_c = 1;
476 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
477 scl_data->taps.v_taps_c = 1;
478 }
479
480 return true;
481 }
482
dpp3_deferred_update(struct dpp * dpp_base)483 static void dpp3_deferred_update(struct dpp *dpp_base)
484 {
485 int bypass_state;
486 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
487
488 if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
489 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);
490 dpp_base->deferred_reg_writes.bits.disable_dscl = false;
491 }
492
493 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) {
494 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state);
495 if (bypass_state == 0) { // only program if bypass was latched
496 REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3);
497 } else
498 ASSERT(0); // LUT select was updated again before vupdate
499 dpp_base->deferred_reg_writes.bits.disable_gamcor = false;
500 }
501
502 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {
503 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
504 if (bypass_state == 0) { // only program if bypass was latched
505 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);
506 } else
507 ASSERT(0); // LUT select was updated again before vupdate
508 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
509 }
510
511 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {
512 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
513 if (bypass_state == 0) { // only program if bypass was latched
514 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);
515 } else
516 ASSERT(0); // LUT select was updated again before vupdate
517 dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
518 }
519
520 if (dpp_base->deferred_reg_writes.bits.disable_shaper) {
521 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
522 if (bypass_state == 0) { // only program if bypass was latched
523 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);
524 } else
525 ASSERT(0); // LUT select was updated again before vupdate
526 dpp_base->deferred_reg_writes.bits.disable_shaper = false;
527 }
528 }
529
dpp3_power_on_blnd_lut(struct dpp * dpp_base,bool power_on)530 static void dpp3_power_on_blnd_lut(
531 struct dpp *dpp_base,
532 bool power_on)
533 {
534 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
535
536 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
537 if (power_on) {
538 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);
539 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
540 } else {
541 dpp_base->ctx->dc->optimized_required = true;
542 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
543 }
544 } else {
545 REG_SET(CM_MEM_PWR_CTRL, 0,
546 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
547 }
548 }
549
dpp3_power_on_hdr3dlut(struct dpp * dpp_base,bool power_on)550 static void dpp3_power_on_hdr3dlut(
551 struct dpp *dpp_base,
552 bool power_on)
553 {
554 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
555
556 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
557 if (power_on) {
558 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);
559 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
560 } else {
561 dpp_base->ctx->dc->optimized_required = true;
562 dpp_base->deferred_reg_writes.bits.disable_3dlut = true;
563 }
564 }
565 }
566
dpp3_power_on_shaper(struct dpp * dpp_base,bool power_on)567 static void dpp3_power_on_shaper(
568 struct dpp *dpp_base,
569 bool power_on)
570 {
571 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
572
573 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
574 if (power_on) {
575 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);
576 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
577 } else {
578 dpp_base->ctx->dc->optimized_required = true;
579 dpp_base->deferred_reg_writes.bits.disable_shaper = true;
580 }
581 }
582 }
583
dpp3_configure_blnd_lut(struct dpp * dpp_base,bool is_ram_a)584 static void dpp3_configure_blnd_lut(
585 struct dpp *dpp_base,
586 bool is_ram_a)
587 {
588 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
589
590 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
591 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
592 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
593
594 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
595 }
596
dpp3_program_blnd_pwl(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)597 static void dpp3_program_blnd_pwl(
598 struct dpp *dpp_base,
599 const struct pwl_result_data *rgb,
600 uint32_t num)
601 {
602 uint32_t i;
603 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
604 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
605 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
606 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
607
608 if (is_rgb_equal(rgb, num)) {
609 for (i = 0 ; i < num; i++)
610 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
611 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
612 } else {
613 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
614 for (i = 0 ; i < num; i++)
615 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
616 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
617
618 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
619 for (i = 0 ; i < num; i++)
620 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
621 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
622
623 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
624 for (i = 0 ; i < num; i++)
625 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
626 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
627 }
628 }
629
dcn3_dpp_cm_get_reg_field(struct dcn3_dpp * dpp,struct dcn3_xfer_func_reg * reg)630 static void dcn3_dpp_cm_get_reg_field(
631 struct dcn3_dpp *dpp,
632 struct dcn3_xfer_func_reg *reg)
633 {
634 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
635 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
636 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
637 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
638 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
639 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
640 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
641 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
642
643 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
644 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
645 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
646 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
647 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
648 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
649 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
650 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
651 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
652 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
653 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
654 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
655 }
656
657 /*program blnd lut RAM A*/
dpp3_program_blnd_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)658 static void dpp3_program_blnd_luta_settings(
659 struct dpp *dpp_base,
660 const struct pwl_params *params)
661 {
662 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
663 struct dcn3_xfer_func_reg gam_regs;
664
665 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
666
667 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
668 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
669 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
670 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
671 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
672 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
673 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
674 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
675 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
676 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
677 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
678 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
679 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
680 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
681
682 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
683 }
684
685 /*program blnd lut RAM B*/
dpp3_program_blnd_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)686 static void dpp3_program_blnd_lutb_settings(
687 struct dpp *dpp_base,
688 const struct pwl_params *params)
689 {
690 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
691 struct dcn3_xfer_func_reg gam_regs;
692
693 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
694
695 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
696 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
697 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
698 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
699 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
700 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
701 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
702 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
703 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
704 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
705 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
706 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
707 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
708 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
709
710 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
711 }
712
dpp3_get_blndgam_current(struct dpp * dpp_base)713 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
714 {
715 enum dc_lut_mode mode;
716 uint32_t mode_current = 0;
717 uint32_t in_use = 0;
718
719 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
720
721 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current);
722 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use);
723
724 switch (mode_current) {
725 case 0:
726 case 1:
727 mode = LUT_BYPASS;
728 break;
729
730 case 2:
731 if (in_use == 0)
732 mode = LUT_RAM_A;
733 else
734 mode = LUT_RAM_B;
735 break;
736 default:
737 mode = LUT_BYPASS;
738 break;
739 }
740
741 return mode;
742 }
743
dpp3_program_blnd_lut(struct dpp * dpp_base,const struct pwl_params * params)744 static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
745 const struct pwl_params *params)
746 {
747 enum dc_lut_mode current_mode;
748 enum dc_lut_mode next_mode;
749 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
750
751 if (params == NULL) {
752 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
753 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
754 dpp3_power_on_blnd_lut(dpp_base, false);
755 return false;
756 }
757
758 current_mode = dpp3_get_blndgam_current(dpp_base);
759 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
760 next_mode = LUT_RAM_A;
761 else
762 next_mode = LUT_RAM_B;
763
764 dpp3_power_on_blnd_lut(dpp_base, true);
765 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
766
767 if (next_mode == LUT_RAM_A)
768 dpp3_program_blnd_luta_settings(dpp_base, params);
769 else
770 dpp3_program_blnd_lutb_settings(dpp_base, params);
771
772 dpp3_program_blnd_pwl(
773 dpp_base, params->rgb_resulted, params->hw_points_num);
774
775 REG_UPDATE_2(CM_BLNDGAM_CONTROL,
776 CM_BLNDGAM_MODE, 2,
777 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
778
779 return true;
780 }
781
782
dpp3_program_shaper_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)783 static void dpp3_program_shaper_lut(
784 struct dpp *dpp_base,
785 const struct pwl_result_data *rgb,
786 uint32_t num)
787 {
788 uint32_t i, red, green, blue;
789 uint32_t red_delta, green_delta, blue_delta;
790 uint32_t red_value, green_value, blue_value;
791
792 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
793
794 for (i = 0 ; i < num; i++) {
795
796 red = rgb[i].red_reg;
797 green = rgb[i].green_reg;
798 blue = rgb[i].blue_reg;
799
800 red_delta = rgb[i].delta_red_reg;
801 green_delta = rgb[i].delta_green_reg;
802 blue_delta = rgb[i].delta_blue_reg;
803
804 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
805 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
806 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
807
808 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
809 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
810 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
811 }
812
813 }
814
dpp3_get_shaper_current(struct dpp * dpp_base)815 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
816 {
817 enum dc_lut_mode mode;
818 uint32_t state_mode;
819 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
820
821 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode);
822
823 switch (state_mode) {
824 case 0:
825 mode = LUT_BYPASS;
826 break;
827 case 1:
828 mode = LUT_RAM_A;
829 break;
830 case 2:
831 mode = LUT_RAM_B;
832 break;
833 default:
834 mode = LUT_BYPASS;
835 break;
836 }
837
838 return mode;
839 }
840
dpp3_configure_shaper_lut(struct dpp * dpp_base,bool is_ram_a)841 static void dpp3_configure_shaper_lut(
842 struct dpp *dpp_base,
843 bool is_ram_a)
844 {
845 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
846
847 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
848 CM_SHAPER_LUT_WRITE_EN_MASK, 7);
849 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
850 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
851 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
852 }
853
854 /*program shaper RAM A*/
855
dpp3_program_shaper_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)856 static void dpp3_program_shaper_luta_settings(
857 struct dpp *dpp_base,
858 const struct pwl_params *params)
859 {
860 const struct gamma_curve *curve;
861 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
862
863 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
864 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
865 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
866 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
867 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
868 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
869 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
870 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
871 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
872
873 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
874 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
875 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
876
877 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
878 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
879 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
880
881 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
882 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
883 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
884
885 curve = params->arr_curve_points;
886 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
887 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
888 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
889 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
890 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
891
892 curve += 2;
893 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
894 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
895 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
896 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
897 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
898
899 curve += 2;
900 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
901 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
902 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
903 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
904 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
905
906 curve += 2;
907 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
908 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
909 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
910 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
911 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
912
913 curve += 2;
914 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
915 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
916 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
917 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
918 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
919
920 curve += 2;
921 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
922 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
923 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
924 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
925 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
926
927 curve += 2;
928 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
929 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
930 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
931 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
932 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
933
934 curve += 2;
935 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
936 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
937 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
938 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
939 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
940
941 curve += 2;
942 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
943 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
944 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
945 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
946 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
947
948 curve += 2;
949 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
950 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
951 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
952 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
953 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
954
955 curve += 2;
956 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
957 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
958 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
959 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
960 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
961
962 curve += 2;
963 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
964 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
965 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
966 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
967 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
968
969 curve += 2;
970 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
971 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
972 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
973 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
974 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
975
976 curve += 2;
977 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
978 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
979 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
980 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
981 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
982
983 curve += 2;
984 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
985 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
986 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
987 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
988 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
989
990 curve += 2;
991 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
992 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
993 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
994 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
995 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
996
997 curve += 2;
998 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
999 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1000 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1001 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1002 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1003 }
1004
1005 /*program shaper RAM B*/
dpp3_program_shaper_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)1006 static void dpp3_program_shaper_lutb_settings(
1007 struct dpp *dpp_base,
1008 const struct pwl_params *params)
1009 {
1010 const struct gamma_curve *curve;
1011 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1012
1013 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
1014 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
1015 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
1016 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
1017 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
1018 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
1019 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
1020 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
1021 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
1022
1023 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
1024 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
1025 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
1026
1027 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
1028 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
1029 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
1030
1031 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
1032 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
1033 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
1034
1035 curve = params->arr_curve_points;
1036 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
1037 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1038 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1039 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1040 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1041
1042 curve += 2;
1043 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
1044 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
1045 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
1046 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
1047 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
1048
1049 curve += 2;
1050 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1051 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1052 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1053 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1054 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1055
1056 curve += 2;
1057 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1058 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1059 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1060 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1061 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1062
1063 curve += 2;
1064 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1065 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1066 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1067 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1068 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1069
1070 curve += 2;
1071 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1072 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1073 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1074 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1075 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1076
1077 curve += 2;
1078 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1079 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1080 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1081 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1082 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1083
1084 curve += 2;
1085 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1086 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1087 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1088 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1089 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1090
1091 curve += 2;
1092 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1093 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1094 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1095 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1096 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1097
1098 curve += 2;
1099 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1100 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1101 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1102 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1103 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1104
1105 curve += 2;
1106 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1107 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1108 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1109 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1110 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1111
1112 curve += 2;
1113 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1114 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1115 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1116 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1117 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1118
1119 curve += 2;
1120 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1121 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1122 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1123 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1124 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1125
1126 curve += 2;
1127 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1128 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1129 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1130 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1131 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1132
1133 curve += 2;
1134 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1135 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1136 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1137 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1138 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1139
1140 curve += 2;
1141 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1142 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1143 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1144 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1145 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1146
1147 curve += 2;
1148 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1149 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1150 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1151 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1152 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1153
1154 }
1155
1156
dpp3_program_shaper(struct dpp * dpp_base,const struct pwl_params * params)1157 static bool dpp3_program_shaper(struct dpp *dpp_base,
1158 const struct pwl_params *params)
1159 {
1160 enum dc_lut_mode current_mode;
1161 enum dc_lut_mode next_mode;
1162
1163 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1164
1165 if (params == NULL) {
1166 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1167 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1168 dpp3_power_on_shaper(dpp_base, false);
1169 return false;
1170 }
1171
1172 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1173 dpp3_power_on_shaper(dpp_base, true);
1174
1175 current_mode = dpp3_get_shaper_current(dpp_base);
1176
1177 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1178 next_mode = LUT_RAM_B;
1179 else
1180 next_mode = LUT_RAM_A;
1181
1182 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
1183
1184 if (next_mode == LUT_RAM_A)
1185 dpp3_program_shaper_luta_settings(dpp_base, params);
1186 else
1187 dpp3_program_shaper_lutb_settings(dpp_base, params);
1188
1189 dpp3_program_shaper_lut(
1190 dpp_base, params->rgb_resulted, params->hw_points_num);
1191
1192 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1193
1194 return true;
1195
1196 }
1197
get3dlut_config(struct dpp * dpp_base,bool * is_17x17x17,bool * is_12bits_color_channel)1198 static enum dc_lut_mode get3dlut_config(
1199 struct dpp *dpp_base,
1200 bool *is_17x17x17,
1201 bool *is_12bits_color_channel)
1202 {
1203 uint32_t i_mode, i_enable_10bits, lut_size;
1204 enum dc_lut_mode mode;
1205 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1206
1207 REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1208 CM_3DLUT_30BIT_EN, &i_enable_10bits);
1209 REG_GET(CM_3DLUT_MODE,
1210 CM_3DLUT_MODE_CURRENT, &i_mode);
1211
1212 switch (i_mode) {
1213 case 0:
1214 mode = LUT_BYPASS;
1215 break;
1216 case 1:
1217 mode = LUT_RAM_A;
1218 break;
1219 case 2:
1220 mode = LUT_RAM_B;
1221 break;
1222 default:
1223 mode = LUT_BYPASS;
1224 break;
1225 }
1226 if (i_enable_10bits > 0)
1227 *is_12bits_color_channel = false;
1228 else
1229 *is_12bits_color_channel = true;
1230
1231 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1232
1233 if (lut_size == 0)
1234 *is_17x17x17 = true;
1235 else
1236 *is_17x17x17 = false;
1237
1238 return mode;
1239 }
1240 /*
1241 * select ramA or ramB, or bypass
1242 * select color channel size 10 or 12 bits
1243 * select 3dlut size 17x17x17 or 9x9x9
1244 */
dpp3_set_3dlut_mode(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17)1245 static void dpp3_set_3dlut_mode(
1246 struct dpp *dpp_base,
1247 enum dc_lut_mode mode,
1248 bool is_color_channel_12bits,
1249 bool is_lut_size17x17x17)
1250 {
1251 uint32_t lut_mode;
1252 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1253
1254 if (mode == LUT_BYPASS)
1255 lut_mode = 0;
1256 else if (mode == LUT_RAM_A)
1257 lut_mode = 1;
1258 else
1259 lut_mode = 2;
1260
1261 REG_UPDATE_2(CM_3DLUT_MODE,
1262 CM_3DLUT_MODE, lut_mode,
1263 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1264 }
1265
dpp3_select_3dlut_ram(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits)1266 static void dpp3_select_3dlut_ram(
1267 struct dpp *dpp_base,
1268 enum dc_lut_mode mode,
1269 bool is_color_channel_12bits)
1270 {
1271 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1272
1273 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1274 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1275 CM_3DLUT_30BIT_EN,
1276 is_color_channel_12bits == true ? 0:1);
1277 }
1278
1279
1280
dpp3_set3dlut_ram12(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1281 static void dpp3_set3dlut_ram12(
1282 struct dpp *dpp_base,
1283 const struct dc_rgb *lut,
1284 uint32_t entries)
1285 {
1286 uint32_t i, red, green, blue, red1, green1, blue1;
1287 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1288
1289 for (i = 0 ; i < entries; i += 2) {
1290 red = lut[i].red<<4;
1291 green = lut[i].green<<4;
1292 blue = lut[i].blue<<4;
1293 red1 = lut[i+1].red<<4;
1294 green1 = lut[i+1].green<<4;
1295 blue1 = lut[i+1].blue<<4;
1296
1297 REG_SET_2(CM_3DLUT_DATA, 0,
1298 CM_3DLUT_DATA0, red,
1299 CM_3DLUT_DATA1, red1);
1300
1301 REG_SET_2(CM_3DLUT_DATA, 0,
1302 CM_3DLUT_DATA0, green,
1303 CM_3DLUT_DATA1, green1);
1304
1305 REG_SET_2(CM_3DLUT_DATA, 0,
1306 CM_3DLUT_DATA0, blue,
1307 CM_3DLUT_DATA1, blue1);
1308
1309 }
1310 }
1311
1312 /*
1313 * load selected lut with 10 bits color channels
1314 */
dpp3_set3dlut_ram10(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1315 static void dpp3_set3dlut_ram10(
1316 struct dpp *dpp_base,
1317 const struct dc_rgb *lut,
1318 uint32_t entries)
1319 {
1320 uint32_t i, red, green, blue, value;
1321 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1322
1323 for (i = 0; i < entries; i++) {
1324 red = lut[i].red;
1325 green = lut[i].green;
1326 blue = lut[i].blue;
1327
1328 value = (red<<20) | (green<<10) | blue;
1329
1330 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1331 }
1332
1333 }
1334
1335
dpp3_select_3dlut_ram_mask(struct dpp * dpp_base,uint32_t ram_selection_mask)1336 static void dpp3_select_3dlut_ram_mask(
1337 struct dpp *dpp_base,
1338 uint32_t ram_selection_mask)
1339 {
1340 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1341
1342 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1343 ram_selection_mask);
1344 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1345 }
1346
dpp3_program_3dlut(struct dpp * dpp_base,struct tetrahedral_params * params)1347 static bool dpp3_program_3dlut(struct dpp *dpp_base,
1348 struct tetrahedral_params *params)
1349 {
1350 enum dc_lut_mode mode;
1351 bool is_17x17x17;
1352 bool is_12bits_color_channel;
1353 struct dc_rgb *lut0;
1354 struct dc_rgb *lut1;
1355 struct dc_rgb *lut2;
1356 struct dc_rgb *lut3;
1357 int lut_size0;
1358 int lut_size;
1359
1360 if (params == NULL) {
1361 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1362 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1363 dpp3_power_on_hdr3dlut(dpp_base, false);
1364 return false;
1365 }
1366
1367 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1368 dpp3_power_on_hdr3dlut(dpp_base, true);
1369
1370 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1371
1372 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1373 mode = LUT_RAM_A;
1374 else
1375 mode = LUT_RAM_B;
1376
1377 is_17x17x17 = !params->use_tetrahedral_9;
1378 is_12bits_color_channel = params->use_12bits;
1379 if (is_17x17x17) {
1380 lut0 = params->tetrahedral_17.lut0;
1381 lut1 = params->tetrahedral_17.lut1;
1382 lut2 = params->tetrahedral_17.lut2;
1383 lut3 = params->tetrahedral_17.lut3;
1384 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1385 sizeof(params->tetrahedral_17.lut0[0]);
1386 lut_size = sizeof(params->tetrahedral_17.lut1)/
1387 sizeof(params->tetrahedral_17.lut1[0]);
1388 } else {
1389 lut0 = params->tetrahedral_9.lut0;
1390 lut1 = params->tetrahedral_9.lut1;
1391 lut2 = params->tetrahedral_9.lut2;
1392 lut3 = params->tetrahedral_9.lut3;
1393 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1394 sizeof(params->tetrahedral_9.lut0[0]);
1395 lut_size = sizeof(params->tetrahedral_9.lut1)/
1396 sizeof(params->tetrahedral_9.lut1[0]);
1397 }
1398
1399 dpp3_select_3dlut_ram(dpp_base, mode,
1400 is_12bits_color_channel);
1401 dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1402 if (is_12bits_color_channel)
1403 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1404 else
1405 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1406
1407 dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1408 if (is_12bits_color_channel)
1409 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1410 else
1411 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1412
1413 dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1414 if (is_12bits_color_channel)
1415 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1416 else
1417 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1418
1419 dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1420 if (is_12bits_color_channel)
1421 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1422 else
1423 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1424
1425
1426 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1427 is_17x17x17);
1428
1429 return true;
1430 }
1431 static struct dpp_funcs dcn30_dpp_funcs = {
1432 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1433 .dpp_read_state = dpp30_read_state,
1434 .dpp_reset = dpp_reset,
1435 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
1436 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1437 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,
1438 .dpp_set_csc_adjustment = NULL,
1439 .dpp_set_csc_default = NULL,
1440 .dpp_program_regamma_pwl = NULL,
1441 .dpp_set_pre_degam = dpp3_set_pre_degam,
1442 .dpp_program_input_lut = NULL,
1443 .dpp_full_bypass = dpp1_full_bypass,
1444 .dpp_setup = dpp3_cnv_setup,
1445 .dpp_program_degamma_pwl = NULL,
1446 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1447 .dpp_program_cm_bias = dpp3_program_cm_bias,
1448 .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1449 .dpp_program_shaper_lut = dpp3_program_shaper,
1450 .dpp_program_3dlut = dpp3_program_3dlut,
1451 .dpp_deferred_update = dpp3_deferred_update,
1452 .dpp_program_bias_and_scale = NULL,
1453 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
1454 .set_cursor_attributes = dpp3_set_cursor_attributes,
1455 .set_cursor_position = dpp1_set_cursor_position,
1456 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1457 .dpp_dppclk_control = dpp1_dppclk_control,
1458 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
1459 };
1460
1461
1462 static struct dpp_caps dcn30_dpp_cap = {
1463 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1464 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1465 };
1466
dpp3_construct(struct dcn3_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn3_dpp_registers * tf_regs,const struct dcn3_dpp_shift * tf_shift,const struct dcn3_dpp_mask * tf_mask)1467 bool dpp3_construct(
1468 struct dcn3_dpp *dpp,
1469 struct dc_context *ctx,
1470 uint32_t inst,
1471 const struct dcn3_dpp_registers *tf_regs,
1472 const struct dcn3_dpp_shift *tf_shift,
1473 const struct dcn3_dpp_mask *tf_mask)
1474 {
1475 dpp->base.ctx = ctx;
1476
1477 dpp->base.inst = inst;
1478 dpp->base.funcs = &dcn30_dpp_funcs;
1479 dpp->base.caps = &dcn30_dpp_cap;
1480
1481 dpp->tf_regs = tf_regs;
1482 dpp->tf_shift = tf_shift;
1483 dpp->tf_mask = tf_mask;
1484
1485 return true;
1486 }
1487
1488