1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "reg_helper.h"
29 #include "dcn30_dpp.h"
30 #include "basics/conversion.h"
31 #include "dcn30_cm_common.h"
32
33 #define REG(reg)\
34 dpp->tf_regs->reg
35
36 #define CTX \
37 dpp->base.ctx
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
43
dpp30_read_state(struct dpp * dpp_base,struct dcn_dpp_state * s)44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
45 {
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
47
48 REG_GET(DPP_CONTROL,
49 DPP_CLOCK_ENABLE, &s->is_enabled);
50
51 // TODO: Implement for DCN3
52 }
53 /*program post scaler scs block in dpp CM*/
dpp3_program_post_csc(struct dpp * dpp_base,enum dc_color_space color_space,enum dcn10_input_csc_select input_select,const struct out_csc_color_matrix * tbl_entry)54 void dpp3_program_post_csc(
55 struct dpp *dpp_base,
56 enum dc_color_space color_space,
57 enum dcn10_input_csc_select input_select,
58 const struct out_csc_color_matrix *tbl_entry)
59 {
60 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
61 int i;
62 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
63 const uint16_t *regval = NULL;
64 uint32_t cur_select = 0;
65 enum dcn10_input_csc_select select;
66 struct color_matrices_reg gam_regs;
67
68 if (input_select == INPUT_CSC_SELECT_BYPASS) {
69 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
70 return;
71 }
72
73 if (tbl_entry == NULL) {
74 for (i = 0; i < arr_size; i++)
75 if (dpp_input_csc_matrix[i].color_space == color_space) {
76 regval = dpp_input_csc_matrix[i].regval;
77 break;
78 }
79
80 if (regval == NULL) {
81 BREAK_TO_DEBUGGER();
82 return;
83 }
84 } else {
85 regval = tbl_entry->regval;
86 }
87
88 /* determine which CSC matrix (icsc or coma) we are using
89 * currently. select the alternate set to double buffer
90 * the CSC update so CSC is updated on frame boundary
91 */
92 REG_GET(CM_POST_CSC_CONTROL,
93 CM_POST_CSC_MODE_CURRENT, &cur_select);
94
95 if (cur_select != INPUT_CSC_SELECT_ICSC)
96 select = INPUT_CSC_SELECT_ICSC;
97 else
98 select = INPUT_CSC_SELECT_COMA;
99
100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
104
105 if (select == INPUT_CSC_SELECT_ICSC) {
106
107 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
108 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
109
110 } else {
111
112 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
113 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
114
115 }
116
117 cm_helper_program_color_matrices(
118 dpp->base.ctx,
119 regval,
120 &gam_regs);
121
122 REG_SET(CM_POST_CSC_CONTROL, 0,
123 CM_POST_CSC_MODE, select);
124 }
125
126
127 /*CNVC degam unit has read only LUTs*/
dpp3_set_pre_degam(struct dpp * dpp_base,enum dc_transfer_func_predefined tr)128 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
129 {
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
131 int pre_degam_en = 1;
132 int degamma_lut_selection = 0;
133
134 switch (tr) {
135 case TRANSFER_FUNCTION_LINEAR:
136 case TRANSFER_FUNCTION_UNITY:
137 pre_degam_en = 0; //bypass
138 break;
139 case TRANSFER_FUNCTION_SRGB:
140 degamma_lut_selection = 0;
141 break;
142 case TRANSFER_FUNCTION_BT709:
143 degamma_lut_selection = 4;
144 break;
145 case TRANSFER_FUNCTION_PQ:
146 degamma_lut_selection = 5;
147 break;
148 case TRANSFER_FUNCTION_HLG:
149 degamma_lut_selection = 6;
150 break;
151 case TRANSFER_FUNCTION_GAMMA22:
152 degamma_lut_selection = 1;
153 break;
154 case TRANSFER_FUNCTION_GAMMA24:
155 degamma_lut_selection = 2;
156 break;
157 case TRANSFER_FUNCTION_GAMMA26:
158 degamma_lut_selection = 3;
159 break;
160 default:
161 pre_degam_en = 0;
162 break;
163 }
164
165 REG_SET_2(PRE_DEGAM, 0,
166 PRE_DEGAM_MODE, pre_degam_en,
167 PRE_DEGAM_SELECT, degamma_lut_selection);
168 }
169
dpp3_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut)170 void dpp3_cnv_setup (
171 struct dpp *dpp_base,
172 enum surface_pixel_format format,
173 enum expansion_mode mode,
174 struct dc_csc_transform input_csc_color_matrix,
175 enum dc_color_space input_color_space,
176 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
177 {
178 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
179 uint32_t pixel_format = 0;
180 uint32_t alpha_en = 1;
181 enum dc_color_space color_space = COLOR_SPACE_SRGB;
182 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
183 bool force_disable_cursor = false;
184 uint32_t is_2bit = 0;
185 uint32_t alpha_plane_enable = 0;
186 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
187 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
188 uint32_t program_prealpha_dealpha = 0;
189 struct out_csc_color_matrix tbl_entry;
190 int i;
191
192 REG_SET_2(FORMAT_CONTROL, 0,
193 CNVC_BYPASS, 0,
194 FORMAT_EXPANSION_MODE, mode);
195
196 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
197 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
198 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
200
201 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
204
205 switch (format) {
206 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
207 pixel_format = 1;
208 break;
209 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
210 pixel_format = 3;
211 alpha_en = 0;
212 break;
213 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
214 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
215 pixel_format = 8;
216 break;
217 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
218 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
219 pixel_format = 10;
220 is_2bit = 1;
221 break;
222 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
223 force_disable_cursor = false;
224 pixel_format = 65;
225 color_space = COLOR_SPACE_YCBCR709;
226 select = INPUT_CSC_SELECT_ICSC;
227 break;
228 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
229 force_disable_cursor = true;
230 pixel_format = 64;
231 color_space = COLOR_SPACE_YCBCR709;
232 select = INPUT_CSC_SELECT_ICSC;
233 break;
234 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
235 force_disable_cursor = true;
236 pixel_format = 67;
237 color_space = COLOR_SPACE_YCBCR709;
238 select = INPUT_CSC_SELECT_ICSC;
239 break;
240 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
241 force_disable_cursor = true;
242 pixel_format = 66;
243 color_space = COLOR_SPACE_YCBCR709;
244 select = INPUT_CSC_SELECT_ICSC;
245 break;
246 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
247 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
248 pixel_format = 26; /* ARGB16161616_UNORM */
249 break;
250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
251 pixel_format = 24;
252 break;
253 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
254 pixel_format = 25;
255 break;
256 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
257 pixel_format = 12;
258 color_space = COLOR_SPACE_YCBCR709;
259 select = INPUT_CSC_SELECT_ICSC;
260 break;
261 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
262 pixel_format = 112;
263 break;
264 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
265 pixel_format = 113;
266 break;
267 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
268 pixel_format = 114;
269 color_space = COLOR_SPACE_YCBCR709;
270 select = INPUT_CSC_SELECT_ICSC;
271 is_2bit = 1;
272 break;
273 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
274 pixel_format = 115;
275 color_space = COLOR_SPACE_YCBCR709;
276 select = INPUT_CSC_SELECT_ICSC;
277 is_2bit = 1;
278 break;
279 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
280 pixel_format = 116;
281 alpha_plane_enable = 0;
282 break;
283 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
284 pixel_format = 116;
285 alpha_plane_enable = 1;
286 break;
287 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
288 pixel_format = 118;
289 break;
290 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
291 pixel_format = 119;
292 break;
293 default:
294 break;
295 }
296
297 /* Set default color space based on format if none is given. */
298 color_space = input_color_space ? input_color_space : color_space;
299
300 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
302 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
303 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
304 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
305 }
306
307 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
308 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
309 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
310 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
311
312 if (program_prealpha_dealpha) {
313 dealpha_en = 1;
314 realpha_en = 1;
315 }
316 REG_SET_2(PRE_DEALPHA, 0,
317 PRE_DEALPHA_EN, dealpha_en,
318 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
319 REG_SET_2(PRE_REALPHA, 0,
320 PRE_REALPHA_EN, realpha_en,
321 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
322
323 /* If input adjustment exists, program the ICSC with those values. */
324 if (input_csc_color_matrix.enable_adjustment == true) {
325 for (i = 0; i < 12; i++)
326 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
327
328 tbl_entry.color_space = input_color_space;
329
330 if (color_space >= COLOR_SPACE_YCBCR601)
331 select = INPUT_CSC_SELECT_ICSC;
332 else
333 select = INPUT_CSC_SELECT_BYPASS;
334
335 dpp3_program_post_csc(dpp_base, color_space, select,
336 &tbl_entry);
337 } else {
338 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
339 }
340
341 if (force_disable_cursor) {
342 REG_UPDATE(CURSOR_CONTROL,
343 CURSOR_ENABLE, 0);
344 REG_UPDATE(CURSOR0_CONTROL,
345 CUR0_ENABLE, 0);
346 }
347 }
348
349 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
350
dpp3_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes)351 void dpp3_set_cursor_attributes(
352 struct dpp *dpp_base,
353 struct dc_cursor_attributes *cursor_attributes)
354 {
355 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
356 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
357 int cur_rom_en = 0;
358
359 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
360 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
361 if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
362 cur_rom_en = 1;
363 }
364 }
365
366 REG_UPDATE_3(CURSOR0_CONTROL,
367 CUR0_MODE, color_format,
368 CUR0_EXPANSION_MODE, 0,
369 CUR0_ROM_EN, cur_rom_en);
370
371 if (color_format == CURSOR_MODE_MONO) {
372 /* todo: clarify what to program these to */
373 REG_UPDATE(CURSOR0_COLOR0,
374 CUR0_COLOR0, 0x00000000);
375 REG_UPDATE(CURSOR0_COLOR1,
376 CUR0_COLOR1, 0xFFFFFFFF);
377 }
378
379 dpp_base->att.cur0_ctl.bits.expansion_mode = 0;
380 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;
381 dpp_base->att.cur0_ctl.bits.mode = color_format;
382 }
383
384
dpp3_get_optimal_number_of_taps(struct dpp * dpp,struct scaler_data * scl_data,const struct scaling_taps * in_taps)385 bool dpp3_get_optimal_number_of_taps(
386 struct dpp *dpp,
387 struct scaler_data *scl_data,
388 const struct scaling_taps *in_taps)
389 {
390 int num_part_y, num_part_c;
391 int max_taps_y, max_taps_c;
392 int min_taps_y, min_taps_c;
393 enum lb_memory_config lb_config;
394
395 if (scl_data->viewport.width > scl_data->h_active &&
396 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
397 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
398 return false;
399
400 /*
401 * Set default taps if none are provided
402 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
403 * taps = 4 for upscaling
404 */
405 if (in_taps->h_taps == 0) {
406 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
407 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
408 else
409 scl_data->taps.h_taps = 4;
410 } else
411 scl_data->taps.h_taps = in_taps->h_taps;
412 if (in_taps->v_taps == 0) {
413 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
414 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
415 else
416 scl_data->taps.v_taps = 4;
417 } else
418 scl_data->taps.v_taps = in_taps->v_taps;
419 if (in_taps->v_taps_c == 0) {
420 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
421 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
422 else
423 scl_data->taps.v_taps_c = 4;
424 } else
425 scl_data->taps.v_taps_c = in_taps->v_taps_c;
426 if (in_taps->h_taps_c == 0) {
427 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
428 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
429 else
430 scl_data->taps.h_taps_c = 4;
431 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
432 /* Only 1 and even h_taps_c are supported by hw */
433 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
434 else
435 scl_data->taps.h_taps_c = in_taps->h_taps_c;
436
437 /*Ensure we can support the requested number of vtaps*/
438 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
439 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
440
441 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
442 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
443 lb_config = LB_MEMORY_CONFIG_3;
444 else
445 lb_config = LB_MEMORY_CONFIG_0;
446
447 dpp->caps->dscl_calc_lb_num_partitions(
448 scl_data, lb_config, &num_part_y, &num_part_c);
449
450 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
451 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
452 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
453 else
454 max_taps_y = num_part_y;
455
456 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
457 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
458 else
459 max_taps_c = num_part_c;
460
461 if (max_taps_y < min_taps_y)
462 return false;
463 else if (max_taps_c < min_taps_c)
464 return false;
465
466 if (scl_data->taps.v_taps > max_taps_y)
467 scl_data->taps.v_taps = max_taps_y;
468
469 if (scl_data->taps.v_taps_c > max_taps_c)
470 scl_data->taps.v_taps_c = max_taps_c;
471
472 if (!dpp->ctx->dc->debug.always_scale) {
473 if (IDENTITY_RATIO(scl_data->ratios.horz))
474 scl_data->taps.h_taps = 1;
475 if (IDENTITY_RATIO(scl_data->ratios.vert))
476 scl_data->taps.v_taps = 1;
477 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
478 scl_data->taps.h_taps_c = 1;
479 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
480 scl_data->taps.v_taps_c = 1;
481 }
482
483 return true;
484 }
485
dpp3_deferred_update(struct dpp * dpp_base)486 static void dpp3_deferred_update(struct dpp *dpp_base)
487 {
488 int bypass_state;
489 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
490
491 if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
492 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);
493 dpp_base->deferred_reg_writes.bits.disable_dscl = false;
494 }
495
496 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) {
497 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state);
498 if (bypass_state == 0) { // only program if bypass was latched
499 REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3);
500 } else
501 ASSERT(0); // LUT select was updated again before vupdate
502 dpp_base->deferred_reg_writes.bits.disable_gamcor = false;
503 }
504
505 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {
506 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
507 if (bypass_state == 0) { // only program if bypass was latched
508 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);
509 } else
510 ASSERT(0); // LUT select was updated again before vupdate
511 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
512 }
513
514 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {
515 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
516 if (bypass_state == 0) { // only program if bypass was latched
517 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);
518 } else
519 ASSERT(0); // LUT select was updated again before vupdate
520 dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
521 }
522
523 if (dpp_base->deferred_reg_writes.bits.disable_shaper) {
524 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
525 if (bypass_state == 0) { // only program if bypass was latched
526 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);
527 } else
528 ASSERT(0); // LUT select was updated again before vupdate
529 dpp_base->deferred_reg_writes.bits.disable_shaper = false;
530 }
531 }
532
dpp3_power_on_blnd_lut(struct dpp * dpp_base,bool power_on)533 static void dpp3_power_on_blnd_lut(
534 struct dpp *dpp_base,
535 bool power_on)
536 {
537 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
538
539 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
540 if (power_on) {
541 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);
542 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
543 } else {
544 dpp_base->ctx->dc->optimized_required = true;
545 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
546 }
547 } else {
548 REG_SET(CM_MEM_PWR_CTRL, 0,
549 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
550 }
551 }
552
dpp3_power_on_hdr3dlut(struct dpp * dpp_base,bool power_on)553 static void dpp3_power_on_hdr3dlut(
554 struct dpp *dpp_base,
555 bool power_on)
556 {
557 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
558
559 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
560 if (power_on) {
561 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);
562 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
563 } else {
564 dpp_base->ctx->dc->optimized_required = true;
565 dpp_base->deferred_reg_writes.bits.disable_3dlut = true;
566 }
567 }
568 }
569
dpp3_power_on_shaper(struct dpp * dpp_base,bool power_on)570 static void dpp3_power_on_shaper(
571 struct dpp *dpp_base,
572 bool power_on)
573 {
574 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
575
576 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
577 if (power_on) {
578 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);
579 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
580 } else {
581 dpp_base->ctx->dc->optimized_required = true;
582 dpp_base->deferred_reg_writes.bits.disable_shaper = true;
583 }
584 }
585 }
586
dpp3_configure_blnd_lut(struct dpp * dpp_base,bool is_ram_a)587 static void dpp3_configure_blnd_lut(
588 struct dpp *dpp_base,
589 bool is_ram_a)
590 {
591 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
592
593 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
594 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
595 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
596
597 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
598 }
599
dpp3_program_blnd_pwl(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)600 static void dpp3_program_blnd_pwl(
601 struct dpp *dpp_base,
602 const struct pwl_result_data *rgb,
603 uint32_t num)
604 {
605 uint32_t i;
606 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
607 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
608 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
609 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
610
611 if (is_rgb_equal(rgb, num)) {
612 for (i = 0 ; i < num; i++)
613 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
614 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
615 } else {
616 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
617 for (i = 0 ; i < num; i++)
618 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
619 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
620
621 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
622 for (i = 0 ; i < num; i++)
623 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
624 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
625
626 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
627 for (i = 0 ; i < num; i++)
628 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
629 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
630 }
631 }
632
dcn3_dpp_cm_get_reg_field(struct dcn3_dpp * dpp,struct dcn3_xfer_func_reg * reg)633 static void dcn3_dpp_cm_get_reg_field(
634 struct dcn3_dpp *dpp,
635 struct dcn3_xfer_func_reg *reg)
636 {
637 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
638 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
639 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
640 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
641 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
642 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
643 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
644 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
645
646 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
647 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
648 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
649 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
650 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
651 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
652 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
653 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
654 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
655 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
656 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
657 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
658 }
659
660 /*program blnd lut RAM A*/
dpp3_program_blnd_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)661 static void dpp3_program_blnd_luta_settings(
662 struct dpp *dpp_base,
663 const struct pwl_params *params)
664 {
665 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
666 struct dcn3_xfer_func_reg gam_regs;
667
668 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
669
670 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
671 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
672 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
673 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
674 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
675 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
676 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
677 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
678 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
679 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
680 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
681 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
682 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
683 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
684
685 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
686 }
687
688 /*program blnd lut RAM B*/
dpp3_program_blnd_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)689 static void dpp3_program_blnd_lutb_settings(
690 struct dpp *dpp_base,
691 const struct pwl_params *params)
692 {
693 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
694 struct dcn3_xfer_func_reg gam_regs;
695
696 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
697
698 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
699 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
700 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
701 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
702 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
703 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
704 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
705 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
706 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
707 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
708 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
709 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
710 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
711 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
712
713 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
714 }
715
dpp3_get_blndgam_current(struct dpp * dpp_base)716 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
717 {
718 enum dc_lut_mode mode;
719 uint32_t mode_current = 0;
720 uint32_t in_use = 0;
721
722 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
723
724 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current);
725 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use);
726
727 switch (mode_current) {
728 case 0:
729 case 1:
730 mode = LUT_BYPASS;
731 break;
732
733 case 2:
734 if (in_use == 0)
735 mode = LUT_RAM_A;
736 else
737 mode = LUT_RAM_B;
738 break;
739 default:
740 mode = LUT_BYPASS;
741 break;
742 }
743
744 return mode;
745 }
746
dpp3_program_blnd_lut(struct dpp * dpp_base,const struct pwl_params * params)747 static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
748 const struct pwl_params *params)
749 {
750 enum dc_lut_mode current_mode;
751 enum dc_lut_mode next_mode;
752 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
753
754 if (params == NULL) {
755 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
756 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
757 dpp3_power_on_blnd_lut(dpp_base, false);
758 return false;
759 }
760
761 current_mode = dpp3_get_blndgam_current(dpp_base);
762 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
763 next_mode = LUT_RAM_A;
764 else
765 next_mode = LUT_RAM_B;
766
767 dpp3_power_on_blnd_lut(dpp_base, true);
768 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
769
770 if (next_mode == LUT_RAM_A)
771 dpp3_program_blnd_luta_settings(dpp_base, params);
772 else
773 dpp3_program_blnd_lutb_settings(dpp_base, params);
774
775 dpp3_program_blnd_pwl(
776 dpp_base, params->rgb_resulted, params->hw_points_num);
777
778 REG_UPDATE_2(CM_BLNDGAM_CONTROL,
779 CM_BLNDGAM_MODE, 2,
780 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
781
782 return true;
783 }
784
785
dpp3_program_shaper_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)786 static void dpp3_program_shaper_lut(
787 struct dpp *dpp_base,
788 const struct pwl_result_data *rgb,
789 uint32_t num)
790 {
791 uint32_t i, red, green, blue;
792 uint32_t red_delta, green_delta, blue_delta;
793 uint32_t red_value, green_value, blue_value;
794
795 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
796
797 for (i = 0 ; i < num; i++) {
798
799 red = rgb[i].red_reg;
800 green = rgb[i].green_reg;
801 blue = rgb[i].blue_reg;
802
803 red_delta = rgb[i].delta_red_reg;
804 green_delta = rgb[i].delta_green_reg;
805 blue_delta = rgb[i].delta_blue_reg;
806
807 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
808 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
809 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
810
811 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
812 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
813 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
814 }
815
816 }
817
dpp3_get_shaper_current(struct dpp * dpp_base)818 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
819 {
820 enum dc_lut_mode mode;
821 uint32_t state_mode;
822 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
823
824 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode);
825
826 switch (state_mode) {
827 case 0:
828 mode = LUT_BYPASS;
829 break;
830 case 1:
831 mode = LUT_RAM_A;
832 break;
833 case 2:
834 mode = LUT_RAM_B;
835 break;
836 default:
837 mode = LUT_BYPASS;
838 break;
839 }
840
841 return mode;
842 }
843
dpp3_configure_shaper_lut(struct dpp * dpp_base,bool is_ram_a)844 static void dpp3_configure_shaper_lut(
845 struct dpp *dpp_base,
846 bool is_ram_a)
847 {
848 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
849
850 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
851 CM_SHAPER_LUT_WRITE_EN_MASK, 7);
852 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
853 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
854 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
855 }
856
857 /*program shaper RAM A*/
858
dpp3_program_shaper_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)859 static void dpp3_program_shaper_luta_settings(
860 struct dpp *dpp_base,
861 const struct pwl_params *params)
862 {
863 const struct gamma_curve *curve;
864 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
865
866 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
867 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
868 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
869 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
870 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
871 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
872 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
873 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
874 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
875
876 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
877 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
878 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
879
880 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
881 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
882 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
883
884 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
885 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
886 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
887
888 curve = params->arr_curve_points;
889 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
890 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
891 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
892 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
893 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
894
895 curve += 2;
896 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
897 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
898 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
899 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
900 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
901
902 curve += 2;
903 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
904 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
905 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
906 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
907 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
908
909 curve += 2;
910 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
911 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
912 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
913 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
914 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
915
916 curve += 2;
917 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
918 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
919 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
920 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
921 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
922
923 curve += 2;
924 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
925 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
926 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
927 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
928 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
929
930 curve += 2;
931 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
932 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
933 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
934 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
935 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
936
937 curve += 2;
938 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
939 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
940 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
941 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
942 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
943
944 curve += 2;
945 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
946 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
947 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
948 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
949 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
950
951 curve += 2;
952 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
953 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
954 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
955 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
956 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
957
958 curve += 2;
959 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
960 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
961 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
962 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
963 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
964
965 curve += 2;
966 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
967 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
968 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
969 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
970 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
971
972 curve += 2;
973 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
974 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
975 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
976 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
977 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
978
979 curve += 2;
980 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
981 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
982 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
983 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
984 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
985
986 curve += 2;
987 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
988 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
989 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
990 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
991 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
992
993 curve += 2;
994 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
995 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
996 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
997 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
998 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
999
1000 curve += 2;
1001 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
1002 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1003 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1004 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1005 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1006 }
1007
1008 /*program shaper RAM B*/
dpp3_program_shaper_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)1009 static void dpp3_program_shaper_lutb_settings(
1010 struct dpp *dpp_base,
1011 const struct pwl_params *params)
1012 {
1013 const struct gamma_curve *curve;
1014 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1015
1016 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
1017 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
1018 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
1019 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
1020 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
1021 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
1022 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
1023 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
1024 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
1025
1026 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
1027 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
1028 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
1029
1030 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
1031 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
1032 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
1033
1034 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
1035 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
1036 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
1037
1038 curve = params->arr_curve_points;
1039 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
1040 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1041 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1042 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1043 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1044
1045 curve += 2;
1046 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
1047 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
1048 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
1049 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
1050 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
1051
1052 curve += 2;
1053 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1054 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1055 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1056 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1057 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1058
1059 curve += 2;
1060 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1061 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1062 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1063 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1064 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1065
1066 curve += 2;
1067 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1068 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1069 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1070 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1071 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1072
1073 curve += 2;
1074 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1075 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1076 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1077 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1078 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1079
1080 curve += 2;
1081 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1082 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1083 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1084 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1085 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1086
1087 curve += 2;
1088 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1089 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1090 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1091 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1092 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1093
1094 curve += 2;
1095 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1096 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1097 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1098 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1099 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1100
1101 curve += 2;
1102 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1103 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1104 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1105 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1106 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1107
1108 curve += 2;
1109 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1110 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1111 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1112 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1113 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1114
1115 curve += 2;
1116 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1117 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1118 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1119 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1120 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1121
1122 curve += 2;
1123 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1124 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1125 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1126 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1127 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1128
1129 curve += 2;
1130 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1131 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1132 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1133 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1134 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1135
1136 curve += 2;
1137 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1138 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1139 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1140 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1141 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1142
1143 curve += 2;
1144 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1145 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1146 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1147 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1148 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1149
1150 curve += 2;
1151 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1152 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1153 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1154 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1155 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1156
1157 }
1158
1159
dpp3_program_shaper(struct dpp * dpp_base,const struct pwl_params * params)1160 static bool dpp3_program_shaper(struct dpp *dpp_base,
1161 const struct pwl_params *params)
1162 {
1163 enum dc_lut_mode current_mode;
1164 enum dc_lut_mode next_mode;
1165
1166 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1167
1168 if (params == NULL) {
1169 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1170 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1171 dpp3_power_on_shaper(dpp_base, false);
1172 return false;
1173 }
1174
1175 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1176 dpp3_power_on_shaper(dpp_base, true);
1177
1178 current_mode = dpp3_get_shaper_current(dpp_base);
1179
1180 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1181 next_mode = LUT_RAM_B;
1182 else
1183 next_mode = LUT_RAM_A;
1184
1185 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
1186
1187 if (next_mode == LUT_RAM_A)
1188 dpp3_program_shaper_luta_settings(dpp_base, params);
1189 else
1190 dpp3_program_shaper_lutb_settings(dpp_base, params);
1191
1192 dpp3_program_shaper_lut(
1193 dpp_base, params->rgb_resulted, params->hw_points_num);
1194
1195 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1196
1197 return true;
1198
1199 }
1200
get3dlut_config(struct dpp * dpp_base,bool * is_17x17x17,bool * is_12bits_color_channel)1201 static enum dc_lut_mode get3dlut_config(
1202 struct dpp *dpp_base,
1203 bool *is_17x17x17,
1204 bool *is_12bits_color_channel)
1205 {
1206 uint32_t i_mode, i_enable_10bits, lut_size;
1207 enum dc_lut_mode mode;
1208 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1209
1210 REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1211 CM_3DLUT_30BIT_EN, &i_enable_10bits);
1212 REG_GET(CM_3DLUT_MODE,
1213 CM_3DLUT_MODE_CURRENT, &i_mode);
1214
1215 switch (i_mode) {
1216 case 0:
1217 mode = LUT_BYPASS;
1218 break;
1219 case 1:
1220 mode = LUT_RAM_A;
1221 break;
1222 case 2:
1223 mode = LUT_RAM_B;
1224 break;
1225 default:
1226 mode = LUT_BYPASS;
1227 break;
1228 }
1229 if (i_enable_10bits > 0)
1230 *is_12bits_color_channel = false;
1231 else
1232 *is_12bits_color_channel = true;
1233
1234 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1235
1236 if (lut_size == 0)
1237 *is_17x17x17 = true;
1238 else
1239 *is_17x17x17 = false;
1240
1241 return mode;
1242 }
1243 /*
1244 * select ramA or ramB, or bypass
1245 * select color channel size 10 or 12 bits
1246 * select 3dlut size 17x17x17 or 9x9x9
1247 */
dpp3_set_3dlut_mode(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17)1248 static void dpp3_set_3dlut_mode(
1249 struct dpp *dpp_base,
1250 enum dc_lut_mode mode,
1251 bool is_color_channel_12bits,
1252 bool is_lut_size17x17x17)
1253 {
1254 uint32_t lut_mode;
1255 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1256
1257 if (mode == LUT_BYPASS)
1258 lut_mode = 0;
1259 else if (mode == LUT_RAM_A)
1260 lut_mode = 1;
1261 else
1262 lut_mode = 2;
1263
1264 REG_UPDATE_2(CM_3DLUT_MODE,
1265 CM_3DLUT_MODE, lut_mode,
1266 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1267 }
1268
dpp3_select_3dlut_ram(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits)1269 static void dpp3_select_3dlut_ram(
1270 struct dpp *dpp_base,
1271 enum dc_lut_mode mode,
1272 bool is_color_channel_12bits)
1273 {
1274 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1275
1276 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1277 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1278 CM_3DLUT_30BIT_EN,
1279 is_color_channel_12bits == true ? 0:1);
1280 }
1281
1282
1283
dpp3_set3dlut_ram12(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1284 static void dpp3_set3dlut_ram12(
1285 struct dpp *dpp_base,
1286 const struct dc_rgb *lut,
1287 uint32_t entries)
1288 {
1289 uint32_t i, red, green, blue, red1, green1, blue1;
1290 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1291
1292 for (i = 0 ; i < entries; i += 2) {
1293 red = lut[i].red<<4;
1294 green = lut[i].green<<4;
1295 blue = lut[i].blue<<4;
1296 red1 = lut[i+1].red<<4;
1297 green1 = lut[i+1].green<<4;
1298 blue1 = lut[i+1].blue<<4;
1299
1300 REG_SET_2(CM_3DLUT_DATA, 0,
1301 CM_3DLUT_DATA0, red,
1302 CM_3DLUT_DATA1, red1);
1303
1304 REG_SET_2(CM_3DLUT_DATA, 0,
1305 CM_3DLUT_DATA0, green,
1306 CM_3DLUT_DATA1, green1);
1307
1308 REG_SET_2(CM_3DLUT_DATA, 0,
1309 CM_3DLUT_DATA0, blue,
1310 CM_3DLUT_DATA1, blue1);
1311
1312 }
1313 }
1314
1315 /*
1316 * load selected lut with 10 bits color channels
1317 */
dpp3_set3dlut_ram10(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1318 static void dpp3_set3dlut_ram10(
1319 struct dpp *dpp_base,
1320 const struct dc_rgb *lut,
1321 uint32_t entries)
1322 {
1323 uint32_t i, red, green, blue, value;
1324 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1325
1326 for (i = 0; i < entries; i++) {
1327 red = lut[i].red;
1328 green = lut[i].green;
1329 blue = lut[i].blue;
1330
1331 value = (red<<20) | (green<<10) | blue;
1332
1333 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1334 }
1335
1336 }
1337
1338
dpp3_select_3dlut_ram_mask(struct dpp * dpp_base,uint32_t ram_selection_mask)1339 static void dpp3_select_3dlut_ram_mask(
1340 struct dpp *dpp_base,
1341 uint32_t ram_selection_mask)
1342 {
1343 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1344
1345 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1346 ram_selection_mask);
1347 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1348 }
1349
dpp3_program_3dlut(struct dpp * dpp_base,struct tetrahedral_params * params)1350 static bool dpp3_program_3dlut(struct dpp *dpp_base,
1351 struct tetrahedral_params *params)
1352 {
1353 enum dc_lut_mode mode;
1354 bool is_17x17x17;
1355 bool is_12bits_color_channel;
1356 struct dc_rgb *lut0;
1357 struct dc_rgb *lut1;
1358 struct dc_rgb *lut2;
1359 struct dc_rgb *lut3;
1360 int lut_size0;
1361 int lut_size;
1362
1363 if (params == NULL) {
1364 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1365 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1366 dpp3_power_on_hdr3dlut(dpp_base, false);
1367 return false;
1368 }
1369
1370 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1371 dpp3_power_on_hdr3dlut(dpp_base, true);
1372
1373 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1374
1375 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1376 mode = LUT_RAM_A;
1377 else
1378 mode = LUT_RAM_B;
1379
1380 is_17x17x17 = !params->use_tetrahedral_9;
1381 is_12bits_color_channel = params->use_12bits;
1382 if (is_17x17x17) {
1383 lut0 = params->tetrahedral_17.lut0;
1384 lut1 = params->tetrahedral_17.lut1;
1385 lut2 = params->tetrahedral_17.lut2;
1386 lut3 = params->tetrahedral_17.lut3;
1387 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1388 sizeof(params->tetrahedral_17.lut0[0]);
1389 lut_size = sizeof(params->tetrahedral_17.lut1)/
1390 sizeof(params->tetrahedral_17.lut1[0]);
1391 } else {
1392 lut0 = params->tetrahedral_9.lut0;
1393 lut1 = params->tetrahedral_9.lut1;
1394 lut2 = params->tetrahedral_9.lut2;
1395 lut3 = params->tetrahedral_9.lut3;
1396 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1397 sizeof(params->tetrahedral_9.lut0[0]);
1398 lut_size = sizeof(params->tetrahedral_9.lut1)/
1399 sizeof(params->tetrahedral_9.lut1[0]);
1400 }
1401
1402 dpp3_select_3dlut_ram(dpp_base, mode,
1403 is_12bits_color_channel);
1404 dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1405 if (is_12bits_color_channel)
1406 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1407 else
1408 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1409
1410 dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1411 if (is_12bits_color_channel)
1412 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1413 else
1414 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1415
1416 dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1417 if (is_12bits_color_channel)
1418 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1419 else
1420 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1421
1422 dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1423 if (is_12bits_color_channel)
1424 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1425 else
1426 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1427
1428
1429 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1430 is_17x17x17);
1431
1432 return true;
1433 }
1434 static struct dpp_funcs dcn30_dpp_funcs = {
1435 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1436 .dpp_read_state = dpp30_read_state,
1437 .dpp_reset = dpp_reset,
1438 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
1439 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1440 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,
1441 .dpp_set_csc_adjustment = NULL,
1442 .dpp_set_csc_default = NULL,
1443 .dpp_program_regamma_pwl = NULL,
1444 .dpp_set_pre_degam = dpp3_set_pre_degam,
1445 .dpp_program_input_lut = NULL,
1446 .dpp_full_bypass = dpp1_full_bypass,
1447 .dpp_setup = dpp3_cnv_setup,
1448 .dpp_program_degamma_pwl = NULL,
1449 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1450 .dpp_program_cm_bias = dpp3_program_cm_bias,
1451 .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1452 .dpp_program_shaper_lut = dpp3_program_shaper,
1453 .dpp_program_3dlut = dpp3_program_3dlut,
1454 .dpp_deferred_update = dpp3_deferred_update,
1455 .dpp_program_bias_and_scale = NULL,
1456 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
1457 .set_cursor_attributes = dpp3_set_cursor_attributes,
1458 .set_cursor_position = dpp1_set_cursor_position,
1459 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1460 .dpp_dppclk_control = dpp1_dppclk_control,
1461 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
1462 };
1463
1464
1465 static struct dpp_caps dcn30_dpp_cap = {
1466 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1467 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1468 };
1469
dpp3_construct(struct dcn3_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn3_dpp_registers * tf_regs,const struct dcn3_dpp_shift * tf_shift,const struct dcn3_dpp_mask * tf_mask)1470 bool dpp3_construct(
1471 struct dcn3_dpp *dpp,
1472 struct dc_context *ctx,
1473 uint32_t inst,
1474 const struct dcn3_dpp_registers *tf_regs,
1475 const struct dcn3_dpp_shift *tf_shift,
1476 const struct dcn3_dpp_mask *tf_mask)
1477 {
1478 dpp->base.ctx = ctx;
1479
1480 dpp->base.inst = inst;
1481 dpp->base.funcs = &dcn30_dpp_funcs;
1482 dpp->base.caps = &dcn30_dpp_cap;
1483
1484 dpp->tf_regs = tf_regs;
1485 dpp->tf_shift = tf_shift;
1486 dpp->tf_mask = tf_mask;
1487
1488 return true;
1489 }
1490
1491