1 /*
2 * arch/arm/mach-dove/addr-map.c
3 *
4 * Address map functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/mbus.h>
14 #include <linux/io.h>
15 #include <asm/mach/arch.h>
16 #include <asm/setup.h>
17 #include "common.h"
18
19 /*
20 * Generic Address Decode Windows bit settings
21 */
22 #define TARGET_DDR 0x0
23 #define TARGET_BOOTROM 0x1
24 #define TARGET_CESA 0x3
25 #define TARGET_PCIE0 0x4
26 #define TARGET_PCIE1 0x8
27 #define TARGET_SCRATCHPAD 0xd
28
29 #define ATTR_CESA 0x01
30 #define ATTR_BOOTROM 0xfd
31 #define ATTR_DEV_SPI0_ROM 0xfe
32 #define ATTR_DEV_SPI1_ROM 0xfb
33 #define ATTR_PCIE_IO 0xe0
34 #define ATTR_PCIE_MEM 0xe8
35 #define ATTR_SCRATCHPAD 0x0
36
37 /*
38 * CPU Address Decode Windows registers
39 */
40 #define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
41 #define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
42 #define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
43 #define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
44
45 struct mbus_dram_target_info dove_mbus_dram_info;
46
ddr_map_sc(int i)47 static inline void __iomem *ddr_map_sc(int i)
48 {
49 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
50 }
51
cpu_win_can_remap(int win)52 static int cpu_win_can_remap(int win)
53 {
54 if (win < 4)
55 return 1;
56
57 return 0;
58 }
59
setup_cpu_win(int win,u32 base,u32 size,u8 target,u8 attr,int remap)60 static void __init setup_cpu_win(int win, u32 base, u32 size,
61 u8 target, u8 attr, int remap)
62 {
63 u32 ctrl;
64
65 base &= 0xffff0000;
66 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
67
68 writel(base, WIN_BASE(win));
69 writel(ctrl, WIN_CTRL(win));
70 if (cpu_win_can_remap(win)) {
71 if (remap < 0)
72 remap = base;
73 writel(remap & 0xffff0000, WIN_REMAP_LO(win));
74 writel(0, WIN_REMAP_HI(win));
75 }
76 }
77
dove_setup_cpu_mbus(void)78 void __init dove_setup_cpu_mbus(void)
79 {
80 int i;
81 int cs;
82
83 /*
84 * First, disable and clear windows.
85 */
86 for (i = 0; i < 8; i++) {
87 writel(0, WIN_BASE(i));
88 writel(0, WIN_CTRL(i));
89 if (cpu_win_can_remap(i)) {
90 writel(0, WIN_REMAP_LO(i));
91 writel(0, WIN_REMAP_HI(i));
92 }
93 }
94
95 /*
96 * Setup windows for PCIe IO+MEM space.
97 */
98 setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
99 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
100 setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
101 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
102 setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
103 TARGET_PCIE0, ATTR_PCIE_MEM, -1);
104 setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
105 TARGET_PCIE1, ATTR_PCIE_MEM, -1);
106
107 /*
108 * Setup window for CESA engine.
109 */
110 setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
111 TARGET_CESA, ATTR_CESA, -1);
112
113 /*
114 * Setup the Window to the BootROM for Standby and Sleep Resume
115 */
116 setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
117 TARGET_BOOTROM, ATTR_BOOTROM, -1);
118
119 /*
120 * Setup the Window to the PMU Scratch Pad space
121 */
122 setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
123 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
124
125 /*
126 * Setup MBUS dram target info.
127 */
128 dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
129
130 for (i = 0, cs = 0; i < 2; i++) {
131 u32 map = readl(ddr_map_sc(i));
132
133 /*
134 * Chip select enabled?
135 */
136 if (map & 1) {
137 struct mbus_dram_window *w;
138
139 w = &dove_mbus_dram_info.cs[cs++];
140 w->cs_index = i;
141 w->mbus_attr = 0; /* CS address decoding done inside */
142 /* the DDR controller, no need to */
143 /* provide attributes */
144 w->base = map & 0xff800000;
145 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
146 }
147 }
148 dove_mbus_dram_info.num_cs = cs;
149 }
150