1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * arch/sh64/kernel/traps.c
7 *
8 * Copyright (C) 2000, 2001 Paolo Alberelli
9 * Copyright (C) 2003 Paul Mundt
10 * Copyright (C) 2003 Richard Curnow
11 *
12 */
13
14 /*
15 * 'Traps.c' handles hardware traps and faults after we have saved some
16 * state in 'entry.S'.
17 */
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/string.h>
21 #include <linux/errno.h>
22 #include <linux/ptrace.h>
23 #include <linux/timer.h>
24 #include <linux/mm.h>
25 #include <linux/smp.h>
26 #include <linux/smp_lock.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/spinlock.h>
30
31 #include <linux/interrupt.h>
32 #include <linux/sysctl.h>
33
34 #include <asm/system.h>
35 #include <asm/uaccess.h>
36 #include <asm/io.h>
37 #include <asm/atomic.h>
38 #include <asm/processor.h>
39 #include <asm/pgtable.h>
40
41 #undef DEBUG_EXCEPTION
42 #ifdef DEBUG_EXCEPTION
43 /* implemented in ../lib/dbg.c */
44 extern void show_excp_regs(char *fname, int trapnr, int signr,
45 struct pt_regs *regs);
46 #else
47 #define show_excp_regs(a, b, c, d)
48 #endif
49
50 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
51 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
52
53 #define DO_ERROR(trapnr, signr, str, name, tsk) \
54 asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
55 { \
56 do_unhandled_exception(trapnr, signr, str, __FUNCTION__, error_code, regs, current); \
57 }
58
59 spinlock_t die_lock;
60
die(const char * str,struct pt_regs * regs,long err)61 void die(const char * str, struct pt_regs * regs, long err)
62 {
63 console_verbose();
64 spin_lock_irq(&die_lock);
65 printk("%s: %lx\n", str, (err & 0xffffff));
66 show_regs(regs);
67 spin_unlock_irq(&die_lock);
68 do_exit(SIGSEGV);
69 }
70
die_if_kernel(const char * str,struct pt_regs * regs,long err)71 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
72 {
73 if (!user_mode(regs))
74 die(str, regs, err);
75 }
76
die_if_no_fixup(const char * str,struct pt_regs * regs,long err)77 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
78 {
79 if (!user_mode(regs))
80 {
81 unsigned long fixup;
82 fixup = search_exception_table(regs->pc);
83 if (fixup) {
84 regs->pc = fixup;
85 return;
86 }
87 die(str, regs, err);
88 }
89 }
90
91 DO_ERROR(13, SIGILL, "illegal slot instruction", illegal_slot_inst, current)
92 DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
93
94
95 /* Implement misaligned load/store handling for kernel (and optionally for user
96 mode too). Limitation : only SHmedia mode code is handled - there is no
97 handling at all for misaligned accesses occurring in SHcompact code yet. */
98
99 static int misaligned_fixup(struct pt_regs *regs);
100
do_address_error_load(unsigned long error_code,struct pt_regs * regs)101 asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
102 {
103 if (misaligned_fixup(regs) < 0) {
104 do_unhandled_exception(7, SIGSEGV, "address error(load)", __FUNCTION__,
105 error_code, regs, current);
106 }
107 return;
108 }
109
do_address_error_store(unsigned long error_code,struct pt_regs * regs)110 asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
111 {
112 if (misaligned_fixup(regs) < 0) {
113 do_unhandled_exception(8, SIGSEGV, "address error(store)", __FUNCTION__,
114 error_code, regs, current);
115 }
116 return;
117 }
118
119 #if defined(CONFIG_SH64_ID2815_WORKAROUND)
120
121 #define OPCODE_INVALID 0
122 #define OPCODE_USER_VALID 1
123 #define OPCODE_PRIV_VALID 2
124
125 /* getcon/putcon - requires checking which control register is referenced. */
126 #define OPCODE_CTRL_REG 3
127
128 /* Table of valid opcodes for SHmedia mode.
129 Form a 10-bit value by concatenating the major/minor opcodes i.e.
130 opcode[31:26,20:16]. The 6 MSBs of this value index into the following
131 array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
132 LSBs==4'b0000 etc). */
133 static unsigned long shmedia_opcode_table[64] = {
134 0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
135 0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
136 0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
137 0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
138 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
139 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
140 0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
141 0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
142 };
143
do_reserved_inst(unsigned long error_code,struct pt_regs * regs)144 void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
145 {
146 /* Workaround SH5-101 cut2 silicon defect #2815 :
147 in some situations, inter-mode branches from SHcompact -> SHmedia
148 which should take ITLBMISS or EXECPROT exceptions at the target
149 falsely take RESINST at the target instead. */
150
151 unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
152 unsigned long pc, aligned_pc;
153 int get_user_error;
154 int trapnr = 12;
155 int signr = SIGILL;
156 char *exception_name = "reserved_instruction";
157
158 pc = regs->pc;
159 if ((pc & 3) == 1) {
160 /* SHmedia : check for defect. This requires executable vmas
161 to be readable too. */
162 aligned_pc = pc & ~3;
163 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
164 get_user_error = -EFAULT;
165 } else {
166 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
167 }
168 if (get_user_error >= 0) {
169 unsigned long index, shift;
170 unsigned long major, minor, combined;
171 unsigned long reserved_field;
172 reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
173 major = (opcode >> 26) & 0x3f;
174 minor = (opcode >> 16) & 0xf;
175 combined = (major << 4) | minor;
176 index = major;
177 shift = minor << 1;
178 if (reserved_field == 0) {
179 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
180 switch (opcode_state) {
181 case OPCODE_INVALID:
182 /* Trap. */
183 break;
184 case OPCODE_USER_VALID:
185 /* Restart the instruction : the branch to the instruction will now be from an RTE
186 not from SHcompact so the silicon defect won't be triggered. */
187 return;
188 case OPCODE_PRIV_VALID:
189 if (!user_mode(regs)) {
190 /* Should only ever get here if a module has
191 SHcompact code inside it. If so, the same fix up is needed. */
192 return; /* same reason */
193 }
194 /* Otherwise, user mode trying to execute a privileged instruction -
195 fall through to trap. */
196 break;
197 case OPCODE_CTRL_REG:
198 /* If in privileged mode, return as above. */
199 if (!user_mode(regs)) return;
200 /* In user mode ... */
201 if (combined == 0x9f) { /* GETCON */
202 unsigned long regno = (opcode >> 20) & 0x3f;
203 if (regno >= 62) {
204 return;
205 }
206 /* Otherwise, reserved or privileged control register, => trap */
207 } else if (combined == 0x1bf) { /* PUTCON */
208 unsigned long regno = (opcode >> 4) & 0x3f;
209 if (regno >= 62) {
210 return;
211 }
212 /* Otherwise, reserved or privileged control register, => trap */
213 } else {
214 /* Trap */
215 }
216 break;
217 default:
218 /* Fall through to trap. */
219 break;
220 }
221 }
222 /* fall through to normal resinst processing */
223 } else {
224 /* Error trying to read opcode. This typically means a
225 real fault, not a RESINST any more. So change the
226 codes. */
227 trapnr = 87;
228 exception_name = "address error (exec)";
229 signr = SIGSEGV;
230 }
231 }
232
233 do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
234 }
235
236 #else /* CONFIG_SH64_ID2815_WORKAROUND */
237
238 /* If the workaround isn't needed, this is just a straightforward reserved
239 instruction */
240 DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
241
242 #endif /* CONFIG_SH64_ID2815_WORKAROUND */
243
244
245 #include <asm/system.h>
246
247 /* Called with interrupts disabled */
do_exception_error(unsigned long ex,struct pt_regs * regs)248 asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
249 {
250 PLS();
251 show_excp_regs(__FUNCTION__, -1, -1, regs);
252 die_if_kernel("exception", regs, ex);
253 }
254
do_unknown_trapa(unsigned long scId,struct pt_regs * regs)255 int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
256 {
257 /* Syscall debug */
258 printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
259
260 die_if_kernel("unknown trapa", regs, scId);
261
262 return -ENOSYS;
263 }
264
show_task(unsigned long * sp)265 void show_task(unsigned long *sp)
266 {
267 unsigned long module_start, module_end;
268 unsigned long kernel_start, kernel_end;
269 unsigned long *stack;
270 extern int _text, _etext;
271 int i = 1;
272
273 kernel_start = (unsigned long)&_text;
274 kernel_end = (unsigned long)&_etext;
275
276 module_start = VMALLOC_START;
277 module_end = VMALLOC_END;
278
279 if (!sp) {
280 /*
281 * If we haven't specified a sane sp, fetch it..
282 */
283 __asm__ __volatile__ (
284 "or r15, r63, %0\n\t"
285 "getcon " __c17 ", %1\n\t"
286 : "=r" (module_start),
287 "=r" (module_end)
288 );
289
290 sp = (unsigned long *)module_start;
291 }
292
293 stack = sp;
294
295 printk("\nCall Trace: ");
296
297 while ((unsigned long)stack & (PAGE_SIZE - 1)) {
298 unsigned long addr = *stack++;
299
300 if ((addr >= kernel_start && addr < kernel_end) ||
301 (addr >= module_start && addr < module_end)) {
302 /*
303 * Do a bit of formatting here.. on an 80 column
304 * display, 6 entries is the most we can deal with
305 * per-line, since each address will take up 13 spaces.
306 */
307 if (i && ((i % 6) == 0))
308 printk("\n ");
309
310 printk("[<%08lx>] ", addr);
311 i++;
312 }
313 }
314
315 printk("\n");
316 }
317
show_trace_task(struct task_struct * tsk)318 void show_trace_task(struct task_struct *tsk)
319 {
320 show_task((unsigned long *)tsk->thread.sp);
321 }
322
dump_stack(void)323 void dump_stack(void)
324 {
325 show_task(NULL);
326 }
327
do_unhandled_exception(int trapnr,int signr,char * str,char * fn_name,unsigned long error_code,struct pt_regs * regs,struct task_struct * tsk)328 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
329 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
330 {
331 show_excp_regs(fn_name, trapnr, signr, regs);
332 tsk->thread.error_code = error_code;
333 tsk->thread.trap_no = trapnr;
334 if (user_mode(regs)) force_sig(signr, tsk);
335 die_if_no_fixup(str, regs, error_code);
336 }
337
read_opcode(unsigned long long pc,unsigned long * result_opcode)338 static int read_opcode(unsigned long long pc, unsigned long *result_opcode)
339 {
340 int get_user_error;
341 unsigned long aligned_pc;
342 unsigned long opcode;
343
344 if ((pc & 3) == 1) {
345 /* SHmedia */
346 aligned_pc = pc & ~3;
347 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
348 get_user_error = -EFAULT;
349 } else {
350 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
351 *result_opcode = opcode;
352 }
353 return get_user_error;
354 } else if ((pc & 1) == 0) {
355 /* SHcompact */
356 /* TODO : provide handling for this. */
357 return -EFAULT;
358 } else {
359 /* misaligned */
360 return -EFAULT;
361 }
362 }
363
address_is_sign_extended(__u64 a)364 static int address_is_sign_extended(__u64 a)
365 {
366 __u64 b;
367 #if (NEFF == 32)
368 b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
369 return (b == a) ? 1 : 0;
370 #else
371 #error "Sign extend check only works for NEFF==32"
372 #endif
373 }
374
generate_and_check_address(struct pt_regs * regs,__u32 opcode,int displacement_not_indexed,int width_shift,__u64 * address)375 static int generate_and_check_address(struct pt_regs *regs,
376 __u32 opcode,
377 int displacement_not_indexed,
378 int width_shift,
379 __u64 *address)
380 {
381 /* return -1 for fault, 0 for OK */
382
383 __u64 base_address, addr;
384 int basereg;
385 int do_as_user = user_mode(regs);
386
387 basereg = (opcode >> 20) & 0x3f;
388 base_address = regs->regs[basereg];
389 if (displacement_not_indexed) {
390 __s64 displacement;
391 displacement = (opcode >> 10) & 0x3ff;
392 displacement = ((displacement << 54) >> 54); /* sign extend */
393 addr = (__u64)((__s64)base_address + (displacement << width_shift));
394 } else {
395 __u64 offset;
396 int offsetreg;
397 offsetreg = (opcode >> 10) & 0x3f;
398 offset = regs->regs[offsetreg];
399 addr = base_address + offset;
400 }
401
402 /* Check sign extended */
403 if (!address_is_sign_extended(addr)) {
404 return -1;
405 }
406
407 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
408 /* Check accessible. For misaligned access in the kernel, assume the
409 address is always accessible (and if not, just fault when the
410 load/store gets done.) */
411 if (do_as_user) {
412 if (addr >= TASK_SIZE) {
413 return -1;
414 }
415 /* Do access_ok check later - it depends on whether it's a load or a store. */
416 }
417 #endif
418
419 *address = addr;
420 return 0;
421 }
422
423 /* Default value as for sh */
424 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
425 static int user_mode_unaligned_fixup_count = 10;
426 static int user_mode_unaligned_fixup_enable = 1;
427 #endif
428
429 static int kernel_mode_unaligned_fixup_count = 32;
430
misaligned_kernel_word_load(__u64 address,int do_sign_extend,__u64 * result)431 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
432 {
433 unsigned short x;
434 unsigned char *p, *q;
435 p = (unsigned char *) (int) address;
436 q = (unsigned char *) &x;
437 q[0] = p[0];
438 q[1] = p[1];
439
440 if (do_sign_extend) {
441 *result = (__u64)(__s64) *(short *) &x;
442 } else {
443 *result = (__u64) x;
444 }
445 }
446
misaligned_kernel_word_store(__u64 address,__u64 value)447 static void misaligned_kernel_word_store(__u64 address, __u64 value)
448 {
449 unsigned short x;
450 unsigned char *p, *q;
451 p = (unsigned char *) (int) address;
452 q = (unsigned char *) &x;
453
454 x = (__u16) value;
455 p[0] = q[0];
456 p[1] = q[1];
457 }
458
misaligned_load(struct pt_regs * regs,__u32 opcode,int displacement_not_indexed,int width_shift,int do_sign_extend)459 static int misaligned_load(struct pt_regs *regs,
460 __u32 opcode,
461 int displacement_not_indexed,
462 int width_shift,
463 int do_sign_extend)
464 {
465 /* Return -1 for a fault, 0 for OK */
466 int error;
467 int destreg;
468 __u64 address;
469
470 error = generate_and_check_address(regs, opcode,
471 displacement_not_indexed, width_shift, &address);
472 if (error < 0) {
473 return error;
474 }
475
476 destreg = (opcode >> 4) & 0x3f;
477 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
478 if (user_mode(regs)) {
479 __u64 buffer;
480
481 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
482 return -1;
483 }
484
485 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
486 return -1; /* fault */
487 }
488 switch (width_shift) {
489 case 1:
490 if (do_sign_extend) {
491 regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
492 } else {
493 regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
494 }
495 break;
496 case 2:
497 regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
498 break;
499 case 3:
500 regs->regs[destreg] = buffer;
501 break;
502 default:
503 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
504 width_shift, (unsigned long) regs->pc);
505 break;
506 }
507 } else
508 #endif
509 {
510 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
511 __u64 lo, hi;
512
513 switch (width_shift) {
514 case 1:
515 misaligned_kernel_word_load(address, do_sign_extend, ®s->regs[destreg]);
516 break;
517 case 2:
518 asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
519 asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
520 regs->regs[destreg] = lo | hi;
521 break;
522 case 3:
523 asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
524 asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
525 regs->regs[destreg] = lo | hi;
526 break;
527
528 default:
529 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
530 width_shift, (unsigned long) regs->pc);
531 break;
532 }
533 }
534
535 return 0;
536
537 }
538
misaligned_store(struct pt_regs * regs,__u32 opcode,int displacement_not_indexed,int width_shift)539 static int misaligned_store(struct pt_regs *regs,
540 __u32 opcode,
541 int displacement_not_indexed,
542 int width_shift)
543 {
544 /* Return -1 for a fault, 0 for OK */
545 int error;
546 int srcreg;
547 __u64 address;
548
549 error = generate_and_check_address(regs, opcode,
550 displacement_not_indexed, width_shift, &address);
551 if (error < 0) {
552 return error;
553 }
554
555 srcreg = (opcode >> 4) & 0x3f;
556 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
557 if (user_mode(regs)) {
558 __u64 buffer;
559
560 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
561 return -1;
562 }
563
564 switch (width_shift) {
565 case 1:
566 *(__u16 *) &buffer = (__u16) regs->regs[srcreg];
567 break;
568 case 2:
569 *(__u32 *) &buffer = (__u32) regs->regs[srcreg];
570 break;
571 case 3:
572 buffer = regs->regs[srcreg];
573 break;
574 default:
575 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
576 width_shift, (unsigned long) regs->pc);
577 break;
578 }
579
580 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
581 return -1; /* fault */
582 }
583 } else
584 #endif
585 {
586 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
587 __u64 val = regs->regs[srcreg];
588
589 switch (width_shift) {
590 case 1:
591 misaligned_kernel_word_store(address, val);
592 break;
593 case 2:
594 asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
595 asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
596 break;
597 case 3:
598 asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
599 asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
600 break;
601
602 default:
603 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
604 width_shift, (unsigned long) regs->pc);
605 break;
606 }
607 }
608
609 return 0;
610
611 }
612
613 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
614 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
615 error. */
misaligned_fpu_load(struct pt_regs * regs,__u32 opcode,int displacement_not_indexed,int width_shift,int do_paired_load)616 static int misaligned_fpu_load(struct pt_regs *regs,
617 __u32 opcode,
618 int displacement_not_indexed,
619 int width_shift,
620 int do_paired_load)
621 {
622 /* Return -1 for a fault, 0 for OK */
623 int error;
624 int destreg;
625 __u64 address;
626
627 error = generate_and_check_address(regs, opcode,
628 displacement_not_indexed, width_shift, &address);
629 if (error < 0) {
630 return error;
631 }
632
633 destreg = (opcode >> 4) & 0x3f;
634 if (user_mode(regs)) {
635 __u64 buffer;
636 __u32 buflo, bufhi;
637
638 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
639 return -1;
640 }
641
642 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
643 return -1; /* fault */
644 }
645 /* 'current' may be the current owner of the FPU state, so
646 context switch the registers into memory so they can be
647 indexed by register number. */
648 if (last_task_used_math == current) {
649 grab_fpu();
650 fpsave(¤t->thread.fpu.hard);
651 release_fpu();
652 last_task_used_math = NULL;
653 regs->sr |= SR_FD;
654 }
655
656 buflo = *(__u32*) &buffer;
657 bufhi = *(1 + (__u32*) &buffer);
658
659 switch (width_shift) {
660 case 2:
661 current->thread.fpu.hard.fp_regs[destreg] = buflo;
662 break;
663 case 3:
664 if (do_paired_load) {
665 current->thread.fpu.hard.fp_regs[destreg] = buflo;
666 current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
667 } else {
668 #if defined(CONFIG_LITTLE_ENDIAN)
669 current->thread.fpu.hard.fp_regs[destreg] = bufhi;
670 current->thread.fpu.hard.fp_regs[destreg+1] = buflo;
671 #else
672 current->thread.fpu.hard.fp_regs[destreg] = buflo;
673 current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
674 #endif
675 }
676 break;
677 default:
678 printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
679 width_shift, (unsigned long) regs->pc);
680 break;
681 }
682 return 0;
683 } else {
684 die ("Misaligned FPU load inside kernel", regs, 0);
685 return -1;
686 }
687
688
689 }
690
misaligned_fpu_store(struct pt_regs * regs,__u32 opcode,int displacement_not_indexed,int width_shift,int do_paired_load)691 static int misaligned_fpu_store(struct pt_regs *regs,
692 __u32 opcode,
693 int displacement_not_indexed,
694 int width_shift,
695 int do_paired_load)
696 {
697 /* Return -1 for a fault, 0 for OK */
698 int error;
699 int srcreg;
700 __u64 address;
701
702 error = generate_and_check_address(regs, opcode,
703 displacement_not_indexed, width_shift, &address);
704 if (error < 0) {
705 return error;
706 }
707
708 srcreg = (opcode >> 4) & 0x3f;
709 if (user_mode(regs)) {
710 __u64 buffer;
711 /* Initialise these to NaNs. */
712 __u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
713
714 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
715 return -1;
716 }
717
718 /* 'current' may be the current owner of the FPU state, so
719 context switch the registers into memory so they can be
720 indexed by register number. */
721 if (last_task_used_math == current) {
722 grab_fpu();
723 fpsave(¤t->thread.fpu.hard);
724 release_fpu();
725 last_task_used_math = NULL;
726 regs->sr |= SR_FD;
727 }
728
729 switch (width_shift) {
730 case 2:
731 buflo = current->thread.fpu.hard.fp_regs[srcreg];
732 break;
733 case 3:
734 if (do_paired_load) {
735 buflo = current->thread.fpu.hard.fp_regs[srcreg];
736 bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
737 } else {
738 #if defined(CONFIG_LITTLE_ENDIAN)
739 bufhi = current->thread.fpu.hard.fp_regs[srcreg];
740 buflo = current->thread.fpu.hard.fp_regs[srcreg+1];
741 #else
742 buflo = current->thread.fpu.hard.fp_regs[srcreg];
743 bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
744 #endif
745 }
746 break;
747 default:
748 printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
749 width_shift, (unsigned long) regs->pc);
750 break;
751 }
752
753 *(__u32*) &buffer = buflo;
754 *(1 + (__u32*) &buffer) = bufhi;
755 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
756 return -1; /* fault */
757 }
758 return 0;
759 } else {
760 die ("Misaligned FPU load inside kernel", regs, 0);
761 return -1;
762 }
763 }
764 #endif
765
misaligned_fixup(struct pt_regs * regs)766 static int misaligned_fixup(struct pt_regs *regs)
767 {
768 unsigned long opcode;
769 int error;
770 int major, minor;
771
772 #if !defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
773 /* Never fixup user mode misaligned accesses without this option enabled. */
774 return -1;
775 #else
776 if (!user_mode_unaligned_fixup_enable) return -1;
777 #endif
778
779 error = read_opcode(regs->pc, &opcode);
780 if (error < 0) {
781 return error;
782 }
783 major = (opcode >> 26) & 0x3f;
784 minor = (opcode >> 16) & 0xf;
785
786 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
787 if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
788 --user_mode_unaligned_fixup_count;
789 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
790 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
791 current->comm, current->pid, (__u32)regs->pc, opcode);
792 } else
793 #endif
794 if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
795 --kernel_mode_unaligned_fixup_count;
796 if (in_interrupt()) {
797 printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
798 (__u32)regs->pc, opcode);
799 } else {
800 printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
801 current->comm, current->pid, (__u32)regs->pc, opcode);
802 }
803 }
804
805
806 switch (major) {
807 case (0x84>>2): /* LD.W */
808 error = misaligned_load(regs, opcode, 1, 1, 1);
809 break;
810 case (0xb0>>2): /* LD.UW */
811 error = misaligned_load(regs, opcode, 1, 1, 0);
812 break;
813 case (0x88>>2): /* LD.L */
814 error = misaligned_load(regs, opcode, 1, 2, 1);
815 break;
816 case (0x8c>>2): /* LD.Q */
817 error = misaligned_load(regs, opcode, 1, 3, 0);
818 break;
819
820 case (0xa4>>2): /* ST.W */
821 error = misaligned_store(regs, opcode, 1, 1);
822 break;
823 case (0xa8>>2): /* ST.L */
824 error = misaligned_store(regs, opcode, 1, 2);
825 break;
826 case (0xac>>2): /* ST.Q */
827 error = misaligned_store(regs, opcode, 1, 3);
828 break;
829
830 case (0x40>>2): /* indexed loads */
831 switch (minor) {
832 case 0x1: /* LDX.W */
833 error = misaligned_load(regs, opcode, 0, 1, 1);
834 break;
835 case 0x5: /* LDX.UW */
836 error = misaligned_load(regs, opcode, 0, 1, 0);
837 break;
838 case 0x2: /* LDX.L */
839 error = misaligned_load(regs, opcode, 0, 2, 1);
840 break;
841 case 0x3: /* LDX.Q */
842 error = misaligned_load(regs, opcode, 0, 3, 0);
843 break;
844 default:
845 error = -1;
846 break;
847 }
848 break;
849
850 case (0x60>>2): /* indexed stores */
851 switch (minor) {
852 case 0x1: /* STX.W */
853 error = misaligned_store(regs, opcode, 0, 1);
854 break;
855 case 0x2: /* STX.L */
856 error = misaligned_store(regs, opcode, 0, 2);
857 break;
858 case 0x3: /* STX.Q */
859 error = misaligned_store(regs, opcode, 0, 3);
860 break;
861 default:
862 error = -1;
863 break;
864 }
865 break;
866
867 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
868 case (0x94>>2): /* FLD.S */
869 error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
870 break;
871 case (0x98>>2): /* FLD.P */
872 error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
873 break;
874 case (0x9c>>2): /* FLD.D */
875 error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
876 break;
877 case (0x1c>>2): /* floating indexed loads */
878 switch (minor) {
879 case 0x8: /* FLDX.S */
880 error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
881 break;
882 case 0xd: /* FLDX.P */
883 error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
884 break;
885 case 0x9: /* FLDX.D */
886 error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
887 break;
888 default:
889 error = -1;
890 break;
891 }
892 break;
893 case (0xb4>>2): /* FLD.S */
894 error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
895 break;
896 case (0xb8>>2): /* FLD.P */
897 error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
898 break;
899 case (0xbc>>2): /* FLD.D */
900 error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
901 break;
902 case (0x3c>>2): /* floating indexed stores */
903 switch (minor) {
904 case 0x8: /* FSTX.S */
905 error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
906 break;
907 case 0xd: /* FSTX.P */
908 error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
909 break;
910 case 0x9: /* FSTX.D */
911 error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
912 break;
913 default:
914 error = -1;
915 break;
916 }
917 break;
918 #endif
919
920 default:
921 /* Fault */
922 error = -1;
923 break;
924 }
925
926 if (error < 0) {
927 return error;
928 } else {
929 regs->pc += 4; /* Skip the instruction that's just been emulated */
930 return 0;
931 }
932
933 }
934
935 static ctl_table unaligned_table[] = {
936 {1, "kernel_reports", &kernel_mode_unaligned_fixup_count,
937 sizeof(int), 0644, NULL, &proc_dointvec},
938 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
939 {2, "user_reports", &user_mode_unaligned_fixup_count,
940 sizeof(int), 0644, NULL, &proc_dointvec},
941 {3, "user_enable", &user_mode_unaligned_fixup_enable,
942 sizeof(int), 0644, NULL, &proc_dointvec},
943 #endif
944 {0}
945 };
946
947 static ctl_table unaligned_root[] = {
948 {1, "unaligned_fixup", NULL, 0, 0555, unaligned_table},
949 {0}
950 };
951
952 static ctl_table sh64_root[] = {
953 {1, "sh64", NULL, 0, 0555, unaligned_root},
954 {0}
955 };
956 static struct ctl_table_header *sysctl_header;
init_sysctl(void)957 static int __init init_sysctl(void)
958 {
959 sysctl_header = register_sysctl_table(sh64_root, 0);
960 return 0;
961 }
962
963 __initcall(init_sysctl);
964
965