1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "../dmub_srv.h"
27 #include "dmub_dcn20.h"
28 #include "dmub_dcn21.h"
29 #include "dmub_cmd.h"
30 #include "dmub_dcn30.h"
31 #include "dmub_dcn301.h"
32 #include "dmub_dcn302.h"
33 #include "dmub_dcn303.h"
34 #include "dmub_dcn31.h"
35 #include "dmub_dcn315.h"
36 #include "dmub_dcn316.h"
37 #include "dmub_dcn32.h"
38 #include "os_types.h"
39 /*
40 * Note: the DMUB service is standalone. No additional headers should be
41 * added below or above this line unless they reside within the DMUB
42 * folder.
43 */
44
45 /* Alignment for framebuffer memory. */
46 #define DMUB_FB_ALIGNMENT (1024 * 1024)
47
48 /* Stack size. */
49 #define DMUB_STACK_SIZE (128 * 1024)
50
51 /* Context size. */
52 #define DMUB_CONTEXT_SIZE (512 * 1024)
53
54 /* Mailbox size : Ring buffers are required for both inbox and outbox */
55 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
56
57 /* Default state size if meta is absent. */
58 #define DMUB_FW_STATE_SIZE (64 * 1024)
59
60 /* Default tracebuffer size if meta is absent. */
61 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
62
63
64 /* Default scratch mem size. */
65 #define DMUB_SCRATCH_MEM_SIZE (256)
66
67 /* Number of windows in use. */
68 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)
69 /* Base addresses. */
70
71 #define DMUB_CW0_BASE (0x60000000)
72 #define DMUB_CW1_BASE (0x61000000)
73 #define DMUB_CW3_BASE (0x63000000)
74 #define DMUB_CW4_BASE (0x64000000)
75 #define DMUB_CW5_BASE (0x65000000)
76 #define DMUB_CW6_BASE (0x66000000)
77
78 #define DMUB_REGION5_BASE (0xA0000000)
79
dmub_align(uint32_t val,uint32_t factor)80 static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
81 {
82 return (val + factor - 1) / factor * factor;
83 }
84
dmub_flush_buffer_mem(const struct dmub_fb * fb)85 void dmub_flush_buffer_mem(const struct dmub_fb *fb)
86 {
87 const uint8_t *base = (const uint8_t *)fb->cpu_addr;
88 uint8_t buf[64];
89 uint32_t pos, end;
90
91 /**
92 * Read 64-byte chunks since we don't want to store a
93 * large temporary buffer for this purpose.
94 */
95 end = fb->size / sizeof(buf) * sizeof(buf);
96
97 for (pos = 0; pos < end; pos += sizeof(buf))
98 dmub_memcpy(buf, base + pos, sizeof(buf));
99
100 /* Read anything leftover into the buffer. */
101 if (end < fb->size)
102 dmub_memcpy(buf, base + pos, fb->size - end);
103 }
104
105 static const struct dmub_fw_meta_info *
dmub_get_fw_meta_info_from_blob(const uint8_t * blob,uint32_t blob_size,uint32_t meta_offset)106 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)
107 {
108 const union dmub_fw_meta *meta;
109
110 if (!blob || !blob_size)
111 return NULL;
112
113 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset)
114 return NULL;
115
116 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset -
117 sizeof(union dmub_fw_meta));
118
119 if (meta->info.magic_value != DMUB_FW_META_MAGIC)
120 return NULL;
121
122 return &meta->info;
123 }
124
125 static const struct dmub_fw_meta_info *
dmub_get_fw_meta_info(const struct dmub_srv_region_params * params)126 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params)
127 {
128 const struct dmub_fw_meta_info *info = NULL;
129
130 if (params->fw_bss_data && params->bss_data_size) {
131 /* Legacy metadata region. */
132 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data,
133 params->bss_data_size,
134 DMUB_FW_META_OFFSET);
135 } else if (params->fw_inst_const && params->inst_const_size) {
136 /* Combined metadata region - can be aligned to 16-bytes. */
137 uint32_t i;
138
139 for (i = 0; i < 16; ++i) {
140 info = dmub_get_fw_meta_info_from_blob(
141 params->fw_inst_const, params->inst_const_size, i);
142
143 if (info)
144 break;
145 }
146 }
147
148 return info;
149 }
150
dmub_srv_hw_setup(struct dmub_srv * dmub,enum dmub_asic asic)151 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
152 {
153 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
154
155 switch (asic) {
156 case DMUB_ASIC_DCN20:
157 case DMUB_ASIC_DCN21:
158 case DMUB_ASIC_DCN30:
159 case DMUB_ASIC_DCN301:
160 case DMUB_ASIC_DCN302:
161 case DMUB_ASIC_DCN303:
162 dmub->regs = &dmub_srv_dcn20_regs;
163
164 funcs->reset = dmub_dcn20_reset;
165 funcs->reset_release = dmub_dcn20_reset_release;
166 funcs->backdoor_load = dmub_dcn20_backdoor_load;
167 funcs->setup_windows = dmub_dcn20_setup_windows;
168 funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
169 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
170 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
171 funcs->is_supported = dmub_dcn20_is_supported;
172 funcs->is_hw_init = dmub_dcn20_is_hw_init;
173 funcs->set_gpint = dmub_dcn20_set_gpint;
174 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
175 funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
176 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
177 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
178 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
179 funcs->get_current_time = dmub_dcn20_get_current_time;
180
181 // Out mailbox register access functions for RN and above
182 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
183 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
184 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
185
186 //outbox0 call stacks
187 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;
188 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
189 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
190
191 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
192
193 if (asic == DMUB_ASIC_DCN21) {
194 dmub->regs = &dmub_srv_dcn21_regs;
195
196 funcs->is_phy_init = dmub_dcn21_is_phy_init;
197 }
198 if (asic == DMUB_ASIC_DCN30) {
199 dmub->regs = &dmub_srv_dcn30_regs;
200
201 funcs->backdoor_load = dmub_dcn30_backdoor_load;
202 funcs->setup_windows = dmub_dcn30_setup_windows;
203 }
204 if (asic == DMUB_ASIC_DCN301) {
205 dmub->regs = &dmub_srv_dcn301_regs;
206
207 funcs->backdoor_load = dmub_dcn30_backdoor_load;
208 funcs->setup_windows = dmub_dcn30_setup_windows;
209 }
210 if (asic == DMUB_ASIC_DCN302) {
211 dmub->regs = &dmub_srv_dcn302_regs;
212
213 funcs->backdoor_load = dmub_dcn30_backdoor_load;
214 funcs->setup_windows = dmub_dcn30_setup_windows;
215 }
216 if (asic == DMUB_ASIC_DCN303) {
217 dmub->regs = &dmub_srv_dcn303_regs;
218
219 funcs->backdoor_load = dmub_dcn30_backdoor_load;
220 funcs->setup_windows = dmub_dcn30_setup_windows;
221 }
222 break;
223
224 case DMUB_ASIC_DCN31:
225 case DMUB_ASIC_DCN31B:
226 case DMUB_ASIC_DCN314:
227 case DMUB_ASIC_DCN315:
228 case DMUB_ASIC_DCN316:
229 if (asic == DMUB_ASIC_DCN315)
230 dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
231 else if (asic == DMUB_ASIC_DCN316)
232 dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
233 else
234 dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
235 funcs->reset = dmub_dcn31_reset;
236 funcs->reset_release = dmub_dcn31_reset_release;
237 funcs->backdoor_load = dmub_dcn31_backdoor_load;
238 funcs->setup_windows = dmub_dcn31_setup_windows;
239 funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
240 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
241 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
242 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
243 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
244 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
245 funcs->is_supported = dmub_dcn31_is_supported;
246 funcs->is_hw_init = dmub_dcn31_is_hw_init;
247 funcs->set_gpint = dmub_dcn31_set_gpint;
248 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
249 funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
250 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
251 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
252 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
253 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
254 //outbox0 call stacks
255 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
256 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
257 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
258
259 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
260 funcs->should_detect = dmub_dcn31_should_detect;
261 funcs->get_current_time = dmub_dcn31_get_current_time;
262
263 break;
264
265 case DMUB_ASIC_DCN32:
266 case DMUB_ASIC_DCN321:
267 dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
268 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
269 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
270 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
271 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
272 funcs->reset = dmub_dcn32_reset;
273 funcs->reset_release = dmub_dcn32_reset_release;
274 funcs->backdoor_load = dmub_dcn32_backdoor_load;
275 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
276 funcs->setup_windows = dmub_dcn32_setup_windows;
277 funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
278 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
279 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
280 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
281 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
282 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
283 funcs->is_supported = dmub_dcn32_is_supported;
284 funcs->is_hw_init = dmub_dcn32_is_hw_init;
285 funcs->set_gpint = dmub_dcn32_set_gpint;
286 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
287 funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
288 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
289 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
290 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
291 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
292
293 /* outbox0 call stacks */
294 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
295 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
296 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
297 funcs->get_current_time = dmub_dcn32_get_current_time;
298 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
299
300 break;
301
302 default:
303 return false;
304 }
305
306 return true;
307 }
308
dmub_srv_create(struct dmub_srv * dmub,const struct dmub_srv_create_params * params)309 enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
310 const struct dmub_srv_create_params *params)
311 {
312 enum dmub_status status = DMUB_STATUS_OK;
313
314 dmub_memset(dmub, 0, sizeof(*dmub));
315
316 dmub->funcs = params->funcs;
317 dmub->user_ctx = params->user_ctx;
318 dmub->asic = params->asic;
319 dmub->fw_version = params->fw_version;
320 dmub->is_virtual = params->is_virtual;
321
322 /* Setup asic dependent hardware funcs. */
323 if (!dmub_srv_hw_setup(dmub, params->asic)) {
324 status = DMUB_STATUS_INVALID;
325 goto cleanup;
326 }
327
328 /* Override (some) hardware funcs based on user params. */
329 if (params->hw_funcs) {
330 if (params->hw_funcs->emul_get_inbox1_rptr)
331 dmub->hw_funcs.emul_get_inbox1_rptr =
332 params->hw_funcs->emul_get_inbox1_rptr;
333
334 if (params->hw_funcs->emul_set_inbox1_wptr)
335 dmub->hw_funcs.emul_set_inbox1_wptr =
336 params->hw_funcs->emul_set_inbox1_wptr;
337
338 if (params->hw_funcs->is_supported)
339 dmub->hw_funcs.is_supported =
340 params->hw_funcs->is_supported;
341 }
342
343 /* Sanity checks for required hw func pointers. */
344 if (!dmub->hw_funcs.get_inbox1_rptr ||
345 !dmub->hw_funcs.set_inbox1_wptr) {
346 status = DMUB_STATUS_INVALID;
347 goto cleanup;
348 }
349
350 cleanup:
351 if (status == DMUB_STATUS_OK)
352 dmub->sw_init = true;
353 else
354 dmub_srv_destroy(dmub);
355
356 return status;
357 }
358
dmub_srv_destroy(struct dmub_srv * dmub)359 void dmub_srv_destroy(struct dmub_srv *dmub)
360 {
361 dmub_memset(dmub, 0, sizeof(*dmub));
362 }
363
364 enum dmub_status
dmub_srv_calc_region_info(struct dmub_srv * dmub,const struct dmub_srv_region_params * params,struct dmub_srv_region_info * out)365 dmub_srv_calc_region_info(struct dmub_srv *dmub,
366 const struct dmub_srv_region_params *params,
367 struct dmub_srv_region_info *out)
368 {
369 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
370 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
371 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
372 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
373 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
374 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
375 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
376 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM];
377 const struct dmub_fw_meta_info *fw_info;
378 uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
379 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
380 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE;
381
382 if (!dmub->sw_init)
383 return DMUB_STATUS_INVALID;
384
385 memset(out, 0, sizeof(*out));
386
387 out->num_regions = DMUB_NUM_WINDOWS;
388
389 inst->base = 0x0;
390 inst->top = inst->base + params->inst_const_size;
391
392 data->base = dmub_align(inst->top, 256);
393 data->top = data->base + params->bss_data_size;
394
395 /*
396 * All cache windows below should be aligned to the size
397 * of the DMCUB cache line, 64 bytes.
398 */
399
400 stack->base = dmub_align(data->top, 256);
401 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
402
403 bios->base = dmub_align(stack->top, 256);
404 bios->top = bios->base + params->vbios_size;
405
406 mail->base = dmub_align(bios->top, 256);
407 mail->top = mail->base + DMUB_MAILBOX_SIZE;
408
409 fw_info = dmub_get_fw_meta_info(params);
410
411 if (fw_info) {
412 fw_state_size = fw_info->fw_region_size;
413 trace_buffer_size = fw_info->trace_buffer_size;
414
415 /**
416 * If DM didn't fill in a version, then fill it in based on
417 * the firmware meta now that we have it.
418 *
419 * TODO: Make it easier for driver to extract this out to
420 * pass during creation.
421 */
422 if (dmub->fw_version == 0)
423 dmub->fw_version = fw_info->fw_version;
424 }
425
426 trace_buff->base = dmub_align(mail->top, 256);
427 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
428
429 fw_state->base = dmub_align(trace_buff->top, 256);
430 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
431
432 scratch_mem->base = dmub_align(fw_state->top, 256);
433 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64);
434
435 out->fb_size = dmub_align(scratch_mem->top, 4096);
436
437 return DMUB_STATUS_OK;
438 }
439
dmub_srv_calc_fb_info(struct dmub_srv * dmub,const struct dmub_srv_fb_params * params,struct dmub_srv_fb_info * out)440 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
441 const struct dmub_srv_fb_params *params,
442 struct dmub_srv_fb_info *out)
443 {
444 uint8_t *cpu_base;
445 uint64_t gpu_base;
446 uint32_t i;
447
448 if (!dmub->sw_init)
449 return DMUB_STATUS_INVALID;
450
451 memset(out, 0, sizeof(*out));
452
453 if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
454 return DMUB_STATUS_INVALID;
455
456 cpu_base = (uint8_t *)params->cpu_addr;
457 gpu_base = params->gpu_addr;
458
459 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
460 const struct dmub_region *reg =
461 ¶ms->region_info->regions[i];
462
463 out->fb[i].cpu_addr = cpu_base + reg->base;
464 out->fb[i].gpu_addr = gpu_base + reg->base;
465 out->fb[i].size = reg->top - reg->base;
466 }
467
468 out->num_fb = DMUB_NUM_WINDOWS;
469
470 return DMUB_STATUS_OK;
471 }
472
dmub_srv_has_hw_support(struct dmub_srv * dmub,bool * is_supported)473 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
474 bool *is_supported)
475 {
476 *is_supported = false;
477
478 if (!dmub->sw_init)
479 return DMUB_STATUS_INVALID;
480
481 if (dmub->hw_funcs.is_supported)
482 *is_supported = dmub->hw_funcs.is_supported(dmub);
483
484 return DMUB_STATUS_OK;
485 }
486
dmub_srv_is_hw_init(struct dmub_srv * dmub,bool * is_hw_init)487 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
488 {
489 *is_hw_init = false;
490
491 if (!dmub->sw_init)
492 return DMUB_STATUS_INVALID;
493
494 if (!dmub->hw_init)
495 return DMUB_STATUS_OK;
496
497 if (dmub->hw_funcs.is_hw_init)
498 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
499
500 return DMUB_STATUS_OK;
501 }
502
dmub_srv_hw_init(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)503 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
504 const struct dmub_srv_hw_params *params)
505 {
506 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
507 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
508 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
509 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
510 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
511 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
512 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
513 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
514
515 struct dmub_rb_init_params rb_params, outbox0_rb_params;
516 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
517 struct dmub_region inbox1, outbox1, outbox0;
518
519 if (!dmub->sw_init)
520 return DMUB_STATUS_INVALID;
521
522 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
523 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
524 ASSERT(0);
525 return DMUB_STATUS_INVALID;
526 }
527
528 dmub->fb_base = params->fb_base;
529 dmub->fb_offset = params->fb_offset;
530 dmub->psp_version = params->psp_version;
531
532 if (dmub->hw_funcs.reset)
533 dmub->hw_funcs.reset(dmub);
534
535 cw0.offset.quad_part = inst_fb->gpu_addr;
536 cw0.region.base = DMUB_CW0_BASE;
537 cw0.region.top = cw0.region.base + inst_fb->size - 1;
538
539 cw1.offset.quad_part = stack_fb->gpu_addr;
540 cw1.region.base = DMUB_CW1_BASE;
541 cw1.region.top = cw1.region.base + stack_fb->size - 1;
542
543 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
544 dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
545
546 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
547 /**
548 * Read back all the instruction memory so we don't hang the
549 * DMCUB when backdoor loading if the write from x86 hasn't been
550 * flushed yet. This only occurs in backdoor loading.
551 */
552 dmub_flush_buffer_mem(inst_fb);
553
554 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
555 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
556 else
557 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
558 }
559
560 cw2.offset.quad_part = data_fb->gpu_addr;
561 cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
562 cw2.region.top = cw2.region.base + data_fb->size;
563
564 cw3.offset.quad_part = bios_fb->gpu_addr;
565 cw3.region.base = DMUB_CW3_BASE;
566 cw3.region.top = cw3.region.base + bios_fb->size;
567
568 cw4.offset.quad_part = mail_fb->gpu_addr;
569 cw4.region.base = DMUB_CW4_BASE;
570 cw4.region.top = cw4.region.base + mail_fb->size;
571
572 /**
573 * Doubled the mailbox region to accomodate inbox and outbox.
574 * Note: Currently, currently total mailbox size is 16KB. It is split
575 * equally into 8KB between inbox and outbox. If this config is
576 * changed, then uncached base address configuration of outbox1
577 * has to be updated in funcs->setup_out_mailbox.
578 */
579 inbox1.base = cw4.region.base;
580 inbox1.top = cw4.region.base + DMUB_RB_SIZE;
581 outbox1.base = inbox1.top;
582 outbox1.top = cw4.region.top;
583
584 cw5.offset.quad_part = tracebuff_fb->gpu_addr;
585 cw5.region.base = DMUB_CW5_BASE;
586 cw5.region.top = cw5.region.base + tracebuff_fb->size;
587
588 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
589 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
590
591 cw6.offset.quad_part = fw_state_fb->gpu_addr;
592 cw6.region.base = DMUB_CW6_BASE;
593 cw6.region.top = cw6.region.base + fw_state_fb->size;
594
595 dmub->fw_state = fw_state_fb->cpu_addr;
596
597 dmub->scratch_mem_fb = *scratch_mem_fb;
598
599 if (dmub->hw_funcs.setup_windows)
600 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
601
602 if (dmub->hw_funcs.setup_outbox0)
603 dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
604
605 if (dmub->hw_funcs.setup_mailbox)
606 dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
607 if (dmub->hw_funcs.setup_out_mailbox)
608 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
609
610 dmub_memset(&rb_params, 0, sizeof(rb_params));
611 rb_params.ctx = dmub;
612 rb_params.base_address = mail_fb->cpu_addr;
613 rb_params.capacity = DMUB_RB_SIZE;
614 dmub_rb_init(&dmub->inbox1_rb, &rb_params);
615
616 // Initialize outbox1 ring buffer
617 rb_params.ctx = dmub;
618 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
619 rb_params.capacity = DMUB_RB_SIZE;
620 dmub_rb_init(&dmub->outbox1_rb, &rb_params);
621
622 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
623 outbox0_rb_params.ctx = dmub;
624 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
625 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
626 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
627
628 /* Report to DMUB what features are supported by current driver */
629 if (dmub->hw_funcs.enable_dmub_boot_options)
630 dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
631
632 if (dmub->hw_funcs.skip_dmub_panel_power_sequence)
633 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
634 params->skip_panel_power_sequence);
635
636 if (dmub->hw_funcs.reset_release)
637 dmub->hw_funcs.reset_release(dmub);
638
639 dmub->hw_init = true;
640
641 return DMUB_STATUS_OK;
642 }
643
dmub_srv_hw_reset(struct dmub_srv * dmub)644 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
645 {
646 if (!dmub->sw_init)
647 return DMUB_STATUS_INVALID;
648
649 if (dmub->hw_funcs.reset)
650 dmub->hw_funcs.reset(dmub);
651
652 dmub->hw_init = false;
653
654 return DMUB_STATUS_OK;
655 }
656
dmub_srv_cmd_queue(struct dmub_srv * dmub,const union dmub_rb_cmd * cmd)657 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
658 const union dmub_rb_cmd *cmd)
659 {
660 if (!dmub->hw_init)
661 return DMUB_STATUS_INVALID;
662
663 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
664 return DMUB_STATUS_OK;
665
666 return DMUB_STATUS_QUEUE_FULL;
667 }
668
dmub_srv_cmd_execute(struct dmub_srv * dmub)669 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
670 {
671 struct dmub_rb flush_rb;
672
673 if (!dmub->hw_init)
674 return DMUB_STATUS_INVALID;
675
676 /**
677 * Read back all the queued commands to ensure that they've
678 * been flushed to framebuffer memory. Otherwise DMCUB might
679 * read back stale, fully invalid or partially invalid data.
680 */
681 flush_rb = dmub->inbox1_rb;
682 flush_rb.rptr = dmub->inbox1_last_wptr;
683 dmub_rb_flush_pending(&flush_rb);
684
685 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
686
687 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
688
689 return DMUB_STATUS_OK;
690 }
691
dmub_srv_wait_for_auto_load(struct dmub_srv * dmub,uint32_t timeout_us)692 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
693 uint32_t timeout_us)
694 {
695 uint32_t i;
696
697 if (!dmub->hw_init)
698 return DMUB_STATUS_INVALID;
699
700 for (i = 0; i <= timeout_us; i += 100) {
701 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
702
703 if (status.bits.dal_fw && status.bits.mailbox_rdy)
704 return DMUB_STATUS_OK;
705
706 udelay(100);
707 }
708
709 return DMUB_STATUS_TIMEOUT;
710 }
711
dmub_srv_wait_for_phy_init(struct dmub_srv * dmub,uint32_t timeout_us)712 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
713 uint32_t timeout_us)
714 {
715 uint32_t i = 0;
716
717 if (!dmub->hw_init)
718 return DMUB_STATUS_INVALID;
719
720 if (!dmub->hw_funcs.is_phy_init)
721 return DMUB_STATUS_OK;
722
723 for (i = 0; i <= timeout_us; i += 10) {
724 if (dmub->hw_funcs.is_phy_init(dmub))
725 return DMUB_STATUS_OK;
726
727 udelay(10);
728 }
729
730 return DMUB_STATUS_TIMEOUT;
731 }
732
dmub_srv_wait_for_idle(struct dmub_srv * dmub,uint32_t timeout_us)733 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
734 uint32_t timeout_us)
735 {
736 uint32_t i, rptr;
737
738 if (!dmub->hw_init)
739 return DMUB_STATUS_INVALID;
740
741 for (i = 0; i <= timeout_us; ++i) {
742 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
743
744 if (rptr > dmub->inbox1_rb.capacity)
745 return DMUB_STATUS_HW_FAILURE;
746
747 dmub->inbox1_rb.rptr = rptr;
748
749 if (dmub_rb_empty(&dmub->inbox1_rb))
750 return DMUB_STATUS_OK;
751
752 udelay(1);
753 }
754
755 return DMUB_STATUS_TIMEOUT;
756 }
757
758 enum dmub_status
dmub_srv_send_gpint_command(struct dmub_srv * dmub,enum dmub_gpint_command command_code,uint16_t param,uint32_t timeout_us)759 dmub_srv_send_gpint_command(struct dmub_srv *dmub,
760 enum dmub_gpint_command command_code,
761 uint16_t param, uint32_t timeout_us)
762 {
763 union dmub_gpint_data_register reg;
764 uint32_t i;
765
766 if (!dmub->sw_init)
767 return DMUB_STATUS_INVALID;
768
769 if (!dmub->hw_funcs.set_gpint)
770 return DMUB_STATUS_INVALID;
771
772 if (!dmub->hw_funcs.is_gpint_acked)
773 return DMUB_STATUS_INVALID;
774
775 reg.bits.status = 1;
776 reg.bits.command_code = command_code;
777 reg.bits.param = param;
778
779 dmub->hw_funcs.set_gpint(dmub, reg);
780
781 for (i = 0; i < timeout_us; ++i) {
782 udelay(1);
783
784 if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
785 return DMUB_STATUS_OK;
786 }
787
788 return DMUB_STATUS_TIMEOUT;
789 }
790
dmub_srv_get_gpint_response(struct dmub_srv * dmub,uint32_t * response)791 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
792 uint32_t *response)
793 {
794 *response = 0;
795
796 if (!dmub->sw_init)
797 return DMUB_STATUS_INVALID;
798
799 if (!dmub->hw_funcs.get_gpint_response)
800 return DMUB_STATUS_INVALID;
801
802 *response = dmub->hw_funcs.get_gpint_response(dmub);
803
804 return DMUB_STATUS_OK;
805 }
806
dmub_srv_get_gpint_dataout(struct dmub_srv * dmub,uint32_t * dataout)807 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
808 uint32_t *dataout)
809 {
810 *dataout = 0;
811
812 if (!dmub->sw_init)
813 return DMUB_STATUS_INVALID;
814
815 if (!dmub->hw_funcs.get_gpint_dataout)
816 return DMUB_STATUS_INVALID;
817
818 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
819
820 return DMUB_STATUS_OK;
821 }
822
dmub_srv_get_fw_boot_status(struct dmub_srv * dmub,union dmub_fw_boot_status * status)823 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
824 union dmub_fw_boot_status *status)
825 {
826 status->all = 0;
827
828 if (!dmub->sw_init)
829 return DMUB_STATUS_INVALID;
830
831 if (dmub->hw_funcs.get_fw_status)
832 *status = dmub->hw_funcs.get_fw_status(dmub);
833
834 return DMUB_STATUS_OK;
835 }
836
dmub_srv_cmd_with_reply_data(struct dmub_srv * dmub,union dmub_rb_cmd * cmd)837 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
838 union dmub_rb_cmd *cmd)
839 {
840 enum dmub_status status = DMUB_STATUS_OK;
841
842 // Queue command
843 status = dmub_srv_cmd_queue(dmub, cmd);
844
845 if (status != DMUB_STATUS_OK)
846 return status;
847
848 // Execute command
849 status = dmub_srv_cmd_execute(dmub);
850
851 if (status != DMUB_STATUS_OK)
852 return status;
853
854 // Wait for DMUB to process command
855 status = dmub_srv_wait_for_idle(dmub, 100000);
856
857 if (status != DMUB_STATUS_OK)
858 return status;
859
860 // Copy data back from ring buffer into command
861 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd);
862
863 return status;
864 }
865
dmub_rb_out_trace_buffer_front(struct dmub_rb * rb,void * entry)866 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
867 void *entry)
868 {
869 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
870 uint64_t *dst = (uint64_t *)entry;
871 uint8_t i;
872 uint8_t loop_count;
873
874 if (rb->rptr == rb->wrpt)
875 return false;
876
877 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t);
878 // copying data
879 for (i = 0; i < loop_count; i++)
880 *dst++ = *src++;
881
882 rb->rptr += sizeof(struct dmcub_trace_buf_entry);
883
884 rb->rptr %= rb->capacity;
885
886 return true;
887 }
888
dmub_srv_get_outbox0_msg(struct dmub_srv * dmub,struct dmcub_trace_buf_entry * entry)889 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
890 {
891 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub);
892
893 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
894 }
895
dmub_srv_get_diagnostic_data(struct dmub_srv * dmub,struct dmub_diagnostic_data * diag_data)896 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
897 {
898 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
899 return false;
900 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
901 return true;
902 }
903
dmub_srv_should_detect(struct dmub_srv * dmub)904 bool dmub_srv_should_detect(struct dmub_srv *dmub)
905 {
906 if (!dmub->hw_init || !dmub->hw_funcs.should_detect)
907 return false;
908
909 return dmub->hw_funcs.should_detect(dmub);
910 }
911
dmub_srv_clear_inbox0_ack(struct dmub_srv * dmub)912 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
913 {
914 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
915 return DMUB_STATUS_INVALID;
916
917 dmub->hw_funcs.clear_inbox0_ack_register(dmub);
918 return DMUB_STATUS_OK;
919 }
920
dmub_srv_wait_for_inbox0_ack(struct dmub_srv * dmub,uint32_t timeout_us)921 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)
922 {
923 uint32_t i = 0;
924 uint32_t ack = 0;
925
926 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register)
927 return DMUB_STATUS_INVALID;
928
929 for (i = 0; i <= timeout_us; i++) {
930 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
931 if (ack)
932 return DMUB_STATUS_OK;
933 }
934 return DMUB_STATUS_TIMEOUT;
935 }
936
dmub_srv_send_inbox0_cmd(struct dmub_srv * dmub,union dmub_inbox0_data_register data)937 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
938 union dmub_inbox0_data_register data)
939 {
940 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
941 return DMUB_STATUS_INVALID;
942
943 dmub->hw_funcs.send_inbox0_cmd(dmub, data);
944 return DMUB_STATUS_OK;
945 }
946