1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "../dmub_srv.h"
27 #include "dmub_reg.h"
28 #include "dmub_dcn20.h"
29 
30 #include "dcn/dcn_2_0_0_offset.h"
31 #include "dcn/dcn_2_0_0_sh_mask.h"
32 #include "soc15_hw_ip.h"
33 #include "vega10_ip_offset.h"
34 
35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
36 #define CTX dmub
37 #define REGS dmub->regs
38 
39 /* Registers. */
40 
41 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
42 #define DMUB_SR(reg) REG_OFFSET(reg),
43 	{
44 		DMUB_COMMON_REGS()
45 		DMCUB_INTERNAL_REGS()
46 	},
47 #undef DMUB_SR
48 
49 #define DMUB_SF(reg, field) FD_MASK(reg, field),
50 	{ DMUB_COMMON_FIELDS() },
51 #undef DMUB_SF
52 
53 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
54 	{ DMUB_COMMON_FIELDS() },
55 #undef DMUB_SF
56 };
57 
58 /* Shared functions. */
59 
dmub_dcn20_get_fb_base_offset(struct dmub_srv * dmub,uint64_t * fb_base,uint64_t * fb_offset)60 static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
61 					  uint64_t *fb_base,
62 					  uint64_t *fb_offset)
63 {
64 	uint32_t tmp;
65 
66 	if (dmub->fb_base || dmub->fb_offset) {
67 		*fb_base = dmub->fb_base;
68 		*fb_offset = dmub->fb_offset;
69 		return;
70 	}
71 
72 	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
73 	*fb_base = (uint64_t)tmp << 24;
74 
75 	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
76 	*fb_offset = (uint64_t)tmp << 24;
77 }
78 
dmub_dcn20_translate_addr(const union dmub_addr * addr_in,uint64_t fb_base,uint64_t fb_offset,union dmub_addr * addr_out)79 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
80 					     uint64_t fb_base,
81 					     uint64_t fb_offset,
82 					     union dmub_addr *addr_out)
83 {
84 	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
85 }
86 
dmub_dcn20_use_cached_inbox(struct dmub_srv * dmub)87 bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
88 {
89 	/* Cached inbox is not supported in this fw version range */
90 	return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&
91 		 dmub->fw_version <= DMUB_FW_VERSION(1, 10, 0));
92 }
93 
dmub_dcn20_reset(struct dmub_srv * dmub)94 void dmub_dcn20_reset(struct dmub_srv *dmub)
95 {
96 	union dmub_gpint_data_register cmd;
97 	const uint32_t timeout = 30;
98 	uint32_t in_reset, scratch, i;
99 
100 	REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset);
101 
102 	if (in_reset == 0) {
103 		cmd.bits.status = 1;
104 		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
105 		cmd.bits.param = 0;
106 
107 		dmub->hw_funcs.set_gpint(dmub, cmd);
108 
109 		/**
110 		 * Timeout covers both the ACK and the wait
111 		 * for remaining work to finish.
112 		 *
113 		 * This is mostly bound by the PHY disable sequence.
114 		 * Each register check will be greater than 1us, so
115 		 * don't bother using udelay.
116 		 */
117 
118 		for (i = 0; i < timeout; ++i) {
119 			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
120 				break;
121 		}
122 
123 		for (i = 0; i < timeout; ++i) {
124 			scratch = dmub->hw_funcs.get_gpint_response(dmub);
125 			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
126 				break;
127 		}
128 
129 		/* Clear the GPINT command manually so we don't reset again. */
130 		cmd.all = 0;
131 		dmub->hw_funcs.set_gpint(dmub, cmd);
132 
133 		/* Force reset in case we timed out, DMCUB is likely hung. */
134 	}
135 
136 	REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
137 	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
138 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
139 	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
140 	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
141 	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
142 	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
143 	REG_WRITE(DMCUB_SCRATCH0, 0);
144 }
145 
dmub_dcn20_reset_release(struct dmub_srv * dmub)146 void dmub_dcn20_reset_release(struct dmub_srv *dmub)
147 {
148 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
149 	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
150 	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
151 	REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
152 }
153 
dmub_dcn20_backdoor_load(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)154 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
155 			      const struct dmub_window *cw0,
156 			      const struct dmub_window *cw1)
157 {
158 	union dmub_addr offset;
159 	uint64_t fb_base, fb_offset;
160 
161 	dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
162 
163 	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
164 	REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
165 		     DMCUB_MEM_WRITE_SPACE, 0x3);
166 
167 	dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
168 
169 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
170 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
171 	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
172 	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
173 		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
174 		  DMCUB_REGION3_CW0_ENABLE, 1);
175 
176 	dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
177 
178 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
179 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
180 	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
181 	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
182 		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
183 		  DMCUB_REGION3_CW1_ENABLE, 1);
184 
185 	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
186 		     0x20);
187 }
188 
dmub_dcn20_setup_windows(struct dmub_srv * dmub,const struct dmub_window * cw2,const struct dmub_window * cw3,const struct dmub_window * cw4,const struct dmub_window * cw5,const struct dmub_window * cw6)189 void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
190 			      const struct dmub_window *cw2,
191 			      const struct dmub_window *cw3,
192 			      const struct dmub_window *cw4,
193 			      const struct dmub_window *cw5,
194 			      const struct dmub_window *cw6)
195 {
196 	union dmub_addr offset;
197 	uint64_t fb_base, fb_offset;
198 
199 	dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
200 
201 	if (cw2->region.base != cw2->region.top) {
202 		dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset,
203 					  &offset);
204 
205 		REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
206 		REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
207 		REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
208 		REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
209 			  DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
210 			  DMCUB_REGION3_CW2_ENABLE, 1);
211 	} else {
212 		REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
213 		REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
214 		REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
215 		REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
216 	}
217 
218 	dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
219 
220 	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
221 	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
222 	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
223 	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
224 		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
225 		  DMCUB_REGION3_CW3_ENABLE, 1);
226 
227 	/* TODO: Move this to CW4. */
228 	dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
229 
230 	/* New firmware can support CW4. */
231 	if (dmub_dcn20_use_cached_inbox(dmub)) {
232 		REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
233 		REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
234 		REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
235 		REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
236 			  DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
237 			  DMCUB_REGION3_CW4_ENABLE, 1);
238 	} else {
239 		REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
240 		REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
241 		REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
242 			  DMCUB_REGION4_TOP_ADDRESS,
243 			  cw4->region.top - cw4->region.base - 1,
244 			  DMCUB_REGION4_ENABLE, 1);
245 	}
246 
247 	dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
248 
249 	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
250 	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
251 	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
252 	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
253 		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
254 		  DMCUB_REGION3_CW5_ENABLE, 1);
255 
256 	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
257 	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
258 	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
259 		  DMCUB_REGION5_TOP_ADDRESS,
260 		  cw5->region.top - cw5->region.base - 1,
261 		  DMCUB_REGION5_ENABLE, 1);
262 
263 	dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
264 
265 	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
266 	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
267 	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
268 	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
269 		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
270 		  DMCUB_REGION3_CW6_ENABLE, 1);
271 }
272 
dmub_dcn20_setup_mailbox(struct dmub_srv * dmub,const struct dmub_region * inbox1)273 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
274 			      const struct dmub_region *inbox1)
275 {
276 	/* New firmware can support CW4 for the inbox. */
277 	if (dmub_dcn20_use_cached_inbox(dmub))
278 		REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
279 	else
280 		REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
281 
282 	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
283 }
284 
dmub_dcn20_get_inbox1_rptr(struct dmub_srv * dmub)285 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
286 {
287 	return REG_READ(DMCUB_INBOX1_RPTR);
288 }
289 
dmub_dcn20_set_inbox1_wptr(struct dmub_srv * dmub,uint32_t wptr_offset)290 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
291 {
292 	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
293 }
294 
dmub_dcn20_setup_out_mailbox(struct dmub_srv * dmub,const struct dmub_region * outbox1)295 void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,
296 			      const struct dmub_region *outbox1)
297 {
298 	/* New firmware can support CW4 for the outbox. */
299 	if (dmub_dcn20_use_cached_inbox(dmub))
300 		REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
301 	else
302 		REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000);
303 
304 	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
305 }
306 
dmub_dcn20_get_outbox1_wptr(struct dmub_srv * dmub)307 uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)
308 {
309 	/**
310 	 * outbox1 wptr register is accessed without locks (dal & dc)
311 	 * and to be called only by dmub_srv_stat_get_notification()
312 	 */
313 	return REG_READ(DMCUB_OUTBOX1_WPTR);
314 }
315 
dmub_dcn20_set_outbox1_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)316 void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
317 {
318 	/**
319 	 * outbox1 rptr register is accessed without locks (dal & dc)
320 	 * and to be called only by dmub_srv_stat_get_notification()
321 	 */
322 	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
323 }
324 
dmub_dcn20_setup_outbox0(struct dmub_srv * dmub,const struct dmub_region * outbox0)325 void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,
326 			      const struct dmub_region *outbox0)
327 {
328 	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
329 
330 	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
331 }
332 
dmub_dcn20_get_outbox0_wptr(struct dmub_srv * dmub)333 uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)
334 {
335 	return REG_READ(DMCUB_OUTBOX0_WPTR);
336 }
337 
dmub_dcn20_set_outbox0_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)338 void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
339 {
340 	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
341 }
342 
dmub_dcn20_is_hw_init(struct dmub_srv * dmub)343 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
344 {
345 	uint32_t is_hw_init;
346 
347 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
348 
349 	return is_hw_init != 0;
350 }
351 
dmub_dcn20_is_supported(struct dmub_srv * dmub)352 bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
353 {
354 	uint32_t supported = 0;
355 
356 	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
357 
358 	return supported;
359 }
360 
dmub_dcn20_set_gpint(struct dmub_srv * dmub,union dmub_gpint_data_register reg)361 void dmub_dcn20_set_gpint(struct dmub_srv *dmub,
362 			  union dmub_gpint_data_register reg)
363 {
364 	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
365 }
366 
dmub_dcn20_is_gpint_acked(struct dmub_srv * dmub,union dmub_gpint_data_register reg)367 bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
368 			       union dmub_gpint_data_register reg)
369 {
370 	union dmub_gpint_data_register test;
371 
372 	reg.bits.status = 0;
373 	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
374 
375 	return test.all == reg.all;
376 }
377 
dmub_dcn20_get_gpint_response(struct dmub_srv * dmub)378 uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
379 {
380 	return REG_READ(DMCUB_SCRATCH7);
381 }
382 
dmub_dcn20_get_fw_boot_status(struct dmub_srv * dmub)383 union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
384 {
385 	union dmub_fw_boot_status status;
386 
387 	status.all = REG_READ(DMCUB_SCRATCH0);
388 	return status;
389 }
390 
dmub_dcn20_enable_dmub_boot_options(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)391 void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
392 {
393 	union dmub_fw_boot_options boot_options = {0};
394 
395 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
396 }
397 
dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv * dmub,bool skip)398 void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
399 {
400 	union dmub_fw_boot_options boot_options;
401 	boot_options.all = REG_READ(DMCUB_SCRATCH14);
402 	boot_options.bits.skip_phy_init_panel_sequence = skip;
403 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
404 }
405 
dmub_dcn20_get_current_time(struct dmub_srv * dmub)406 uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)
407 {
408 	return REG_READ(DMCUB_TIMER_CURRENT);
409 }
410 
dmub_dcn20_get_diagnostic_data(struct dmub_srv * dmub,struct dmub_diagnostic_data * diag_data)411 void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
412 {
413 	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
414 	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
415 
416 	if (!dmub || !diag_data)
417 		return;
418 
419 	memset(diag_data, 0, sizeof(*diag_data));
420 
421 	diag_data->dmcub_version = dmub->fw_version;
422 
423 	diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
424 	diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
425 	diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
426 	diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
427 	diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
428 	diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
429 	diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
430 	diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
431 	diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
432 	diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
433 	diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
434 	diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
435 	diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
436 	diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
437 	diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
438 	diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
439 
440 	diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
441 	diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
442 	diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
443 
444 	diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
445 	diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
446 	diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
447 
448 	diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
449 	diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
450 	diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
451 
452 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
453 	diag_data->is_dmcub_enabled = is_dmub_enabled;
454 
455 	REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
456 	diag_data->is_dmcub_soft_reset = is_soft_reset;
457 
458 	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
459 	diag_data->is_dmcub_secure_reset = is_sec_reset;
460 
461 	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
462 	diag_data->is_traceport_en  = is_traceport_enabled;
463 
464 	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
465 	diag_data->is_cw0_enabled = is_cw0_enabled;
466 
467 	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
468 	diag_data->is_cw6_enabled = is_cw6_enabled;
469 }
470