1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "../display_mode_lib.h"
28 #include "../display_mode_vba.h"
29 #include "../dml_inline_defs.h"
30 #include "display_rq_dlg_calc_314.h"
31
CalculateBytePerPixelAnd256BBlockSizes(enum source_format_class SourcePixelFormat,enum dm_swizzle_mode SurfaceTiling,unsigned int * BytePerPixelY,unsigned int * BytePerPixelC,double * BytePerPixelDETY,double * BytePerPixelDETC,unsigned int * BlockHeight256BytesY,unsigned int * BlockHeight256BytesC,unsigned int * BlockWidth256BytesY,unsigned int * BlockWidth256BytesC)32 static bool CalculateBytePerPixelAnd256BBlockSizes(
33 enum source_format_class SourcePixelFormat,
34 enum dm_swizzle_mode SurfaceTiling,
35 unsigned int *BytePerPixelY,
36 unsigned int *BytePerPixelC,
37 double *BytePerPixelDETY,
38 double *BytePerPixelDETC,
39 unsigned int *BlockHeight256BytesY,
40 unsigned int *BlockHeight256BytesC,
41 unsigned int *BlockWidth256BytesY,
42 unsigned int *BlockWidth256BytesC)
43 {
44 if (SourcePixelFormat == dm_444_64) {
45 *BytePerPixelDETY = 8;
46 *BytePerPixelDETC = 0;
47 *BytePerPixelY = 8;
48 *BytePerPixelC = 0;
49 } else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) {
50 *BytePerPixelDETY = 4;
51 *BytePerPixelDETC = 0;
52 *BytePerPixelY = 4;
53 *BytePerPixelC = 0;
54 } else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) {
55 *BytePerPixelDETY = 2;
56 *BytePerPixelDETC = 0;
57 *BytePerPixelY = 2;
58 *BytePerPixelC = 0;
59 } else if (SourcePixelFormat == dm_444_8) {
60 *BytePerPixelDETY = 1;
61 *BytePerPixelDETC = 0;
62 *BytePerPixelY = 1;
63 *BytePerPixelC = 0;
64 } else if (SourcePixelFormat == dm_rgbe_alpha) {
65 *BytePerPixelDETY = 4;
66 *BytePerPixelDETC = 1;
67 *BytePerPixelY = 4;
68 *BytePerPixelC = 1;
69 } else if (SourcePixelFormat == dm_420_8) {
70 *BytePerPixelDETY = 1;
71 *BytePerPixelDETC = 2;
72 *BytePerPixelY = 1;
73 *BytePerPixelC = 2;
74 } else if (SourcePixelFormat == dm_420_12) {
75 *BytePerPixelDETY = 2;
76 *BytePerPixelDETC = 4;
77 *BytePerPixelY = 2;
78 *BytePerPixelC = 4;
79 } else {
80 *BytePerPixelDETY = 4.0 / 3;
81 *BytePerPixelDETC = 8.0 / 3;
82 *BytePerPixelY = 2;
83 *BytePerPixelC = 4;
84 }
85
86 if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 || SourcePixelFormat == dm_mono_16
87 || SourcePixelFormat == dm_mono_8 || SourcePixelFormat == dm_rgbe)) {
88 if (SurfaceTiling == dm_sw_linear)
89 *BlockHeight256BytesY = 1;
90 else if (SourcePixelFormat == dm_444_64)
91 *BlockHeight256BytesY = 4;
92 else if (SourcePixelFormat == dm_444_8)
93 *BlockHeight256BytesY = 16;
94 else
95 *BlockHeight256BytesY = 8;
96
97 *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
98 *BlockHeight256BytesC = 0;
99 *BlockWidth256BytesC = 0;
100 } else {
101 if (SurfaceTiling == dm_sw_linear) {
102 *BlockHeight256BytesY = 1;
103 *BlockHeight256BytesC = 1;
104 } else if (SourcePixelFormat == dm_rgbe_alpha) {
105 *BlockHeight256BytesY = 8;
106 *BlockHeight256BytesC = 16;
107 } else if (SourcePixelFormat == dm_420_8) {
108 *BlockHeight256BytesY = 16;
109 *BlockHeight256BytesC = 8;
110 } else {
111 *BlockHeight256BytesY = 8;
112 *BlockHeight256BytesC = 8;
113 }
114 *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
115 *BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC;
116 }
117 return true;
118 }
119
is_dual_plane(enum source_format_class source_format)120 static bool is_dual_plane(enum source_format_class source_format)
121 {
122 bool ret_val = 0;
123
124 if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha))
125 ret_val = 1;
126
127 return ret_val;
128 }
129
get_refcyc_per_delivery(struct display_mode_lib * mode_lib,double refclk_freq_in_mhz,double pclk_freq_in_mhz,unsigned int odm_combine,unsigned int recout_width,unsigned int hactive,double vratio,double hscale_pixel_rate,unsigned int delivery_width,unsigned int req_per_swath_ub)130 static double get_refcyc_per_delivery(
131 struct display_mode_lib *mode_lib,
132 double refclk_freq_in_mhz,
133 double pclk_freq_in_mhz,
134 unsigned int odm_combine,
135 unsigned int recout_width,
136 unsigned int hactive,
137 double vratio,
138 double hscale_pixel_rate,
139 unsigned int delivery_width,
140 unsigned int req_per_swath_ub)
141 {
142 double refcyc_per_delivery = 0.0;
143
144 if (vratio <= 1.0) {
145 if (odm_combine)
146 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) ((unsigned int) odm_combine * 2)
147 * dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_in_mhz / (double) req_per_swath_ub;
148 else
149 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width / pclk_freq_in_mhz / (double) req_per_swath_ub;
150 } else {
151 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width / (double) hscale_pixel_rate / (double) req_per_swath_ub;
152 }
153
154 #ifdef __DML_RQ_DLG_CALC_DEBUG__
155 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
156 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
157 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width);
158 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio);
159 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub);
160 dml_print("DML_DLG: %s: hscale_pixel_rate = %3.2f\n", __func__, hscale_pixel_rate);
161 dml_print("DML_DLG: %s: delivery_width = %d\n", __func__, delivery_width);
162 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
163 #endif
164
165 return refcyc_per_delivery;
166
167 }
168
get_blk_size_bytes(const enum source_macro_tile_size tile_size)169 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
170 {
171 if (tile_size == dm_256k_tile)
172 return (256 * 1024);
173 else if (tile_size == dm_64k_tile)
174 return (64 * 1024);
175 else
176 return (4 * 1024);
177 }
178
extract_rq_sizing_regs(struct display_mode_lib * mode_lib,display_data_rq_regs_st * rq_regs,const display_data_rq_sizing_params_st * rq_sizing)179 static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_data_rq_sizing_params_st *rq_sizing)
180 {
181 print__data_rq_sizing_params_st(mode_lib, rq_sizing);
182
183 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10;
184
185 if (rq_sizing->min_chunk_bytes == 0)
186 rq_regs->min_chunk_size = 0;
187 else
188 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1;
189
190 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10;
191 if (rq_sizing->min_meta_chunk_bytes == 0)
192 rq_regs->min_meta_chunk_size = 0;
193 else
194 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1;
195
196 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6;
197 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6;
198 }
199
extract_rq_regs(struct display_mode_lib * mode_lib,display_rq_regs_st * rq_regs,const display_rq_params_st * rq_param)200 static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st *rq_param)
201 {
202 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
203 unsigned int detile_buf_plane1_addr = 0;
204
205 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l);
206
207 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3;
208
209 if (rq_param->yuv420) {
210 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c);
211 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3;
212 }
213
214 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height);
215 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height);
216
217 // FIXME: take the max between luma, chroma chunk size?
218 // okay for now, as we are setting chunk_bytes to 8kb anyways
219 if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param->yuv420 && rq_param->sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb
220 rq_regs->drq_expansion_mode = 0;
221 } else {
222 rq_regs->drq_expansion_mode = 2;
223 }
224 rq_regs->prq_expansion_mode = 1;
225 rq_regs->mrq_expansion_mode = 1;
226 rq_regs->crq_expansion_mode = 1;
227
228 // Note: detile_buf_plane1_addr is in unit of 1KB
229 if (rq_param->yuv420) {
230 if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) {
231 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma
232 #ifdef __DML_RQ_DLG_CALC_DEBUG__
233 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr);
234 #endif
235 } else {
236 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma
237 #ifdef __DML_RQ_DLG_CALC_DEBUG__
238 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr);
239 #endif
240 }
241 }
242 rq_regs->plane1_base_address = detile_buf_plane1_addr;
243
244 #ifdef __DML_RQ_DLG_CALC_DEBUG__
245 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes);
246 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d\n", __func__, detile_buf_plane1_addr);
247 dml_print("DML_DLG: %s: plane1_base_address = %0d\n", __func__, rq_regs->plane1_base_address);
248 dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes);
249 dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes);
250 dml_print("DML_DLG: %s: rq_l.swath_height = %0d\n", __func__, rq_param->dlg.rq_l.swath_height);
251 dml_print("DML_DLG: %s: rq_c.swath_height = %0d\n", __func__, rq_param->dlg.rq_c.swath_height);
252 #endif
253 }
254
handle_det_buf_split(struct display_mode_lib * mode_lib,display_rq_params_st * rq_param,const display_pipe_source_params_st * pipe_src_param)255 static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_source_params_st *pipe_src_param)
256 {
257 unsigned int total_swath_bytes = 0;
258 unsigned int swath_bytes_l = 0;
259 unsigned int swath_bytes_c = 0;
260 unsigned int full_swath_bytes_packed_l = 0;
261 unsigned int full_swath_bytes_packed_c = 0;
262 bool req128_l = 0;
263 bool req128_c = 0;
264 bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
265 bool surf_vert = (pipe_src_param->source_scan == dm_vert);
266 unsigned int log2_swath_height_l = 0;
267 unsigned int log2_swath_height_c = 0;
268 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
269
270 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
271 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
272
273 #ifdef __DML_RQ_DLG_CALC_DEBUG__
274 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l);
275 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c);
276 #endif
277
278 if (rq_param->yuv420_10bpc) {
279 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256;
280 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256;
281 #ifdef __DML_RQ_DLG_CALC_DEBUG__
282 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l);
283 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c);
284 #endif
285 }
286
287 if (rq_param->yuv420)
288 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
289 else
290 total_swath_bytes = 2 * full_swath_bytes_packed_l;
291
292 #ifdef __DML_RQ_DLG_CALC_DEBUG__
293 dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes);
294 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes);
295 #endif
296
297 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
298 req128_l = 0;
299 req128_c = 0;
300 swath_bytes_l = full_swath_bytes_packed_l;
301 swath_bytes_c = full_swath_bytes_packed_c;
302 } else if (!rq_param->yuv420) {
303 req128_l = 1;
304 req128_c = 0;
305 swath_bytes_c = full_swath_bytes_packed_c;
306 swath_bytes_l = full_swath_bytes_packed_l / 2;
307 } else if ((double) full_swath_bytes_packed_l / (double) full_swath_bytes_packed_c < 1.5) {
308 req128_l = 0;
309 req128_c = 1;
310 swath_bytes_l = full_swath_bytes_packed_l;
311 swath_bytes_c = full_swath_bytes_packed_c / 2;
312
313 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
314
315 if (total_swath_bytes > detile_buf_size_in_bytes) {
316 req128_l = 1;
317 swath_bytes_l = full_swath_bytes_packed_l / 2;
318 }
319 } else {
320 req128_l = 1;
321 req128_c = 0;
322 swath_bytes_l = full_swath_bytes_packed_l / 2;
323 swath_bytes_c = full_swath_bytes_packed_c;
324
325 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
326
327 if (total_swath_bytes > detile_buf_size_in_bytes) {
328 req128_c = 1;
329 swath_bytes_c = full_swath_bytes_packed_c / 2;
330 }
331 }
332
333 if (rq_param->yuv420)
334 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
335 else
336 total_swath_bytes = 2 * swath_bytes_l;
337
338 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
339 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
340
341 #ifdef __DML_RQ_DLG_CALC_DEBUG__
342 dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes);
343 dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes);
344 dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes);
345 #endif
346 if (surf_linear) {
347 log2_swath_height_l = 0;
348 log2_swath_height_c = 0;
349 } else {
350 unsigned int swath_height_l;
351 unsigned int swath_height_c;
352
353 if (!surf_vert) {
354 swath_height_l = rq_param->misc.rq_l.blk256_height;
355 swath_height_c = rq_param->misc.rq_c.blk256_height;
356 } else {
357 swath_height_l = rq_param->misc.rq_l.blk256_width;
358 swath_height_c = rq_param->misc.rq_c.blk256_width;
359 }
360
361 if (swath_height_l > 0)
362 log2_swath_height_l = dml_log2(swath_height_l);
363
364 if (req128_l && log2_swath_height_l > 0)
365 log2_swath_height_l -= 1;
366
367 if (swath_height_c > 0)
368 log2_swath_height_c = dml_log2(swath_height_c);
369
370 if (req128_c && log2_swath_height_c > 0)
371 log2_swath_height_c -= 1;
372 }
373
374 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
375 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
376
377 #ifdef __DML_RQ_DLG_CALC_DEBUG__
378 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
379 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
380 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l);
381 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c);
382 dml_print("DML_DLG: %s: swath_height luma = %0d\n", __func__, rq_param->dlg.rq_l.swath_height);
383 dml_print("DML_DLG: %s: swath_height chroma = %0d\n", __func__, rq_param->dlg.rq_c.swath_height);
384 #endif
385 }
386
get_meta_and_pte_attr(struct display_mode_lib * mode_lib,display_data_rq_dlg_params_st * rq_dlg_param,display_data_rq_misc_params_st * rq_misc_param,display_data_rq_sizing_params_st * rq_sizing_param,unsigned int vp_width,unsigned int vp_height,unsigned int data_pitch,unsigned int meta_pitch,unsigned int source_format,unsigned int tiling,unsigned int macro_tile_size,unsigned int source_scan,unsigned int hostvm_enable,unsigned int is_chroma,unsigned int surface_height)387 static void get_meta_and_pte_attr(
388 struct display_mode_lib *mode_lib,
389 display_data_rq_dlg_params_st *rq_dlg_param,
390 display_data_rq_misc_params_st *rq_misc_param,
391 display_data_rq_sizing_params_st *rq_sizing_param,
392 unsigned int vp_width,
393 unsigned int vp_height,
394 unsigned int data_pitch,
395 unsigned int meta_pitch,
396 unsigned int source_format,
397 unsigned int tiling,
398 unsigned int macro_tile_size,
399 unsigned int source_scan,
400 unsigned int hostvm_enable,
401 unsigned int is_chroma,
402 unsigned int surface_height)
403 {
404 bool surf_linear = (tiling == dm_sw_linear);
405 bool surf_vert = (source_scan == dm_vert);
406
407 unsigned int bytes_per_element;
408 unsigned int bytes_per_element_y;
409 unsigned int bytes_per_element_c;
410
411 unsigned int blk256_width = 0;
412 unsigned int blk256_height = 0;
413
414 unsigned int blk256_width_y = 0;
415 unsigned int blk256_height_y = 0;
416 unsigned int blk256_width_c = 0;
417 unsigned int blk256_height_c = 0;
418 unsigned int log2_bytes_per_element;
419 unsigned int log2_blk256_width;
420 unsigned int log2_blk256_height;
421 unsigned int blk_bytes;
422 unsigned int log2_blk_bytes;
423 unsigned int log2_blk_height;
424 unsigned int log2_blk_width;
425 unsigned int log2_meta_req_bytes;
426 unsigned int log2_meta_req_height;
427 unsigned int log2_meta_req_width;
428 unsigned int meta_req_width;
429 unsigned int meta_req_height;
430 unsigned int log2_meta_row_height;
431 unsigned int meta_row_width_ub;
432 unsigned int log2_meta_chunk_bytes;
433 unsigned int log2_meta_chunk_height;
434
435 //full sized meta chunk width in unit of data elements
436 unsigned int log2_meta_chunk_width;
437 unsigned int log2_min_meta_chunk_bytes;
438 unsigned int min_meta_chunk_width;
439 unsigned int meta_chunk_width;
440 unsigned int meta_chunk_per_row_int;
441 unsigned int meta_row_remainder;
442 unsigned int meta_chunk_threshold;
443 unsigned int meta_blk_height;
444 unsigned int meta_surface_bytes;
445 unsigned int vmpg_bytes;
446 unsigned int meta_pte_req_per_frame_ub;
447 unsigned int meta_pte_bytes_per_frame_ub;
448 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes);
449 const bool dual_plane_en = is_dual_plane((enum source_format_class) (source_format));
450 const unsigned int dpte_buf_in_pte_reqs =
451 dual_plane_en ? (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma
452 + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma);
453
454 unsigned int log2_vmpg_height = 0;
455 unsigned int log2_vmpg_width = 0;
456 unsigned int log2_dpte_req_height_ptes = 0;
457 unsigned int log2_dpte_req_height = 0;
458 unsigned int log2_dpte_req_width = 0;
459 unsigned int log2_dpte_row_height_linear = 0;
460 unsigned int log2_dpte_row_height = 0;
461 unsigned int log2_dpte_group_width = 0;
462 unsigned int dpte_row_width_ub = 0;
463 unsigned int dpte_req_height = 0;
464 unsigned int dpte_req_width = 0;
465 unsigned int dpte_group_width = 0;
466 unsigned int log2_dpte_group_bytes = 0;
467 unsigned int log2_dpte_group_length = 0;
468 double byte_per_pixel_det_y;
469 double byte_per_pixel_det_c;
470
471 CalculateBytePerPixelAnd256BBlockSizes(
472 (enum source_format_class) (source_format),
473 (enum dm_swizzle_mode) (tiling),
474 &bytes_per_element_y,
475 &bytes_per_element_c,
476 &byte_per_pixel_det_y,
477 &byte_per_pixel_det_c,
478 &blk256_height_y,
479 &blk256_height_c,
480 &blk256_width_y,
481 &blk256_width_c);
482
483 if (!is_chroma) {
484 blk256_width = blk256_width_y;
485 blk256_height = blk256_height_y;
486 bytes_per_element = bytes_per_element_y;
487 } else {
488 blk256_width = blk256_width_c;
489 blk256_height = blk256_height_c;
490 bytes_per_element = bytes_per_element_c;
491 }
492
493 log2_bytes_per_element = dml_log2(bytes_per_element);
494
495 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear);
496 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert);
497 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width);
498 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height);
499
500 log2_blk256_width = dml_log2((double) blk256_width);
501 log2_blk256_height = dml_log2((double) blk256_height);
502 blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
503 log2_blk_bytes = dml_log2((double) blk_bytes);
504 log2_blk_height = 0;
505 log2_blk_width = 0;
506
507 // remember log rule
508 // "+" in log is multiply
509 // "-" in log is divide
510 // "/2" is like square root
511 // blk is vertical biased
512 if (tiling != dm_sw_linear)
513 log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
514 else
515 log2_blk_height = 0; // blk height of 1
516
517 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
518
519 if (!surf_vert) {
520 unsigned int temp;
521
522 temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width;
523 if (data_pitch < blk256_width) {
524 dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width);
525 } else {
526 if (temp > data_pitch) {
527 if (data_pitch >= vp_width)
528 temp = data_pitch;
529 else
530 dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width);
531 }
532 }
533 rq_dlg_param->swath_width_ub = temp;
534 rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width;
535 } else {
536 unsigned int temp;
537
538 temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height;
539 if (surface_height < blk256_height) {
540 dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height);
541 } else {
542 if (temp > surface_height) {
543 if (surface_height >= vp_height)
544 temp = surface_height;
545 else
546 dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height);
547 }
548 }
549 rq_dlg_param->swath_width_ub = temp;
550 rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height;
551 }
552
553 if (!surf_vert)
554 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height * bytes_per_element;
555 else
556 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width * bytes_per_element;
557
558 rq_misc_param->blk256_height = blk256_height;
559 rq_misc_param->blk256_width = blk256_width;
560
561 // -------
562 // meta
563 // -------
564 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
565
566 // each 64b meta request for dcn is 8x8 meta elements and
567 // a meta element covers one 256b block of the data surface.
568 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
569 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height;
570 meta_req_width = 1 << log2_meta_req_width;
571 meta_req_height = 1 << log2_meta_req_height;
572 log2_meta_row_height = 0;
573 meta_row_width_ub = 0;
574
575 // the dimensions of a meta row are meta_row_width x meta_row_height in elements.
576 // calculate upper bound of the meta_row_width
577 if (!surf_vert) {
578 log2_meta_row_height = log2_meta_req_height;
579 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width;
580 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
581 } else {
582 log2_meta_row_height = log2_meta_req_width;
583 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height;
584 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
585 }
586 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
587
588 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
589
590 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
591 log2_meta_chunk_height = log2_meta_row_height;
592
593 //full sized meta chunk width in unit of data elements
594 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height;
595 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
596 min_meta_chunk_width = 1 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height);
597 meta_chunk_width = 1 << log2_meta_chunk_width;
598 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
599 meta_row_remainder = meta_row_width_ub % meta_chunk_width;
600 meta_chunk_threshold = 0;
601 meta_blk_height = blk256_height * 64;
602 meta_surface_bytes = meta_pitch * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) * bytes_per_element / 256;
603 vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes;
604 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 8 * vmpg_bytes, 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
605 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
606 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
607
608 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height);
609 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes);
610 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", __func__, meta_pte_req_per_frame_ub);
611 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", __func__, meta_pte_bytes_per_frame_ub);
612
613 if (!surf_vert)
614 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
615 else
616 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
617
618 if (meta_row_remainder <= meta_chunk_threshold)
619 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
620 else
621 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
622
623 // ------
624 // dpte
625 // ------
626 if (surf_linear)
627 log2_vmpg_height = 0; // one line high
628 else
629 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
630
631 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
632
633 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
634 if (surf_linear) { //one 64B PTE request returns 8 PTEs
635 log2_dpte_req_height_ptes = 0;
636 log2_dpte_req_width = log2_vmpg_width + 3;
637 log2_dpte_req_height = 0;
638 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
639 //one 64B req gives 8x1 PTEs for 4KB tile
640 log2_dpte_req_height_ptes = 0;
641 log2_dpte_req_width = log2_blk_width + 3;
642 log2_dpte_req_height = log2_blk_height + 0;
643 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
644 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
645 log2_dpte_req_height_ptes = 4;
646 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
647 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
648 } else { //64KB page size and must 64KB tile block
649 //one 64B req gives 8x1 PTEs for 64KB tile
650 log2_dpte_req_height_ptes = 0;
651 log2_dpte_req_width = log2_blk_width + 3;
652 log2_dpte_req_height = log2_blk_height + 0;
653 }
654
655 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
656 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
657 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
658 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
659 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
660 dpte_req_height = 1 << log2_dpte_req_height;
661 dpte_req_width = 1 << log2_dpte_req_width;
662
663 // calculate pitch dpte row buffer can hold
664 // round the result down to a power of two.
665 if (surf_linear) {
666 unsigned int dpte_row_height;
667
668 log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1);
669
670 dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma);
671 dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs);
672 dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear);
673
674 ASSERT(log2_dpte_row_height_linear >= 3);
675
676 if (log2_dpte_row_height_linear > 7)
677 log2_dpte_row_height_linear = 7;
678
679 log2_dpte_row_height = log2_dpte_row_height_linear;
680 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
681 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
682 dpte_row_height = 1 << log2_dpte_row_height;
683 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, dpte_req_width, 1) + dpte_req_width;
684 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
685 } else {
686 // the upper bound of the dpte_row_width without dependency on viewport position follows.
687 // for tiled mode, row height is the same as req height and row store up to vp size upper bound
688 if (!surf_vert) {
689 log2_dpte_row_height = log2_dpte_req_height;
690 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) + dpte_req_width;
691 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
692 } else {
693 log2_dpte_row_height = (log2_blk_width < log2_dpte_req_width) ? log2_blk_width : log2_dpte_req_width;
694 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) + dpte_req_height;
695 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
696 }
697 }
698 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
699 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
700 else
701 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
702
703 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
704
705 // the dpte_group_bytes is reduced for the specific case of vertical
706 // access of a tile surface that has dpte request of 8x1 ptes.
707 if (hostvm_enable)
708 rq_sizing_param->dpte_group_bytes = 512;
709 else {
710 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
711 rq_sizing_param->dpte_group_bytes = 512;
712 else
713 rq_sizing_param->dpte_group_bytes = 2048;
714 }
715
716 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
717 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
718 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
719
720 // full sized data pte group width in elements
721 if (!surf_vert)
722 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
723 else
724 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
725
726 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
727 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
728 log2_dpte_group_width = log2_dpte_group_width - 1;
729
730 dpte_group_width = 1 << log2_dpte_group_width;
731
732 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
733 // the upper bound for the dpte groups per row is as follows.
734 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1);
735 }
736
get_surf_rq_param(struct display_mode_lib * mode_lib,display_data_rq_sizing_params_st * rq_sizing_param,display_data_rq_dlg_params_st * rq_dlg_param,display_data_rq_misc_params_st * rq_misc_param,const display_pipe_params_st * pipe_param,bool is_chroma,bool is_alpha)737 static void get_surf_rq_param(
738 struct display_mode_lib *mode_lib,
739 display_data_rq_sizing_params_st *rq_sizing_param,
740 display_data_rq_dlg_params_st *rq_dlg_param,
741 display_data_rq_misc_params_st *rq_misc_param,
742 const display_pipe_params_st *pipe_param,
743 bool is_chroma,
744 bool is_alpha)
745 {
746 bool mode_422 = 0;
747 unsigned int vp_width = 0;
748 unsigned int vp_height = 0;
749 unsigned int data_pitch = 0;
750 unsigned int meta_pitch = 0;
751 unsigned int surface_height = 0;
752 unsigned int ppe = mode_422 ? 2 : 1;
753
754 // FIXME check if ppe apply for both luma and chroma in 422 case
755 if (is_chroma | is_alpha) {
756 vp_width = pipe_param->src.viewport_width_c / ppe;
757 vp_height = pipe_param->src.viewport_height_c;
758 data_pitch = pipe_param->src.data_pitch_c;
759 meta_pitch = pipe_param->src.meta_pitch_c;
760 surface_height = pipe_param->src.surface_height_y / 2.0;
761 } else {
762 vp_width = pipe_param->src.viewport_width / ppe;
763 vp_height = pipe_param->src.viewport_height;
764 data_pitch = pipe_param->src.data_pitch;
765 meta_pitch = pipe_param->src.meta_pitch;
766 surface_height = pipe_param->src.surface_height_y;
767 }
768
769 if (pipe_param->dest.odm_combine) {
770 unsigned int access_dir;
771 unsigned int full_src_vp_width;
772 unsigned int hactive_odm;
773 unsigned int src_hactive_odm;
774
775 access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
776 hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine * 2);
777 if (is_chroma) {
778 full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width;
779 src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm;
780 } else {
781 full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width;
782 src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm;
783 }
784
785 if (access_dir == 0) {
786 vp_width = dml_min(full_src_vp_width, src_hactive_odm);
787 dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width);
788 } else {
789 vp_height = dml_min(full_src_vp_width, src_hactive_odm);
790 dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height);
791
792 }
793 dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width);
794 dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm);
795 dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm);
796 }
797
798 rq_sizing_param->chunk_bytes = 8192;
799
800 if (is_alpha)
801 rq_sizing_param->chunk_bytes = 4096;
802
803 if (rq_sizing_param->chunk_bytes == 64 * 1024)
804 rq_sizing_param->min_chunk_bytes = 0;
805 else
806 rq_sizing_param->min_chunk_bytes = 1024;
807
808 rq_sizing_param->meta_chunk_bytes = 2048;
809 rq_sizing_param->min_meta_chunk_bytes = 256;
810
811 if (pipe_param->src.hostvm)
812 rq_sizing_param->mpte_group_bytes = 512;
813 else
814 rq_sizing_param->mpte_group_bytes = 2048;
815
816 get_meta_and_pte_attr(
817 mode_lib,
818 rq_dlg_param,
819 rq_misc_param,
820 rq_sizing_param,
821 vp_width,
822 vp_height,
823 data_pitch,
824 meta_pitch,
825 pipe_param->src.source_format,
826 pipe_param->src.sw_mode,
827 pipe_param->src.macro_tile_size,
828 pipe_param->src.source_scan,
829 pipe_param->src.hostvm,
830 is_chroma,
831 surface_height);
832 }
833
dml_rq_dlg_get_rq_params(struct display_mode_lib * mode_lib,display_rq_params_st * rq_param,const display_pipe_params_st * pipe_param)834 static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_params_st *pipe_param)
835 {
836 // get param for luma surface
837 rq_param->yuv420 = pipe_param->src.source_format == dm_420_8 || pipe_param->src.source_format == dm_420_10 || pipe_param->src.source_format == dm_rgbe_alpha
838 || pipe_param->src.source_format == dm_420_12;
839
840 rq_param->yuv420_10bpc = pipe_param->src.source_format == dm_420_10;
841
842 rq_param->rgbe_alpha = (pipe_param->src.source_format == dm_rgbe_alpha) ? 1 : 0;
843
844 get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_l), &(rq_param->dlg.rq_l), &(rq_param->misc.rq_l), pipe_param, 0, 0);
845
846 if (is_dual_plane((enum source_format_class) (pipe_param->src.source_format))) {
847 // get param for chroma surface
848 get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_c), &(rq_param->dlg.rq_c), &(rq_param->misc.rq_c), pipe_param, 1, rq_param->rgbe_alpha);
849 }
850
851 // calculate how to split the det buffer space between luma and chroma
852 handle_det_buf_split(mode_lib, rq_param, &pipe_param->src);
853 print__rq_params_st(mode_lib, rq_param);
854 }
855
dml314_rq_dlg_get_rq_reg(struct display_mode_lib * mode_lib,display_rq_regs_st * rq_regs,const display_pipe_params_st * pipe_param)856 void dml314_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st *pipe_param)
857 {
858 display_rq_params_st rq_param = {0};
859
860 memset(rq_regs, 0, sizeof(*rq_regs));
861 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);
862 extract_rq_regs(mode_lib, rq_regs, &rq_param);
863
864 print__rq_regs_st(mode_lib, rq_regs);
865 }
866
calculate_ttu_cursor(struct display_mode_lib * mode_lib,double * refcyc_per_req_delivery_pre_cur,double * refcyc_per_req_delivery_cur,double refclk_freq_in_mhz,double ref_freq_to_pix_freq,double hscale_pixel_rate_l,double hscl_ratio,double vratio_pre_l,double vratio_l,unsigned int cur_width,enum cursor_bpp cur_bpp)867 static void calculate_ttu_cursor(
868 struct display_mode_lib *mode_lib,
869 double *refcyc_per_req_delivery_pre_cur,
870 double *refcyc_per_req_delivery_cur,
871 double refclk_freq_in_mhz,
872 double ref_freq_to_pix_freq,
873 double hscale_pixel_rate_l,
874 double hscl_ratio,
875 double vratio_pre_l,
876 double vratio_l,
877 unsigned int cur_width,
878 enum cursor_bpp cur_bpp)
879 {
880 unsigned int cur_src_width = cur_width;
881 unsigned int cur_req_size = 0;
882 unsigned int cur_req_width = 0;
883 double cur_width_ub = 0.0;
884 double cur_req_per_width = 0.0;
885 double hactive_cur = 0.0;
886
887 ASSERT(cur_src_width <= 256);
888
889 *refcyc_per_req_delivery_pre_cur = 0.0;
890 *refcyc_per_req_delivery_cur = 0.0;
891 if (cur_src_width > 0) {
892 unsigned int cur_bit_per_pixel = 0;
893
894 if (cur_bpp == dm_cur_2bit) {
895 cur_req_size = 64; // byte
896 cur_bit_per_pixel = 2;
897 } else { // 32bit
898 cur_bit_per_pixel = 32;
899 if (cur_src_width >= 1 && cur_src_width <= 16)
900 cur_req_size = 64;
901 else if (cur_src_width >= 17 && cur_src_width <= 31)
902 cur_req_size = 128;
903 else
904 cur_req_size = 256;
905 }
906
907 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
908 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width;
909 cur_req_per_width = cur_width_ub / (double) cur_req_width;
910 hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
911
912 if (vratio_pre_l <= 1.0)
913 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width;
914 else
915 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width;
916
917 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
918
919 if (vratio_l <= 1.0)
920 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width;
921 else
922 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width;
923
924 dml_print("DML_DLG: %s: cur_req_width = %d\n", __func__, cur_req_width);
925 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", __func__, cur_width_ub);
926 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", __func__, cur_req_per_width);
927 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", __func__, hactive_cur);
928 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", __func__, *refcyc_per_req_delivery_pre_cur);
929 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", __func__, *refcyc_per_req_delivery_cur);
930
931 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
932 }
933 }
934
935 // Note: currently taken in as is.
936 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
dml_rq_dlg_get_dlg_params(struct display_mode_lib * mode_lib,const display_e2e_pipe_params_st * e2e_pipe_param,const unsigned int num_pipes,const unsigned int pipe_idx,display_dlg_regs_st * disp_dlg_regs,display_ttu_regs_st * disp_ttu_regs,const display_rq_dlg_params_st * rq_dlg_param,const display_dlg_sys_params_st * dlg_sys_param,const bool cstate_en,const bool pstate_en,const bool vm_en,const bool ignore_viewport_pos,const bool immediate_flip_support)937 static void dml_rq_dlg_get_dlg_params(
938 struct display_mode_lib *mode_lib,
939 const display_e2e_pipe_params_st *e2e_pipe_param,
940 const unsigned int num_pipes,
941 const unsigned int pipe_idx,
942 display_dlg_regs_st *disp_dlg_regs,
943 display_ttu_regs_st *disp_ttu_regs,
944 const display_rq_dlg_params_st *rq_dlg_param,
945 const display_dlg_sys_params_st *dlg_sys_param,
946 const bool cstate_en,
947 const bool pstate_en,
948 const bool vm_en,
949 const bool ignore_viewport_pos,
950 const bool immediate_flip_support)
951 {
952 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
953 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
954 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
955 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
956 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
957 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
958 unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
959
960 // -------------------------
961 // Section 1.15.2.1: OTG dependent Params
962 // -------------------------
963 // Timing
964 unsigned int htotal = dst->htotal;
965 unsigned int hblank_end = dst->hblank_end;
966 unsigned int vblank_start = dst->vblank_start;
967 unsigned int vblank_end = dst->vblank_end;
968
969 double dppclk_freq_in_mhz = clks->dppclk_mhz;
970 double refclk_freq_in_mhz = clks->refclk_mhz;
971 double pclk_freq_in_mhz = dst->pixel_rate_mhz;
972 bool interlaced = dst->interlaced;
973 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
974 double min_ttu_vblank;
975 unsigned int dlg_vblank_start;
976 bool dual_plane;
977 bool mode_422;
978 unsigned int access_dir;
979 unsigned int vp_height_l;
980 unsigned int vp_width_l;
981 unsigned int vp_height_c;
982 unsigned int vp_width_c;
983
984 // Scaling
985 unsigned int htaps_l;
986 unsigned int htaps_c;
987 double hratio_l;
988 double hratio_c;
989 double vratio_l;
990 double vratio_c;
991 bool scl_enable;
992
993 unsigned int swath_width_ub_l;
994 unsigned int dpte_groups_per_row_ub_l;
995 unsigned int swath_width_ub_c;
996 unsigned int dpte_groups_per_row_ub_c;
997
998 unsigned int meta_chunks_per_row_ub_l;
999 unsigned int meta_chunks_per_row_ub_c;
1000 unsigned int vupdate_offset;
1001 unsigned int vupdate_width;
1002 unsigned int vready_offset;
1003
1004 unsigned int dppclk_delay_subtotal;
1005 unsigned int dispclk_delay_subtotal;
1006
1007 unsigned int vstartup_start;
1008 unsigned int dst_x_after_scaler;
1009 unsigned int dst_y_after_scaler;
1010 double dst_y_prefetch;
1011 double dst_y_per_vm_vblank;
1012 double dst_y_per_row_vblank;
1013 double dst_y_per_vm_flip;
1014 double dst_y_per_row_flip;
1015 double max_dst_y_per_vm_vblank;
1016 double max_dst_y_per_row_vblank;
1017 double vratio_pre_l;
1018 double vratio_pre_c;
1019 unsigned int req_per_swath_ub_l;
1020 unsigned int req_per_swath_ub_c;
1021 unsigned int meta_row_height_l;
1022 unsigned int meta_row_height_c;
1023 unsigned int swath_width_pixels_ub_l;
1024 unsigned int swath_width_pixels_ub_c;
1025 unsigned int scaler_rec_in_width_l;
1026 unsigned int scaler_rec_in_width_c;
1027 unsigned int dpte_row_height_l;
1028 unsigned int dpte_row_height_c;
1029 double hscale_pixel_rate_l;
1030 double hscale_pixel_rate_c;
1031 double min_hratio_fact_l;
1032 double min_hratio_fact_c;
1033 double refcyc_per_line_delivery_pre_l;
1034 double refcyc_per_line_delivery_pre_c;
1035 double refcyc_per_line_delivery_l;
1036 double refcyc_per_line_delivery_c;
1037
1038 double refcyc_per_req_delivery_pre_l;
1039 double refcyc_per_req_delivery_pre_c;
1040 double refcyc_per_req_delivery_l;
1041 double refcyc_per_req_delivery_c;
1042
1043 unsigned int full_recout_width;
1044 double refcyc_per_req_delivery_pre_cur0;
1045 double refcyc_per_req_delivery_cur0;
1046 double refcyc_per_req_delivery_pre_cur1;
1047 double refcyc_per_req_delivery_cur1;
1048 unsigned int vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
1049 unsigned int vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1050
1051 float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1052 float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1053
1054 float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1055 float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1056 int blank_lines = 0;
1057
1058 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
1059 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
1060
1061 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
1062 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
1063 dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en);
1064 dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos);
1065 dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support);
1066
1067 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz);
1068 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
1069 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
1070 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0);
1071
1072 disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
1073 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
1074 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
1075
1076 //set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
1077 min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1078
1079 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
1080 disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
1081 disp_dlg_regs->optimized_min_dst_y_next_start_us = 0;
1082 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
1083 blank_lines = (dst->vblank_end + dst->vtotal_min - dst->vblank_start - dst->vstartup_start - 1);
1084 if (blank_lines < 0)
1085 blank_lines = 0;
1086 if (blank_lines != 0) {
1087 disp_dlg_regs->optimized_min_dst_y_next_start = vba__min_dst_y_next_start;
1088 disp_dlg_regs->optimized_min_dst_y_next_start_us = (disp_dlg_regs->optimized_min_dst_y_next_start * dst->hactive) / (unsigned int) dst->pixel_rate_mhz;
1089 disp_dlg_regs->min_dst_y_next_start = disp_dlg_regs->optimized_min_dst_y_next_start;
1090 }
1091 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
1092
1093 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank);
1094 dml_print("DML_DLG: %s: min_dst_y_next_start = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start);
1095 dml_print("DML_DLG: %s: dlg_vblank_start = 0x%0x\n", __func__, dlg_vblank_start);
1096 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq);
1097 dml_print("DML_DLG: %s: vba__min_dst_y_next_start = 0x%0x\n", __func__, vba__min_dst_y_next_start);
1098
1099 //old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start);
1100
1101 // -------------------------
1102 // Section 1.15.2.2: Prefetch, Active and TTU
1103 // -------------------------
1104 // Prefetch Calc
1105 // Source
1106 dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
1107 mode_422 = 0;
1108 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
1109 vp_height_l = src->viewport_height;
1110 vp_width_l = src->viewport_width;
1111 vp_height_c = src->viewport_height_c;
1112 vp_width_c = src->viewport_width_c;
1113
1114 // Scaling
1115 htaps_l = taps->htaps;
1116 htaps_c = taps->htaps_c;
1117 hratio_l = scl->hscl_ratio;
1118 hratio_c = scl->hscl_ratio_c;
1119 vratio_l = scl->vscl_ratio;
1120 vratio_c = scl->vscl_ratio_c;
1121 scl_enable = scl->scl_enable;
1122
1123 swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub;
1124 dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub;
1125 swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub;
1126 dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub;
1127
1128 meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub;
1129 meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub;
1130 vupdate_offset = dst->vupdate_offset;
1131 vupdate_width = dst->vupdate_width;
1132 vready_offset = dst->vready_offset;
1133
1134 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
1135 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
1136
1137 if (scl_enable)
1138 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
1139 else
1140 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
1141
1142 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
1143
1144 if (dout->dsc_enable) {
1145 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
1146
1147 dispclk_delay_subtotal += dsc_delay;
1148 }
1149
1150 vstartup_start = dst->vstartup_start;
1151 if (interlaced) {
1152 if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0)
1153 disp_dlg_regs->vready_after_vcount0 = 1;
1154 else
1155 disp_dlg_regs->vready_after_vcount0 = 0;
1156 } else {
1157 if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end)
1158 disp_dlg_regs->vready_after_vcount0 = 1;
1159 else
1160 disp_dlg_regs->vready_after_vcount0 = 0;
1161 }
1162
1163 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0);
1164 dml_print("DML_DLG: %s: vba__vready_after_vcount0 = %d\n", __func__, vba__vready_after_vcount0);
1165 //old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0);
1166
1167 if (interlaced)
1168 vstartup_start = vstartup_start / 2;
1169
1170 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1171 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1172
1173 // do some adjustment on the dst_after scaler to account for odm combine mode
1174 dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler);
1175 dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", __func__, dst_y_after_scaler);
1176
1177 // need to figure out which side of odm combine we're in
1178 if (dst->odm_combine) {
1179 // figure out which pipes go together
1180 bool visited[DC__NUM_PIPES__MAX];
1181 unsigned int i, j, k;
1182
1183 for (k = 0; k < num_pipes; ++k) {
1184 visited[k] = false;
1185 pipe_index_in_combine[k] = 0;
1186 }
1187
1188 for (i = 0; i < num_pipes; i++) {
1189 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
1190
1191 unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
1192 unsigned int grp_idx = 0;
1193
1194 for (j = i; j < num_pipes; j++) {
1195 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {
1196 pipe_index_in_combine[j] = grp_idx;
1197 dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx);
1198 grp_idx++;
1199 visited[j] = true;
1200 }
1201 }
1202 }
1203 }
1204
1205 }
1206
1207 if (dst->odm_combine == dm_odm_combine_mode_disabled) {
1208 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq);
1209 } else {
1210 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4
1211 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx];
1212
1213 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq);
1214 } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
1215
1216 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal);
1217 dml_print("DML_DLG: %s: dst_x_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_x_after_scaler);
1218 dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler);
1219
1220 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1221 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1222 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1223 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1224 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1225
1226 max_dst_y_per_vm_vblank = 32.0; //U5.2
1227 max_dst_y_per_row_vblank = 16.0; //U4.2
1228
1229 // magic!
1230 if (htotal <= 75) {
1231 max_dst_y_per_vm_vblank = 100.0;
1232 max_dst_y_per_row_vblank = 100.0;
1233 }
1234
1235 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
1236 dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip);
1237 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip);
1238 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank);
1239 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
1240
1241 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
1242
1243 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
1244
1245 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1246 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1247
1248 dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l);
1249 dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c);
1250
1251 // Active
1252 req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub;
1253 req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub;
1254 meta_row_height_l = rq_dlg_param->rq_l.meta_row_height;
1255 meta_row_height_c = rq_dlg_param->rq_c.meta_row_height;
1256 swath_width_pixels_ub_l = 0;
1257 swath_width_pixels_ub_c = 0;
1258 scaler_rec_in_width_l = 0;
1259 scaler_rec_in_width_c = 0;
1260 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height;
1261 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height;
1262
1263 if (mode_422) {
1264 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element
1265 swath_width_pixels_ub_c = swath_width_ub_c * 2;
1266 } else {
1267 swath_width_pixels_ub_l = swath_width_ub_l * 1;
1268 swath_width_pixels_ub_c = swath_width_ub_c * 1;
1269 }
1270
1271 hscale_pixel_rate_l = 0.;
1272 hscale_pixel_rate_c = 0.;
1273 min_hratio_fact_l = 1.0;
1274 min_hratio_fact_c = 1.0;
1275
1276 if (hratio_l <= 1)
1277 min_hratio_fact_l = 2.0;
1278 else if (htaps_l <= 6) {
1279 if ((hratio_l * 2.0) > 4.0)
1280 min_hratio_fact_l = 4.0;
1281 else
1282 min_hratio_fact_l = hratio_l * 2.0;
1283 } else {
1284 if (hratio_l > 4.0)
1285 min_hratio_fact_l = 4.0;
1286 else
1287 min_hratio_fact_l = hratio_l;
1288 }
1289
1290 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
1291
1292 dml_print("DML_DLG: %s: hratio_l = %3.2f\n", __func__, hratio_l);
1293 dml_print("DML_DLG: %s: min_hratio_fact_l = %3.2f\n", __func__, min_hratio_fact_l);
1294 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l);
1295
1296 if (hratio_c <= 1)
1297 min_hratio_fact_c = 2.0;
1298 else if (htaps_c <= 6) {
1299 if ((hratio_c * 2.0) > 4.0)
1300 min_hratio_fact_c = 4.0;
1301 else
1302 min_hratio_fact_c = hratio_c * 2.0;
1303 } else {
1304 if (hratio_c > 4.0)
1305 min_hratio_fact_c = 4.0;
1306 else
1307 min_hratio_fact_c = hratio_c;
1308 }
1309
1310 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
1311
1312 refcyc_per_line_delivery_pre_l = 0.;
1313 refcyc_per_line_delivery_pre_c = 0.;
1314 refcyc_per_line_delivery_l = 0.;
1315 refcyc_per_line_delivery_c = 0.;
1316
1317 refcyc_per_req_delivery_pre_l = 0.;
1318 refcyc_per_req_delivery_pre_c = 0.;
1319 refcyc_per_req_delivery_l = 0.;
1320 refcyc_per_req_delivery_c = 0.;
1321
1322 full_recout_width = 0;
1323 // In ODM
1324 if (src->is_hsplit) {
1325 // This "hack" is only allowed (and valid) for MPC combine. In ODM
1326 // combine, you MUST specify the full_recout_width...according to Oswin
1327 if (dst->full_recout_width == 0 && !dst->odm_combine) {
1328 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", __func__);
1329 full_recout_width = dst->recout_width * 2; // assume half split for dcn1
1330 } else
1331 full_recout_width = dst->full_recout_width;
1332 } else
1333 full_recout_width = dst->recout_width;
1334
1335 // As of DCN2, mpc_combine and odm_combine are mutually exclusive
1336 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
1337 mode_lib,
1338 refclk_freq_in_mhz,
1339 pclk_freq_in_mhz,
1340 dst->odm_combine,
1341 full_recout_width,
1342 dst->hactive,
1343 vratio_pre_l,
1344 hscale_pixel_rate_l,
1345 swath_width_pixels_ub_l,
1346 1); // per line
1347
1348 refcyc_per_line_delivery_l = get_refcyc_per_delivery(
1349 mode_lib,
1350 refclk_freq_in_mhz,
1351 pclk_freq_in_mhz,
1352 dst->odm_combine,
1353 full_recout_width,
1354 dst->hactive,
1355 vratio_l,
1356 hscale_pixel_rate_l,
1357 swath_width_pixels_ub_l,
1358 1); // per line
1359
1360 dml_print("DML_DLG: %s: full_recout_width = %d\n", __func__, full_recout_width);
1361 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l);
1362 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l);
1363 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, refcyc_per_line_delivery_l);
1364 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_l);
1365 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_l);
1366
1367 //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_l", refcyc_per_line_delivery_pre_l, vba__refcyc_per_line_delivery_pre_l);
1368 //old_impl_vs_vba_impl("refcyc_per_line_delivery_l", refcyc_per_line_delivery_l, vba__refcyc_per_line_delivery_l);
1369
1370 if (dual_plane) {
1371 float vba__refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1372 float vba__refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1373
1374 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
1375 mode_lib,
1376 refclk_freq_in_mhz,
1377 pclk_freq_in_mhz,
1378 dst->odm_combine,
1379 full_recout_width,
1380 dst->hactive,
1381 vratio_pre_c,
1382 hscale_pixel_rate_c,
1383 swath_width_pixels_ub_c,
1384 1); // per line
1385
1386 refcyc_per_line_delivery_c = get_refcyc_per_delivery(
1387 mode_lib,
1388 refclk_freq_in_mhz,
1389 pclk_freq_in_mhz,
1390 dst->odm_combine,
1391 full_recout_width,
1392 dst->hactive,
1393 vratio_c,
1394 hscale_pixel_rate_c,
1395 swath_width_pixels_ub_c,
1396 1); // per line
1397
1398 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, refcyc_per_line_delivery_pre_c);
1399 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", __func__, refcyc_per_line_delivery_c);
1400 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_c);
1401 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_c);
1402
1403 //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_c", refcyc_per_line_delivery_pre_c, vba__refcyc_per_line_delivery_pre_c);
1404 //old_impl_vs_vba_impl("refcyc_per_line_delivery_c", refcyc_per_line_delivery_c, vba__refcyc_per_line_delivery_c);
1405 }
1406
1407 if (src->dynamic_metadata_enable && src->gpuvm)
1408 disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1409
1410 disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1411
1412 // TTU - Luma / Chroma
1413 if (access_dir) { // vertical access
1414 scaler_rec_in_width_l = vp_height_l;
1415 scaler_rec_in_width_c = vp_height_c;
1416 } else {
1417 scaler_rec_in_width_l = vp_width_l;
1418 scaler_rec_in_width_c = vp_width_c;
1419 }
1420
1421 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
1422 mode_lib,
1423 refclk_freq_in_mhz,
1424 pclk_freq_in_mhz,
1425 dst->odm_combine,
1426 full_recout_width,
1427 dst->hactive,
1428 vratio_pre_l,
1429 hscale_pixel_rate_l,
1430 scaler_rec_in_width_l,
1431 req_per_swath_ub_l); // per req
1432
1433 refcyc_per_req_delivery_l = get_refcyc_per_delivery(
1434 mode_lib,
1435 refclk_freq_in_mhz,
1436 pclk_freq_in_mhz,
1437 dst->odm_combine,
1438 full_recout_width,
1439 dst->hactive,
1440 vratio_l,
1441 hscale_pixel_rate_l,
1442 scaler_rec_in_width_l,
1443 req_per_swath_ub_l); // per req
1444
1445 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l);
1446 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l);
1447 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_l);
1448 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_l);
1449
1450 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_l", refcyc_per_req_delivery_pre_l, vba__refcyc_per_req_delivery_pre_l);
1451 //old_impl_vs_vba_impl("refcyc_per_req_delivery_l", refcyc_per_req_delivery_l, vba__refcyc_per_req_delivery_l);
1452
1453 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
1454
1455 if (dual_plane) {
1456 float vba__refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1457 float vba__refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1458
1459 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
1460 mode_lib,
1461 refclk_freq_in_mhz,
1462 pclk_freq_in_mhz,
1463 dst->odm_combine,
1464 full_recout_width,
1465 dst->hactive,
1466 vratio_pre_c,
1467 hscale_pixel_rate_c,
1468 scaler_rec_in_width_c,
1469 req_per_swath_ub_c); // per req
1470 refcyc_per_req_delivery_c = get_refcyc_per_delivery(
1471 mode_lib,
1472 refclk_freq_in_mhz,
1473 pclk_freq_in_mhz,
1474 dst->odm_combine,
1475 full_recout_width,
1476 dst->hactive,
1477 vratio_c,
1478 hscale_pixel_rate_c,
1479 scaler_rec_in_width_c,
1480 req_per_swath_ub_c); // per req
1481
1482 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, refcyc_per_req_delivery_pre_c);
1483 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, refcyc_per_req_delivery_c);
1484 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_c);
1485 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_c);
1486
1487 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_c", refcyc_per_req_delivery_pre_c, vba__refcyc_per_req_delivery_pre_c);
1488 //old_impl_vs_vba_impl("refcyc_per_req_delivery_c", refcyc_per_req_delivery_c, vba__refcyc_per_req_delivery_c);
1489
1490 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
1491 }
1492
1493 // TTU - Cursor
1494 refcyc_per_req_delivery_pre_cur0 = 0.0;
1495 refcyc_per_req_delivery_cur0 = 0.0;
1496
1497 ASSERT(src->num_cursors <= 1);
1498
1499 if (src->num_cursors > 0) {
1500 float vba__refcyc_per_req_delivery_pre_cur0;
1501 float vba__refcyc_per_req_delivery_cur0;
1502
1503 calculate_ttu_cursor(
1504 mode_lib,
1505 &refcyc_per_req_delivery_pre_cur0,
1506 &refcyc_per_req_delivery_cur0,
1507 refclk_freq_in_mhz,
1508 ref_freq_to_pix_freq,
1509 hscale_pixel_rate_l,
1510 scl->hscl_ratio,
1511 vratio_pre_l,
1512 vratio_l,
1513 src->cur0_src_width,
1514 (enum cursor_bpp) (src->cur0_bpp));
1515
1516 vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1517 vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1518
1519 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0);
1520 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0);
1521 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_cur0);
1522 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_cur0);
1523
1524 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_cur0", refcyc_per_req_delivery_pre_cur0, vba__refcyc_per_req_delivery_pre_cur0);
1525 //old_impl_vs_vba_impl("refcyc_per_req_delivery_cur0", refcyc_per_req_delivery_cur0, vba__refcyc_per_req_delivery_cur0);
1526 }
1527
1528 refcyc_per_req_delivery_pre_cur1 = 0.0;
1529 refcyc_per_req_delivery_cur1 = 0.0;
1530
1531 // TTU - Misc
1532 // all hard-coded
1533
1534 // Assignment to register structures
1535 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
1536 ASSERT(disp_dlg_regs->dst_y_after_scaler < 8);
1537 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
1538 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
1539 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
1540 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
1541 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
1542 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
1543 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1544
1545 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
1546 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
1547
1548 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank);
1549 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank);
1550 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
1551 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
1552
1553 // hack for FPGA
1554 if (mode_lib->project == DML_PROJECT_DCN31_FPGA) {
1555 if (disp_dlg_regs->vratio_prefetch >= (unsigned int) dml_pow(2, 22)) {
1556 disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 22) - 1;
1557 dml_print("vratio_prefetch exceed the max value, the register field is [21:0]\n");
1558 }
1559 }
1560
1561 disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
1562 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
1563
1564 if (dual_plane) {
1565 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c);
1566 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
1567 }
1568
1569 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
1570 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
1571
1572 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now
1573
1574 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
1575 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
1576
1577 if (dual_plane) {
1578 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
1579 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
1580 }
1581
1582 disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1583 disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1584 disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA
1585 disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA
1586
1587 // Clamp to max for now
1588 if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))
1589 disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
1590
1591 if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))
1592 disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
1593
1594 if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))
1595 disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
1596
1597 if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))
1598 disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
1599
1600 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));
1601 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
1602 if (dual_plane) {
1603 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));
1604 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
1605 dml_print(
1606 "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
1607 __func__,
1608 disp_dlg_regs->dst_y_per_pte_row_nom_c,
1609 (unsigned int) dml_pow(2, 17) - 1);
1610 }
1611 }
1612
1613 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));
1614 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
1615
1616 disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));
1617 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
1618
1619 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1620 / (double) dpte_groups_per_row_ub_l);
1621 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
1622 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
1623 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1624 / (double) meta_chunks_per_row_ub_l);
1625 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
1626 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
1627
1628 if (dual_plane) {
1629 disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
1630 / (double) dpte_groups_per_row_ub_c);
1631 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
1632 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
1633
1634 // TODO: Is this the right calculation? Does htotal need to be halved?
1635 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
1636 / (double) meta_chunks_per_row_ub_c);
1637 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
1638 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
1639 }
1640
1641 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1);
1642 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1);
1643 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
1644
1645 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1);
1646 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1);
1647 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
1648
1649 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
1650 disp_dlg_regs->dst_y_offset_cur0 = 0;
1651 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
1652 disp_dlg_regs->dst_y_offset_cur1 = 0;
1653
1654 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
1655
1656 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));
1657 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));
1658 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
1659 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));
1660 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
1661 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
1662 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
1663 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));
1664
1665 disp_ttu_regs->qos_level_low_wm = 0;
1666 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1667
1668 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
1669 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
1670
1671 disp_ttu_regs->qos_level_flip = 14;
1672 disp_ttu_regs->qos_level_fixed_l = 8;
1673 disp_ttu_regs->qos_level_fixed_c = 8;
1674 disp_ttu_regs->qos_level_fixed_cur0 = 8;
1675 disp_ttu_regs->qos_ramp_disable_l = 0;
1676 disp_ttu_regs->qos_ramp_disable_c = 0;
1677 disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1678
1679 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1680 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1681
1682 print__ttu_regs_st(mode_lib, disp_ttu_regs);
1683 print__dlg_regs_st(mode_lib, disp_dlg_regs);
1684 }
1685
dml314_rq_dlg_get_dlg_reg(struct display_mode_lib * mode_lib,display_dlg_regs_st * dlg_regs,display_ttu_regs_st * ttu_regs,const display_e2e_pipe_params_st * e2e_pipe_param,const unsigned int num_pipes,const unsigned int pipe_idx,const bool cstate_en,const bool pstate_en,const bool vm_en,const bool ignore_viewport_pos,const bool immediate_flip_support)1686 void dml314_rq_dlg_get_dlg_reg(
1687 struct display_mode_lib *mode_lib,
1688 display_dlg_regs_st *dlg_regs,
1689 display_ttu_regs_st *ttu_regs,
1690 const display_e2e_pipe_params_st *e2e_pipe_param,
1691 const unsigned int num_pipes,
1692 const unsigned int pipe_idx,
1693 const bool cstate_en,
1694 const bool pstate_en,
1695 const bool vm_en,
1696 const bool ignore_viewport_pos,
1697 const bool immediate_flip_support)
1698 {
1699 display_rq_params_st rq_param = {0};
1700 display_dlg_sys_params_st dlg_sys_param = {0};
1701
1702 // Get watermark and Tex.
1703 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1704 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, e2e_pipe_param, num_pipes);
1705 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1706 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1707 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1708 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
1709 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes);
1710 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes);
1711
1712 print__dlg_sys_params_st(mode_lib, &dlg_sys_param);
1713
1714 // system parameter calculation done
1715
1716 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
1717 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);
1718 dml_rq_dlg_get_dlg_params(
1719 mode_lib,
1720 e2e_pipe_param,
1721 num_pipes,
1722 pipe_idx,
1723 dlg_regs,
1724 ttu_regs,
1725 &rq_param.dlg,
1726 &dlg_sys_param,
1727 cstate_en,
1728 pstate_en,
1729 vm_en,
1730 ignore_viewport_pos,
1731 immediate_flip_support);
1732 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
1733 }
1734