1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _sbhnddma_h_ 18 #define _sbhnddma_h_ 19 20 /* DMA structure: 21 * support two DMA engines: 32 bits address or 64 bit addressing 22 * basic DMA register set is per channel(transmit or receive) 23 * a pair of channels is defined for convenience 24 */ 25 26 /* 32 bits addressing */ 27 28 /* dma registers per channel(xmt or rcv) */ 29 typedef volatile struct { 30 u32 control; /* enable, et al */ 31 u32 addr; /* descriptor ring base address (4K aligned) */ 32 u32 ptr; /* last descriptor posted to chip */ 33 u32 status; /* current active descriptor, et al */ 34 } dma32regs_t; 35 36 typedef volatile struct { 37 dma32regs_t xmt; /* dma tx channel */ 38 dma32regs_t rcv; /* dma rx channel */ 39 } dma32regp_t; 40 41 typedef volatile struct { /* diag access */ 42 u32 fifoaddr; /* diag address */ 43 u32 fifodatalow; /* low 32bits of data */ 44 u32 fifodatahigh; /* high 32bits of data */ 45 u32 pad; /* reserved */ 46 } dma32diag_t; 47 48 /* 49 * DMA Descriptor 50 * Descriptors are only read by the hardware, never written back. 51 */ 52 typedef volatile struct { 53 u32 ctrl; /* misc control bits & bufcount */ 54 u32 addr; /* data buffer address */ 55 } dma32dd_t; 56 57 /* 58 * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page. 59 */ 60 #define D32RINGALIGN_BITS 12 61 #define D32MAXRINGSZ (1 << D32RINGALIGN_BITS) 62 #define D32RINGALIGN (1 << D32RINGALIGN_BITS) 63 64 #define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) 65 66 /* transmit channel control */ 67 #define XC_XE ((u32)1 << 0) /* transmit enable */ 68 #define XC_SE ((u32)1 << 1) /* transmit suspend request */ 69 #define XC_LE ((u32)1 << 2) /* loopback enable */ 70 #define XC_FL ((u32)1 << 4) /* flush request */ 71 #define XC_PD ((u32)1 << 11) /* parity check disable */ 72 #define XC_AE ((u32)3 << 16) /* address extension bits */ 73 #define XC_AE_SHIFT 16 74 75 /* transmit descriptor table pointer */ 76 #define XP_LD_MASK 0xfff /* last valid descriptor */ 77 78 /* transmit channel status */ 79 #define XS_CD_MASK 0x0fff /* current descriptor pointer */ 80 #define XS_XS_MASK 0xf000 /* transmit state */ 81 #define XS_XS_SHIFT 12 82 #define XS_XS_DISABLED 0x0000 /* disabled */ 83 #define XS_XS_ACTIVE 0x1000 /* active */ 84 #define XS_XS_IDLE 0x2000 /* idle wait */ 85 #define XS_XS_STOPPED 0x3000 /* stopped */ 86 #define XS_XS_SUSP 0x4000 /* suspend pending */ 87 #define XS_XE_MASK 0xf0000 /* transmit errors */ 88 #define XS_XE_SHIFT 16 89 #define XS_XE_NOERR 0x00000 /* no error */ 90 #define XS_XE_DPE 0x10000 /* descriptor protocol error */ 91 #define XS_XE_DFU 0x20000 /* data fifo underrun */ 92 #define XS_XE_BEBR 0x30000 /* bus error on buffer read */ 93 #define XS_XE_BEDA 0x40000 /* bus error on descriptor access */ 94 #define XS_AD_MASK 0xfff00000 /* active descriptor */ 95 #define XS_AD_SHIFT 20 96 97 /* receive channel control */ 98 #define RC_RE ((u32)1 << 0) /* receive enable */ 99 #define RC_RO_MASK 0xfe /* receive frame offset */ 100 #define RC_RO_SHIFT 1 101 #define RC_FM ((u32)1 << 8) /* direct fifo receive (pio) mode */ 102 #define RC_SH ((u32)1 << 9) /* separate rx header descriptor enable */ 103 #define RC_OC ((u32)1 << 10) /* overflow continue */ 104 #define RC_PD ((u32)1 << 11) /* parity check disable */ 105 #define RC_AE ((u32)3 << 16) /* address extension bits */ 106 #define RC_AE_SHIFT 16 107 108 /* receive descriptor table pointer */ 109 #define RP_LD_MASK 0xfff /* last valid descriptor */ 110 111 /* receive channel status */ 112 #define RS_CD_MASK 0x0fff /* current descriptor pointer */ 113 #define RS_RS_MASK 0xf000 /* receive state */ 114 #define RS_RS_SHIFT 12 115 #define RS_RS_DISABLED 0x0000 /* disabled */ 116 #define RS_RS_ACTIVE 0x1000 /* active */ 117 #define RS_RS_IDLE 0x2000 /* idle wait */ 118 #define RS_RS_STOPPED 0x3000 /* reserved */ 119 #define RS_RE_MASK 0xf0000 /* receive errors */ 120 #define RS_RE_SHIFT 16 121 #define RS_RE_NOERR 0x00000 /* no error */ 122 #define RS_RE_DPE 0x10000 /* descriptor protocol error */ 123 #define RS_RE_DFO 0x20000 /* data fifo overflow */ 124 #define RS_RE_BEBW 0x30000 /* bus error on buffer write */ 125 #define RS_RE_BEDA 0x40000 /* bus error on descriptor access */ 126 #define RS_AD_MASK 0xfff00000 /* active descriptor */ 127 #define RS_AD_SHIFT 20 128 129 /* fifoaddr */ 130 #define FA_OFF_MASK 0xffff /* offset */ 131 #define FA_SEL_MASK 0xf0000 /* select */ 132 #define FA_SEL_SHIFT 16 133 #define FA_SEL_XDD 0x00000 /* transmit dma data */ 134 #define FA_SEL_XDP 0x10000 /* transmit dma pointers */ 135 #define FA_SEL_RDD 0x40000 /* receive dma data */ 136 #define FA_SEL_RDP 0x50000 /* receive dma pointers */ 137 #define FA_SEL_XFD 0x80000 /* transmit fifo data */ 138 #define FA_SEL_XFP 0x90000 /* transmit fifo pointers */ 139 #define FA_SEL_RFD 0xc0000 /* receive fifo data */ 140 #define FA_SEL_RFP 0xd0000 /* receive fifo pointers */ 141 #define FA_SEL_RSD 0xe0000 /* receive frame status data */ 142 #define FA_SEL_RSP 0xf0000 /* receive frame status pointers */ 143 144 /* descriptor control flags */ 145 #define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */ 146 #define CTRL_AE ((u32)3 << 16) /* address extension bits */ 147 #define CTRL_AE_SHIFT 16 148 #define CTRL_PARITY ((u32)3 << 18) /* parity bit */ 149 #define CTRL_EOT ((u32)1 << 28) /* end of descriptor table */ 150 #define CTRL_IOC ((u32)1 << 29) /* interrupt on completion */ 151 #define CTRL_EOF ((u32)1 << 30) /* end of frame */ 152 #define CTRL_SOF ((u32)1 << 31) /* start of frame */ 153 154 /* control flags in the range [27:20] are core-specific and not defined here */ 155 #define CTRL_CORE_MASK 0x0ff00000 156 157 /* 64 bits addressing */ 158 159 /* dma registers per channel(xmt or rcv) */ 160 typedef volatile struct { 161 u32 control; /* enable, et al */ 162 u32 ptr; /* last descriptor posted to chip */ 163 u32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */ 164 u32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */ 165 u32 status0; /* current descriptor, xmt state */ 166 u32 status1; /* active descriptor, xmt error */ 167 } dma64regs_t; 168 169 typedef volatile struct { 170 dma64regs_t tx; /* dma64 tx channel */ 171 dma64regs_t rx; /* dma64 rx channel */ 172 } dma64regp_t; 173 174 typedef volatile struct { /* diag access */ 175 u32 fifoaddr; /* diag address */ 176 u32 fifodatalow; /* low 32bits of data */ 177 u32 fifodatahigh; /* high 32bits of data */ 178 u32 pad; /* reserved */ 179 } dma64diag_t; 180 181 /* 182 * DMA Descriptor 183 * Descriptors are only read by the hardware, never written back. 184 */ 185 typedef volatile struct { 186 u32 ctrl1; /* misc control bits & bufcount */ 187 u32 ctrl2; /* buffer count and address extension */ 188 u32 addrlow; /* memory address of the date buffer, bits 31:0 */ 189 u32 addrhigh; /* memory address of the date buffer, bits 63:32 */ 190 } dma64dd_t; 191 192 /* 193 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical address. 194 */ 195 #define D64RINGALIGN_BITS 13 196 #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) 197 #define D64RINGALIGN (1 << D64RINGALIGN_BITS) 198 199 #define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) 200 201 /* transmit channel control */ 202 #define D64_XC_XE 0x00000001 /* transmit enable */ 203 #define D64_XC_SE 0x00000002 /* transmit suspend request */ 204 #define D64_XC_LE 0x00000004 /* loopback enable */ 205 #define D64_XC_FL 0x00000010 /* flush request */ 206 #define D64_XC_PD 0x00000800 /* parity check disable */ 207 #define D64_XC_AE 0x00030000 /* address extension bits */ 208 #define D64_XC_AE_SHIFT 16 209 210 /* transmit descriptor table pointer */ 211 #define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */ 212 213 /* transmit channel status */ 214 #define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */ 215 #define D64_XS0_XS_MASK 0xf0000000 /* transmit state */ 216 #define D64_XS0_XS_SHIFT 28 217 #define D64_XS0_XS_DISABLED 0x00000000 /* disabled */ 218 #define D64_XS0_XS_ACTIVE 0x10000000 /* active */ 219 #define D64_XS0_XS_IDLE 0x20000000 /* idle wait */ 220 #define D64_XS0_XS_STOPPED 0x30000000 /* stopped */ 221 #define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */ 222 223 #define D64_XS1_AD_MASK 0x00001fff /* active descriptor */ 224 #define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */ 225 #define D64_XS1_XE_SHIFT 28 226 #define D64_XS1_XE_NOERR 0x00000000 /* no error */ 227 #define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */ 228 #define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */ 229 #define D64_XS1_XE_DTE 0x30000000 /* data transfer error */ 230 #define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */ 231 #define D64_XS1_XE_COREE 0x50000000 /* core error */ 232 233 /* receive channel control */ 234 #define D64_RC_RE 0x00000001 /* receive enable */ 235 #define D64_RC_RO_MASK 0x000000fe /* receive frame offset */ 236 #define D64_RC_RO_SHIFT 1 237 #define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */ 238 #define D64_RC_SH 0x00000200 /* separate rx header descriptor enable */ 239 #define D64_RC_OC 0x00000400 /* overflow continue */ 240 #define D64_RC_PD 0x00000800 /* parity check disable */ 241 #define D64_RC_AE 0x00030000 /* address extension bits */ 242 #define D64_RC_AE_SHIFT 16 243 244 /* flags for dma controller */ 245 #define DMA_CTRL_PEN (1 << 0) /* partity enable */ 246 #define DMA_CTRL_ROC (1 << 1) /* rx overflow continue */ 247 #define DMA_CTRL_RXMULTI (1 << 2) /* allow rx scatter to multiple descriptors */ 248 #define DMA_CTRL_UNFRAMED (1 << 3) /* Unframed Rx/Tx data */ 249 250 /* receive descriptor table pointer */ 251 #define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */ 252 253 /* receive channel status */ 254 #define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */ 255 #define D64_RS0_RS_MASK 0xf0000000 /* receive state */ 256 #define D64_RS0_RS_SHIFT 28 257 #define D64_RS0_RS_DISABLED 0x00000000 /* disabled */ 258 #define D64_RS0_RS_ACTIVE 0x10000000 /* active */ 259 #define D64_RS0_RS_IDLE 0x20000000 /* idle wait */ 260 #define D64_RS0_RS_STOPPED 0x30000000 /* stopped */ 261 #define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */ 262 263 #define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */ 264 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */ 265 #define D64_RS1_RE_SHIFT 28 266 #define D64_RS1_RE_NOERR 0x00000000 /* no error */ 267 #define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */ 268 #define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */ 269 #define D64_RS1_RE_DTE 0x30000000 /* data transfer error */ 270 #define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */ 271 #define D64_RS1_RE_COREE 0x50000000 /* core error */ 272 273 /* fifoaddr */ 274 #define D64_FA_OFF_MASK 0xffff /* offset */ 275 #define D64_FA_SEL_MASK 0xf0000 /* select */ 276 #define D64_FA_SEL_SHIFT 16 277 #define D64_FA_SEL_XDD 0x00000 /* transmit dma data */ 278 #define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */ 279 #define D64_FA_SEL_RDD 0x40000 /* receive dma data */ 280 #define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */ 281 #define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */ 282 #define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */ 283 #define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */ 284 #define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */ 285 #define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */ 286 #define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */ 287 288 /* descriptor control flags 1 */ 289 #define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */ 290 #define D64_CTRL1_EOT ((u32)1 << 28) /* end of descriptor table */ 291 #define D64_CTRL1_IOC ((u32)1 << 29) /* interrupt on completion */ 292 #define D64_CTRL1_EOF ((u32)1 << 30) /* end of frame */ 293 #define D64_CTRL1_SOF ((u32)1 << 31) /* start of frame */ 294 295 /* descriptor control flags 2 */ 296 #define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */ 297 #define D64_CTRL2_AE 0x00030000 /* address extension bits */ 298 #define D64_CTRL2_AE_SHIFT 16 299 #define D64_CTRL2_PARITY 0x00040000 /* parity bit */ 300 301 /* control flags in the range [27:20] are core-specific and not defined here */ 302 #define D64_CTRL_CORE_MASK 0x0ff00000 303 304 #define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */ 305 #define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */ 306 #define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1 */ 307 #define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */ 308 309 /* receive frame status */ 310 typedef volatile struct { 311 u16 len; 312 u16 flags; 313 } dma_rxh_t; 314 315 #endif /* _sbhnddma_h_ */ 316