1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <drm/display/drm_dp_helper.h>
27 #include <drm/display/drm_dp_mst_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include "dm_services.h"
31 #include "amdgpu.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_mst_types.h"
34
35 #include "dc.h"
36 #include "dm_helpers.h"
37
38 #include "dc_link_ddc.h"
39 #include "dc_link_dp.h"
40 #include "ddc_service_types.h"
41 #include "dpcd_defs.h"
42
43 #include "i2caux_interface.h"
44 #include "dmub_cmd.h"
45 #if defined(CONFIG_DEBUG_FS)
46 #include "amdgpu_dm_debugfs.h"
47 #endif
48
49 #include "dc/dcn20/dcn20_resource.h"
50 bool is_timing_changed(struct dc_stream_state *cur_stream,
51 struct dc_stream_state *new_stream);
52
53
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)54 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
55 struct drm_dp_aux_msg *msg)
56 {
57 ssize_t result = 0;
58 struct aux_payload payload;
59 enum aux_return_code_type operation_result;
60 struct amdgpu_device *adev;
61 struct ddc_service *ddc;
62
63 if (WARN_ON(msg->size > 16))
64 return -E2BIG;
65
66 payload.address = msg->address;
67 payload.data = msg->buffer;
68 payload.length = msg->size;
69 payload.reply = &msg->reply;
70 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
71 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
72 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
73 payload.write_status_update =
74 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
75 payload.defer_delay = 0;
76
77 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
78 &operation_result);
79
80 /*
81 * w/a on certain intel platform where hpd is unexpected to pull low during
82 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
83 * aux transaction is succuess in such case, therefore bypass the error
84 */
85 ddc = TO_DM_AUX(aux)->ddc_service;
86 adev = ddc->ctx->driver_context;
87 if (adev->dm.aux_hpd_discon_quirk) {
88 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
89 operation_result == AUX_RET_ERROR_HPD_DISCON) {
90 result = 0;
91 operation_result = AUX_RET_SUCCESS;
92 }
93 }
94
95 if (payload.write && result >= 0)
96 result = msg->size;
97
98 if (result < 0)
99 switch (operation_result) {
100 case AUX_RET_SUCCESS:
101 break;
102 case AUX_RET_ERROR_HPD_DISCON:
103 case AUX_RET_ERROR_UNKNOWN:
104 case AUX_RET_ERROR_INVALID_OPERATION:
105 case AUX_RET_ERROR_PROTOCOL_ERROR:
106 result = -EIO;
107 break;
108 case AUX_RET_ERROR_INVALID_REPLY:
109 case AUX_RET_ERROR_ENGINE_ACQUIRE:
110 result = -EBUSY;
111 break;
112 case AUX_RET_ERROR_TIMEOUT:
113 result = -ETIMEDOUT;
114 break;
115 }
116
117 return result;
118 }
119
120 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)121 dm_dp_mst_connector_destroy(struct drm_connector *connector)
122 {
123 struct amdgpu_dm_connector *aconnector =
124 to_amdgpu_dm_connector(connector);
125
126 if (aconnector->dc_sink) {
127 dc_link_remove_remote_sink(aconnector->dc_link,
128 aconnector->dc_sink);
129 dc_sink_release(aconnector->dc_sink);
130 }
131
132 kfree(aconnector->edid);
133
134 drm_connector_cleanup(connector);
135 drm_dp_mst_put_port_malloc(aconnector->port);
136 kfree(aconnector);
137 }
138
139 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)140 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
141 {
142 struct amdgpu_dm_connector *amdgpu_dm_connector =
143 to_amdgpu_dm_connector(connector);
144 int r;
145
146 r = drm_dp_mst_connector_late_register(connector,
147 amdgpu_dm_connector->port);
148 if (r < 0)
149 return r;
150
151 #if defined(CONFIG_DEBUG_FS)
152 connector_debugfs_init(amdgpu_dm_connector);
153 #endif
154
155 return 0;
156 }
157
158 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)159 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
160 {
161 struct amdgpu_dm_connector *aconnector =
162 to_amdgpu_dm_connector(connector);
163 struct drm_dp_mst_port *port = aconnector->port;
164 struct amdgpu_dm_connector *root = aconnector->mst_port;
165 struct dc_link *dc_link = aconnector->dc_link;
166 struct dc_sink *dc_sink = aconnector->dc_sink;
167
168 drm_dp_mst_connector_early_unregister(connector, port);
169
170 /*
171 * Release dc_sink for connector which its attached port is
172 * no longer in the mst topology
173 */
174 drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
175 if (dc_sink) {
176 if (dc_link->sink_count)
177 dc_link_remove_remote_sink(dc_link, dc_sink);
178
179 dc_sink_release(dc_sink);
180 aconnector->dc_sink = NULL;
181 aconnector->edid = NULL;
182 }
183
184 aconnector->mst_status = MST_STATUS_DEFAULT;
185 drm_modeset_unlock(&root->mst_mgr.base.lock);
186 }
187
188 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
189 .fill_modes = drm_helper_probe_single_connector_modes,
190 .destroy = dm_dp_mst_connector_destroy,
191 .reset = amdgpu_dm_connector_funcs_reset,
192 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
193 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
194 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
195 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
196 .late_register = amdgpu_dm_mst_connector_late_register,
197 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
198 };
199
200 #if defined(CONFIG_DRM_AMD_DC_DCN)
needs_dsc_aux_workaround(struct dc_link * link)201 bool needs_dsc_aux_workaround(struct dc_link *link)
202 {
203 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
204 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
205 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
206 return true;
207
208 return false;
209 }
210
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)211 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
212 {
213 struct dc_sink *dc_sink = aconnector->dc_sink;
214 struct drm_dp_mst_port *port = aconnector->port;
215 u8 dsc_caps[16] = { 0 };
216 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
217 u8 *dsc_branch_dec_caps = NULL;
218
219 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
220
221 /*
222 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
223 * because it only check the dsc/fec caps of the "port variable" and not the dock
224 *
225 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
226 *
227 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
228 *
229 */
230 if (!aconnector->dsc_aux && !port->parent->port_parent &&
231 needs_dsc_aux_workaround(aconnector->dc_link))
232 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
233
234 if (!aconnector->dsc_aux)
235 return false;
236
237 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
238 return false;
239
240 if (drm_dp_dpcd_read(aconnector->dsc_aux,
241 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
242 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
243
244 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
245 dsc_caps, dsc_branch_dec_caps,
246 &dc_sink->dsc_caps.dsc_dec_caps))
247 return false;
248
249 return true;
250 }
251
retrieve_downstream_port_device(struct amdgpu_dm_connector * aconnector)252 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
253 {
254 union dp_downstream_port_present ds_port_present;
255
256 if (!aconnector->dsc_aux)
257 return false;
258
259 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
260 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
261 return false;
262 }
263
264 aconnector->mst_downstream_port_present = ds_port_present;
265 DRM_INFO("Downstream port present %d, type %d\n",
266 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
267
268 return true;
269 }
270 #endif
271
dm_dp_mst_get_modes(struct drm_connector * connector)272 static int dm_dp_mst_get_modes(struct drm_connector *connector)
273 {
274 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
275 int ret = 0;
276
277 if (!aconnector)
278 return drm_add_edid_modes(connector, NULL);
279
280 if (!aconnector->edid) {
281 struct edid *edid;
282 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
283
284 if (!edid) {
285 amdgpu_dm_set_mst_status(&aconnector->mst_status,
286 MST_REMOTE_EDID, false);
287
288 drm_connector_update_edid_property(
289 &aconnector->base,
290 NULL);
291
292 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
293 if (!aconnector->dc_sink) {
294 struct dc_sink *dc_sink;
295 struct dc_sink_init_data init_params = {
296 .link = aconnector->dc_link,
297 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
298
299 dc_sink = dc_link_add_remote_sink(
300 aconnector->dc_link,
301 NULL,
302 0,
303 &init_params);
304
305 if (!dc_sink) {
306 DRM_ERROR("Unable to add a remote sink\n");
307 return 0;
308 }
309
310 dc_sink->priv = aconnector;
311 aconnector->dc_sink = dc_sink;
312 }
313
314 return ret;
315 }
316
317 aconnector->edid = edid;
318 amdgpu_dm_set_mst_status(&aconnector->mst_status,
319 MST_REMOTE_EDID, true);
320 }
321
322 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
323 dc_sink_release(aconnector->dc_sink);
324 aconnector->dc_sink = NULL;
325 }
326
327 if (!aconnector->dc_sink) {
328 struct dc_sink *dc_sink;
329 struct dc_sink_init_data init_params = {
330 .link = aconnector->dc_link,
331 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
332 dc_sink = dc_link_add_remote_sink(
333 aconnector->dc_link,
334 (uint8_t *)aconnector->edid,
335 (aconnector->edid->extensions + 1) * EDID_LENGTH,
336 &init_params);
337
338 if (!dc_sink) {
339 DRM_ERROR("Unable to add a remote sink\n");
340 return 0;
341 }
342
343 dc_sink->priv = aconnector;
344 /* dc_link_add_remote_sink returns a new reference */
345 aconnector->dc_sink = dc_sink;
346
347 if (aconnector->dc_sink) {
348 amdgpu_dm_update_freesync_caps(
349 connector, aconnector->edid);
350
351 #if defined(CONFIG_DRM_AMD_DC_DCN)
352 if (!validate_dsc_caps_on_connector(aconnector))
353 memset(&aconnector->dc_sink->dsc_caps,
354 0, sizeof(aconnector->dc_sink->dsc_caps));
355
356 if (!retrieve_downstream_port_device(aconnector))
357 memset(&aconnector->mst_downstream_port_present,
358 0, sizeof(aconnector->mst_downstream_port_present));
359 #endif
360 }
361 }
362
363 drm_connector_update_edid_property(
364 &aconnector->base, aconnector->edid);
365
366 ret = drm_add_edid_modes(connector, aconnector->edid);
367
368 return ret;
369 }
370
371 static struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_atomic_state * state)372 dm_mst_atomic_best_encoder(struct drm_connector *connector,
373 struct drm_atomic_state *state)
374 {
375 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
376 connector);
377 struct drm_device *dev = connector->dev;
378 struct amdgpu_device *adev = drm_to_adev(dev);
379 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
380
381 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
382 }
383
384 static int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)385 dm_dp_mst_detect(struct drm_connector *connector,
386 struct drm_modeset_acquire_ctx *ctx, bool force)
387 {
388 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
389 struct amdgpu_dm_connector *master = aconnector->mst_port;
390 struct drm_dp_mst_port *port = aconnector->port;
391 int connection_status;
392
393 if (drm_connector_is_unregistered(connector))
394 return connector_status_disconnected;
395
396 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
397 aconnector->port);
398
399 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
400 uint8_t dpcd_rev;
401 int ret;
402
403 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
404
405 if (ret == 1) {
406 port->dpcd_rev = dpcd_rev;
407
408 /* Could be DP1.2 DP Rx case*/
409 if (!dpcd_rev) {
410 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
411
412 if (ret == 1)
413 port->dpcd_rev = dpcd_rev;
414 }
415
416 if (!dpcd_rev)
417 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
418 }
419
420 /*
421 * Could be legacy sink, logical port etc on DP1.2.
422 * Will get Nack under these cases when issue remote
423 * DPCD read.
424 */
425 if (ret != 1)
426 DRM_DEBUG_KMS("Can't access DPCD");
427 } else if (port->pdt == DP_PEER_DEVICE_NONE) {
428 port->dpcd_rev = 0;
429 }
430
431 /*
432 * Release dc_sink for connector which unplug event is notified by CSN msg
433 */
434 if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
435 if (aconnector->dc_link->sink_count)
436 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
437
438 dc_sink_release(aconnector->dc_sink);
439 aconnector->dc_sink = NULL;
440 aconnector->edid = NULL;
441
442 amdgpu_dm_set_mst_status(&aconnector->mst_status,
443 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
444 false);
445 }
446
447 return connection_status;
448 }
449
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)450 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
451 struct drm_atomic_state *state)
452 {
453 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
454 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr;
455 struct drm_dp_mst_port *mst_port = aconnector->port;
456
457 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
458 }
459
460 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
461 .get_modes = dm_dp_mst_get_modes,
462 .mode_valid = amdgpu_dm_connector_mode_valid,
463 .atomic_best_encoder = dm_mst_atomic_best_encoder,
464 .detect_ctx = dm_dp_mst_detect,
465 .atomic_check = dm_dp_mst_atomic_check,
466 };
467
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)468 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
469 {
470 drm_encoder_cleanup(encoder);
471 }
472
473 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
474 .destroy = amdgpu_dm_encoder_destroy,
475 };
476
477 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)478 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
479 {
480 struct drm_device *dev = adev_to_drm(adev);
481 int i;
482
483 for (i = 0; i < adev->dm.display_indexes_num; i++) {
484 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
485 struct drm_encoder *encoder = &amdgpu_encoder->base;
486
487 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
488
489 drm_encoder_init(
490 dev,
491 &amdgpu_encoder->base,
492 &amdgpu_dm_encoder_funcs,
493 DRM_MODE_ENCODER_DPMST,
494 NULL);
495
496 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
497 }
498 }
499
500 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)501 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
502 struct drm_dp_mst_port *port,
503 const char *pathprop)
504 {
505 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
506 struct drm_device *dev = master->base.dev;
507 struct amdgpu_device *adev = drm_to_adev(dev);
508 struct amdgpu_dm_connector *aconnector;
509 struct drm_connector *connector;
510 int i;
511
512 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
513 if (!aconnector)
514 return NULL;
515
516 connector = &aconnector->base;
517 aconnector->port = port;
518 aconnector->mst_port = master;
519 amdgpu_dm_set_mst_status(&aconnector->mst_status,
520 MST_PROBE, true);
521
522 if (drm_connector_init(
523 dev,
524 connector,
525 &dm_dp_mst_connector_funcs,
526 DRM_MODE_CONNECTOR_DisplayPort)) {
527 kfree(aconnector);
528 return NULL;
529 }
530 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
531
532 amdgpu_dm_connector_init_helper(
533 &adev->dm,
534 aconnector,
535 DRM_MODE_CONNECTOR_DisplayPort,
536 master->dc_link,
537 master->connector_id);
538
539 for (i = 0; i < adev->dm.display_indexes_num; i++) {
540 drm_connector_attach_encoder(&aconnector->base,
541 &adev->dm.mst_encoders[i].base);
542 }
543
544 connector->max_bpc_property = master->base.max_bpc_property;
545 if (connector->max_bpc_property)
546 drm_connector_attach_max_bpc_property(connector, 8, 16);
547
548 connector->vrr_capable_property = master->base.vrr_capable_property;
549 if (connector->vrr_capable_property)
550 drm_connector_attach_vrr_capable_property(connector);
551
552 drm_object_attach_property(
553 &connector->base,
554 dev->mode_config.path_property,
555 0);
556 drm_object_attach_property(
557 &connector->base,
558 dev->mode_config.tile_property,
559 0);
560
561 drm_connector_set_path_property(connector, pathprop);
562
563 /*
564 * Initialize connector state before adding the connectror to drm and
565 * framebuffer lists
566 */
567 amdgpu_dm_connector_funcs_reset(connector);
568
569 drm_dp_mst_get_port_malloc(port);
570
571 return connector;
572 }
573
574 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
575 .add_connector = dm_dp_add_mst_connector,
576 };
577
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)578 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
579 struct amdgpu_dm_connector *aconnector,
580 int link_index)
581 {
582 struct dc_link_settings max_link_enc_cap = {0};
583
584 aconnector->dm_dp_aux.aux.name =
585 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
586 link_index);
587 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
588 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
589 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
590
591 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
592 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
593 &aconnector->base);
594
595 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
596 return;
597
598 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
599 aconnector->mst_mgr.cbs = &dm_mst_cbs;
600 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
601 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
602
603 drm_connector_attach_dp_subconnector_property(&aconnector->base);
604 }
605
dm_mst_get_pbn_divider(struct dc_link * link)606 int dm_mst_get_pbn_divider(struct dc_link *link)
607 {
608 if (!link)
609 return 0;
610
611 return dc_link_bandwidth_kbps(link,
612 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
613 }
614
615 #if defined(CONFIG_DRM_AMD_DC_DCN)
616
617 struct dsc_mst_fairness_params {
618 struct dc_crtc_timing *timing;
619 struct dc_sink *sink;
620 struct dc_dsc_bw_range bw_range;
621 bool compression_possible;
622 struct drm_dp_mst_port *port;
623 enum dsc_clock_force_state clock_force_enable;
624 uint32_t num_slices_h;
625 uint32_t num_slices_v;
626 uint32_t bpp_overwrite;
627 struct amdgpu_dm_connector *aconnector;
628 };
629
kbps_to_peak_pbn(int kbps)630 static int kbps_to_peak_pbn(int kbps)
631 {
632 u64 peak_kbps = kbps;
633
634 peak_kbps *= 1006;
635 peak_kbps = div_u64(peak_kbps, 1000);
636 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
637 }
638
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)639 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
640 struct dsc_mst_fairness_vars *vars,
641 int count,
642 int k)
643 {
644 int i;
645
646 for (i = 0; i < count; i++) {
647 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
648 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
649 params[i].sink->ctx->dc->res_pool->dscs[0],
650 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
651 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
652 params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit,
653 0,
654 params[i].timing,
655 ¶ms[i].timing->dsc_cfg)) {
656 params[i].timing->flags.DSC = 1;
657
658 if (params[i].bpp_overwrite)
659 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
660 else
661 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
662
663 if (params[i].num_slices_h)
664 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
665
666 if (params[i].num_slices_v)
667 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
668 } else {
669 params[i].timing->flags.DSC = 0;
670 }
671 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
672 }
673
674 for (i = 0; i < count; i++) {
675 if (params[i].sink) {
676 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
677 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
678 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i,
679 params[i].sink->edid_caps.display_name);
680 }
681
682 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n",
683 params[i].timing->flags.DSC,
684 params[i].timing->dsc_cfg.bits_per_pixel,
685 vars[i + k].pbn);
686 }
687 }
688
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)689 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
690 {
691 struct dc_dsc_config dsc_config;
692 u64 kbps;
693
694 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
695 dc_dsc_compute_config(
696 param.sink->ctx->dc->res_pool->dscs[0],
697 ¶m.sink->dsc_caps.dsc_dec_caps,
698 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
699 param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit,
700 (int) kbps, param.timing, &dsc_config);
701
702 return dsc_config.bits_per_pixel;
703 }
704
increase_dsc_bpp(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)705 static int increase_dsc_bpp(struct drm_atomic_state *state,
706 struct drm_dp_mst_topology_state *mst_state,
707 struct dc_link *dc_link,
708 struct dsc_mst_fairness_params *params,
709 struct dsc_mst_fairness_vars *vars,
710 int count,
711 int k)
712 {
713 int i;
714 bool bpp_increased[MAX_PIPES];
715 int initial_slack[MAX_PIPES];
716 int min_initial_slack;
717 int next_index;
718 int remaining_to_increase = 0;
719 int link_timeslots_used;
720 int fair_pbn_alloc;
721 int ret = 0;
722
723 for (i = 0; i < count; i++) {
724 if (vars[i + k].dsc_enabled) {
725 initial_slack[i] =
726 kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i + k].pbn;
727 bpp_increased[i] = false;
728 remaining_to_increase += 1;
729 } else {
730 initial_slack[i] = 0;
731 bpp_increased[i] = true;
732 }
733 }
734
735 while (remaining_to_increase) {
736 next_index = -1;
737 min_initial_slack = -1;
738 for (i = 0; i < count; i++) {
739 if (!bpp_increased[i]) {
740 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
741 min_initial_slack = initial_slack[i];
742 next_index = i;
743 }
744 }
745 }
746
747 if (next_index == -1)
748 break;
749
750 link_timeslots_used = 0;
751
752 for (i = 0; i < count; i++)
753 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div);
754
755 fair_pbn_alloc =
756 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div;
757
758 if (initial_slack[next_index] > fair_pbn_alloc) {
759 vars[next_index].pbn += fair_pbn_alloc;
760 ret = drm_dp_atomic_find_time_slots(state,
761 params[next_index].port->mgr,
762 params[next_index].port,
763 vars[next_index].pbn);
764 if (ret < 0)
765 return ret;
766
767 ret = drm_dp_mst_atomic_check(state);
768 if (ret == 0) {
769 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
770 } else {
771 vars[next_index].pbn -= fair_pbn_alloc;
772 ret = drm_dp_atomic_find_time_slots(state,
773 params[next_index].port->mgr,
774 params[next_index].port,
775 vars[next_index].pbn);
776 if (ret < 0)
777 return ret;
778 }
779 } else {
780 vars[next_index].pbn += initial_slack[next_index];
781 ret = drm_dp_atomic_find_time_slots(state,
782 params[next_index].port->mgr,
783 params[next_index].port,
784 vars[next_index].pbn);
785 if (ret < 0)
786 return ret;
787
788 ret = drm_dp_mst_atomic_check(state);
789 if (ret == 0) {
790 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
791 } else {
792 vars[next_index].pbn -= initial_slack[next_index];
793 ret = drm_dp_atomic_find_time_slots(state,
794 params[next_index].port->mgr,
795 params[next_index].port,
796 vars[next_index].pbn);
797 if (ret < 0)
798 return ret;
799 }
800 }
801
802 bpp_increased[next_index] = true;
803 remaining_to_increase--;
804 }
805 return 0;
806 }
807
try_disable_dsc(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)808 static int try_disable_dsc(struct drm_atomic_state *state,
809 struct dc_link *dc_link,
810 struct dsc_mst_fairness_params *params,
811 struct dsc_mst_fairness_vars *vars,
812 int count,
813 int k)
814 {
815 int i;
816 bool tried[MAX_PIPES];
817 int kbps_increase[MAX_PIPES];
818 int max_kbps_increase;
819 int next_index;
820 int remaining_to_try = 0;
821 int ret;
822
823 for (i = 0; i < count; i++) {
824 if (vars[i + k].dsc_enabled
825 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
826 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
827 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
828 tried[i] = false;
829 remaining_to_try += 1;
830 } else {
831 kbps_increase[i] = 0;
832 tried[i] = true;
833 }
834 }
835
836 while (remaining_to_try) {
837 next_index = -1;
838 max_kbps_increase = -1;
839 for (i = 0; i < count; i++) {
840 if (!tried[i]) {
841 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
842 max_kbps_increase = kbps_increase[i];
843 next_index = i;
844 }
845 }
846 }
847
848 if (next_index == -1)
849 break;
850
851 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
852 ret = drm_dp_atomic_find_time_slots(state,
853 params[next_index].port->mgr,
854 params[next_index].port,
855 vars[next_index].pbn);
856 if (ret < 0)
857 return ret;
858
859 ret = drm_dp_mst_atomic_check(state);
860 if (ret == 0) {
861 vars[next_index].dsc_enabled = false;
862 vars[next_index].bpp_x16 = 0;
863 } else {
864 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
865 ret = drm_dp_atomic_find_time_slots(state,
866 params[next_index].port->mgr,
867 params[next_index].port,
868 vars[next_index].pbn);
869 if (ret < 0)
870 return ret;
871 }
872
873 tried[next_index] = true;
874 remaining_to_try--;
875 }
876 return 0;
877 }
878
compute_mst_dsc_configs_for_link(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link,struct dsc_mst_fairness_vars * vars,struct drm_dp_mst_topology_mgr * mgr,int * link_vars_start_index)879 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
880 struct dc_state *dc_state,
881 struct dc_link *dc_link,
882 struct dsc_mst_fairness_vars *vars,
883 struct drm_dp_mst_topology_mgr *mgr,
884 int *link_vars_start_index)
885 {
886 struct dc_stream_state *stream;
887 struct dsc_mst_fairness_params params[MAX_PIPES];
888 struct amdgpu_dm_connector *aconnector;
889 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
890 int count = 0;
891 int i, k, ret;
892 bool debugfs_overwrite = false;
893
894 memset(params, 0, sizeof(params));
895
896 if (IS_ERR(mst_state))
897 return PTR_ERR(mst_state);
898
899 /* Set up params */
900 for (i = 0; i < dc_state->stream_count; i++) {
901 struct dc_dsc_policy dsc_policy = {0};
902
903 stream = dc_state->streams[i];
904
905 if (stream->link != dc_link)
906 continue;
907
908 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
909 if (!aconnector)
910 continue;
911
912 if (!aconnector->port)
913 continue;
914
915 stream->timing.flags.DSC = 0;
916
917 params[count].timing = &stream->timing;
918 params[count].sink = stream->sink;
919 params[count].aconnector = aconnector;
920 params[count].port = aconnector->port;
921 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
922 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
923 debugfs_overwrite = true;
924 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
925 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
926 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
927 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
928 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
929 if (!dc_dsc_compute_bandwidth_range(
930 stream->sink->ctx->dc->res_pool->dscs[0],
931 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
932 dsc_policy.min_target_bpp * 16,
933 dsc_policy.max_target_bpp * 16,
934 &stream->sink->dsc_caps.dsc_dec_caps,
935 &stream->timing, ¶ms[count].bw_range))
936 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
937
938 count++;
939 }
940
941 if (count == 0) {
942 ASSERT(0);
943 return 0;
944 }
945
946 /* k is start index of vars for current phy link used by mst hub */
947 k = *link_vars_start_index;
948 /* set vars start index for next mst hub phy link */
949 *link_vars_start_index += count;
950
951 /* Try no compression */
952 for (i = 0; i < count; i++) {
953 vars[i + k].aconnector = params[i].aconnector;
954 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
955 vars[i + k].dsc_enabled = false;
956 vars[i + k].bpp_x16 = 0;
957 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
958 vars[i + k].pbn);
959 if (ret < 0)
960 return ret;
961 }
962 ret = drm_dp_mst_atomic_check(state);
963 if (ret == 0 && !debugfs_overwrite) {
964 set_dsc_configs_from_fairness_vars(params, vars, count, k);
965 return 0;
966 } else if (ret != -ENOSPC) {
967 return ret;
968 }
969
970 /* Try max compression */
971 for (i = 0; i < count; i++) {
972 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
973 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
974 vars[i + k].dsc_enabled = true;
975 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
976 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
977 params[i].port, vars[i + k].pbn);
978 if (ret < 0)
979 return ret;
980 } else {
981 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
982 vars[i + k].dsc_enabled = false;
983 vars[i + k].bpp_x16 = 0;
984 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
985 params[i].port, vars[i + k].pbn);
986 if (ret < 0)
987 return ret;
988 }
989 }
990 ret = drm_dp_mst_atomic_check(state);
991 if (ret != 0)
992 return ret;
993
994 /* Optimize degree of compression */
995 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
996 if (ret < 0)
997 return ret;
998
999 ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1000 if (ret < 0)
1001 return ret;
1002
1003 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1004
1005 return 0;
1006 }
1007
is_dsc_need_re_compute(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link)1008 static bool is_dsc_need_re_compute(
1009 struct drm_atomic_state *state,
1010 struct dc_state *dc_state,
1011 struct dc_link *dc_link)
1012 {
1013 int i, j;
1014 bool is_dsc_need_re_compute = false;
1015 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1016 int new_stream_on_link_num = 0;
1017 struct amdgpu_dm_connector *aconnector;
1018 struct dc_stream_state *stream;
1019 const struct dc *dc = dc_link->dc;
1020
1021 /* only check phy used by dsc mst branch */
1022 if (dc_link->type != dc_connection_mst_branch)
1023 return false;
1024
1025 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1026 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1027 return false;
1028
1029 for (i = 0; i < MAX_PIPES; i++)
1030 stream_on_link[i] = NULL;
1031
1032 /* check if there is mode change in new request */
1033 for (i = 0; i < dc_state->stream_count; i++) {
1034 struct drm_crtc_state *new_crtc_state;
1035 struct drm_connector_state *new_conn_state;
1036
1037 stream = dc_state->streams[i];
1038 if (!stream)
1039 continue;
1040
1041 /* check if stream using the same link for mst */
1042 if (stream->link != dc_link)
1043 continue;
1044
1045 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1046 if (!aconnector)
1047 continue;
1048
1049 stream_on_link[new_stream_on_link_num] = aconnector;
1050 new_stream_on_link_num++;
1051
1052 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1053 if (!new_conn_state)
1054 continue;
1055
1056 if (IS_ERR(new_conn_state))
1057 continue;
1058
1059 if (!new_conn_state->crtc)
1060 continue;
1061
1062 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1063 if (!new_crtc_state)
1064 continue;
1065
1066 if (IS_ERR(new_crtc_state))
1067 continue;
1068
1069 if (new_crtc_state->enable && new_crtc_state->active) {
1070 if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1071 new_crtc_state->connectors_changed)
1072 return true;
1073 }
1074 }
1075
1076 /* check current_state if there stream on link but it is not in
1077 * new request state
1078 */
1079 for (i = 0; i < dc->current_state->stream_count; i++) {
1080 stream = dc->current_state->streams[i];
1081 /* only check stream on the mst hub */
1082 if (stream->link != dc_link)
1083 continue;
1084
1085 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1086 if (!aconnector)
1087 continue;
1088
1089 for (j = 0; j < new_stream_on_link_num; j++) {
1090 if (stream_on_link[j]) {
1091 if (aconnector == stream_on_link[j])
1092 break;
1093 }
1094 }
1095
1096 if (j == new_stream_on_link_num) {
1097 /* not in new state */
1098 is_dsc_need_re_compute = true;
1099 break;
1100 }
1101 }
1102
1103 return is_dsc_need_re_compute;
1104 }
1105
compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1106 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1107 struct dc_state *dc_state,
1108 struct dsc_mst_fairness_vars *vars)
1109 {
1110 int i, j;
1111 struct dc_stream_state *stream;
1112 bool computed_streams[MAX_PIPES];
1113 struct amdgpu_dm_connector *aconnector;
1114 struct drm_dp_mst_topology_mgr *mst_mgr;
1115 int link_vars_start_index = 0;
1116 int ret = 0;
1117
1118 for (i = 0; i < dc_state->stream_count; i++)
1119 computed_streams[i] = false;
1120
1121 for (i = 0; i < dc_state->stream_count; i++) {
1122 stream = dc_state->streams[i];
1123
1124 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1125 continue;
1126
1127 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1128
1129 if (!aconnector || !aconnector->dc_sink || !aconnector->port)
1130 continue;
1131
1132 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1133 continue;
1134
1135 if (computed_streams[i])
1136 continue;
1137
1138 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1139 return -EINVAL;
1140
1141 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1142 continue;
1143
1144 mst_mgr = aconnector->port->mgr;
1145 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1146 &link_vars_start_index);
1147 if (ret != 0)
1148 return ret;
1149
1150 for (j = 0; j < dc_state->stream_count; j++) {
1151 if (dc_state->streams[j]->link == stream->link)
1152 computed_streams[j] = true;
1153 }
1154 }
1155
1156 for (i = 0; i < dc_state->stream_count; i++) {
1157 stream = dc_state->streams[i];
1158
1159 if (stream->timing.flags.DSC == 1)
1160 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
1161 return -EINVAL;
1162 }
1163
1164 return ret;
1165 }
1166
pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1167 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1168 struct dc_state *dc_state,
1169 struct dsc_mst_fairness_vars *vars)
1170 {
1171 int i, j;
1172 struct dc_stream_state *stream;
1173 bool computed_streams[MAX_PIPES];
1174 struct amdgpu_dm_connector *aconnector;
1175 struct drm_dp_mst_topology_mgr *mst_mgr;
1176 int link_vars_start_index = 0;
1177 int ret = 0;
1178
1179 for (i = 0; i < dc_state->stream_count; i++)
1180 computed_streams[i] = false;
1181
1182 for (i = 0; i < dc_state->stream_count; i++) {
1183 stream = dc_state->streams[i];
1184
1185 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1186 continue;
1187
1188 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1189
1190 if (!aconnector || !aconnector->dc_sink || !aconnector->port)
1191 continue;
1192
1193 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1194 continue;
1195
1196 if (computed_streams[i])
1197 continue;
1198
1199 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1200 continue;
1201
1202 mst_mgr = aconnector->port->mgr;
1203 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1204 &link_vars_start_index);
1205 if (ret != 0)
1206 return ret;
1207
1208 for (j = 0; j < dc_state->stream_count; j++) {
1209 if (dc_state->streams[j]->link == stream->link)
1210 computed_streams[j] = true;
1211 }
1212 }
1213
1214 return ret;
1215 }
1216
find_crtc_index_in_state_by_stream(struct drm_atomic_state * state,struct dc_stream_state * stream)1217 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1218 struct dc_stream_state *stream)
1219 {
1220 int i;
1221 struct drm_crtc *crtc;
1222 struct drm_crtc_state *new_state, *old_state;
1223
1224 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1225 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1226
1227 if (dm_state->stream == stream)
1228 return i;
1229 }
1230 return -1;
1231 }
1232
is_link_to_dschub(struct dc_link * dc_link)1233 static bool is_link_to_dschub(struct dc_link *dc_link)
1234 {
1235 union dpcd_dsc_basic_capabilities *dsc_caps =
1236 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1237
1238 /* only check phy used by dsc mst branch */
1239 if (dc_link->type != dc_connection_mst_branch)
1240 return false;
1241
1242 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1243 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1244 return false;
1245 return true;
1246 }
1247
is_dsc_precompute_needed(struct drm_atomic_state * state)1248 static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1249 {
1250 int i;
1251 struct drm_crtc *crtc;
1252 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1253 bool ret = false;
1254
1255 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1256 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1257
1258 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1259 ret = false;
1260 break;
1261 }
1262 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1263 if (is_link_to_dschub(dm_crtc_state->stream->link))
1264 ret = true;
1265 }
1266 return ret;
1267 }
1268
pre_validate_dsc(struct drm_atomic_state * state,struct dm_atomic_state ** dm_state_ptr,struct dsc_mst_fairness_vars * vars)1269 int pre_validate_dsc(struct drm_atomic_state *state,
1270 struct dm_atomic_state **dm_state_ptr,
1271 struct dsc_mst_fairness_vars *vars)
1272 {
1273 int i;
1274 struct dm_atomic_state *dm_state;
1275 struct dc_state *local_dc_state = NULL;
1276 int ret = 0;
1277
1278 if (!is_dsc_precompute_needed(state)) {
1279 DRM_INFO_ONCE("DSC precompute is not needed.\n");
1280 return 0;
1281 }
1282 ret = dm_atomic_get_state(state, dm_state_ptr);
1283 if (ret != 0) {
1284 DRM_INFO_ONCE("dm_atomic_get_state() failed\n");
1285 return ret;
1286 }
1287 dm_state = *dm_state_ptr;
1288
1289 /*
1290 * create local vailable for dc_state. copy content of streams of dm_state->context
1291 * to local variable. make sure stream pointer of local variable not the same as stream
1292 * from dm_state->context.
1293 */
1294
1295 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL);
1296 if (!local_dc_state)
1297 return -ENOMEM;
1298
1299 for (i = 0; i < local_dc_state->stream_count; i++) {
1300 struct dc_stream_state *stream = dm_state->context->streams[i];
1301 int ind = find_crtc_index_in_state_by_stream(state, stream);
1302
1303 if (ind >= 0) {
1304 struct amdgpu_dm_connector *aconnector;
1305 struct drm_connector_state *drm_new_conn_state;
1306 struct dm_connector_state *dm_new_conn_state;
1307 struct dm_crtc_state *dm_old_crtc_state;
1308
1309 aconnector =
1310 amdgpu_dm_find_first_crtc_matching_connector(state,
1311 state->crtcs[ind].ptr);
1312 drm_new_conn_state =
1313 drm_atomic_get_new_connector_state(state,
1314 &aconnector->base);
1315 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1316 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1317
1318 local_dc_state->streams[i] =
1319 create_validate_stream_for_sink(aconnector,
1320 &state->crtcs[ind].new_state->mode,
1321 dm_new_conn_state,
1322 dm_old_crtc_state->stream);
1323 if (local_dc_state->streams[i] == NULL) {
1324 ret = -EINVAL;
1325 break;
1326 }
1327 }
1328 }
1329
1330 if (ret != 0)
1331 goto clean_exit;
1332
1333 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
1334 if (ret != 0) {
1335 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n");
1336 goto clean_exit;
1337 }
1338
1339 /*
1340 * compare local_streams -> timing with dm_state->context,
1341 * if the same set crtc_state->mode-change = 0;
1342 */
1343 for (i = 0; i < local_dc_state->stream_count; i++) {
1344 struct dc_stream_state *stream = dm_state->context->streams[i];
1345
1346 if (local_dc_state->streams[i] &&
1347 is_timing_changed(stream, local_dc_state->streams[i])) {
1348 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i);
1349 } else {
1350 int ind = find_crtc_index_in_state_by_stream(state, stream);
1351
1352 if (ind >= 0)
1353 state->crtcs[ind].new_state->mode_changed = 0;
1354 }
1355 }
1356 clean_exit:
1357 for (i = 0; i < local_dc_state->stream_count; i++) {
1358 struct dc_stream_state *stream = dm_state->context->streams[i];
1359
1360 if (local_dc_state->streams[i] != stream)
1361 dc_stream_release(local_dc_state->streams[i]);
1362 }
1363
1364 kfree(local_dc_state);
1365
1366 return ret;
1367 }
1368
kbps_from_pbn(unsigned int pbn)1369 static unsigned int kbps_from_pbn(unsigned int pbn)
1370 {
1371 unsigned int kbps = pbn;
1372
1373 kbps *= (1000000 / PEAK_FACTOR_X1000);
1374 kbps *= 8;
1375 kbps *= 54;
1376 kbps /= 64;
1377
1378 return kbps;
1379 }
1380
is_dsc_common_config_possible(struct dc_stream_state * stream,struct dc_dsc_bw_range * bw_range)1381 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1382 struct dc_dsc_bw_range *bw_range)
1383 {
1384 struct dc_dsc_policy dsc_policy = {0};
1385
1386 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
1387 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1388 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1389 dsc_policy.min_target_bpp * 16,
1390 dsc_policy.max_target_bpp * 16,
1391 &stream->sink->dsc_caps.dsc_dec_caps,
1392 &stream->timing, bw_range);
1393
1394 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
1395 }
1396 #endif /* CONFIG_DRM_AMD_DC_DCN */
1397
dm_dp_mst_is_port_support_mode(struct amdgpu_dm_connector * aconnector,struct dc_stream_state * stream)1398 enum dc_status dm_dp_mst_is_port_support_mode(
1399 struct amdgpu_dm_connector *aconnector,
1400 struct dc_stream_state *stream)
1401 {
1402 int bpp, pbn, branch_max_throughput_mps = 0;
1403 #if defined(CONFIG_DRM_AMD_DC_DCN)
1404 struct dc_link_settings cur_link_settings;
1405 unsigned int end_to_end_bw_in_kbps = 0;
1406 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
1407 unsigned int max_compressed_bw_in_kbps = 0;
1408 struct dc_dsc_bw_range bw_range = {0};
1409 struct drm_dp_mst_topology_mgr *mst_mgr;
1410
1411 /*
1412 * check if the mode could be supported if DSC pass-through is supported
1413 * AND check if there enough bandwidth available to support the mode
1414 * with DSC enabled.
1415 */
1416 if (is_dsc_common_config_possible(stream, &bw_range) &&
1417 aconnector->port->passthrough_aux) {
1418 mst_mgr = aconnector->port->mgr;
1419 mutex_lock(&mst_mgr->lock);
1420
1421 cur_link_settings = stream->link->verified_link_cap;
1422
1423 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
1424 &cur_link_settings
1425 );
1426 down_link_bw_in_kbps = kbps_from_pbn(aconnector->port->full_pbn);
1427
1428 /* pick the bottleneck */
1429 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,
1430 down_link_bw_in_kbps);
1431
1432 mutex_unlock(&mst_mgr->lock);
1433
1434 /*
1435 * use the maximum dsc compression bandwidth as the required
1436 * bandwidth for the mode
1437 */
1438 max_compressed_bw_in_kbps = bw_range.min_kbps;
1439
1440 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
1441 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");
1442 return DC_FAIL_BANDWIDTH_VALIDATE;
1443 }
1444 } else {
1445 #endif
1446 /* check if mode could be supported within full_pbn */
1447 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
1448 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
1449
1450 if (pbn > aconnector->port->full_pbn)
1451 return DC_FAIL_BANDWIDTH_VALIDATE;
1452 #if defined(CONFIG_DRM_AMD_DC_DCN)
1453 }
1454 #endif
1455
1456 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1457 switch (stream->timing.pixel_encoding) {
1458 case PIXEL_ENCODING_RGB:
1459 case PIXEL_ENCODING_YCBCR444:
1460 branch_max_throughput_mps =
1461 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1462 break;
1463 case PIXEL_ENCODING_YCBCR422:
1464 case PIXEL_ENCODING_YCBCR420:
1465 branch_max_throughput_mps =
1466 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1467 break;
1468 default:
1469 break;
1470 }
1471
1472 if (branch_max_throughput_mps != 0 &&
1473 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000))
1474 return DC_FAIL_BANDWIDTH_VALIDATE;
1475
1476 return DC_OK;
1477 }
1478