1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
28
29 #include <linux/i2c.h>
30 #include <linux/pm_qos.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
33
34 #include <drm/display/drm_dp_dual_mode_helper.h>
35 #include <drm/display/drm_dp_mst_helper.h>
36 #include <drm/display/drm_dsc.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_encoder.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_framebuffer.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_rect.h>
44 #include <drm/drm_vblank.h>
45 #include <drm/drm_vblank_work.h>
46 #include <drm/i915_mei_hdcp_interface.h>
47 #include <media/cec-notifier.h>
48
49 #include "i915_vma.h"
50 #include "i915_vma_types.h"
51 #include "intel_bios.h"
52 #include "intel_display.h"
53 #include "intel_display_power.h"
54 #include "intel_dpll_mgr.h"
55 #include "intel_pm_types.h"
56
57 struct drm_printer;
58 struct __intel_global_objs_state;
59 struct intel_ddi_buf_trans;
60 struct intel_fbc;
61 struct intel_connector;
62
63 /*
64 * Display related stuff
65 */
66
67 /* these are outputs from the chip - integrated only
68 external chips are via DVO or SDVO output */
69 enum intel_output_type {
70 INTEL_OUTPUT_UNUSED = 0,
71 INTEL_OUTPUT_ANALOG = 1,
72 INTEL_OUTPUT_DVO = 2,
73 INTEL_OUTPUT_SDVO = 3,
74 INTEL_OUTPUT_LVDS = 4,
75 INTEL_OUTPUT_TVOUT = 5,
76 INTEL_OUTPUT_HDMI = 6,
77 INTEL_OUTPUT_DP = 7,
78 INTEL_OUTPUT_EDP = 8,
79 INTEL_OUTPUT_DSI = 9,
80 INTEL_OUTPUT_DDI = 10,
81 INTEL_OUTPUT_DP_MST = 11,
82 };
83
84 enum hdmi_force_audio {
85 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
86 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
87 HDMI_AUDIO_AUTO, /* trust EDID */
88 HDMI_AUDIO_ON, /* force turn on HDMI audio */
89 };
90
91 /* "Broadcast RGB" property */
92 enum intel_broadcast_rgb {
93 INTEL_BROADCAST_RGB_AUTO,
94 INTEL_BROADCAST_RGB_FULL,
95 INTEL_BROADCAST_RGB_LIMITED,
96 };
97
98 struct intel_fb_view {
99 /*
100 * The remap information used in the remapped and rotated views to
101 * create the DMA scatter-gather list for each FB color plane. This sg
102 * list is created along with the view type (gtt.type) specific
103 * i915_vma object and contains the list of FB object pages (reordered
104 * in the rotated view) that are visible in the view.
105 * In the normal view the FB object's backing store sg list is used
106 * directly and hence the remap information here is not used.
107 */
108 struct i915_gtt_view gtt;
109
110 /*
111 * The GTT view (gtt.type) specific information for each FB color
112 * plane. In the normal GTT view all formats (up to 4 color planes),
113 * in the rotated and remapped GTT view all no-CCS formats (up to 2
114 * color planes) are supported.
115 *
116 * The view information shared by all FB color planes in the FB,
117 * like dst x/y and src/dst width, is stored separately in
118 * intel_plane_state.
119 */
120 struct i915_color_plane_view {
121 u32 offset;
122 unsigned int x, y;
123 /*
124 * Plane stride in:
125 * bytes for 0/180 degree rotation
126 * pixels for 90/270 degree rotation
127 */
128 unsigned int mapping_stride;
129 unsigned int scanout_stride;
130 } color_plane[4];
131 };
132
133 struct intel_framebuffer {
134 struct drm_framebuffer base;
135 struct intel_frontbuffer *frontbuffer;
136
137 /* Params to remap the FB pages and program the plane registers in each view. */
138 struct intel_fb_view normal_view;
139 union {
140 struct intel_fb_view rotated_view;
141 struct intel_fb_view remapped_view;
142 };
143
144 struct i915_address_space *dpt_vm;
145 };
146
147 enum intel_hotplug_state {
148 INTEL_HOTPLUG_UNCHANGED,
149 INTEL_HOTPLUG_CHANGED,
150 INTEL_HOTPLUG_RETRY,
151 };
152
153 struct intel_encoder {
154 struct drm_encoder base;
155
156 enum intel_output_type type;
157 enum port port;
158 u16 cloneable;
159 u8 pipe_mask;
160 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
161 struct intel_connector *connector);
162 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
163 struct intel_crtc_state *,
164 struct drm_connector_state *);
165 int (*compute_config)(struct intel_encoder *,
166 struct intel_crtc_state *,
167 struct drm_connector_state *);
168 int (*compute_config_late)(struct intel_encoder *,
169 struct intel_crtc_state *,
170 struct drm_connector_state *);
171 void (*update_prepare)(struct intel_atomic_state *,
172 struct intel_encoder *,
173 struct intel_crtc *);
174 void (*pre_pll_enable)(struct intel_atomic_state *,
175 struct intel_encoder *,
176 const struct intel_crtc_state *,
177 const struct drm_connector_state *);
178 void (*pre_enable)(struct intel_atomic_state *,
179 struct intel_encoder *,
180 const struct intel_crtc_state *,
181 const struct drm_connector_state *);
182 void (*enable)(struct intel_atomic_state *,
183 struct intel_encoder *,
184 const struct intel_crtc_state *,
185 const struct drm_connector_state *);
186 void (*update_complete)(struct intel_atomic_state *,
187 struct intel_encoder *,
188 struct intel_crtc *);
189 void (*disable)(struct intel_atomic_state *,
190 struct intel_encoder *,
191 const struct intel_crtc_state *,
192 const struct drm_connector_state *);
193 void (*post_disable)(struct intel_atomic_state *,
194 struct intel_encoder *,
195 const struct intel_crtc_state *,
196 const struct drm_connector_state *);
197 void (*post_pll_disable)(struct intel_atomic_state *,
198 struct intel_encoder *,
199 const struct intel_crtc_state *,
200 const struct drm_connector_state *);
201 void (*update_pipe)(struct intel_atomic_state *,
202 struct intel_encoder *,
203 const struct intel_crtc_state *,
204 const struct drm_connector_state *);
205 /* Read out the current hw state of this connector, returning true if
206 * the encoder is active. If the encoder is enabled it also set the pipe
207 * it is connected to in the pipe parameter. */
208 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
209 /* Reconstructs the equivalent mode flags for the current hardware
210 * state. This must be called _after_ display->get_pipe_config has
211 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
212 * be set correctly before calling this function. */
213 void (*get_config)(struct intel_encoder *,
214 struct intel_crtc_state *pipe_config);
215
216 /*
217 * Optional hook called during init/resume to sync any state
218 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
219 */
220 void (*sync_state)(struct intel_encoder *encoder,
221 const struct intel_crtc_state *crtc_state);
222
223 /*
224 * Optional hook, returning true if this encoder allows a fastset
225 * during the initial commit, false otherwise.
226 */
227 bool (*initial_fastset_check)(struct intel_encoder *encoder,
228 struct intel_crtc_state *crtc_state);
229
230 /*
231 * Acquires the power domains needed for an active encoder during
232 * hardware state readout.
233 */
234 void (*get_power_domains)(struct intel_encoder *encoder,
235 struct intel_crtc_state *crtc_state);
236 /*
237 * Called during system suspend after all pending requests for the
238 * encoder are flushed (for example for DP AUX transactions) and
239 * device interrupts are disabled.
240 */
241 void (*suspend)(struct intel_encoder *);
242 /*
243 * Called during system reboot/shutdown after all the
244 * encoders have been disabled and suspended.
245 */
246 void (*shutdown)(struct intel_encoder *encoder);
247 /*
248 * Enable/disable the clock to the port.
249 */
250 void (*enable_clock)(struct intel_encoder *encoder,
251 const struct intel_crtc_state *crtc_state);
252 void (*disable_clock)(struct intel_encoder *encoder);
253 /*
254 * Returns whether the port clock is enabled or not.
255 */
256 bool (*is_clock_enabled)(struct intel_encoder *encoder);
257 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
258 const struct intel_crtc_state *crtc_state,
259 int *n_entries);
260 void (*set_signal_levels)(struct intel_encoder *encoder,
261 const struct intel_crtc_state *crtc_state);
262
263 enum hpd_pin hpd_pin;
264 enum intel_display_power_domain power_domain;
265 /* for communication with audio component; protected by av_mutex */
266 const struct drm_connector *audio_connector;
267
268 /* VBT information for this encoder (may be NULL for older platforms) */
269 const struct intel_bios_encoder_data *devdata;
270 };
271
272 struct intel_panel_bl_funcs {
273 /* Connector and platform specific backlight functions */
274 int (*setup)(struct intel_connector *connector, enum pipe pipe);
275 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
276 void (*set)(const struct drm_connector_state *conn_state, u32 level);
277 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
278 void (*enable)(const struct intel_crtc_state *crtc_state,
279 const struct drm_connector_state *conn_state, u32 level);
280 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
281 };
282
283 enum drrs_type {
284 DRRS_TYPE_NONE,
285 DRRS_TYPE_STATIC,
286 DRRS_TYPE_SEAMLESS,
287 };
288
289 struct intel_vbt_panel_data {
290 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
291 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
292
293 /* Feature bits */
294 unsigned int panel_type:4;
295 unsigned int lvds_dither:1;
296 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
297
298 bool vrr;
299
300 u8 seamless_drrs_min_refresh_rate;
301 enum drrs_type drrs_type;
302
303 struct {
304 int max_link_rate;
305 int rate;
306 int lanes;
307 int preemphasis;
308 int vswing;
309 int bpp;
310 struct edp_power_seq pps;
311 u8 drrs_msa_timing_delay;
312 bool low_vswing;
313 bool initialized;
314 bool hobl;
315 } edp;
316
317 struct {
318 bool enable;
319 bool full_link;
320 bool require_aux_wakeup;
321 int idle_frames;
322 int tp1_wakeup_time_us;
323 int tp2_tp3_wakeup_time_us;
324 int psr2_tp2_tp3_wakeup_time_us;
325 } psr;
326
327 struct {
328 u16 pwm_freq_hz;
329 u16 brightness_precision_bits;
330 bool present;
331 bool active_low_pwm;
332 u8 min_brightness; /* min_brightness/255 of max */
333 u8 controller; /* brightness controller number */
334 enum intel_backlight_type type;
335 } backlight;
336
337 /* MIPI DSI */
338 struct {
339 u16 panel_id;
340 struct mipi_config *config;
341 struct mipi_pps_data *pps;
342 u16 bl_ports;
343 u16 cabc_ports;
344 u8 seq_version;
345 u32 size;
346 u8 *data;
347 const u8 *sequence[MIPI_SEQ_MAX];
348 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
349 enum drm_panel_orientation orientation;
350 } dsi;
351 };
352
353 struct intel_panel {
354 struct list_head fixed_modes;
355
356 /* backlight */
357 struct {
358 bool present;
359 u32 level;
360 u32 min;
361 u32 max;
362 bool enabled;
363 bool combination_mode; /* gen 2/4 only */
364 bool active_low_pwm;
365 bool alternate_pwm_increment; /* lpt+ */
366
367 /* PWM chip */
368 u32 pwm_level_min;
369 u32 pwm_level_max;
370 bool pwm_enabled;
371 bool util_pin_active_low; /* bxt+ */
372 u8 controller; /* bxt+ only */
373 struct pwm_device *pwm;
374 struct pwm_state pwm_state;
375
376 /* DPCD backlight */
377 union {
378 struct {
379 struct drm_edp_backlight_info info;
380 } vesa;
381 struct {
382 bool sdr_uses_aux;
383 } intel;
384 } edp;
385
386 struct backlight_device *device;
387
388 const struct intel_panel_bl_funcs *funcs;
389 const struct intel_panel_bl_funcs *pwm_funcs;
390 void (*power)(struct intel_connector *, bool enable);
391 } backlight;
392
393 struct intel_vbt_panel_data vbt;
394 };
395
396 struct intel_digital_port;
397
398 enum check_link_response {
399 HDCP_LINK_PROTECTED = 0,
400 HDCP_TOPOLOGY_CHANGE,
401 HDCP_LINK_INTEGRITY_FAILURE,
402 HDCP_REAUTH_REQUEST
403 };
404
405 /*
406 * This structure serves as a translation layer between the generic HDCP code
407 * and the bus-specific code. What that means is that HDCP over HDMI differs
408 * from HDCP over DP, so to account for these differences, we need to
409 * communicate with the receiver through this shim.
410 *
411 * For completeness, the 2 buses differ in the following ways:
412 * - DP AUX vs. DDC
413 * HDCP registers on the receiver are set via DP AUX for DP, and
414 * they are set via DDC for HDMI.
415 * - Receiver register offsets
416 * The offsets of the registers are different for DP vs. HDMI
417 * - Receiver register masks/offsets
418 * For instance, the ready bit for the KSV fifo is in a different
419 * place on DP vs HDMI
420 * - Receiver register names
421 * Seriously. In the DP spec, the 16-bit register containing
422 * downstream information is called BINFO, on HDMI it's called
423 * BSTATUS. To confuse matters further, DP has a BSTATUS register
424 * with a completely different definition.
425 * - KSV FIFO
426 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
427 * be read 3 keys at a time
428 * - Aksv output
429 * Since Aksv is hidden in hardware, there's different procedures
430 * to send it over DP AUX vs DDC
431 */
432 struct intel_hdcp_shim {
433 /* Outputs the transmitter's An and Aksv values to the receiver. */
434 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
435
436 /* Reads the receiver's key selection vector */
437 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
438
439 /*
440 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
441 * definitions are the same in the respective specs, but the names are
442 * different. Call it BSTATUS since that's the name the HDMI spec
443 * uses and it was there first.
444 */
445 int (*read_bstatus)(struct intel_digital_port *dig_port,
446 u8 *bstatus);
447
448 /* Determines whether a repeater is present downstream */
449 int (*repeater_present)(struct intel_digital_port *dig_port,
450 bool *repeater_present);
451
452 /* Reads the receiver's Ri' value */
453 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
454
455 /* Determines if the receiver's KSV FIFO is ready for consumption */
456 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
457 bool *ksv_ready);
458
459 /* Reads the ksv fifo for num_downstream devices */
460 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
461 int num_downstream, u8 *ksv_fifo);
462
463 /* Reads a 32-bit part of V' from the receiver */
464 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
465 int i, u32 *part);
466
467 /* Enables HDCP signalling on the port */
468 int (*toggle_signalling)(struct intel_digital_port *dig_port,
469 enum transcoder cpu_transcoder,
470 bool enable);
471
472 /* Enable/Disable stream encryption on DP MST Transport Link */
473 int (*stream_encryption)(struct intel_connector *connector,
474 bool enable);
475
476 /* Ensures the link is still protected */
477 bool (*check_link)(struct intel_digital_port *dig_port,
478 struct intel_connector *connector);
479
480 /* Detects panel's hdcp capability. This is optional for HDMI. */
481 int (*hdcp_capable)(struct intel_digital_port *dig_port,
482 bool *hdcp_capable);
483
484 /* HDCP adaptation(DP/HDMI) required on the port */
485 enum hdcp_wired_protocol protocol;
486
487 /* Detects whether sink is HDCP2.2 capable */
488 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
489 bool *capable);
490
491 /* Write HDCP2.2 messages */
492 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
493 void *buf, size_t size);
494
495 /* Read HDCP2.2 messages */
496 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
497 u8 msg_id, void *buf, size_t size);
498
499 /*
500 * Implementation of DP HDCP2.2 Errata for the communication of stream
501 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
502 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
503 */
504 int (*config_stream_type)(struct intel_digital_port *dig_port,
505 bool is_repeater, u8 type);
506
507 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
508 int (*stream_2_2_encryption)(struct intel_connector *connector,
509 bool enable);
510
511 /* HDCP2.2 Link Integrity Check */
512 int (*check_2_2_link)(struct intel_digital_port *dig_port,
513 struct intel_connector *connector);
514 };
515
516 struct intel_hdcp {
517 const struct intel_hdcp_shim *shim;
518 /* Mutex for hdcp state of the connector */
519 struct mutex mutex;
520 u64 value;
521 struct delayed_work check_work;
522 struct work_struct prop_work;
523
524 /* HDCP1.4 Encryption status */
525 bool hdcp_encrypted;
526
527 /* HDCP2.2 related definitions */
528 /* Flag indicates whether this connector supports HDCP2.2 or not. */
529 bool hdcp2_supported;
530
531 /* HDCP2.2 Encryption status */
532 bool hdcp2_encrypted;
533
534 /*
535 * Content Stream Type defined by content owner. TYPE0(0x0) content can
536 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
537 * content can flow only through a link protected by HDCP2.2.
538 */
539 u8 content_type;
540
541 bool is_paired;
542 bool is_repeater;
543
544 /*
545 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
546 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
547 * When it rolls over re-auth has to be triggered.
548 */
549 u32 seq_num_v;
550
551 /*
552 * Count of RepeaterAuth_Stream_Manage msg propagated.
553 * Initialized to 0 on AKE_INIT. Incremented after every successful
554 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
555 * over re-Auth has to be triggered.
556 */
557 u32 seq_num_m;
558
559 /*
560 * Work queue to signal the CP_IRQ. Used for the waiters to read the
561 * available information from HDCP DP sink.
562 */
563 wait_queue_head_t cp_irq_queue;
564 atomic_t cp_irq_count;
565 int cp_irq_count_cached;
566
567 /*
568 * HDCP register access for gen12+ need the transcoder associated.
569 * Transcoder attached to the connector could be changed at modeset.
570 * Hence caching the transcoder here.
571 */
572 enum transcoder cpu_transcoder;
573 /* Only used for DP MST stream encryption */
574 enum transcoder stream_transcoder;
575 };
576
577 struct intel_connector {
578 struct drm_connector base;
579 /*
580 * The fixed encoder this connector is connected to.
581 */
582 struct intel_encoder *encoder;
583
584 /* ACPI device id for ACPI and driver cooperation */
585 u32 acpi_device_id;
586
587 /* Reads out the current hw, returning true if the connector is enabled
588 * and active (i.e. dpms ON state). */
589 bool (*get_hw_state)(struct intel_connector *);
590
591 /* Panel info for eDP and LVDS */
592 struct intel_panel panel;
593
594 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
595 struct edid *edid;
596 struct edid *detect_edid;
597
598 /* Number of times hotplug detection was tried after an HPD interrupt */
599 int hotplug_retries;
600
601 /* since POLL and HPD connectors may use the same HPD line keep the native
602 state of connector->polled in case hotplug storm detection changes it */
603 u8 polled;
604
605 struct drm_dp_mst_port *port;
606
607 struct intel_dp *mst_port;
608
609 /* Work struct to schedule a uevent on link train failure */
610 struct work_struct modeset_retry_work;
611
612 struct intel_hdcp hdcp;
613 };
614
615 struct intel_digital_connector_state {
616 struct drm_connector_state base;
617
618 enum hdmi_force_audio force_audio;
619 int broadcast_rgb;
620 };
621
622 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
623
624 struct dpll {
625 /* given values */
626 int n;
627 int m1, m2;
628 int p1, p2;
629 /* derived values */
630 int dot;
631 int vco;
632 int m;
633 int p;
634 };
635
636 struct intel_atomic_state {
637 struct drm_atomic_state base;
638
639 intel_wakeref_t wakeref;
640
641 struct __intel_global_objs_state *global_objs;
642 int num_global_objs;
643
644 bool dpll_set, modeset;
645
646 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
647
648 /*
649 * Current watermarks can't be trusted during hardware readout, so
650 * don't bother calculating intermediate watermarks.
651 */
652 bool skip_intermediate_wm;
653
654 bool rps_interactive;
655
656 struct i915_sw_fence commit_ready;
657
658 struct llist_node freed;
659 };
660
661 struct intel_plane_state {
662 struct drm_plane_state uapi;
663
664 /*
665 * actual hardware state, the state we program to the hardware.
666 * The following members are used to verify the hardware state:
667 * During initial hw readout, they need to be copied from uapi.
668 */
669 struct {
670 struct drm_crtc *crtc;
671 struct drm_framebuffer *fb;
672
673 u16 alpha;
674 u16 pixel_blend_mode;
675 unsigned int rotation;
676 enum drm_color_encoding color_encoding;
677 enum drm_color_range color_range;
678 enum drm_scaling_filter scaling_filter;
679 } hw;
680
681 struct i915_vma *ggtt_vma;
682 struct i915_vma *dpt_vma;
683 unsigned long flags;
684 #define PLANE_HAS_FENCE BIT(0)
685
686 struct intel_fb_view view;
687
688 /* Plane pxp decryption state */
689 bool decrypt;
690
691 /* Plane state to display black pixels when pxp is borked */
692 bool force_black;
693
694 /* plane control register */
695 u32 ctl;
696
697 /* plane color control register */
698 u32 color_ctl;
699
700 /* chroma upsampler control register */
701 u32 cus_ctl;
702
703 /*
704 * scaler_id
705 * = -1 : not using a scaler
706 * >= 0 : using a scalers
707 *
708 * plane requiring a scaler:
709 * - During check_plane, its bit is set in
710 * crtc_state->scaler_state.scaler_users by calling helper function
711 * update_scaler_plane.
712 * - scaler_id indicates the scaler it got assigned.
713 *
714 * plane doesn't require a scaler:
715 * - this can happen when scaling is no more required or plane simply
716 * got disabled.
717 * - During check_plane, corresponding bit is reset in
718 * crtc_state->scaler_state.scaler_users by calling helper function
719 * update_scaler_plane.
720 */
721 int scaler_id;
722
723 /*
724 * planar_linked_plane:
725 *
726 * ICL planar formats require 2 planes that are updated as pairs.
727 * This member is used to make sure the other plane is also updated
728 * when required, and for update_slave() to find the correct
729 * plane_state to pass as argument.
730 */
731 struct intel_plane *planar_linked_plane;
732
733 /*
734 * planar_slave:
735 * If set don't update use the linked plane's state for updating
736 * this plane during atomic commit with the update_slave() callback.
737 *
738 * It's also used by the watermark code to ignore wm calculations on
739 * this plane. They're calculated by the linked plane's wm code.
740 */
741 u32 planar_slave;
742
743 struct drm_intel_sprite_colorkey ckey;
744
745 struct drm_rect psr2_sel_fetch_area;
746
747 /* Clear Color Value */
748 u64 ccval;
749
750 const char *no_fbc_reason;
751 };
752
753 struct intel_initial_plane_config {
754 struct intel_framebuffer *fb;
755 struct i915_vma *vma;
756 unsigned int tiling;
757 int size;
758 u32 base;
759 u8 rotation;
760 };
761
762 struct intel_scaler {
763 int in_use;
764 u32 mode;
765 };
766
767 struct intel_crtc_scaler_state {
768 #define SKL_NUM_SCALERS 2
769 struct intel_scaler scalers[SKL_NUM_SCALERS];
770
771 /*
772 * scaler_users: keeps track of users requesting scalers on this crtc.
773 *
774 * If a bit is set, a user is using a scaler.
775 * Here user can be a plane or crtc as defined below:
776 * bits 0-30 - plane (bit position is index from drm_plane_index)
777 * bit 31 - crtc
778 *
779 * Instead of creating a new index to cover planes and crtc, using
780 * existing drm_plane_index for planes which is well less than 31
781 * planes and bit 31 for crtc. This should be fine to cover all
782 * our platforms.
783 *
784 * intel_atomic_setup_scalers will setup available scalers to users
785 * requesting scalers. It will gracefully fail if request exceeds
786 * avilability.
787 */
788 #define SKL_CRTC_INDEX 31
789 unsigned scaler_users;
790
791 /* scaler used by crtc for panel fitting purpose */
792 int scaler_id;
793 };
794
795 /* {crtc,crtc_state}->mode_flags */
796 /* Flag to get scanline using frame time stamps */
797 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
798 /* Flag to use the scanline counter instead of the pixel counter */
799 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
800 /*
801 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
802 * is operating in command mode.
803 * Flag to use TE from DSI0 instead of VBI in command mode
804 */
805 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
806 /* Flag to use TE from DSI1 instead of VBI in command mode */
807 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
808 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
809 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
810 /* Do tricks to make vblank timestamps sane with VRR? */
811 #define I915_MODE_FLAG_VRR (1<<6)
812
813 struct intel_wm_level {
814 bool enable;
815 u32 pri_val;
816 u32 spr_val;
817 u32 cur_val;
818 u32 fbc_val;
819 };
820
821 struct intel_pipe_wm {
822 struct intel_wm_level wm[5];
823 bool fbc_wm_enabled;
824 bool pipe_enabled;
825 bool sprites_enabled;
826 bool sprites_scaled;
827 };
828
829 struct skl_wm_level {
830 u16 min_ddb_alloc;
831 u16 blocks;
832 u8 lines;
833 bool enable;
834 bool ignore_lines;
835 bool can_sagv;
836 };
837
838 struct skl_plane_wm {
839 struct skl_wm_level wm[8];
840 struct skl_wm_level uv_wm[8];
841 struct skl_wm_level trans_wm;
842 struct {
843 struct skl_wm_level wm0;
844 struct skl_wm_level trans_wm;
845 } sagv;
846 bool is_planar;
847 };
848
849 struct skl_pipe_wm {
850 struct skl_plane_wm planes[I915_MAX_PLANES];
851 bool use_sagv_wm;
852 };
853
854 enum vlv_wm_level {
855 VLV_WM_LEVEL_PM2,
856 VLV_WM_LEVEL_PM5,
857 VLV_WM_LEVEL_DDR_DVFS,
858 NUM_VLV_WM_LEVELS,
859 };
860
861 struct vlv_wm_state {
862 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
863 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
864 u8 num_levels;
865 bool cxsr;
866 };
867
868 struct vlv_fifo_state {
869 u16 plane[I915_MAX_PLANES];
870 };
871
872 enum g4x_wm_level {
873 G4X_WM_LEVEL_NORMAL,
874 G4X_WM_LEVEL_SR,
875 G4X_WM_LEVEL_HPLL,
876 NUM_G4X_WM_LEVELS,
877 };
878
879 struct g4x_wm_state {
880 struct g4x_pipe_wm wm;
881 struct g4x_sr_wm sr;
882 struct g4x_sr_wm hpll;
883 bool cxsr;
884 bool hpll_en;
885 bool fbc_en;
886 };
887
888 struct intel_crtc_wm_state {
889 union {
890 /*
891 * raw:
892 * The "raw" watermark values produced by the formula
893 * given the plane's current state. They do not consider
894 * how much FIFO is actually allocated for each plane.
895 *
896 * optimal:
897 * The "optimal" watermark values given the current
898 * state of the planes and the amount of FIFO
899 * allocated to each, ignoring any previous state
900 * of the planes.
901 *
902 * intermediate:
903 * The "intermediate" watermark values when transitioning
904 * between the old and new "optimal" values. Used when
905 * the watermark registers are single buffered and hence
906 * their state changes asynchronously with regards to the
907 * actual plane registers. These are essentially the
908 * worst case combination of the old and new "optimal"
909 * watermarks, which are therefore safe to use when the
910 * plane is in either its old or new state.
911 */
912 struct {
913 struct intel_pipe_wm intermediate;
914 struct intel_pipe_wm optimal;
915 } ilk;
916
917 struct {
918 struct skl_pipe_wm raw;
919 /* gen9+ only needs 1-step wm programming */
920 struct skl_pipe_wm optimal;
921 struct skl_ddb_entry ddb;
922 /*
923 * pre-icl: for packed/planar CbCr
924 * icl+: for everything
925 */
926 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
927 /* pre-icl: for planar Y */
928 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
929 } skl;
930
931 struct {
932 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
933 struct vlv_wm_state intermediate; /* inverted */
934 struct vlv_wm_state optimal; /* inverted */
935 struct vlv_fifo_state fifo_state;
936 } vlv;
937
938 struct {
939 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
940 struct g4x_wm_state intermediate;
941 struct g4x_wm_state optimal;
942 } g4x;
943 };
944
945 /*
946 * Platforms with two-step watermark programming will need to
947 * update watermark programming post-vblank to switch from the
948 * safe intermediate watermarks to the optimal final
949 * watermarks.
950 */
951 bool need_postvbl_update;
952 };
953
954 enum intel_output_format {
955 INTEL_OUTPUT_FORMAT_RGB,
956 INTEL_OUTPUT_FORMAT_YCBCR420,
957 INTEL_OUTPUT_FORMAT_YCBCR444,
958 };
959
960 struct intel_mpllb_state {
961 u32 clock; /* in KHz */
962 u32 ref_control;
963 u32 mpllb_cp;
964 u32 mpllb_div;
965 u32 mpllb_div2;
966 u32 mpllb_fracn1;
967 u32 mpllb_fracn2;
968 u32 mpllb_sscen;
969 u32 mpllb_sscstep;
970 };
971
972 struct intel_crtc_state {
973 /*
974 * uapi (drm) state. This is the software state shown to userspace.
975 * In particular, the following members are used for bookkeeping:
976 * - crtc
977 * - state
978 * - *_changed
979 * - event
980 * - commit
981 * - mode_blob
982 */
983 struct drm_crtc_state uapi;
984
985 /*
986 * actual hardware state, the state we program to the hardware.
987 * The following members are used to verify the hardware state:
988 * - enable
989 * - active
990 * - mode / pipe_mode / adjusted_mode
991 * - color property blobs.
992 *
993 * During initial hw readout, they need to be copied to uapi.
994 *
995 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
996 * Use the pipe_mode for calculations like watermarks, pipe
997 * scaler, and bandwidth.
998 *
999 * Use adjusted_mode for things that need to know the full
1000 * mode on the transcoder, which spans all pipes.
1001 */
1002 struct {
1003 bool active, enable;
1004 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
1005 struct drm_display_mode mode, pipe_mode, adjusted_mode;
1006 enum drm_scaling_filter scaling_filter;
1007 } hw;
1008
1009 /**
1010 * quirks - bitfield with hw state readout quirks
1011 *
1012 * For various reasons the hw state readout code might not be able to
1013 * completely faithfully read out the current state. These cases are
1014 * tracked with quirk flags so that fastboot and state checker can act
1015 * accordingly.
1016 */
1017 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
1018 unsigned long quirks;
1019
1020 unsigned fb_bits; /* framebuffers to flip */
1021 bool update_pipe; /* can a fast modeset be performed? */
1022 bool disable_cxsr;
1023 bool update_wm_pre, update_wm_post; /* watermarks are updated */
1024 bool fifo_changed; /* FIFO split is changed */
1025 bool preload_luts;
1026 bool inherited; /* state inherited from BIOS? */
1027
1028 /* Ask the hardware to actually async flip? */
1029 bool do_async_flip;
1030
1031 /* Pipe source size (ie. panel fitter input size)
1032 * All planes will be positioned inside this space,
1033 * and get clipped at the edges. */
1034 struct drm_rect pipe_src;
1035
1036 /*
1037 * Pipe pixel rate, adjusted for
1038 * panel fitter/pipe scaler downscaling.
1039 */
1040 unsigned int pixel_rate;
1041
1042 /* Whether to set up the PCH/FDI. Note that we never allow sharing
1043 * between pch encoders and cpu encoders. */
1044 bool has_pch_encoder;
1045
1046 /* Are we sending infoframes on the attached port */
1047 bool has_infoframe;
1048
1049 /* CPU Transcoder for the pipe. Currently this can only differ from the
1050 * pipe on Haswell and later (where we have a special eDP transcoder)
1051 * and Broxton (where we have special DSI transcoders). */
1052 enum transcoder cpu_transcoder;
1053
1054 /*
1055 * Use reduced/limited/broadcast rbg range, compressing from the full
1056 * range fed into the crtcs.
1057 */
1058 bool limited_color_range;
1059
1060 /* Bitmask of encoder types (enum intel_output_type)
1061 * driven by the pipe.
1062 */
1063 unsigned int output_types;
1064
1065 /* Whether we should send NULL infoframes. Required for audio. */
1066 bool has_hdmi_sink;
1067
1068 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1069 * has_dp_encoder is set. */
1070 bool has_audio;
1071
1072 /*
1073 * Enable dithering, used when the selected pipe bpp doesn't match the
1074 * plane bpp.
1075 */
1076 bool dither;
1077
1078 /*
1079 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1080 * compliance video pattern tests.
1081 * Disable dither only if it is a compliance test request for
1082 * 18bpp.
1083 */
1084 bool dither_force_disable;
1085
1086 /* Controls for the clock computation, to override various stages. */
1087 bool clock_set;
1088
1089 /* SDVO TV has a bunch of special case. To make multifunction encoders
1090 * work correctly, we need to track this at runtime.*/
1091 bool sdvo_tv_clock;
1092
1093 /*
1094 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1095 * required. This is set in the 2nd loop of calling encoder's
1096 * ->compute_config if the first pick doesn't work out.
1097 */
1098 bool bw_constrained;
1099
1100 /* Settings for the intel dpll used on pretty much everything but
1101 * haswell. */
1102 struct dpll dpll;
1103
1104 /* Selected dpll when shared or NULL. */
1105 struct intel_shared_dpll *shared_dpll;
1106
1107 /* Actual register state of the dpll, for shared dpll cross-checking. */
1108 union {
1109 struct intel_dpll_hw_state dpll_hw_state;
1110 struct intel_mpllb_state mpllb_state;
1111 };
1112
1113 /*
1114 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1115 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1116 */
1117 struct icl_port_dpll {
1118 struct intel_shared_dpll *pll;
1119 struct intel_dpll_hw_state hw_state;
1120 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1121
1122 /* DSI PLL registers */
1123 struct {
1124 u32 ctrl, div;
1125 } dsi_pll;
1126
1127 int pipe_bpp;
1128 struct intel_link_m_n dp_m_n;
1129
1130 /* m2_n2 for eDP downclock */
1131 struct intel_link_m_n dp_m2_n2;
1132 bool has_drrs;
1133 bool seamless_m_n;
1134
1135 /* PSR is supported but might not be enabled due the lack of enabled planes */
1136 bool has_psr;
1137 bool has_psr2;
1138 bool enable_psr2_sel_fetch;
1139 bool req_psr2_sdp_prior_scanline;
1140 u32 dc3co_exitline;
1141 u16 su_y_granularity;
1142 struct drm_dp_vsc_sdp psr_vsc;
1143
1144 /*
1145 * Frequence the dpll for the port should run at. Differs from the
1146 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1147 * already multiplied by pixel_multiplier.
1148 */
1149 int port_clock;
1150
1151 /* Used by SDVO (and if we ever fix it, HDMI). */
1152 unsigned pixel_multiplier;
1153
1154 /* I915_MODE_FLAG_* */
1155 u8 mode_flags;
1156
1157 u8 lane_count;
1158
1159 /*
1160 * Used by platforms having DP/HDMI PHY with programmable lane
1161 * latency optimization.
1162 */
1163 u8 lane_lat_optim_mask;
1164
1165 /* minimum acceptable voltage level */
1166 u8 min_voltage_level;
1167
1168 /* Panel fitter controls for gen2-gen4 + VLV */
1169 struct {
1170 u32 control;
1171 u32 pgm_ratios;
1172 u32 lvds_border_bits;
1173 } gmch_pfit;
1174
1175 /* Panel fitter placement and size for Ironlake+ */
1176 struct {
1177 struct drm_rect dst;
1178 bool enabled;
1179 bool force_thru;
1180 } pch_pfit;
1181
1182 /* FDI configuration, only valid if has_pch_encoder is set. */
1183 int fdi_lanes;
1184 struct intel_link_m_n fdi_m_n;
1185
1186 bool ips_enabled;
1187
1188 bool crc_enabled;
1189
1190 bool double_wide;
1191
1192 int pbn;
1193
1194 struct intel_crtc_scaler_state scaler_state;
1195
1196 /* w/a for waiting 2 vblanks during crtc enable */
1197 enum pipe hsw_workaround_pipe;
1198
1199 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1200 bool disable_lp_wm;
1201
1202 struct intel_crtc_wm_state wm;
1203
1204 int min_cdclk[I915_MAX_PLANES];
1205
1206 /* for packed/planar CbCr */
1207 u32 data_rate[I915_MAX_PLANES];
1208 /* for planar Y */
1209 u32 data_rate_y[I915_MAX_PLANES];
1210
1211 /* FIXME unify with data_rate[]? */
1212 u64 rel_data_rate[I915_MAX_PLANES];
1213 u64 rel_data_rate_y[I915_MAX_PLANES];
1214
1215 /* Gamma mode programmed on the pipe */
1216 u32 gamma_mode;
1217
1218 union {
1219 /* CSC mode programmed on the pipe */
1220 u32 csc_mode;
1221
1222 /* CHV CGM mode */
1223 u32 cgm_mode;
1224 };
1225
1226 /* bitmask of logically enabled planes (enum plane_id) */
1227 u8 enabled_planes;
1228
1229 /* bitmask of actually visible planes (enum plane_id) */
1230 u8 active_planes;
1231 u8 scaled_planes;
1232 u8 nv12_planes;
1233 u8 c8_planes;
1234
1235 /* bitmask of planes that will be updated during the commit */
1236 u8 update_planes;
1237
1238 u8 framestart_delay; /* 1-4 */
1239 u8 msa_timing_delay; /* 0-3 */
1240
1241 struct {
1242 u32 enable;
1243 u32 gcp;
1244 union hdmi_infoframe avi;
1245 union hdmi_infoframe spd;
1246 union hdmi_infoframe hdmi;
1247 union hdmi_infoframe drm;
1248 struct drm_dp_vsc_sdp vsc;
1249 } infoframes;
1250
1251 /* HDMI scrambling status */
1252 bool hdmi_scrambling;
1253
1254 /* HDMI High TMDS char rate ratio */
1255 bool hdmi_high_tmds_clock_ratio;
1256
1257 /* Output format RGB/YCBCR etc */
1258 enum intel_output_format output_format;
1259
1260 /* enable pipe gamma? */
1261 bool gamma_enable;
1262
1263 /* enable pipe csc? */
1264 bool csc_enable;
1265
1266 /* big joiner pipe bitmask */
1267 u8 bigjoiner_pipes;
1268
1269 /* Display Stream compression state */
1270 struct {
1271 bool compression_enable;
1272 bool dsc_split;
1273 u16 compressed_bpp;
1274 u8 slice_count;
1275 struct drm_dsc_config config;
1276 } dsc;
1277
1278 /* HSW+ linetime watermarks */
1279 u16 linetime;
1280 u16 ips_linetime;
1281
1282 /* Forward Error correction State */
1283 bool fec_enable;
1284
1285 /* Pointer to master transcoder in case of tiled displays */
1286 enum transcoder master_transcoder;
1287
1288 /* Bitmask to indicate slaves attached */
1289 u8 sync_mode_slaves_mask;
1290
1291 /* Only valid on TGL+ */
1292 enum transcoder mst_master_transcoder;
1293
1294 /* For DSB related info */
1295 struct intel_dsb *dsb;
1296
1297 u32 psr2_man_track_ctl;
1298
1299 /* Variable Refresh Rate state */
1300 struct {
1301 bool enable;
1302 u8 pipeline_full;
1303 u16 flipline, vmin, vmax, guardband;
1304 } vrr;
1305
1306 /* Stream Splitter for eDP MSO */
1307 struct {
1308 bool enable;
1309 u8 link_count;
1310 u8 pixel_overlap;
1311 } splitter;
1312
1313 /* for loading single buffered registers during vblank */
1314 struct drm_vblank_work vblank_work;
1315 };
1316
1317 enum intel_pipe_crc_source {
1318 INTEL_PIPE_CRC_SOURCE_NONE,
1319 INTEL_PIPE_CRC_SOURCE_PLANE1,
1320 INTEL_PIPE_CRC_SOURCE_PLANE2,
1321 INTEL_PIPE_CRC_SOURCE_PLANE3,
1322 INTEL_PIPE_CRC_SOURCE_PLANE4,
1323 INTEL_PIPE_CRC_SOURCE_PLANE5,
1324 INTEL_PIPE_CRC_SOURCE_PLANE6,
1325 INTEL_PIPE_CRC_SOURCE_PLANE7,
1326 INTEL_PIPE_CRC_SOURCE_PIPE,
1327 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1328 INTEL_PIPE_CRC_SOURCE_TV,
1329 INTEL_PIPE_CRC_SOURCE_DP_B,
1330 INTEL_PIPE_CRC_SOURCE_DP_C,
1331 INTEL_PIPE_CRC_SOURCE_DP_D,
1332 INTEL_PIPE_CRC_SOURCE_AUTO,
1333 INTEL_PIPE_CRC_SOURCE_MAX,
1334 };
1335
1336 enum drrs_refresh_rate {
1337 DRRS_REFRESH_RATE_HIGH,
1338 DRRS_REFRESH_RATE_LOW,
1339 };
1340
1341 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1342 struct intel_pipe_crc {
1343 spinlock_t lock;
1344 int skipped;
1345 enum intel_pipe_crc_source source;
1346 };
1347
1348 struct intel_crtc {
1349 struct drm_crtc base;
1350 enum pipe pipe;
1351 /*
1352 * Whether the crtc and the connected output pipeline is active. Implies
1353 * that crtc->enabled is set, i.e. the current mode configuration has
1354 * some outputs connected to this crtc.
1355 */
1356 bool active;
1357 u8 plane_ids_mask;
1358
1359 /* I915_MODE_FLAG_* */
1360 u8 mode_flags;
1361
1362 u16 vmax_vblank_start;
1363
1364 struct intel_display_power_domain_set enabled_power_domains;
1365 struct intel_overlay *overlay;
1366
1367 struct intel_crtc_state *config;
1368
1369 /* Access to these should be protected by dev_priv->irq_lock. */
1370 bool cpu_fifo_underrun_disabled;
1371 bool pch_fifo_underrun_disabled;
1372
1373 /* per-pipe watermark state */
1374 struct {
1375 /* watermarks currently being used */
1376 union {
1377 struct intel_pipe_wm ilk;
1378 struct vlv_wm_state vlv;
1379 struct g4x_wm_state g4x;
1380 } active;
1381 } wm;
1382
1383 struct {
1384 struct mutex mutex;
1385 struct delayed_work work;
1386 enum drrs_refresh_rate refresh_rate;
1387 unsigned int frontbuffer_bits;
1388 unsigned int busy_frontbuffer_bits;
1389 enum transcoder cpu_transcoder;
1390 struct intel_link_m_n m_n, m2_n2;
1391 } drrs;
1392
1393 int scanline_offset;
1394
1395 struct {
1396 unsigned start_vbl_count;
1397 ktime_t start_vbl_time;
1398 int min_vbl, max_vbl;
1399 int scanline_start;
1400 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1401 struct {
1402 u64 min;
1403 u64 max;
1404 u64 sum;
1405 unsigned int over;
1406 unsigned int times[17]; /* [1us, 16ms] */
1407 } vbl;
1408 #endif
1409 } debug;
1410
1411 /* scalers available on this crtc */
1412 int num_scalers;
1413
1414 /* for loading single buffered registers during vblank */
1415 struct pm_qos_request vblank_pm_qos;
1416
1417 #ifdef CONFIG_DEBUG_FS
1418 struct intel_pipe_crc pipe_crc;
1419 #endif
1420 };
1421
1422 struct intel_plane {
1423 struct drm_plane base;
1424 enum i9xx_plane_id i9xx_plane;
1425 enum plane_id id;
1426 enum pipe pipe;
1427 bool need_async_flip_disable_wa;
1428 u32 frontbuffer_bit;
1429
1430 struct {
1431 u32 base, cntl, size;
1432 } cursor;
1433
1434 struct intel_fbc *fbc;
1435
1436 /*
1437 * NOTE: Do not place new plane state fields here (e.g., when adding
1438 * new plane properties). New runtime state should now be placed in
1439 * the intel_plane_state structure and accessed via plane_state.
1440 */
1441
1442 int (*min_width)(const struct drm_framebuffer *fb,
1443 int color_plane,
1444 unsigned int rotation);
1445 int (*max_width)(const struct drm_framebuffer *fb,
1446 int color_plane,
1447 unsigned int rotation);
1448 int (*max_height)(const struct drm_framebuffer *fb,
1449 int color_plane,
1450 unsigned int rotation);
1451 unsigned int (*max_stride)(struct intel_plane *plane,
1452 u32 pixel_format, u64 modifier,
1453 unsigned int rotation);
1454 /* Write all non-self arming plane registers */
1455 void (*update_noarm)(struct intel_plane *plane,
1456 const struct intel_crtc_state *crtc_state,
1457 const struct intel_plane_state *plane_state);
1458 /* Write all self-arming plane registers */
1459 void (*update_arm)(struct intel_plane *plane,
1460 const struct intel_crtc_state *crtc_state,
1461 const struct intel_plane_state *plane_state);
1462 /* Disable the plane, must arm */
1463 void (*disable_arm)(struct intel_plane *plane,
1464 const struct intel_crtc_state *crtc_state);
1465 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1466 int (*check_plane)(struct intel_crtc_state *crtc_state,
1467 struct intel_plane_state *plane_state);
1468 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1469 const struct intel_plane_state *plane_state);
1470 void (*async_flip)(struct intel_plane *plane,
1471 const struct intel_crtc_state *crtc_state,
1472 const struct intel_plane_state *plane_state,
1473 bool async_flip);
1474 void (*enable_flip_done)(struct intel_plane *plane);
1475 void (*disable_flip_done)(struct intel_plane *plane);
1476 };
1477
1478 struct intel_watermark_params {
1479 u16 fifo_size;
1480 u16 max_wm;
1481 u8 default_wm;
1482 u8 guard_size;
1483 u8 cacheline_size;
1484 };
1485
1486 struct cxsr_latency {
1487 bool is_desktop : 1;
1488 bool is_ddr3 : 1;
1489 u16 fsb_freq;
1490 u16 mem_freq;
1491 u16 display_sr;
1492 u16 display_hpll_disable;
1493 u16 cursor_sr;
1494 u16 cursor_hpll_disable;
1495 };
1496
1497 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1498 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1499 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1500 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1501 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1502 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1503 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1504 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1505 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1506
1507 struct intel_hdmi {
1508 i915_reg_t hdmi_reg;
1509 int ddc_bus;
1510 struct {
1511 enum drm_dp_dual_mode_type type;
1512 int max_tmds_clock;
1513 } dp_dual_mode;
1514 bool has_hdmi_sink;
1515 bool has_audio;
1516 struct intel_connector *attached_connector;
1517 struct cec_notifier *cec_notifier;
1518 };
1519
1520 struct intel_dp_mst_encoder;
1521
1522 struct intel_dp_compliance_data {
1523 unsigned long edid;
1524 u8 video_pattern;
1525 u16 hdisplay, vdisplay;
1526 u8 bpc;
1527 struct drm_dp_phy_test_params phytest;
1528 };
1529
1530 struct intel_dp_compliance {
1531 unsigned long test_type;
1532 struct intel_dp_compliance_data test_data;
1533 bool test_active;
1534 int test_link_rate;
1535 u8 test_lane_count;
1536 };
1537
1538 struct intel_dp_pcon_frl {
1539 bool is_trained;
1540 int trained_rate_gbps;
1541 };
1542
1543 struct intel_pps {
1544 int panel_power_up_delay;
1545 int panel_power_down_delay;
1546 int panel_power_cycle_delay;
1547 int backlight_on_delay;
1548 int backlight_off_delay;
1549 struct delayed_work panel_vdd_work;
1550 bool want_panel_vdd;
1551 bool initializing;
1552 unsigned long last_power_on;
1553 unsigned long last_backlight_off;
1554 ktime_t panel_power_off_time;
1555 intel_wakeref_t vdd_wakeref;
1556
1557 /*
1558 * Pipe whose power sequencer is currently locked into
1559 * this port. Only relevant on VLV/CHV.
1560 */
1561 enum pipe pps_pipe;
1562 /*
1563 * Pipe currently driving the port. Used for preventing
1564 * the use of the PPS for any pipe currentrly driving
1565 * external DP as that will mess things up on VLV.
1566 */
1567 enum pipe active_pipe;
1568 /*
1569 * Set if the sequencer may be reset due to a power transition,
1570 * requiring a reinitialization. Only relevant on BXT.
1571 */
1572 bool pps_reset;
1573 struct edp_power_seq pps_delays;
1574 struct edp_power_seq bios_pps_delays;
1575 };
1576
1577 struct intel_psr {
1578 /* Mutex for PSR state of the transcoder */
1579 struct mutex lock;
1580
1581 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1582 #define I915_PSR_DEBUG_DEFAULT 0x00
1583 #define I915_PSR_DEBUG_DISABLE 0x01
1584 #define I915_PSR_DEBUG_ENABLE 0x02
1585 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1586 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1587 #define I915_PSR_DEBUG_IRQ 0x10
1588
1589 u32 debug;
1590 bool sink_support;
1591 bool source_support;
1592 bool enabled;
1593 bool paused;
1594 enum pipe pipe;
1595 enum transcoder transcoder;
1596 bool active;
1597 struct work_struct work;
1598 unsigned int busy_frontbuffer_bits;
1599 bool sink_psr2_support;
1600 bool link_standby;
1601 bool colorimetry_support;
1602 bool psr2_enabled;
1603 bool psr2_sel_fetch_enabled;
1604 bool psr2_sel_fetch_cff_enabled;
1605 bool req_psr2_sdp_prior_scanline;
1606 u8 sink_sync_latency;
1607 ktime_t last_entry_attempt;
1608 ktime_t last_exit;
1609 bool sink_not_reliable;
1610 bool irq_aux_error;
1611 u16 su_w_granularity;
1612 u16 su_y_granularity;
1613 u32 dc3co_exitline;
1614 u32 dc3co_exit_delay;
1615 struct delayed_work dc3co_work;
1616 };
1617
1618 struct intel_dp {
1619 i915_reg_t output_reg;
1620 u32 DP;
1621 int link_rate;
1622 u8 lane_count;
1623 u8 sink_count;
1624 bool link_trained;
1625 bool has_hdmi_sink;
1626 bool has_audio;
1627 bool reset_link_params;
1628 bool use_max_params;
1629 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1630 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1631 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1632 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1633 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1634 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1635 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1636 u8 fec_capable;
1637 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1638 /* source rates */
1639 int num_source_rates;
1640 const int *source_rates;
1641 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1642 int num_sink_rates;
1643 int sink_rates[DP_MAX_SUPPORTED_RATES];
1644 bool use_rate_select;
1645 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1646 int max_sink_lane_count;
1647 /* intersection of source and sink rates */
1648 int num_common_rates;
1649 int common_rates[DP_MAX_SUPPORTED_RATES];
1650 /* Max lane count for the current link */
1651 int max_link_lane_count;
1652 /* Max rate for the current link */
1653 int max_link_rate;
1654 int mso_link_count;
1655 int mso_pixel_overlap;
1656 /* sink or branch descriptor */
1657 struct drm_dp_desc desc;
1658 struct drm_dp_aux aux;
1659 u32 aux_busy_last_status;
1660 u8 train_set[4];
1661
1662 struct intel_pps pps;
1663
1664 bool is_mst;
1665 int active_mst_links;
1666
1667 /* connector directly attached - won't be use for modeset in mst world */
1668 struct intel_connector *attached_connector;
1669
1670 /* mst connector list */
1671 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1672 struct drm_dp_mst_topology_mgr mst_mgr;
1673
1674 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1675 /*
1676 * This function returns the value we have to program the AUX_CTL
1677 * register with to kick off an AUX transaction.
1678 */
1679 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1680 u32 aux_clock_divider);
1681
1682 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1683 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1684
1685 /* This is called before a link training is starterd */
1686 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1687 const struct intel_crtc_state *crtc_state);
1688 void (*set_link_train)(struct intel_dp *intel_dp,
1689 const struct intel_crtc_state *crtc_state,
1690 u8 dp_train_pat);
1691 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1692 const struct intel_crtc_state *crtc_state);
1693
1694 u8 (*preemph_max)(struct intel_dp *intel_dp);
1695 u8 (*voltage_max)(struct intel_dp *intel_dp,
1696 const struct intel_crtc_state *crtc_state);
1697
1698 /* Displayport compliance testing */
1699 struct intel_dp_compliance compliance;
1700
1701 /* Downstream facing port caps */
1702 struct {
1703 int min_tmds_clock, max_tmds_clock;
1704 int max_dotclock;
1705 int pcon_max_frl_bw;
1706 u8 max_bpc;
1707 bool ycbcr_444_to_420;
1708 bool rgb_to_ycbcr;
1709 } dfp;
1710
1711 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1712 struct pm_qos_request pm_qos;
1713
1714 /* Display stream compression testing */
1715 bool force_dsc_en;
1716 int force_dsc_bpc;
1717
1718 bool hobl_failed;
1719 bool hobl_active;
1720
1721 struct intel_dp_pcon_frl frl;
1722
1723 struct intel_psr psr;
1724
1725 /* When we last wrote the OUI for eDP */
1726 unsigned long last_oui_write;
1727 };
1728
1729 enum lspcon_vendor {
1730 LSPCON_VENDOR_MCA,
1731 LSPCON_VENDOR_PARADE
1732 };
1733
1734 struct intel_lspcon {
1735 bool active;
1736 bool hdr_supported;
1737 enum drm_lspcon_mode mode;
1738 enum lspcon_vendor vendor;
1739 };
1740
1741 struct intel_digital_port {
1742 struct intel_encoder base;
1743 u32 saved_port_bits;
1744 struct intel_dp dp;
1745 struct intel_hdmi hdmi;
1746 struct intel_lspcon lspcon;
1747 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1748 bool release_cl2_override;
1749 u8 max_lanes;
1750 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1751 enum aux_ch aux_ch;
1752 enum intel_display_power_domain ddi_io_power_domain;
1753 intel_wakeref_t ddi_io_wakeref;
1754 intel_wakeref_t aux_wakeref;
1755
1756 struct mutex tc_lock; /* protects the TypeC port mode */
1757 intel_wakeref_t tc_lock_wakeref;
1758 enum intel_display_power_domain tc_lock_power_domain;
1759 struct delayed_work tc_disconnect_phy_work;
1760 int tc_link_refcount;
1761 bool tc_legacy_port:1;
1762 char tc_port_name[8];
1763 enum tc_port_mode tc_mode;
1764 enum phy_fia tc_phy_fia;
1765 u8 tc_phy_fia_idx;
1766
1767 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1768 struct mutex hdcp_mutex;
1769 /* the number of pipes using HDCP signalling out of this port */
1770 unsigned int num_hdcp_streams;
1771 /* port HDCP auth status */
1772 bool hdcp_auth_status;
1773 /* HDCP port data need to pass to security f/w */
1774 struct hdcp_port_data hdcp_port_data;
1775 /* Whether the MST topology supports HDCP Type 1 Content */
1776 bool hdcp_mst_type1_capable;
1777
1778 void (*write_infoframe)(struct intel_encoder *encoder,
1779 const struct intel_crtc_state *crtc_state,
1780 unsigned int type,
1781 const void *frame, ssize_t len);
1782 void (*read_infoframe)(struct intel_encoder *encoder,
1783 const struct intel_crtc_state *crtc_state,
1784 unsigned int type,
1785 void *frame, ssize_t len);
1786 void (*set_infoframes)(struct intel_encoder *encoder,
1787 bool enable,
1788 const struct intel_crtc_state *crtc_state,
1789 const struct drm_connector_state *conn_state);
1790 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1791 const struct intel_crtc_state *pipe_config);
1792 bool (*connected)(struct intel_encoder *encoder);
1793 };
1794
1795 struct intel_dp_mst_encoder {
1796 struct intel_encoder base;
1797 enum pipe pipe;
1798 struct intel_digital_port *primary;
1799 struct intel_connector *connector;
1800 };
1801
1802 static inline enum dpio_channel
vlv_dig_port_to_channel(struct intel_digital_port * dig_port)1803 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1804 {
1805 switch (dig_port->base.port) {
1806 default:
1807 MISSING_CASE(dig_port->base.port);
1808 fallthrough;
1809 case PORT_B:
1810 case PORT_D:
1811 return DPIO_CH0;
1812 case PORT_C:
1813 return DPIO_CH1;
1814 }
1815 }
1816
1817 static inline enum dpio_phy
vlv_dig_port_to_phy(struct intel_digital_port * dig_port)1818 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1819 {
1820 switch (dig_port->base.port) {
1821 default:
1822 MISSING_CASE(dig_port->base.port);
1823 fallthrough;
1824 case PORT_B:
1825 case PORT_C:
1826 return DPIO_PHY0;
1827 case PORT_D:
1828 return DPIO_PHY1;
1829 }
1830 }
1831
1832 static inline enum dpio_channel
vlv_pipe_to_channel(enum pipe pipe)1833 vlv_pipe_to_channel(enum pipe pipe)
1834 {
1835 switch (pipe) {
1836 default:
1837 MISSING_CASE(pipe);
1838 fallthrough;
1839 case PIPE_A:
1840 case PIPE_C:
1841 return DPIO_CH0;
1842 case PIPE_B:
1843 return DPIO_CH1;
1844 }
1845 }
1846
1847 struct intel_load_detect_pipe {
1848 struct drm_atomic_state *restore_state;
1849 };
1850
1851 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1852 intel_attached_encoder(struct intel_connector *connector)
1853 {
1854 return connector->encoder;
1855 }
1856
intel_encoder_is_dig_port(struct intel_encoder * encoder)1857 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1858 {
1859 switch (encoder->type) {
1860 case INTEL_OUTPUT_DDI:
1861 case INTEL_OUTPUT_DP:
1862 case INTEL_OUTPUT_EDP:
1863 case INTEL_OUTPUT_HDMI:
1864 return true;
1865 default:
1866 return false;
1867 }
1868 }
1869
intel_encoder_is_mst(struct intel_encoder * encoder)1870 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1871 {
1872 return encoder->type == INTEL_OUTPUT_DP_MST;
1873 }
1874
1875 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)1876 enc_to_mst(struct intel_encoder *encoder)
1877 {
1878 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1879 base.base);
1880 }
1881
1882 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)1883 enc_to_dig_port(struct intel_encoder *encoder)
1884 {
1885 struct intel_encoder *intel_encoder = encoder;
1886
1887 if (intel_encoder_is_dig_port(intel_encoder))
1888 return container_of(&encoder->base, struct intel_digital_port,
1889 base.base);
1890 else if (intel_encoder_is_mst(intel_encoder))
1891 return enc_to_mst(encoder)->primary;
1892 else
1893 return NULL;
1894 }
1895
1896 static inline struct intel_digital_port *
intel_attached_dig_port(struct intel_connector * connector)1897 intel_attached_dig_port(struct intel_connector *connector)
1898 {
1899 return enc_to_dig_port(intel_attached_encoder(connector));
1900 }
1901
1902 static inline struct intel_hdmi *
enc_to_intel_hdmi(struct intel_encoder * encoder)1903 enc_to_intel_hdmi(struct intel_encoder *encoder)
1904 {
1905 return &enc_to_dig_port(encoder)->hdmi;
1906 }
1907
1908 static inline struct intel_hdmi *
intel_attached_hdmi(struct intel_connector * connector)1909 intel_attached_hdmi(struct intel_connector *connector)
1910 {
1911 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1912 }
1913
enc_to_intel_dp(struct intel_encoder * encoder)1914 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1915 {
1916 return &enc_to_dig_port(encoder)->dp;
1917 }
1918
intel_attached_dp(struct intel_connector * connector)1919 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1920 {
1921 return enc_to_intel_dp(intel_attached_encoder(connector));
1922 }
1923
intel_encoder_is_dp(struct intel_encoder * encoder)1924 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1925 {
1926 switch (encoder->type) {
1927 case INTEL_OUTPUT_DP:
1928 case INTEL_OUTPUT_EDP:
1929 return true;
1930 case INTEL_OUTPUT_DDI:
1931 /* Skip pure HDMI/DVI DDI encoders */
1932 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1933 default:
1934 return false;
1935 }
1936 }
1937
1938 static inline struct intel_lspcon *
enc_to_intel_lspcon(struct intel_encoder * encoder)1939 enc_to_intel_lspcon(struct intel_encoder *encoder)
1940 {
1941 return &enc_to_dig_port(encoder)->lspcon;
1942 }
1943
1944 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)1945 dp_to_dig_port(struct intel_dp *intel_dp)
1946 {
1947 return container_of(intel_dp, struct intel_digital_port, dp);
1948 }
1949
1950 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)1951 dp_to_lspcon(struct intel_dp *intel_dp)
1952 {
1953 return &dp_to_dig_port(intel_dp)->lspcon;
1954 }
1955
1956 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
1957
1958 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1959 (intel_dp)->psr.source_support)
1960
intel_encoder_can_psr(struct intel_encoder * encoder)1961 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
1962 {
1963 if (!intel_encoder_is_dp(encoder))
1964 return false;
1965
1966 return CAN_PSR(enc_to_intel_dp(encoder));
1967 }
1968
1969 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)1970 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1971 {
1972 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1973 }
1974
1975 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1976 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1977 struct intel_plane *plane)
1978 {
1979 struct drm_plane_state *ret =
1980 drm_atomic_get_plane_state(&state->base, &plane->base);
1981
1982 if (IS_ERR(ret))
1983 return ERR_CAST(ret);
1984
1985 return to_intel_plane_state(ret);
1986 }
1987
1988 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1989 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1990 struct intel_plane *plane)
1991 {
1992 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1993 &plane->base));
1994 }
1995
1996 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1997 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1998 struct intel_plane *plane)
1999 {
2000 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2001 &plane->base));
2002 }
2003
2004 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2005 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2006 struct intel_crtc *crtc)
2007 {
2008 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2009 &crtc->base));
2010 }
2011
2012 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2013 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2014 struct intel_crtc *crtc)
2015 {
2016 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2017 &crtc->base));
2018 }
2019
2020 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2021 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2022 struct intel_connector *connector)
2023 {
2024 return to_intel_digital_connector_state(
2025 drm_atomic_get_new_connector_state(&state->base,
2026 &connector->base));
2027 }
2028
2029 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2030 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2031 struct intel_connector *connector)
2032 {
2033 return to_intel_digital_connector_state(
2034 drm_atomic_get_old_connector_state(&state->base,
2035 &connector->base));
2036 }
2037
2038 /* intel_display.c */
2039 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)2040 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2041 enum intel_output_type type)
2042 {
2043 return crtc_state->output_types & (1 << type);
2044 }
2045 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)2046 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2047 {
2048 return crtc_state->output_types &
2049 ((1 << INTEL_OUTPUT_DP) |
2050 (1 << INTEL_OUTPUT_DP_MST) |
2051 (1 << INTEL_OUTPUT_EDP));
2052 }
2053
2054 static inline bool
intel_crtc_needs_modeset(const struct intel_crtc_state * crtc_state)2055 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2056 {
2057 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2058 }
2059
intel_plane_ggtt_offset(const struct intel_plane_state * plane_state)2060 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2061 {
2062 return i915_ggtt_offset(plane_state->ggtt_vma);
2063 }
2064
2065 static inline struct intel_frontbuffer *
to_intel_frontbuffer(struct drm_framebuffer * fb)2066 to_intel_frontbuffer(struct drm_framebuffer *fb)
2067 {
2068 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2069 }
2070
2071 #endif /* __INTEL_DISPLAY_TYPES_H__ */
2072