1 /************************************************************************ 2 * Copyright 2003 Digi International (www.digi.com) 3 * 4 * Copyright (C) 2004 IBM Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 14 * PURPOSE. See the GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston, 19 * MA 02111-1307, USA. 20 * 21 * Contact Information: 22 * Scott H Kilau <Scott_Kilau@digi.com> 23 * Wendy Xiong <wendyx@us.ibm.com> 24 * 25 ***********************************************************************/ 26 27 #ifndef __JSM_DRIVER_H 28 #define __JSM_DRIVER_H 29 30 #include <linux/kernel.h> 31 #include <linux/types.h> /* To pick up the varions Linux types */ 32 #include <linux/tty.h> 33 #include <linux/serial_core.h> 34 #include <linux/device.h> 35 36 /* 37 * Debugging levels can be set using debug insmod variable 38 * They can also be compiled out completely. 39 */ 40 enum { 41 DBG_INIT = 0x01, 42 DBG_BASIC = 0x02, 43 DBG_CORE = 0x04, 44 DBG_OPEN = 0x08, 45 DBG_CLOSE = 0x10, 46 DBG_READ = 0x20, 47 DBG_WRITE = 0x40, 48 DBG_IOCTL = 0x80, 49 DBG_PROC = 0x100, 50 DBG_PARAM = 0x200, 51 DBG_PSCAN = 0x400, 52 DBG_EVENT = 0x800, 53 DBG_DRAIN = 0x1000, 54 DBG_MSIGS = 0x2000, 55 DBG_MGMT = 0x4000, 56 DBG_INTR = 0x8000, 57 DBG_CARR = 0x10000, 58 }; 59 60 #define jsm_printk(nlevel, klevel, pdev, fmt, args...) \ 61 if ((DBG_##nlevel & jsm_debug)) \ 62 dev_printk(KERN_##klevel, pdev->dev, fmt, ## args) 63 64 #define MAXLINES 256 65 #define MAXPORTS 8 66 #define MAX_STOPS_SENT 5 67 68 /* Board type definitions */ 69 70 #define T_NEO 0000 71 #define T_CLASSIC 0001 72 #define T_PCIBUS 0400 73 74 /* Board State Definitions */ 75 76 #define BD_RUNNING 0x0 77 #define BD_REASON 0x7f 78 #define BD_NOTFOUND 0x1 79 #define BD_NOIOPORT 0x2 80 #define BD_NOMEM 0x3 81 #define BD_NOBIOS 0x4 82 #define BD_NOFEP 0x5 83 #define BD_FAILED 0x6 84 #define BD_ALLOCATED 0x7 85 #define BD_TRIBOOT 0x8 86 #define BD_BADKME 0x80 87 88 89 /* 4 extra for alignment play space */ 90 #define WRITEBUFLEN ((4096) + 4) 91 92 #define JSM_VERSION "jsm: 1.2-1-INKERNEL" 93 #define JSM_PARTNUM "40002438_A-INKERNEL" 94 95 struct jsm_board; 96 struct jsm_channel; 97 98 /************************************************************************ 99 * Per board operations structure * 100 ************************************************************************/ 101 struct board_ops { 102 irq_handler_t intr; 103 void (*uart_init) (struct jsm_channel *ch); 104 void (*uart_off) (struct jsm_channel *ch); 105 void (*param) (struct jsm_channel *ch); 106 void (*assert_modem_signals) (struct jsm_channel *ch); 107 void (*flush_uart_write) (struct jsm_channel *ch); 108 void (*flush_uart_read) (struct jsm_channel *ch); 109 void (*disable_receiver) (struct jsm_channel *ch); 110 void (*enable_receiver) (struct jsm_channel *ch); 111 void (*send_break) (struct jsm_channel *ch); 112 void (*clear_break) (struct jsm_channel *ch, int); 113 void (*send_start_character) (struct jsm_channel *ch); 114 void (*send_stop_character) (struct jsm_channel *ch); 115 void (*copy_data_from_queue_to_uart) (struct jsm_channel *ch); 116 u32 (*get_uart_bytes_left) (struct jsm_channel *ch); 117 void (*send_immediate_char) (struct jsm_channel *ch, unsigned char); 118 }; 119 120 121 /* 122 * Per-board information 123 */ 124 struct jsm_board 125 { 126 int boardnum; /* Board number: 0-32 */ 127 128 int type; /* Type of board */ 129 u8 rev; /* PCI revision ID */ 130 struct pci_dev *pci_dev; 131 u32 maxports; /* MAX ports this board can handle */ 132 133 spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and 134 * the interrupt routine from each other. 135 */ 136 137 u32 nasync; /* Number of ports on card */ 138 139 u32 irq; /* Interrupt request number */ 140 141 u64 membase; /* Start of base memory of the card */ 142 u64 membase_end; /* End of base memory of the card */ 143 144 u8 __iomem *re_map_membase;/* Remapped memory of the card */ 145 146 u64 iobase; /* Start of io base of the card */ 147 u64 iobase_end; /* End of io base of the card */ 148 149 u32 bd_uart_offset; /* Space between each UART */ 150 151 struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */ 152 153 u32 bd_dividend; /* Board/UARTs specific dividend */ 154 155 struct board_ops *bd_ops; 156 157 struct list_head jsm_board_entry; 158 }; 159 160 /************************************************************************ 161 * Device flag definitions for ch_flags. 162 ************************************************************************/ 163 #define CH_PRON 0x0001 /* Printer on string */ 164 #define CH_STOP 0x0002 /* Output is stopped */ 165 #define CH_STOPI 0x0004 /* Input is stopped */ 166 #define CH_CD 0x0008 /* Carrier is present */ 167 #define CH_FCAR 0x0010 /* Carrier forced on */ 168 #define CH_HANGUP 0x0020 /* Hangup received */ 169 170 #define CH_RECEIVER_OFF 0x0040 /* Receiver is off */ 171 #define CH_OPENING 0x0080 /* Port in fragile open state */ 172 #define CH_CLOSING 0x0100 /* Port in fragile close state */ 173 #define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */ 174 #define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */ 175 #define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */ 176 #define CH_BREAK_SENDING 0x1000 /* Break is being sent */ 177 #define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */ 178 #define CH_BAUD0 0x08000 /* Used for checking B0 transitions */ 179 180 /* Our Read/Error/Write queue sizes */ 181 #define RQUEUEMASK 0x1FFF /* 8 K - 1 */ 182 #define EQUEUEMASK 0x1FFF /* 8 K - 1 */ 183 #define RQUEUESIZE (RQUEUEMASK + 1) 184 #define EQUEUESIZE RQUEUESIZE 185 186 187 /************************************************************************ 188 * Channel information structure. 189 ************************************************************************/ 190 struct jsm_channel { 191 struct uart_port uart_port; 192 struct jsm_board *ch_bd; /* Board structure pointer */ 193 194 spinlock_t ch_lock; /* provide for serialization */ 195 wait_queue_head_t ch_flags_wait; 196 197 u32 ch_portnum; /* Port number, 0 offset. */ 198 u32 ch_open_count; /* open count */ 199 u32 ch_flags; /* Channel flags */ 200 201 u64 ch_close_delay; /* How long we should drop RTS/DTR for */ 202 203 tcflag_t ch_c_iflag; /* channel iflags */ 204 tcflag_t ch_c_cflag; /* channel cflags */ 205 tcflag_t ch_c_oflag; /* channel oflags */ 206 tcflag_t ch_c_lflag; /* channel lflags */ 207 u8 ch_stopc; /* Stop character */ 208 u8 ch_startc; /* Start character */ 209 210 u8 ch_mostat; /* FEP output modem status */ 211 u8 ch_mistat; /* FEP input modem status */ 212 213 struct neo_uart_struct __iomem *ch_neo_uart; /* Pointer to the "mapped" UART struct */ 214 u8 ch_cached_lsr; /* Cached value of the LSR register */ 215 216 u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */ 217 u16 ch_r_head; /* Head location of the read queue */ 218 u16 ch_r_tail; /* Tail location of the read queue */ 219 220 u8 *ch_equeue; /* Our error queue buffer - malloc'ed */ 221 u16 ch_e_head; /* Head location of the error queue */ 222 u16 ch_e_tail; /* Tail location of the error queue */ 223 224 u64 ch_rxcount; /* total of data received so far */ 225 u64 ch_txcount; /* total of data transmitted so far */ 226 227 u8 ch_r_tlevel; /* Receive Trigger level */ 228 u8 ch_t_tlevel; /* Transmit Trigger level */ 229 230 u8 ch_r_watermark; /* Receive Watermark */ 231 232 233 u32 ch_stops_sent; /* How many times I have sent a stop character 234 * to try to stop the other guy sending. 235 */ 236 u64 ch_err_parity; /* Count of parity errors on channel */ 237 u64 ch_err_frame; /* Count of framing errors on channel */ 238 u64 ch_err_break; /* Count of breaks on channel */ 239 u64 ch_err_overrun; /* Count of overruns on channel */ 240 241 u64 ch_xon_sends; /* Count of xons transmitted */ 242 u64 ch_xoff_sends; /* Count of xoffs transmitted */ 243 }; 244 245 246 /************************************************************************ 247 * Per channel/port NEO UART structure * 248 ************************************************************************ 249 * Base Structure Entries Usage Meanings to Host * 250 * * 251 * W = read write R = read only * 252 * U = Unused. * 253 ************************************************************************/ 254 255 struct neo_uart_struct { 256 u8 txrx; /* WR RHR/THR - Holding Reg */ 257 u8 ier; /* WR IER - Interrupt Enable Reg */ 258 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ 259 u8 lcr; /* WR LCR - Line Control Reg */ 260 u8 mcr; /* WR MCR - Modem Control Reg */ 261 u8 lsr; /* WR LSR - Line Status Reg */ 262 u8 msr; /* WR MSR - Modem Status Reg */ 263 u8 spr; /* WR SPR - Scratch Pad Reg */ 264 u8 fctr; /* WR FCTR - Feature Control Reg */ 265 u8 efr; /* WR EFR - Enhanced Function Reg */ 266 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */ 267 u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */ 268 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */ 269 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */ 270 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */ 271 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */ 272 273 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */ 274 u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */ 275 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */ 276 u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */ 277 }; 278 279 /* Where to read the extended interrupt register (32bits instead of 8bits) */ 280 #define UART_17158_POLL_ADDR_OFFSET 0x80 281 282 /* 283 * These are the redefinitions for the FCTR on the XR17C158, since 284 * Exar made them different than their earlier design. (XR16C854) 285 */ 286 287 /* These are only applicable when table D is selected */ 288 #define UART_17158_FCTR_RTS_NODELAY 0x00 289 #define UART_17158_FCTR_RTS_4DELAY 0x01 290 #define UART_17158_FCTR_RTS_6DELAY 0x02 291 #define UART_17158_FCTR_RTS_8DELAY 0x03 292 #define UART_17158_FCTR_RTS_12DELAY 0x12 293 #define UART_17158_FCTR_RTS_16DELAY 0x05 294 #define UART_17158_FCTR_RTS_20DELAY 0x13 295 #define UART_17158_FCTR_RTS_24DELAY 0x06 296 #define UART_17158_FCTR_RTS_28DELAY 0x14 297 #define UART_17158_FCTR_RTS_32DELAY 0x07 298 #define UART_17158_FCTR_RTS_36DELAY 0x16 299 #define UART_17158_FCTR_RTS_40DELAY 0x08 300 #define UART_17158_FCTR_RTS_44DELAY 0x09 301 #define UART_17158_FCTR_RTS_48DELAY 0x10 302 #define UART_17158_FCTR_RTS_52DELAY 0x11 303 304 #define UART_17158_FCTR_RTS_IRDA 0x10 305 #define UART_17158_FCTR_RS485 0x20 306 #define UART_17158_FCTR_TRGA 0x00 307 #define UART_17158_FCTR_TRGB 0x40 308 #define UART_17158_FCTR_TRGC 0x80 309 #define UART_17158_FCTR_TRGD 0xC0 310 311 /* 17158 trigger table selects.. */ 312 #define UART_17158_FCTR_BIT6 0x40 313 #define UART_17158_FCTR_BIT7 0x80 314 315 /* 17158 TX/RX memmapped buffer offsets */ 316 #define UART_17158_RX_FIFOSIZE 64 317 #define UART_17158_TX_FIFOSIZE 64 318 319 /* 17158 Extended IIR's */ 320 #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 321 #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */ 322 #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */ 323 #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */ 324 325 /* 326 * These are the extended interrupts that get sent 327 * back to us from the UART's 32bit interrupt register 328 */ 329 #define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */ 330 #define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */ 331 #define UART_17158_TXRDY 0x3 /* TX Ready */ 332 #define UART_17158_MSR 0x4 /* Modem State Change */ 333 #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */ 334 #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */ 335 336 /* 337 * These are the EXTENDED definitions for the 17C158's Interrupt 338 * Enable Register. 339 */ 340 #define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */ 341 #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 342 #define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 343 #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 344 #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 345 346 #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 347 #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 348 349 #define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */ 350 #define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 351 #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 352 #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 353 354 #define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI" 355 #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator" 356 #define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI" 357 #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator" 358 #define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM" 359 360 /* 361 * Our Global Variables. 362 */ 363 extern struct uart_driver jsm_uart_driver; 364 extern struct board_ops jsm_neo_ops; 365 extern int jsm_debug; 366 367 /************************************************************************* 368 * 369 * Prototypes for non-static functions used in more than one module 370 * 371 *************************************************************************/ 372 int jsm_tty_init(struct jsm_board *); 373 int jsm_uart_port_init(struct jsm_board *); 374 int jsm_remove_uart_port(struct jsm_board *); 375 void jsm_input(struct jsm_channel *ch); 376 void jsm_check_queue_flow_control(struct jsm_channel *ch); 377 378 #endif 379