1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 *
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
7 *
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
9 */
10
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
17 #include <linux/of.h>
18 #include <linux/pci.h>
19 #include <linux/pm.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <asm/dma.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
35 #include "pci.h"
36
37 DEFINE_MUTEX(pci_slot_mutex);
38
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 };
42 EXPORT_SYMBOL_GPL(pci_power_names);
43
44 #ifdef CONFIG_X86_32
45 int isa_dma_bridge_buggy;
46 EXPORT_SYMBOL(isa_dma_bridge_buggy);
47 #endif
48
49 int pci_pci_problems;
50 EXPORT_SYMBOL(pci_pci_problems);
51
52 unsigned int pci_pm_d3hot_delay;
53
54 static void pci_pme_list_scan(struct work_struct *work);
55
56 static LIST_HEAD(pci_pme_list);
57 static DEFINE_MUTEX(pci_pme_list_mutex);
58 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
59
60 struct pci_pme_device {
61 struct list_head list;
62 struct pci_dev *dev;
63 };
64
65 #define PME_TIMEOUT 1000 /* How long between PME checks */
66
pci_dev_d3_sleep(struct pci_dev * dev)67 static void pci_dev_d3_sleep(struct pci_dev *dev)
68 {
69 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
70 unsigned int upper;
71
72 if (delay_ms) {
73 /* Use a 20% upper bound, 1ms minimum */
74 upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
75 usleep_range(delay_ms * USEC_PER_MSEC,
76 (delay_ms + upper) * USEC_PER_MSEC);
77 }
78 }
79
pci_reset_supported(struct pci_dev * dev)80 bool pci_reset_supported(struct pci_dev *dev)
81 {
82 return dev->reset_methods[0] != 0;
83 }
84
85 #ifdef CONFIG_PCI_DOMAINS
86 int pci_domains_supported = 1;
87 #endif
88
89 #define DEFAULT_CARDBUS_IO_SIZE (256)
90 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
91 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
92 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
93 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
94
95 #define DEFAULT_HOTPLUG_IO_SIZE (256)
96 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
97 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
98 /* hpiosize=nn can override this */
99 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
100 /*
101 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
102 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
103 * pci=hpmemsize=nnM overrides both
104 */
105 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
106 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
107
108 #define DEFAULT_HOTPLUG_BUS_SIZE 1
109 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
110
111
112 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
113 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
114 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
115 #elif defined CONFIG_PCIE_BUS_SAFE
116 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
117 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
118 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
119 #elif defined CONFIG_PCIE_BUS_PEER2PEER
120 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
121 #else
122 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
123 #endif
124
125 /*
126 * The default CLS is used if arch didn't set CLS explicitly and not
127 * all pci devices agree on the same value. Arch can override either
128 * the dfl or actual value as it sees fit. Don't forget this is
129 * measured in 32-bit words, not bytes.
130 */
131 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
132 u8 pci_cache_line_size;
133
134 /*
135 * If we set up a device for bus mastering, we need to check the latency
136 * timer as certain BIOSes forget to set it properly.
137 */
138 unsigned int pcibios_max_latency = 255;
139
140 /* If set, the PCIe ARI capability will not be used. */
141 static bool pcie_ari_disabled;
142
143 /* If set, the PCIe ATS capability will not be used. */
144 static bool pcie_ats_disabled;
145
146 /* If set, the PCI config space of each device is printed during boot. */
147 bool pci_early_dump;
148
pci_ats_disabled(void)149 bool pci_ats_disabled(void)
150 {
151 return pcie_ats_disabled;
152 }
153 EXPORT_SYMBOL_GPL(pci_ats_disabled);
154
155 /* Disable bridge_d3 for all PCIe ports */
156 static bool pci_bridge_d3_disable;
157 /* Force bridge_d3 for all PCIe ports */
158 static bool pci_bridge_d3_force;
159
pcie_port_pm_setup(char * str)160 static int __init pcie_port_pm_setup(char *str)
161 {
162 if (!strcmp(str, "off"))
163 pci_bridge_d3_disable = true;
164 else if (!strcmp(str, "force"))
165 pci_bridge_d3_force = true;
166 return 1;
167 }
168 __setup("pcie_port_pm=", pcie_port_pm_setup);
169
170 /* Time to wait after a reset for device to become responsive */
171 #define PCIE_RESET_READY_POLL_MS 60000
172
173 /**
174 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
175 * @bus: pointer to PCI bus structure to search
176 *
177 * Given a PCI bus, returns the highest PCI bus number present in the set
178 * including the given PCI bus and its list of child PCI buses.
179 */
pci_bus_max_busnr(struct pci_bus * bus)180 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
181 {
182 struct pci_bus *tmp;
183 unsigned char max, n;
184
185 max = bus->busn_res.end;
186 list_for_each_entry(tmp, &bus->children, node) {
187 n = pci_bus_max_busnr(tmp);
188 if (n > max)
189 max = n;
190 }
191 return max;
192 }
193 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
194
195 /**
196 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
197 * @pdev: the PCI device
198 *
199 * Returns error bits set in PCI_STATUS and clears them.
200 */
pci_status_get_and_clear_errors(struct pci_dev * pdev)201 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
202 {
203 u16 status;
204 int ret;
205
206 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
207 if (ret != PCIBIOS_SUCCESSFUL)
208 return -EIO;
209
210 status &= PCI_STATUS_ERROR_BITS;
211 if (status)
212 pci_write_config_word(pdev, PCI_STATUS, status);
213
214 return status;
215 }
216 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
217
218 #ifdef CONFIG_HAS_IOMEM
__pci_ioremap_resource(struct pci_dev * pdev,int bar,bool write_combine)219 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
220 bool write_combine)
221 {
222 struct resource *res = &pdev->resource[bar];
223 resource_size_t start = res->start;
224 resource_size_t size = resource_size(res);
225
226 /*
227 * Make sure the BAR is actually a memory resource, not an IO resource
228 */
229 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
230 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
231 return NULL;
232 }
233
234 if (write_combine)
235 return ioremap_wc(start, size);
236
237 return ioremap(start, size);
238 }
239
pci_ioremap_bar(struct pci_dev * pdev,int bar)240 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
241 {
242 return __pci_ioremap_resource(pdev, bar, false);
243 }
244 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
245
pci_ioremap_wc_bar(struct pci_dev * pdev,int bar)246 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
247 {
248 return __pci_ioremap_resource(pdev, bar, true);
249 }
250 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
251 #endif
252
253 /**
254 * pci_dev_str_match_path - test if a path string matches a device
255 * @dev: the PCI device to test
256 * @path: string to match the device against
257 * @endptr: pointer to the string after the match
258 *
259 * Test if a string (typically from a kernel parameter) formatted as a
260 * path of device/function addresses matches a PCI device. The string must
261 * be of the form:
262 *
263 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
264 *
265 * A path for a device can be obtained using 'lspci -t'. Using a path
266 * is more robust against bus renumbering than using only a single bus,
267 * device and function address.
268 *
269 * Returns 1 if the string matches the device, 0 if it does not and
270 * a negative error code if it fails to parse the string.
271 */
pci_dev_str_match_path(struct pci_dev * dev,const char * path,const char ** endptr)272 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
273 const char **endptr)
274 {
275 int ret;
276 unsigned int seg, bus, slot, func;
277 char *wpath, *p;
278 char end;
279
280 *endptr = strchrnul(path, ';');
281
282 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
283 if (!wpath)
284 return -ENOMEM;
285
286 while (1) {
287 p = strrchr(wpath, '/');
288 if (!p)
289 break;
290 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
291 if (ret != 2) {
292 ret = -EINVAL;
293 goto free_and_exit;
294 }
295
296 if (dev->devfn != PCI_DEVFN(slot, func)) {
297 ret = 0;
298 goto free_and_exit;
299 }
300
301 /*
302 * Note: we don't need to get a reference to the upstream
303 * bridge because we hold a reference to the top level
304 * device which should hold a reference to the bridge,
305 * and so on.
306 */
307 dev = pci_upstream_bridge(dev);
308 if (!dev) {
309 ret = 0;
310 goto free_and_exit;
311 }
312
313 *p = 0;
314 }
315
316 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
317 &func, &end);
318 if (ret != 4) {
319 seg = 0;
320 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
321 if (ret != 3) {
322 ret = -EINVAL;
323 goto free_and_exit;
324 }
325 }
326
327 ret = (seg == pci_domain_nr(dev->bus) &&
328 bus == dev->bus->number &&
329 dev->devfn == PCI_DEVFN(slot, func));
330
331 free_and_exit:
332 kfree(wpath);
333 return ret;
334 }
335
336 /**
337 * pci_dev_str_match - test if a string matches a device
338 * @dev: the PCI device to test
339 * @p: string to match the device against
340 * @endptr: pointer to the string after the match
341 *
342 * Test if a string (typically from a kernel parameter) matches a specified
343 * PCI device. The string may be of one of the following formats:
344 *
345 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
346 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
347 *
348 * The first format specifies a PCI bus/device/function address which
349 * may change if new hardware is inserted, if motherboard firmware changes,
350 * or due to changes caused in kernel parameters. If the domain is
351 * left unspecified, it is taken to be 0. In order to be robust against
352 * bus renumbering issues, a path of PCI device/function numbers may be used
353 * to address the specific device. The path for a device can be determined
354 * through the use of 'lspci -t'.
355 *
356 * The second format matches devices using IDs in the configuration
357 * space which may match multiple devices in the system. A value of 0
358 * for any field will match all devices. (Note: this differs from
359 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
360 * legacy reasons and convenience so users don't have to specify
361 * FFFFFFFFs on the command line.)
362 *
363 * Returns 1 if the string matches the device, 0 if it does not and
364 * a negative error code if the string cannot be parsed.
365 */
pci_dev_str_match(struct pci_dev * dev,const char * p,const char ** endptr)366 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
367 const char **endptr)
368 {
369 int ret;
370 int count;
371 unsigned short vendor, device, subsystem_vendor, subsystem_device;
372
373 if (strncmp(p, "pci:", 4) == 0) {
374 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
375 p += 4;
376 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
377 &subsystem_vendor, &subsystem_device, &count);
378 if (ret != 4) {
379 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
380 if (ret != 2)
381 return -EINVAL;
382
383 subsystem_vendor = 0;
384 subsystem_device = 0;
385 }
386
387 p += count;
388
389 if ((!vendor || vendor == dev->vendor) &&
390 (!device || device == dev->device) &&
391 (!subsystem_vendor ||
392 subsystem_vendor == dev->subsystem_vendor) &&
393 (!subsystem_device ||
394 subsystem_device == dev->subsystem_device))
395 goto found;
396 } else {
397 /*
398 * PCI Bus, Device, Function IDs are specified
399 * (optionally, may include a path of devfns following it)
400 */
401 ret = pci_dev_str_match_path(dev, p, &p);
402 if (ret < 0)
403 return ret;
404 else if (ret)
405 goto found;
406 }
407
408 *endptr = p;
409 return 0;
410
411 found:
412 *endptr = p;
413 return 1;
414 }
415
__pci_find_next_cap_ttl(struct pci_bus * bus,unsigned int devfn,u8 pos,int cap,int * ttl)416 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
417 u8 pos, int cap, int *ttl)
418 {
419 u8 id;
420 u16 ent;
421
422 pci_bus_read_config_byte(bus, devfn, pos, &pos);
423
424 while ((*ttl)--) {
425 if (pos < 0x40)
426 break;
427 pos &= ~3;
428 pci_bus_read_config_word(bus, devfn, pos, &ent);
429
430 id = ent & 0xff;
431 if (id == 0xff)
432 break;
433 if (id == cap)
434 return pos;
435 pos = (ent >> 8);
436 }
437 return 0;
438 }
439
__pci_find_next_cap(struct pci_bus * bus,unsigned int devfn,u8 pos,int cap)440 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
441 u8 pos, int cap)
442 {
443 int ttl = PCI_FIND_CAP_TTL;
444
445 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
446 }
447
pci_find_next_capability(struct pci_dev * dev,u8 pos,int cap)448 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
449 {
450 return __pci_find_next_cap(dev->bus, dev->devfn,
451 pos + PCI_CAP_LIST_NEXT, cap);
452 }
453 EXPORT_SYMBOL_GPL(pci_find_next_capability);
454
__pci_bus_find_cap_start(struct pci_bus * bus,unsigned int devfn,u8 hdr_type)455 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
456 unsigned int devfn, u8 hdr_type)
457 {
458 u16 status;
459
460 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
461 if (!(status & PCI_STATUS_CAP_LIST))
462 return 0;
463
464 switch (hdr_type) {
465 case PCI_HEADER_TYPE_NORMAL:
466 case PCI_HEADER_TYPE_BRIDGE:
467 return PCI_CAPABILITY_LIST;
468 case PCI_HEADER_TYPE_CARDBUS:
469 return PCI_CB_CAPABILITY_LIST;
470 }
471
472 return 0;
473 }
474
475 /**
476 * pci_find_capability - query for devices' capabilities
477 * @dev: PCI device to query
478 * @cap: capability code
479 *
480 * Tell if a device supports a given PCI capability.
481 * Returns the address of the requested capability structure within the
482 * device's PCI configuration space or 0 in case the device does not
483 * support it. Possible values for @cap include:
484 *
485 * %PCI_CAP_ID_PM Power Management
486 * %PCI_CAP_ID_AGP Accelerated Graphics Port
487 * %PCI_CAP_ID_VPD Vital Product Data
488 * %PCI_CAP_ID_SLOTID Slot Identification
489 * %PCI_CAP_ID_MSI Message Signalled Interrupts
490 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
491 * %PCI_CAP_ID_PCIX PCI-X
492 * %PCI_CAP_ID_EXP PCI Express
493 */
pci_find_capability(struct pci_dev * dev,int cap)494 u8 pci_find_capability(struct pci_dev *dev, int cap)
495 {
496 u8 pos;
497
498 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
499 if (pos)
500 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
501
502 return pos;
503 }
504 EXPORT_SYMBOL(pci_find_capability);
505
506 /**
507 * pci_bus_find_capability - query for devices' capabilities
508 * @bus: the PCI bus to query
509 * @devfn: PCI device to query
510 * @cap: capability code
511 *
512 * Like pci_find_capability() but works for PCI devices that do not have a
513 * pci_dev structure set up yet.
514 *
515 * Returns the address of the requested capability structure within the
516 * device's PCI configuration space or 0 in case the device does not
517 * support it.
518 */
pci_bus_find_capability(struct pci_bus * bus,unsigned int devfn,int cap)519 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
520 {
521 u8 hdr_type, pos;
522
523 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
524
525 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
526 if (pos)
527 pos = __pci_find_next_cap(bus, devfn, pos, cap);
528
529 return pos;
530 }
531 EXPORT_SYMBOL(pci_bus_find_capability);
532
533 /**
534 * pci_find_next_ext_capability - Find an extended capability
535 * @dev: PCI device to query
536 * @start: address at which to start looking (0 to start at beginning of list)
537 * @cap: capability code
538 *
539 * Returns the address of the next matching extended capability structure
540 * within the device's PCI configuration space or 0 if the device does
541 * not support it. Some capabilities can occur several times, e.g., the
542 * vendor-specific capability, and this provides a way to find them all.
543 */
pci_find_next_ext_capability(struct pci_dev * dev,u16 start,int cap)544 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
545 {
546 u32 header;
547 int ttl;
548 u16 pos = PCI_CFG_SPACE_SIZE;
549
550 /* minimum 8 bytes per capability */
551 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
552
553 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
554 return 0;
555
556 if (start)
557 pos = start;
558
559 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
560 return 0;
561
562 /*
563 * If we have no capabilities, this is indicated by cap ID,
564 * cap version and next pointer all being 0.
565 */
566 if (header == 0)
567 return 0;
568
569 while (ttl-- > 0) {
570 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
571 return pos;
572
573 pos = PCI_EXT_CAP_NEXT(header);
574 if (pos < PCI_CFG_SPACE_SIZE)
575 break;
576
577 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
578 break;
579 }
580
581 return 0;
582 }
583 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
584
585 /**
586 * pci_find_ext_capability - Find an extended capability
587 * @dev: PCI device to query
588 * @cap: capability code
589 *
590 * Returns the address of the requested extended capability structure
591 * within the device's PCI configuration space or 0 if the device does
592 * not support it. Possible values for @cap include:
593 *
594 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
595 * %PCI_EXT_CAP_ID_VC Virtual Channel
596 * %PCI_EXT_CAP_ID_DSN Device Serial Number
597 * %PCI_EXT_CAP_ID_PWR Power Budgeting
598 */
pci_find_ext_capability(struct pci_dev * dev,int cap)599 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
600 {
601 return pci_find_next_ext_capability(dev, 0, cap);
602 }
603 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
604
605 /**
606 * pci_get_dsn - Read and return the 8-byte Device Serial Number
607 * @dev: PCI device to query
608 *
609 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
610 * Number.
611 *
612 * Returns the DSN, or zero if the capability does not exist.
613 */
pci_get_dsn(struct pci_dev * dev)614 u64 pci_get_dsn(struct pci_dev *dev)
615 {
616 u32 dword;
617 u64 dsn;
618 int pos;
619
620 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
621 if (!pos)
622 return 0;
623
624 /*
625 * The Device Serial Number is two dwords offset 4 bytes from the
626 * capability position. The specification says that the first dword is
627 * the lower half, and the second dword is the upper half.
628 */
629 pos += 4;
630 pci_read_config_dword(dev, pos, &dword);
631 dsn = (u64)dword;
632 pci_read_config_dword(dev, pos + 4, &dword);
633 dsn |= ((u64)dword) << 32;
634
635 return dsn;
636 }
637 EXPORT_SYMBOL_GPL(pci_get_dsn);
638
__pci_find_next_ht_cap(struct pci_dev * dev,u8 pos,int ht_cap)639 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
640 {
641 int rc, ttl = PCI_FIND_CAP_TTL;
642 u8 cap, mask;
643
644 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
645 mask = HT_3BIT_CAP_MASK;
646 else
647 mask = HT_5BIT_CAP_MASK;
648
649 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
650 PCI_CAP_ID_HT, &ttl);
651 while (pos) {
652 rc = pci_read_config_byte(dev, pos + 3, &cap);
653 if (rc != PCIBIOS_SUCCESSFUL)
654 return 0;
655
656 if ((cap & mask) == ht_cap)
657 return pos;
658
659 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
660 pos + PCI_CAP_LIST_NEXT,
661 PCI_CAP_ID_HT, &ttl);
662 }
663
664 return 0;
665 }
666
667 /**
668 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
669 * @dev: PCI device to query
670 * @pos: Position from which to continue searching
671 * @ht_cap: HyperTransport capability code
672 *
673 * To be used in conjunction with pci_find_ht_capability() to search for
674 * all capabilities matching @ht_cap. @pos should always be a value returned
675 * from pci_find_ht_capability().
676 *
677 * NB. To be 100% safe against broken PCI devices, the caller should take
678 * steps to avoid an infinite loop.
679 */
pci_find_next_ht_capability(struct pci_dev * dev,u8 pos,int ht_cap)680 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
681 {
682 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
683 }
684 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
685
686 /**
687 * pci_find_ht_capability - query a device's HyperTransport capabilities
688 * @dev: PCI device to query
689 * @ht_cap: HyperTransport capability code
690 *
691 * Tell if a device supports a given HyperTransport capability.
692 * Returns an address within the device's PCI configuration space
693 * or 0 in case the device does not support the request capability.
694 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
695 * which has a HyperTransport capability matching @ht_cap.
696 */
pci_find_ht_capability(struct pci_dev * dev,int ht_cap)697 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
698 {
699 u8 pos;
700
701 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
702 if (pos)
703 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
704
705 return pos;
706 }
707 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
708
709 /**
710 * pci_find_vsec_capability - Find a vendor-specific extended capability
711 * @dev: PCI device to query
712 * @vendor: Vendor ID for which capability is defined
713 * @cap: Vendor-specific capability ID
714 *
715 * If @dev has Vendor ID @vendor, search for a VSEC capability with
716 * VSEC ID @cap. If found, return the capability offset in
717 * config space; otherwise return 0.
718 */
pci_find_vsec_capability(struct pci_dev * dev,u16 vendor,int cap)719 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
720 {
721 u16 vsec = 0;
722 u32 header;
723
724 if (vendor != dev->vendor)
725 return 0;
726
727 while ((vsec = pci_find_next_ext_capability(dev, vsec,
728 PCI_EXT_CAP_ID_VNDR))) {
729 if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
730 &header) == PCIBIOS_SUCCESSFUL &&
731 PCI_VNDR_HEADER_ID(header) == cap)
732 return vsec;
733 }
734
735 return 0;
736 }
737 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
738
739 /**
740 * pci_find_dvsec_capability - Find DVSEC for vendor
741 * @dev: PCI device to query
742 * @vendor: Vendor ID to match for the DVSEC
743 * @dvsec: Designated Vendor-specific capability ID
744 *
745 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
746 * offset in config space; otherwise return 0.
747 */
pci_find_dvsec_capability(struct pci_dev * dev,u16 vendor,u16 dvsec)748 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
749 {
750 int pos;
751
752 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
753 if (!pos)
754 return 0;
755
756 while (pos) {
757 u16 v, id;
758
759 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
760 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
761 if (vendor == v && dvsec == id)
762 return pos;
763
764 pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
765 }
766
767 return 0;
768 }
769 EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
770
771 /**
772 * pci_find_parent_resource - return resource region of parent bus of given
773 * region
774 * @dev: PCI device structure contains resources to be searched
775 * @res: child resource record for which parent is sought
776 *
777 * For given resource region of given device, return the resource region of
778 * parent bus the given region is contained in.
779 */
pci_find_parent_resource(const struct pci_dev * dev,struct resource * res)780 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
781 struct resource *res)
782 {
783 const struct pci_bus *bus = dev->bus;
784 struct resource *r;
785 int i;
786
787 pci_bus_for_each_resource(bus, r, i) {
788 if (!r)
789 continue;
790 if (resource_contains(r, res)) {
791
792 /*
793 * If the window is prefetchable but the BAR is
794 * not, the allocator made a mistake.
795 */
796 if (r->flags & IORESOURCE_PREFETCH &&
797 !(res->flags & IORESOURCE_PREFETCH))
798 return NULL;
799
800 /*
801 * If we're below a transparent bridge, there may
802 * be both a positively-decoded aperture and a
803 * subtractively-decoded region that contain the BAR.
804 * We want the positively-decoded one, so this depends
805 * on pci_bus_for_each_resource() giving us those
806 * first.
807 */
808 return r;
809 }
810 }
811 return NULL;
812 }
813 EXPORT_SYMBOL(pci_find_parent_resource);
814
815 /**
816 * pci_find_resource - Return matching PCI device resource
817 * @dev: PCI device to query
818 * @res: Resource to look for
819 *
820 * Goes over standard PCI resources (BARs) and checks if the given resource
821 * is partially or fully contained in any of them. In that case the
822 * matching resource is returned, %NULL otherwise.
823 */
pci_find_resource(struct pci_dev * dev,struct resource * res)824 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
825 {
826 int i;
827
828 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
829 struct resource *r = &dev->resource[i];
830
831 if (r->start && resource_contains(r, res))
832 return r;
833 }
834
835 return NULL;
836 }
837 EXPORT_SYMBOL(pci_find_resource);
838
839 /**
840 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
841 * @dev: the PCI device to operate on
842 * @pos: config space offset of status word
843 * @mask: mask of bit(s) to care about in status word
844 *
845 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
846 */
pci_wait_for_pending(struct pci_dev * dev,int pos,u16 mask)847 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
848 {
849 int i;
850
851 /* Wait for Transaction Pending bit clean */
852 for (i = 0; i < 4; i++) {
853 u16 status;
854 if (i)
855 msleep((1 << (i - 1)) * 100);
856
857 pci_read_config_word(dev, pos, &status);
858 if (!(status & mask))
859 return 1;
860 }
861
862 return 0;
863 }
864
865 static int pci_acs_enable;
866
867 /**
868 * pci_request_acs - ask for ACS to be enabled if supported
869 */
pci_request_acs(void)870 void pci_request_acs(void)
871 {
872 pci_acs_enable = 1;
873 }
874
875 static const char *disable_acs_redir_param;
876
877 /**
878 * pci_disable_acs_redir - disable ACS redirect capabilities
879 * @dev: the PCI device
880 *
881 * For only devices specified in the disable_acs_redir parameter.
882 */
pci_disable_acs_redir(struct pci_dev * dev)883 static void pci_disable_acs_redir(struct pci_dev *dev)
884 {
885 int ret = 0;
886 const char *p;
887 int pos;
888 u16 ctrl;
889
890 if (!disable_acs_redir_param)
891 return;
892
893 p = disable_acs_redir_param;
894 while (*p) {
895 ret = pci_dev_str_match(dev, p, &p);
896 if (ret < 0) {
897 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
898 disable_acs_redir_param);
899
900 break;
901 } else if (ret == 1) {
902 /* Found a match */
903 break;
904 }
905
906 if (*p != ';' && *p != ',') {
907 /* End of param or invalid format */
908 break;
909 }
910 p++;
911 }
912
913 if (ret != 1)
914 return;
915
916 if (!pci_dev_specific_disable_acs_redir(dev))
917 return;
918
919 pos = dev->acs_cap;
920 if (!pos) {
921 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
922 return;
923 }
924
925 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
926
927 /* P2P Request & Completion Redirect */
928 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
929
930 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
931
932 pci_info(dev, "disabled ACS redirect\n");
933 }
934
935 /**
936 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
937 * @dev: the PCI device
938 */
pci_std_enable_acs(struct pci_dev * dev)939 static void pci_std_enable_acs(struct pci_dev *dev)
940 {
941 int pos;
942 u16 cap;
943 u16 ctrl;
944
945 pos = dev->acs_cap;
946 if (!pos)
947 return;
948
949 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
950 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
951
952 /* Source Validation */
953 ctrl |= (cap & PCI_ACS_SV);
954
955 /* P2P Request Redirect */
956 ctrl |= (cap & PCI_ACS_RR);
957
958 /* P2P Completion Redirect */
959 ctrl |= (cap & PCI_ACS_CR);
960
961 /* Upstream Forwarding */
962 ctrl |= (cap & PCI_ACS_UF);
963
964 /* Enable Translation Blocking for external devices and noats */
965 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
966 ctrl |= (cap & PCI_ACS_TB);
967
968 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
969 }
970
971 /**
972 * pci_enable_acs - enable ACS if hardware support it
973 * @dev: the PCI device
974 */
pci_enable_acs(struct pci_dev * dev)975 static void pci_enable_acs(struct pci_dev *dev)
976 {
977 if (!pci_acs_enable)
978 goto disable_acs_redir;
979
980 if (!pci_dev_specific_enable_acs(dev))
981 goto disable_acs_redir;
982
983 pci_std_enable_acs(dev);
984
985 disable_acs_redir:
986 /*
987 * Note: pci_disable_acs_redir() must be called even if ACS was not
988 * enabled by the kernel because it may have been enabled by
989 * platform firmware. So if we are told to disable it, we should
990 * always disable it after setting the kernel's default
991 * preferences.
992 */
993 pci_disable_acs_redir(dev);
994 }
995
996 /**
997 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
998 * @dev: PCI device to have its BARs restored
999 *
1000 * Restore the BAR values for a given device, so as to make it
1001 * accessible by its driver.
1002 */
pci_restore_bars(struct pci_dev * dev)1003 static void pci_restore_bars(struct pci_dev *dev)
1004 {
1005 int i;
1006
1007 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
1008 pci_update_resource(dev, i);
1009 }
1010
platform_pci_power_manageable(struct pci_dev * dev)1011 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1012 {
1013 if (pci_use_mid_pm())
1014 return true;
1015
1016 return acpi_pci_power_manageable(dev);
1017 }
1018
platform_pci_set_power_state(struct pci_dev * dev,pci_power_t t)1019 static inline int platform_pci_set_power_state(struct pci_dev *dev,
1020 pci_power_t t)
1021 {
1022 if (pci_use_mid_pm())
1023 return mid_pci_set_power_state(dev, t);
1024
1025 return acpi_pci_set_power_state(dev, t);
1026 }
1027
platform_pci_get_power_state(struct pci_dev * dev)1028 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1029 {
1030 if (pci_use_mid_pm())
1031 return mid_pci_get_power_state(dev);
1032
1033 return acpi_pci_get_power_state(dev);
1034 }
1035
platform_pci_refresh_power_state(struct pci_dev * dev)1036 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1037 {
1038 if (!pci_use_mid_pm())
1039 acpi_pci_refresh_power_state(dev);
1040 }
1041
platform_pci_choose_state(struct pci_dev * dev)1042 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1043 {
1044 if (pci_use_mid_pm())
1045 return PCI_POWER_ERROR;
1046
1047 return acpi_pci_choose_state(dev);
1048 }
1049
platform_pci_set_wakeup(struct pci_dev * dev,bool enable)1050 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1051 {
1052 if (pci_use_mid_pm())
1053 return PCI_POWER_ERROR;
1054
1055 return acpi_pci_wakeup(dev, enable);
1056 }
1057
platform_pci_need_resume(struct pci_dev * dev)1058 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1059 {
1060 if (pci_use_mid_pm())
1061 return false;
1062
1063 return acpi_pci_need_resume(dev);
1064 }
1065
platform_pci_bridge_d3(struct pci_dev * dev)1066 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1067 {
1068 if (pci_use_mid_pm())
1069 return false;
1070
1071 return acpi_pci_bridge_d3(dev);
1072 }
1073
1074 /**
1075 * pci_update_current_state - Read power state of given device and cache it
1076 * @dev: PCI device to handle.
1077 * @state: State to cache in case the device doesn't have the PM capability
1078 *
1079 * The power state is read from the PMCSR register, which however is
1080 * inaccessible in D3cold. The platform firmware is therefore queried first
1081 * to detect accessibility of the register. In case the platform firmware
1082 * reports an incorrect state or the device isn't power manageable by the
1083 * platform at all, we try to detect D3cold by testing accessibility of the
1084 * vendor ID in config space.
1085 */
pci_update_current_state(struct pci_dev * dev,pci_power_t state)1086 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1087 {
1088 if (platform_pci_get_power_state(dev) == PCI_D3cold) {
1089 dev->current_state = PCI_D3cold;
1090 } else if (dev->pm_cap) {
1091 u16 pmcsr;
1092
1093 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1094 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1095 dev->current_state = PCI_D3cold;
1096 return;
1097 }
1098 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1099 } else {
1100 dev->current_state = state;
1101 }
1102 }
1103
1104 /**
1105 * pci_refresh_power_state - Refresh the given device's power state data
1106 * @dev: Target PCI device.
1107 *
1108 * Ask the platform to refresh the devices power state information and invoke
1109 * pci_update_current_state() to update its current PCI power state.
1110 */
pci_refresh_power_state(struct pci_dev * dev)1111 void pci_refresh_power_state(struct pci_dev *dev)
1112 {
1113 platform_pci_refresh_power_state(dev);
1114 pci_update_current_state(dev, dev->current_state);
1115 }
1116
1117 /**
1118 * pci_platform_power_transition - Use platform to change device power state
1119 * @dev: PCI device to handle.
1120 * @state: State to put the device into.
1121 */
pci_platform_power_transition(struct pci_dev * dev,pci_power_t state)1122 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1123 {
1124 int error;
1125
1126 error = platform_pci_set_power_state(dev, state);
1127 if (!error)
1128 pci_update_current_state(dev, state);
1129 else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1130 dev->current_state = PCI_D0;
1131
1132 return error;
1133 }
1134 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1135
pci_resume_one(struct pci_dev * pci_dev,void * ign)1136 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1137 {
1138 pm_request_resume(&pci_dev->dev);
1139 return 0;
1140 }
1141
1142 /**
1143 * pci_resume_bus - Walk given bus and runtime resume devices on it
1144 * @bus: Top bus of the subtree to walk.
1145 */
pci_resume_bus(struct pci_bus * bus)1146 void pci_resume_bus(struct pci_bus *bus)
1147 {
1148 if (bus)
1149 pci_walk_bus(bus, pci_resume_one, NULL);
1150 }
1151
pci_dev_wait(struct pci_dev * dev,char * reset_type,int timeout)1152 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1153 {
1154 int delay = 1;
1155 u32 id;
1156
1157 /*
1158 * After reset, the device should not silently discard config
1159 * requests, but it may still indicate that it needs more time by
1160 * responding to them with CRS completions. The Root Port will
1161 * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
1162 * the read (except when CRS SV is enabled and the read was for the
1163 * Vendor ID; in that case it synthesizes 0x0001 data).
1164 *
1165 * Wait for the device to return a non-CRS completion. Read the
1166 * Command register instead of Vendor ID so we don't have to
1167 * contend with the CRS SV value.
1168 */
1169 pci_read_config_dword(dev, PCI_COMMAND, &id);
1170 while (PCI_POSSIBLE_ERROR(id)) {
1171 if (delay > timeout) {
1172 pci_warn(dev, "not ready %dms after %s; giving up\n",
1173 delay - 1, reset_type);
1174 return -ENOTTY;
1175 }
1176
1177 if (delay > 1000)
1178 pci_info(dev, "not ready %dms after %s; waiting\n",
1179 delay - 1, reset_type);
1180
1181 msleep(delay);
1182 delay *= 2;
1183 pci_read_config_dword(dev, PCI_COMMAND, &id);
1184 }
1185
1186 if (delay > 1000)
1187 pci_info(dev, "ready %dms after %s\n", delay - 1,
1188 reset_type);
1189
1190 return 0;
1191 }
1192
1193 /**
1194 * pci_power_up - Put the given device into D0
1195 * @dev: PCI device to power up
1196 *
1197 * On success, return 0 or 1, depending on whether or not it is necessary to
1198 * restore the device's BARs subsequently (1 is returned in that case).
1199 */
pci_power_up(struct pci_dev * dev)1200 int pci_power_up(struct pci_dev *dev)
1201 {
1202 bool need_restore;
1203 pci_power_t state;
1204 u16 pmcsr;
1205
1206 platform_pci_set_power_state(dev, PCI_D0);
1207
1208 if (!dev->pm_cap) {
1209 state = platform_pci_get_power_state(dev);
1210 if (state == PCI_UNKNOWN)
1211 dev->current_state = PCI_D0;
1212 else
1213 dev->current_state = state;
1214
1215 if (state == PCI_D0)
1216 return 0;
1217
1218 return -EIO;
1219 }
1220
1221 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1222 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1223 pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",
1224 pci_power_name(dev->current_state));
1225 dev->current_state = PCI_D3cold;
1226 return -EIO;
1227 }
1228
1229 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1230
1231 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
1232 !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET);
1233
1234 if (state == PCI_D0)
1235 goto end;
1236
1237 /*
1238 * Force the entire word to 0. This doesn't affect PME_Status, disables
1239 * PME_En, and sets PowerState to 0.
1240 */
1241 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
1242
1243 /* Mandatory transition delays; see PCI PM 1.2. */
1244 if (state == PCI_D3hot)
1245 pci_dev_d3_sleep(dev);
1246 else if (state == PCI_D2)
1247 udelay(PCI_PM_D2_DELAY);
1248
1249 end:
1250 dev->current_state = PCI_D0;
1251 if (need_restore)
1252 return 1;
1253
1254 return 0;
1255 }
1256
1257 /**
1258 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1259 * @dev: PCI device to power up
1260 *
1261 * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1262 * to confirm the state change, restore its BARs if they might be lost and
1263 * reconfigure ASPM in acordance with the new power state.
1264 *
1265 * If pci_restore_state() is going to be called right after a power state change
1266 * to D0, it is more efficient to use pci_power_up() directly instead of this
1267 * function.
1268 */
pci_set_full_power_state(struct pci_dev * dev)1269 static int pci_set_full_power_state(struct pci_dev *dev)
1270 {
1271 u16 pmcsr;
1272 int ret;
1273
1274 ret = pci_power_up(dev);
1275 if (ret < 0)
1276 return ret;
1277
1278 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1279 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1280 if (dev->current_state != PCI_D0) {
1281 pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",
1282 pci_power_name(dev->current_state));
1283 } else if (ret > 0) {
1284 /*
1285 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1286 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1287 * from D3hot to D0 _may_ perform an internal reset, thereby
1288 * going to "D0 Uninitialized" rather than "D0 Initialized".
1289 * For example, at least some versions of the 3c905B and the
1290 * 3c556B exhibit this behaviour.
1291 *
1292 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1293 * devices in a D3hot state at boot. Consequently, we need to
1294 * restore at least the BARs so that the device will be
1295 * accessible to its driver.
1296 */
1297 pci_restore_bars(dev);
1298 }
1299
1300 return 0;
1301 }
1302
1303 /**
1304 * __pci_dev_set_current_state - Set current state of a PCI device
1305 * @dev: Device to handle
1306 * @data: pointer to state to be set
1307 */
__pci_dev_set_current_state(struct pci_dev * dev,void * data)1308 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1309 {
1310 pci_power_t state = *(pci_power_t *)data;
1311
1312 dev->current_state = state;
1313 return 0;
1314 }
1315
1316 /**
1317 * pci_bus_set_current_state - Walk given bus and set current state of devices
1318 * @bus: Top bus of the subtree to walk.
1319 * @state: state to be set
1320 */
pci_bus_set_current_state(struct pci_bus * bus,pci_power_t state)1321 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1322 {
1323 if (bus)
1324 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1325 }
1326
1327 /**
1328 * pci_set_low_power_state - Put a PCI device into a low-power state.
1329 * @dev: PCI device to handle.
1330 * @state: PCI power state (D1, D2, D3hot) to put the device into.
1331 *
1332 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1333 *
1334 * RETURN VALUE:
1335 * -EINVAL if the requested state is invalid.
1336 * -EIO if device does not support PCI PM or its PM capabilities register has a
1337 * wrong version, or device doesn't support the requested state.
1338 * 0 if device already is in the requested state.
1339 * 0 if device's power state has been successfully changed.
1340 */
pci_set_low_power_state(struct pci_dev * dev,pci_power_t state)1341 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state)
1342 {
1343 u16 pmcsr;
1344
1345 if (!dev->pm_cap)
1346 return -EIO;
1347
1348 /*
1349 * Validate transition: We can enter D0 from any state, but if
1350 * we're already in a low-power state, we can only go deeper. E.g.,
1351 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1352 * we'd have to go from D3 to D0, then to D1.
1353 */
1354 if (dev->current_state <= PCI_D3cold && dev->current_state > state) {
1355 pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1356 pci_power_name(dev->current_state),
1357 pci_power_name(state));
1358 return -EINVAL;
1359 }
1360
1361 /* Check if this device supports the desired state */
1362 if ((state == PCI_D1 && !dev->d1_support)
1363 || (state == PCI_D2 && !dev->d2_support))
1364 return -EIO;
1365
1366 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1367 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1368 pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",
1369 pci_power_name(dev->current_state),
1370 pci_power_name(state));
1371 dev->current_state = PCI_D3cold;
1372 return -EIO;
1373 }
1374
1375 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1376 pmcsr |= state;
1377
1378 /* Enter specified state */
1379 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1380
1381 /* Mandatory power management transition delays; see PCI PM 1.2. */
1382 if (state == PCI_D3hot)
1383 pci_dev_d3_sleep(dev);
1384 else if (state == PCI_D2)
1385 udelay(PCI_PM_D2_DELAY);
1386
1387 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1388 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1389 if (dev->current_state != state)
1390 pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",
1391 pci_power_name(dev->current_state),
1392 pci_power_name(state));
1393
1394 return 0;
1395 }
1396
1397 /**
1398 * pci_set_power_state - Set the power state of a PCI device
1399 * @dev: PCI device to handle.
1400 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1401 *
1402 * Transition a device to a new power state, using the platform firmware and/or
1403 * the device's PCI PM registers.
1404 *
1405 * RETURN VALUE:
1406 * -EINVAL if the requested state is invalid.
1407 * -EIO if device does not support PCI PM or its PM capabilities register has a
1408 * wrong version, or device doesn't support the requested state.
1409 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1410 * 0 if device already is in the requested state.
1411 * 0 if the transition is to D3 but D3 is not supported.
1412 * 0 if device's power state has been successfully changed.
1413 */
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1414 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1415 {
1416 int error;
1417
1418 /* Bound the state we're entering */
1419 if (state > PCI_D3cold)
1420 state = PCI_D3cold;
1421 else if (state < PCI_D0)
1422 state = PCI_D0;
1423 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1424
1425 /*
1426 * If the device or the parent bridge do not support PCI
1427 * PM, ignore the request if we're doing anything other
1428 * than putting it into D0 (which would only happen on
1429 * boot).
1430 */
1431 return 0;
1432
1433 /* Check if we're already there */
1434 if (dev->current_state == state)
1435 return 0;
1436
1437 if (state == PCI_D0)
1438 return pci_set_full_power_state(dev);
1439
1440 /*
1441 * This device is quirked not to be put into D3, so don't put it in
1442 * D3
1443 */
1444 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1445 return 0;
1446
1447 if (state == PCI_D3cold) {
1448 /*
1449 * To put the device in D3cold, put it into D3hot in the native
1450 * way, then put it into D3cold using platform ops.
1451 */
1452 error = pci_set_low_power_state(dev, PCI_D3hot);
1453
1454 if (pci_platform_power_transition(dev, PCI_D3cold))
1455 return error;
1456
1457 /* Powering off a bridge may power off the whole hierarchy */
1458 if (dev->current_state == PCI_D3cold)
1459 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1460 } else {
1461 error = pci_set_low_power_state(dev, state);
1462
1463 if (pci_platform_power_transition(dev, state))
1464 return error;
1465 }
1466
1467 return 0;
1468 }
1469 EXPORT_SYMBOL(pci_set_power_state);
1470
1471 #define PCI_EXP_SAVE_REGS 7
1472
_pci_find_saved_cap(struct pci_dev * pci_dev,u16 cap,bool extended)1473 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1474 u16 cap, bool extended)
1475 {
1476 struct pci_cap_saved_state *tmp;
1477
1478 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1479 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1480 return tmp;
1481 }
1482 return NULL;
1483 }
1484
pci_find_saved_cap(struct pci_dev * dev,char cap)1485 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1486 {
1487 return _pci_find_saved_cap(dev, cap, false);
1488 }
1489
pci_find_saved_ext_cap(struct pci_dev * dev,u16 cap)1490 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1491 {
1492 return _pci_find_saved_cap(dev, cap, true);
1493 }
1494
pci_save_pcie_state(struct pci_dev * dev)1495 static int pci_save_pcie_state(struct pci_dev *dev)
1496 {
1497 int i = 0;
1498 struct pci_cap_saved_state *save_state;
1499 u16 *cap;
1500
1501 if (!pci_is_pcie(dev))
1502 return 0;
1503
1504 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1505 if (!save_state) {
1506 pci_err(dev, "buffer not found in %s\n", __func__);
1507 return -ENOMEM;
1508 }
1509
1510 cap = (u16 *)&save_state->cap.data[0];
1511 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1512 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1513 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1514 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1515 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1516 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1517 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1518
1519 return 0;
1520 }
1521
pci_bridge_reconfigure_ltr(struct pci_dev * dev)1522 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1523 {
1524 #ifdef CONFIG_PCIEASPM
1525 struct pci_dev *bridge;
1526 u32 ctl;
1527
1528 bridge = pci_upstream_bridge(dev);
1529 if (bridge && bridge->ltr_path) {
1530 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1531 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1532 pci_dbg(bridge, "re-enabling LTR\n");
1533 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1534 PCI_EXP_DEVCTL2_LTR_EN);
1535 }
1536 }
1537 #endif
1538 }
1539
pci_restore_pcie_state(struct pci_dev * dev)1540 static void pci_restore_pcie_state(struct pci_dev *dev)
1541 {
1542 int i = 0;
1543 struct pci_cap_saved_state *save_state;
1544 u16 *cap;
1545
1546 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1547 if (!save_state)
1548 return;
1549
1550 /*
1551 * Downstream ports reset the LTR enable bit when link goes down.
1552 * Check and re-configure the bit here before restoring device.
1553 * PCIe r5.0, sec 7.5.3.16.
1554 */
1555 pci_bridge_reconfigure_ltr(dev);
1556
1557 cap = (u16 *)&save_state->cap.data[0];
1558 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1559 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1560 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1561 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1562 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1563 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1564 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1565 }
1566
pci_save_pcix_state(struct pci_dev * dev)1567 static int pci_save_pcix_state(struct pci_dev *dev)
1568 {
1569 int pos;
1570 struct pci_cap_saved_state *save_state;
1571
1572 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1573 if (!pos)
1574 return 0;
1575
1576 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1577 if (!save_state) {
1578 pci_err(dev, "buffer not found in %s\n", __func__);
1579 return -ENOMEM;
1580 }
1581
1582 pci_read_config_word(dev, pos + PCI_X_CMD,
1583 (u16 *)save_state->cap.data);
1584
1585 return 0;
1586 }
1587
pci_restore_pcix_state(struct pci_dev * dev)1588 static void pci_restore_pcix_state(struct pci_dev *dev)
1589 {
1590 int i = 0, pos;
1591 struct pci_cap_saved_state *save_state;
1592 u16 *cap;
1593
1594 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1595 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1596 if (!save_state || !pos)
1597 return;
1598 cap = (u16 *)&save_state->cap.data[0];
1599
1600 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1601 }
1602
pci_save_ltr_state(struct pci_dev * dev)1603 static void pci_save_ltr_state(struct pci_dev *dev)
1604 {
1605 int ltr;
1606 struct pci_cap_saved_state *save_state;
1607 u32 *cap;
1608
1609 if (!pci_is_pcie(dev))
1610 return;
1611
1612 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1613 if (!ltr)
1614 return;
1615
1616 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1617 if (!save_state) {
1618 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1619 return;
1620 }
1621
1622 /* Some broken devices only support dword access to LTR */
1623 cap = &save_state->cap.data[0];
1624 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1625 }
1626
pci_restore_ltr_state(struct pci_dev * dev)1627 static void pci_restore_ltr_state(struct pci_dev *dev)
1628 {
1629 struct pci_cap_saved_state *save_state;
1630 int ltr;
1631 u32 *cap;
1632
1633 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1634 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1635 if (!save_state || !ltr)
1636 return;
1637
1638 /* Some broken devices only support dword access to LTR */
1639 cap = &save_state->cap.data[0];
1640 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1641 }
1642
1643 /**
1644 * pci_save_state - save the PCI configuration space of a device before
1645 * suspending
1646 * @dev: PCI device that we're dealing with
1647 */
pci_save_state(struct pci_dev * dev)1648 int pci_save_state(struct pci_dev *dev)
1649 {
1650 int i;
1651 /* XXX: 100% dword access ok here? */
1652 for (i = 0; i < 16; i++) {
1653 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1654 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1655 i * 4, dev->saved_config_space[i]);
1656 }
1657 dev->state_saved = true;
1658
1659 i = pci_save_pcie_state(dev);
1660 if (i != 0)
1661 return i;
1662
1663 i = pci_save_pcix_state(dev);
1664 if (i != 0)
1665 return i;
1666
1667 pci_save_ltr_state(dev);
1668 pci_save_aspm_l1ss_state(dev);
1669 pci_save_dpc_state(dev);
1670 pci_save_aer_state(dev);
1671 pci_save_ptm_state(dev);
1672 return pci_save_vc_state(dev);
1673 }
1674 EXPORT_SYMBOL(pci_save_state);
1675
pci_restore_config_dword(struct pci_dev * pdev,int offset,u32 saved_val,int retry,bool force)1676 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1677 u32 saved_val, int retry, bool force)
1678 {
1679 u32 val;
1680
1681 pci_read_config_dword(pdev, offset, &val);
1682 if (!force && val == saved_val)
1683 return;
1684
1685 for (;;) {
1686 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1687 offset, val, saved_val);
1688 pci_write_config_dword(pdev, offset, saved_val);
1689 if (retry-- <= 0)
1690 return;
1691
1692 pci_read_config_dword(pdev, offset, &val);
1693 if (val == saved_val)
1694 return;
1695
1696 mdelay(1);
1697 }
1698 }
1699
pci_restore_config_space_range(struct pci_dev * pdev,int start,int end,int retry,bool force)1700 static void pci_restore_config_space_range(struct pci_dev *pdev,
1701 int start, int end, int retry,
1702 bool force)
1703 {
1704 int index;
1705
1706 for (index = end; index >= start; index--)
1707 pci_restore_config_dword(pdev, 4 * index,
1708 pdev->saved_config_space[index],
1709 retry, force);
1710 }
1711
pci_restore_config_space(struct pci_dev * pdev)1712 static void pci_restore_config_space(struct pci_dev *pdev)
1713 {
1714 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1715 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1716 /* Restore BARs before the command register. */
1717 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1718 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1719 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1720 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1721
1722 /*
1723 * Force rewriting of prefetch registers to avoid S3 resume
1724 * issues on Intel PCI bridges that occur when these
1725 * registers are not explicitly written.
1726 */
1727 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1728 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1729 } else {
1730 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1731 }
1732 }
1733
pci_restore_rebar_state(struct pci_dev * pdev)1734 static void pci_restore_rebar_state(struct pci_dev *pdev)
1735 {
1736 unsigned int pos, nbars, i;
1737 u32 ctrl;
1738
1739 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1740 if (!pos)
1741 return;
1742
1743 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1744 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1745 PCI_REBAR_CTRL_NBAR_SHIFT;
1746
1747 for (i = 0; i < nbars; i++, pos += 8) {
1748 struct resource *res;
1749 int bar_idx, size;
1750
1751 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1752 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1753 res = pdev->resource + bar_idx;
1754 size = pci_rebar_bytes_to_size(resource_size(res));
1755 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1756 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1757 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1758 }
1759 }
1760
1761 /**
1762 * pci_restore_state - Restore the saved state of a PCI device
1763 * @dev: PCI device that we're dealing with
1764 */
pci_restore_state(struct pci_dev * dev)1765 void pci_restore_state(struct pci_dev *dev)
1766 {
1767 if (!dev->state_saved)
1768 return;
1769
1770 /*
1771 * Restore max latencies (in the LTR capability) before enabling
1772 * LTR itself (in the PCIe capability).
1773 */
1774 pci_restore_ltr_state(dev);
1775 pci_restore_aspm_l1ss_state(dev);
1776
1777 pci_restore_pcie_state(dev);
1778 pci_restore_pasid_state(dev);
1779 pci_restore_pri_state(dev);
1780 pci_restore_ats_state(dev);
1781 pci_restore_vc_state(dev);
1782 pci_restore_rebar_state(dev);
1783 pci_restore_dpc_state(dev);
1784 pci_restore_ptm_state(dev);
1785
1786 pci_aer_clear_status(dev);
1787 pci_restore_aer_state(dev);
1788
1789 pci_restore_config_space(dev);
1790
1791 pci_restore_pcix_state(dev);
1792 pci_restore_msi_state(dev);
1793
1794 /* Restore ACS and IOV configuration state */
1795 pci_enable_acs(dev);
1796 pci_restore_iov_state(dev);
1797
1798 dev->state_saved = false;
1799 }
1800 EXPORT_SYMBOL(pci_restore_state);
1801
1802 struct pci_saved_state {
1803 u32 config_space[16];
1804 struct pci_cap_saved_data cap[];
1805 };
1806
1807 /**
1808 * pci_store_saved_state - Allocate and return an opaque struct containing
1809 * the device saved state.
1810 * @dev: PCI device that we're dealing with
1811 *
1812 * Return NULL if no state or error.
1813 */
pci_store_saved_state(struct pci_dev * dev)1814 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1815 {
1816 struct pci_saved_state *state;
1817 struct pci_cap_saved_state *tmp;
1818 struct pci_cap_saved_data *cap;
1819 size_t size;
1820
1821 if (!dev->state_saved)
1822 return NULL;
1823
1824 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1825
1826 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1827 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1828
1829 state = kzalloc(size, GFP_KERNEL);
1830 if (!state)
1831 return NULL;
1832
1833 memcpy(state->config_space, dev->saved_config_space,
1834 sizeof(state->config_space));
1835
1836 cap = state->cap;
1837 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1838 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1839 memcpy(cap, &tmp->cap, len);
1840 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1841 }
1842 /* Empty cap_save terminates list */
1843
1844 return state;
1845 }
1846 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1847
1848 /**
1849 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1850 * @dev: PCI device that we're dealing with
1851 * @state: Saved state returned from pci_store_saved_state()
1852 */
pci_load_saved_state(struct pci_dev * dev,struct pci_saved_state * state)1853 int pci_load_saved_state(struct pci_dev *dev,
1854 struct pci_saved_state *state)
1855 {
1856 struct pci_cap_saved_data *cap;
1857
1858 dev->state_saved = false;
1859
1860 if (!state)
1861 return 0;
1862
1863 memcpy(dev->saved_config_space, state->config_space,
1864 sizeof(state->config_space));
1865
1866 cap = state->cap;
1867 while (cap->size) {
1868 struct pci_cap_saved_state *tmp;
1869
1870 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1871 if (!tmp || tmp->cap.size != cap->size)
1872 return -EINVAL;
1873
1874 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1875 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1876 sizeof(struct pci_cap_saved_data) + cap->size);
1877 }
1878
1879 dev->state_saved = true;
1880 return 0;
1881 }
1882 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1883
1884 /**
1885 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1886 * and free the memory allocated for it.
1887 * @dev: PCI device that we're dealing with
1888 * @state: Pointer to saved state returned from pci_store_saved_state()
1889 */
pci_load_and_free_saved_state(struct pci_dev * dev,struct pci_saved_state ** state)1890 int pci_load_and_free_saved_state(struct pci_dev *dev,
1891 struct pci_saved_state **state)
1892 {
1893 int ret = pci_load_saved_state(dev, *state);
1894 kfree(*state);
1895 *state = NULL;
1896 return ret;
1897 }
1898 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1899
pcibios_enable_device(struct pci_dev * dev,int bars)1900 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1901 {
1902 return pci_enable_resources(dev, bars);
1903 }
1904
do_pci_enable_device(struct pci_dev * dev,int bars)1905 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1906 {
1907 int err;
1908 struct pci_dev *bridge;
1909 u16 cmd;
1910 u8 pin;
1911
1912 err = pci_set_power_state(dev, PCI_D0);
1913 if (err < 0 && err != -EIO)
1914 return err;
1915
1916 bridge = pci_upstream_bridge(dev);
1917 if (bridge)
1918 pcie_aspm_powersave_config_link(bridge);
1919
1920 err = pcibios_enable_device(dev, bars);
1921 if (err < 0)
1922 return err;
1923 pci_fixup_device(pci_fixup_enable, dev);
1924
1925 if (dev->msi_enabled || dev->msix_enabled)
1926 return 0;
1927
1928 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1929 if (pin) {
1930 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1931 if (cmd & PCI_COMMAND_INTX_DISABLE)
1932 pci_write_config_word(dev, PCI_COMMAND,
1933 cmd & ~PCI_COMMAND_INTX_DISABLE);
1934 }
1935
1936 return 0;
1937 }
1938
1939 /**
1940 * pci_reenable_device - Resume abandoned device
1941 * @dev: PCI device to be resumed
1942 *
1943 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1944 * to be called by normal code, write proper resume handler and use it instead.
1945 */
pci_reenable_device(struct pci_dev * dev)1946 int pci_reenable_device(struct pci_dev *dev)
1947 {
1948 if (pci_is_enabled(dev))
1949 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1950 return 0;
1951 }
1952 EXPORT_SYMBOL(pci_reenable_device);
1953
pci_enable_bridge(struct pci_dev * dev)1954 static void pci_enable_bridge(struct pci_dev *dev)
1955 {
1956 struct pci_dev *bridge;
1957 int retval;
1958
1959 bridge = pci_upstream_bridge(dev);
1960 if (bridge)
1961 pci_enable_bridge(bridge);
1962
1963 if (pci_is_enabled(dev)) {
1964 if (!dev->is_busmaster)
1965 pci_set_master(dev);
1966 return;
1967 }
1968
1969 retval = pci_enable_device(dev);
1970 if (retval)
1971 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1972 retval);
1973 pci_set_master(dev);
1974 }
1975
pci_enable_device_flags(struct pci_dev * dev,unsigned long flags)1976 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1977 {
1978 struct pci_dev *bridge;
1979 int err;
1980 int i, bars = 0;
1981
1982 /*
1983 * Power state could be unknown at this point, either due to a fresh
1984 * boot or a device removal call. So get the current power state
1985 * so that things like MSI message writing will behave as expected
1986 * (e.g. if the device really is in D0 at enable time).
1987 */
1988 pci_update_current_state(dev, dev->current_state);
1989
1990 if (atomic_inc_return(&dev->enable_cnt) > 1)
1991 return 0; /* already enabled */
1992
1993 bridge = pci_upstream_bridge(dev);
1994 if (bridge)
1995 pci_enable_bridge(bridge);
1996
1997 /* only skip sriov related */
1998 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1999 if (dev->resource[i].flags & flags)
2000 bars |= (1 << i);
2001 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
2002 if (dev->resource[i].flags & flags)
2003 bars |= (1 << i);
2004
2005 err = do_pci_enable_device(dev, bars);
2006 if (err < 0)
2007 atomic_dec(&dev->enable_cnt);
2008 return err;
2009 }
2010
2011 /**
2012 * pci_enable_device_io - Initialize a device for use with IO space
2013 * @dev: PCI device to be initialized
2014 *
2015 * Initialize device before it's used by a driver. Ask low-level code
2016 * to enable I/O resources. Wake up the device if it was suspended.
2017 * Beware, this function can fail.
2018 */
pci_enable_device_io(struct pci_dev * dev)2019 int pci_enable_device_io(struct pci_dev *dev)
2020 {
2021 return pci_enable_device_flags(dev, IORESOURCE_IO);
2022 }
2023 EXPORT_SYMBOL(pci_enable_device_io);
2024
2025 /**
2026 * pci_enable_device_mem - Initialize a device for use with Memory space
2027 * @dev: PCI device to be initialized
2028 *
2029 * Initialize device before it's used by a driver. Ask low-level code
2030 * to enable Memory resources. Wake up the device if it was suspended.
2031 * Beware, this function can fail.
2032 */
pci_enable_device_mem(struct pci_dev * dev)2033 int pci_enable_device_mem(struct pci_dev *dev)
2034 {
2035 return pci_enable_device_flags(dev, IORESOURCE_MEM);
2036 }
2037 EXPORT_SYMBOL(pci_enable_device_mem);
2038
2039 /**
2040 * pci_enable_device - Initialize device before it's used by a driver.
2041 * @dev: PCI device to be initialized
2042 *
2043 * Initialize device before it's used by a driver. Ask low-level code
2044 * to enable I/O and memory. Wake up the device if it was suspended.
2045 * Beware, this function can fail.
2046 *
2047 * Note we don't actually enable the device many times if we call
2048 * this function repeatedly (we just increment the count).
2049 */
pci_enable_device(struct pci_dev * dev)2050 int pci_enable_device(struct pci_dev *dev)
2051 {
2052 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2053 }
2054 EXPORT_SYMBOL(pci_enable_device);
2055
2056 /*
2057 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2058 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2059 * there's no need to track it separately. pci_devres is initialized
2060 * when a device is enabled using managed PCI device enable interface.
2061 */
2062 struct pci_devres {
2063 unsigned int enabled:1;
2064 unsigned int pinned:1;
2065 unsigned int orig_intx:1;
2066 unsigned int restore_intx:1;
2067 unsigned int mwi:1;
2068 u32 region_mask;
2069 };
2070
pcim_release(struct device * gendev,void * res)2071 static void pcim_release(struct device *gendev, void *res)
2072 {
2073 struct pci_dev *dev = to_pci_dev(gendev);
2074 struct pci_devres *this = res;
2075 int i;
2076
2077 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2078 if (this->region_mask & (1 << i))
2079 pci_release_region(dev, i);
2080
2081 if (this->mwi)
2082 pci_clear_mwi(dev);
2083
2084 if (this->restore_intx)
2085 pci_intx(dev, this->orig_intx);
2086
2087 if (this->enabled && !this->pinned)
2088 pci_disable_device(dev);
2089 }
2090
get_pci_dr(struct pci_dev * pdev)2091 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2092 {
2093 struct pci_devres *dr, *new_dr;
2094
2095 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2096 if (dr)
2097 return dr;
2098
2099 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2100 if (!new_dr)
2101 return NULL;
2102 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2103 }
2104
find_pci_dr(struct pci_dev * pdev)2105 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2106 {
2107 if (pci_is_managed(pdev))
2108 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2109 return NULL;
2110 }
2111
2112 /**
2113 * pcim_enable_device - Managed pci_enable_device()
2114 * @pdev: PCI device to be initialized
2115 *
2116 * Managed pci_enable_device().
2117 */
pcim_enable_device(struct pci_dev * pdev)2118 int pcim_enable_device(struct pci_dev *pdev)
2119 {
2120 struct pci_devres *dr;
2121 int rc;
2122
2123 dr = get_pci_dr(pdev);
2124 if (unlikely(!dr))
2125 return -ENOMEM;
2126 if (dr->enabled)
2127 return 0;
2128
2129 rc = pci_enable_device(pdev);
2130 if (!rc) {
2131 pdev->is_managed = 1;
2132 dr->enabled = 1;
2133 }
2134 return rc;
2135 }
2136 EXPORT_SYMBOL(pcim_enable_device);
2137
2138 /**
2139 * pcim_pin_device - Pin managed PCI device
2140 * @pdev: PCI device to pin
2141 *
2142 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2143 * driver detach. @pdev must have been enabled with
2144 * pcim_enable_device().
2145 */
pcim_pin_device(struct pci_dev * pdev)2146 void pcim_pin_device(struct pci_dev *pdev)
2147 {
2148 struct pci_devres *dr;
2149
2150 dr = find_pci_dr(pdev);
2151 WARN_ON(!dr || !dr->enabled);
2152 if (dr)
2153 dr->pinned = 1;
2154 }
2155 EXPORT_SYMBOL(pcim_pin_device);
2156
2157 /*
2158 * pcibios_device_add - provide arch specific hooks when adding device dev
2159 * @dev: the PCI device being added
2160 *
2161 * Permits the platform to provide architecture specific functionality when
2162 * devices are added. This is the default implementation. Architecture
2163 * implementations can override this.
2164 */
pcibios_device_add(struct pci_dev * dev)2165 int __weak pcibios_device_add(struct pci_dev *dev)
2166 {
2167 return 0;
2168 }
2169
2170 /**
2171 * pcibios_release_device - provide arch specific hooks when releasing
2172 * device dev
2173 * @dev: the PCI device being released
2174 *
2175 * Permits the platform to provide architecture specific functionality when
2176 * devices are released. This is the default implementation. Architecture
2177 * implementations can override this.
2178 */
pcibios_release_device(struct pci_dev * dev)2179 void __weak pcibios_release_device(struct pci_dev *dev) {}
2180
2181 /**
2182 * pcibios_disable_device - disable arch specific PCI resources for device dev
2183 * @dev: the PCI device to disable
2184 *
2185 * Disables architecture specific PCI resources for the device. This
2186 * is the default implementation. Architecture implementations can
2187 * override this.
2188 */
pcibios_disable_device(struct pci_dev * dev)2189 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2190
2191 /**
2192 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2193 * @irq: ISA IRQ to penalize
2194 * @active: IRQ active or not
2195 *
2196 * Permits the platform to provide architecture-specific functionality when
2197 * penalizing ISA IRQs. This is the default implementation. Architecture
2198 * implementations can override this.
2199 */
pcibios_penalize_isa_irq(int irq,int active)2200 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2201
do_pci_disable_device(struct pci_dev * dev)2202 static void do_pci_disable_device(struct pci_dev *dev)
2203 {
2204 u16 pci_command;
2205
2206 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2207 if (pci_command & PCI_COMMAND_MASTER) {
2208 pci_command &= ~PCI_COMMAND_MASTER;
2209 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2210 }
2211
2212 pcibios_disable_device(dev);
2213 }
2214
2215 /**
2216 * pci_disable_enabled_device - Disable device without updating enable_cnt
2217 * @dev: PCI device to disable
2218 *
2219 * NOTE: This function is a backend of PCI power management routines and is
2220 * not supposed to be called drivers.
2221 */
pci_disable_enabled_device(struct pci_dev * dev)2222 void pci_disable_enabled_device(struct pci_dev *dev)
2223 {
2224 if (pci_is_enabled(dev))
2225 do_pci_disable_device(dev);
2226 }
2227
2228 /**
2229 * pci_disable_device - Disable PCI device after use
2230 * @dev: PCI device to be disabled
2231 *
2232 * Signal to the system that the PCI device is not in use by the system
2233 * anymore. This only involves disabling PCI bus-mastering, if active.
2234 *
2235 * Note we don't actually disable the device until all callers of
2236 * pci_enable_device() have called pci_disable_device().
2237 */
pci_disable_device(struct pci_dev * dev)2238 void pci_disable_device(struct pci_dev *dev)
2239 {
2240 struct pci_devres *dr;
2241
2242 dr = find_pci_dr(dev);
2243 if (dr)
2244 dr->enabled = 0;
2245
2246 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2247 "disabling already-disabled device");
2248
2249 if (atomic_dec_return(&dev->enable_cnt) != 0)
2250 return;
2251
2252 do_pci_disable_device(dev);
2253
2254 dev->is_busmaster = 0;
2255 }
2256 EXPORT_SYMBOL(pci_disable_device);
2257
2258 /**
2259 * pcibios_set_pcie_reset_state - set reset state for device dev
2260 * @dev: the PCIe device reset
2261 * @state: Reset state to enter into
2262 *
2263 * Set the PCIe reset state for the device. This is the default
2264 * implementation. Architecture implementations can override this.
2265 */
pcibios_set_pcie_reset_state(struct pci_dev * dev,enum pcie_reset_state state)2266 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2267 enum pcie_reset_state state)
2268 {
2269 return -EINVAL;
2270 }
2271
2272 /**
2273 * pci_set_pcie_reset_state - set reset state for device dev
2274 * @dev: the PCIe device reset
2275 * @state: Reset state to enter into
2276 *
2277 * Sets the PCI reset state for the device.
2278 */
pci_set_pcie_reset_state(struct pci_dev * dev,enum pcie_reset_state state)2279 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2280 {
2281 return pcibios_set_pcie_reset_state(dev, state);
2282 }
2283 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2284
2285 #ifdef CONFIG_PCIEAER
pcie_clear_device_status(struct pci_dev * dev)2286 void pcie_clear_device_status(struct pci_dev *dev)
2287 {
2288 u16 sta;
2289
2290 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2291 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2292 }
2293 #endif
2294
2295 /**
2296 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2297 * @dev: PCIe root port or event collector.
2298 */
pcie_clear_root_pme_status(struct pci_dev * dev)2299 void pcie_clear_root_pme_status(struct pci_dev *dev)
2300 {
2301 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2302 }
2303
2304 /**
2305 * pci_check_pme_status - Check if given device has generated PME.
2306 * @dev: Device to check.
2307 *
2308 * Check the PME status of the device and if set, clear it and clear PME enable
2309 * (if set). Return 'true' if PME status and PME enable were both set or
2310 * 'false' otherwise.
2311 */
pci_check_pme_status(struct pci_dev * dev)2312 bool pci_check_pme_status(struct pci_dev *dev)
2313 {
2314 int pmcsr_pos;
2315 u16 pmcsr;
2316 bool ret = false;
2317
2318 if (!dev->pm_cap)
2319 return false;
2320
2321 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2322 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2323 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2324 return false;
2325
2326 /* Clear PME status. */
2327 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2328 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2329 /* Disable PME to avoid interrupt flood. */
2330 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2331 ret = true;
2332 }
2333
2334 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2335
2336 return ret;
2337 }
2338
2339 /**
2340 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2341 * @dev: Device to handle.
2342 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2343 *
2344 * Check if @dev has generated PME and queue a resume request for it in that
2345 * case.
2346 */
pci_pme_wakeup(struct pci_dev * dev,void * pme_poll_reset)2347 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2348 {
2349 if (pme_poll_reset && dev->pme_poll)
2350 dev->pme_poll = false;
2351
2352 if (pci_check_pme_status(dev)) {
2353 pci_wakeup_event(dev);
2354 pm_request_resume(&dev->dev);
2355 }
2356 return 0;
2357 }
2358
2359 /**
2360 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2361 * @bus: Top bus of the subtree to walk.
2362 */
pci_pme_wakeup_bus(struct pci_bus * bus)2363 void pci_pme_wakeup_bus(struct pci_bus *bus)
2364 {
2365 if (bus)
2366 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2367 }
2368
2369
2370 /**
2371 * pci_pme_capable - check the capability of PCI device to generate PME#
2372 * @dev: PCI device to handle.
2373 * @state: PCI state from which device will issue PME#.
2374 */
pci_pme_capable(struct pci_dev * dev,pci_power_t state)2375 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2376 {
2377 if (!dev->pm_cap)
2378 return false;
2379
2380 return !!(dev->pme_support & (1 << state));
2381 }
2382 EXPORT_SYMBOL(pci_pme_capable);
2383
pci_pme_list_scan(struct work_struct * work)2384 static void pci_pme_list_scan(struct work_struct *work)
2385 {
2386 struct pci_pme_device *pme_dev, *n;
2387
2388 mutex_lock(&pci_pme_list_mutex);
2389 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2390 if (pme_dev->dev->pme_poll) {
2391 struct pci_dev *bridge;
2392
2393 bridge = pme_dev->dev->bus->self;
2394 /*
2395 * If bridge is in low power state, the
2396 * configuration space of subordinate devices
2397 * may be not accessible
2398 */
2399 if (bridge && bridge->current_state != PCI_D0)
2400 continue;
2401 /*
2402 * If the device is in D3cold it should not be
2403 * polled either.
2404 */
2405 if (pme_dev->dev->current_state == PCI_D3cold)
2406 continue;
2407
2408 pci_pme_wakeup(pme_dev->dev, NULL);
2409 } else {
2410 list_del(&pme_dev->list);
2411 kfree(pme_dev);
2412 }
2413 }
2414 if (!list_empty(&pci_pme_list))
2415 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2416 msecs_to_jiffies(PME_TIMEOUT));
2417 mutex_unlock(&pci_pme_list_mutex);
2418 }
2419
__pci_pme_active(struct pci_dev * dev,bool enable)2420 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2421 {
2422 u16 pmcsr;
2423
2424 if (!dev->pme_support)
2425 return;
2426
2427 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2428 /* Clear PME_Status by writing 1 to it and enable PME# */
2429 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2430 if (!enable)
2431 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2432
2433 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2434 }
2435
2436 /**
2437 * pci_pme_restore - Restore PME configuration after config space restore.
2438 * @dev: PCI device to update.
2439 */
pci_pme_restore(struct pci_dev * dev)2440 void pci_pme_restore(struct pci_dev *dev)
2441 {
2442 u16 pmcsr;
2443
2444 if (!dev->pme_support)
2445 return;
2446
2447 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2448 if (dev->wakeup_prepared) {
2449 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2450 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2451 } else {
2452 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2453 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2454 }
2455 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2456 }
2457
2458 /**
2459 * pci_pme_active - enable or disable PCI device's PME# function
2460 * @dev: PCI device to handle.
2461 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2462 *
2463 * The caller must verify that the device is capable of generating PME# before
2464 * calling this function with @enable equal to 'true'.
2465 */
pci_pme_active(struct pci_dev * dev,bool enable)2466 void pci_pme_active(struct pci_dev *dev, bool enable)
2467 {
2468 __pci_pme_active(dev, enable);
2469
2470 /*
2471 * PCI (as opposed to PCIe) PME requires that the device have
2472 * its PME# line hooked up correctly. Not all hardware vendors
2473 * do this, so the PME never gets delivered and the device
2474 * remains asleep. The easiest way around this is to
2475 * periodically walk the list of suspended devices and check
2476 * whether any have their PME flag set. The assumption is that
2477 * we'll wake up often enough anyway that this won't be a huge
2478 * hit, and the power savings from the devices will still be a
2479 * win.
2480 *
2481 * Although PCIe uses in-band PME message instead of PME# line
2482 * to report PME, PME does not work for some PCIe devices in
2483 * reality. For example, there are devices that set their PME
2484 * status bits, but don't really bother to send a PME message;
2485 * there are PCI Express Root Ports that don't bother to
2486 * trigger interrupts when they receive PME messages from the
2487 * devices below. So PME poll is used for PCIe devices too.
2488 */
2489
2490 if (dev->pme_poll) {
2491 struct pci_pme_device *pme_dev;
2492 if (enable) {
2493 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2494 GFP_KERNEL);
2495 if (!pme_dev) {
2496 pci_warn(dev, "can't enable PME#\n");
2497 return;
2498 }
2499 pme_dev->dev = dev;
2500 mutex_lock(&pci_pme_list_mutex);
2501 list_add(&pme_dev->list, &pci_pme_list);
2502 if (list_is_singular(&pci_pme_list))
2503 queue_delayed_work(system_freezable_wq,
2504 &pci_pme_work,
2505 msecs_to_jiffies(PME_TIMEOUT));
2506 mutex_unlock(&pci_pme_list_mutex);
2507 } else {
2508 mutex_lock(&pci_pme_list_mutex);
2509 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2510 if (pme_dev->dev == dev) {
2511 list_del(&pme_dev->list);
2512 kfree(pme_dev);
2513 break;
2514 }
2515 }
2516 mutex_unlock(&pci_pme_list_mutex);
2517 }
2518 }
2519
2520 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2521 }
2522 EXPORT_SYMBOL(pci_pme_active);
2523
2524 /**
2525 * __pci_enable_wake - enable PCI device as wakeup event source
2526 * @dev: PCI device affected
2527 * @state: PCI state from which device will issue wakeup events
2528 * @enable: True to enable event generation; false to disable
2529 *
2530 * This enables the device as a wakeup event source, or disables it.
2531 * When such events involves platform-specific hooks, those hooks are
2532 * called automatically by this routine.
2533 *
2534 * Devices with legacy power management (no standard PCI PM capabilities)
2535 * always require such platform hooks.
2536 *
2537 * RETURN VALUE:
2538 * 0 is returned on success
2539 * -EINVAL is returned if device is not supposed to wake up the system
2540 * Error code depending on the platform is returned if both the platform and
2541 * the native mechanism fail to enable the generation of wake-up events
2542 */
__pci_enable_wake(struct pci_dev * dev,pci_power_t state,bool enable)2543 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2544 {
2545 int ret = 0;
2546
2547 /*
2548 * Bridges that are not power-manageable directly only signal
2549 * wakeup on behalf of subordinate devices which is set up
2550 * elsewhere, so skip them. However, bridges that are
2551 * power-manageable may signal wakeup for themselves (for example,
2552 * on a hotplug event) and they need to be covered here.
2553 */
2554 if (!pci_power_manageable(dev))
2555 return 0;
2556
2557 /* Don't do the same thing twice in a row for one device. */
2558 if (!!enable == !!dev->wakeup_prepared)
2559 return 0;
2560
2561 /*
2562 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2563 * Anderson we should be doing PME# wake enable followed by ACPI wake
2564 * enable. To disable wake-up we call the platform first, for symmetry.
2565 */
2566
2567 if (enable) {
2568 int error;
2569
2570 /*
2571 * Enable PME signaling if the device can signal PME from
2572 * D3cold regardless of whether or not it can signal PME from
2573 * the current target state, because that will allow it to
2574 * signal PME when the hierarchy above it goes into D3cold and
2575 * the device itself ends up in D3cold as a result of that.
2576 */
2577 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2578 pci_pme_active(dev, true);
2579 else
2580 ret = 1;
2581 error = platform_pci_set_wakeup(dev, true);
2582 if (ret)
2583 ret = error;
2584 if (!ret)
2585 dev->wakeup_prepared = true;
2586 } else {
2587 platform_pci_set_wakeup(dev, false);
2588 pci_pme_active(dev, false);
2589 dev->wakeup_prepared = false;
2590 }
2591
2592 return ret;
2593 }
2594
2595 /**
2596 * pci_enable_wake - change wakeup settings for a PCI device
2597 * @pci_dev: Target device
2598 * @state: PCI state from which device will issue wakeup events
2599 * @enable: Whether or not to enable event generation
2600 *
2601 * If @enable is set, check device_may_wakeup() for the device before calling
2602 * __pci_enable_wake() for it.
2603 */
pci_enable_wake(struct pci_dev * pci_dev,pci_power_t state,bool enable)2604 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2605 {
2606 if (enable && !device_may_wakeup(&pci_dev->dev))
2607 return -EINVAL;
2608
2609 return __pci_enable_wake(pci_dev, state, enable);
2610 }
2611 EXPORT_SYMBOL(pci_enable_wake);
2612
2613 /**
2614 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2615 * @dev: PCI device to prepare
2616 * @enable: True to enable wake-up event generation; false to disable
2617 *
2618 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2619 * and this function allows them to set that up cleanly - pci_enable_wake()
2620 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2621 * ordering constraints.
2622 *
2623 * This function only returns error code if the device is not allowed to wake
2624 * up the system from sleep or it is not capable of generating PME# from both
2625 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2626 */
pci_wake_from_d3(struct pci_dev * dev,bool enable)2627 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2628 {
2629 return pci_pme_capable(dev, PCI_D3cold) ?
2630 pci_enable_wake(dev, PCI_D3cold, enable) :
2631 pci_enable_wake(dev, PCI_D3hot, enable);
2632 }
2633 EXPORT_SYMBOL(pci_wake_from_d3);
2634
2635 /**
2636 * pci_target_state - find an appropriate low power state for a given PCI dev
2637 * @dev: PCI device
2638 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2639 *
2640 * Use underlying platform code to find a supported low power state for @dev.
2641 * If the platform can't manage @dev, return the deepest state from which it
2642 * can generate wake events, based on any available PME info.
2643 */
pci_target_state(struct pci_dev * dev,bool wakeup)2644 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2645 {
2646 if (platform_pci_power_manageable(dev)) {
2647 /*
2648 * Call the platform to find the target state for the device.
2649 */
2650 pci_power_t state = platform_pci_choose_state(dev);
2651
2652 switch (state) {
2653 case PCI_POWER_ERROR:
2654 case PCI_UNKNOWN:
2655 return PCI_D3hot;
2656
2657 case PCI_D1:
2658 case PCI_D2:
2659 if (pci_no_d1d2(dev))
2660 return PCI_D3hot;
2661 }
2662
2663 return state;
2664 }
2665
2666 /*
2667 * If the device is in D3cold even though it's not power-manageable by
2668 * the platform, it may have been powered down by non-standard means.
2669 * Best to let it slumber.
2670 */
2671 if (dev->current_state == PCI_D3cold)
2672 return PCI_D3cold;
2673 else if (!dev->pm_cap)
2674 return PCI_D0;
2675
2676 if (wakeup && dev->pme_support) {
2677 pci_power_t state = PCI_D3hot;
2678
2679 /*
2680 * Find the deepest state from which the device can generate
2681 * PME#.
2682 */
2683 while (state && !(dev->pme_support & (1 << state)))
2684 state--;
2685
2686 if (state)
2687 return state;
2688 else if (dev->pme_support & 1)
2689 return PCI_D0;
2690 }
2691
2692 return PCI_D3hot;
2693 }
2694
2695 /**
2696 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2697 * into a sleep state
2698 * @dev: Device to handle.
2699 *
2700 * Choose the power state appropriate for the device depending on whether
2701 * it can wake up the system and/or is power manageable by the platform
2702 * (PCI_D3hot is the default) and put the device into that state.
2703 */
pci_prepare_to_sleep(struct pci_dev * dev)2704 int pci_prepare_to_sleep(struct pci_dev *dev)
2705 {
2706 bool wakeup = device_may_wakeup(&dev->dev);
2707 pci_power_t target_state = pci_target_state(dev, wakeup);
2708 int error;
2709
2710 if (target_state == PCI_POWER_ERROR)
2711 return -EIO;
2712
2713 pci_enable_wake(dev, target_state, wakeup);
2714
2715 error = pci_set_power_state(dev, target_state);
2716
2717 if (error)
2718 pci_enable_wake(dev, target_state, false);
2719
2720 return error;
2721 }
2722 EXPORT_SYMBOL(pci_prepare_to_sleep);
2723
2724 /**
2725 * pci_back_from_sleep - turn PCI device on during system-wide transition
2726 * into working state
2727 * @dev: Device to handle.
2728 *
2729 * Disable device's system wake-up capability and put it into D0.
2730 */
pci_back_from_sleep(struct pci_dev * dev)2731 int pci_back_from_sleep(struct pci_dev *dev)
2732 {
2733 int ret = pci_set_power_state(dev, PCI_D0);
2734
2735 if (ret)
2736 return ret;
2737
2738 pci_enable_wake(dev, PCI_D0, false);
2739 return 0;
2740 }
2741 EXPORT_SYMBOL(pci_back_from_sleep);
2742
2743 /**
2744 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2745 * @dev: PCI device being suspended.
2746 *
2747 * Prepare @dev to generate wake-up events at run time and put it into a low
2748 * power state.
2749 */
pci_finish_runtime_suspend(struct pci_dev * dev)2750 int pci_finish_runtime_suspend(struct pci_dev *dev)
2751 {
2752 pci_power_t target_state;
2753 int error;
2754
2755 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2756 if (target_state == PCI_POWER_ERROR)
2757 return -EIO;
2758
2759 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2760
2761 error = pci_set_power_state(dev, target_state);
2762
2763 if (error)
2764 pci_enable_wake(dev, target_state, false);
2765
2766 return error;
2767 }
2768
2769 /**
2770 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2771 * @dev: Device to check.
2772 *
2773 * Return true if the device itself is capable of generating wake-up events
2774 * (through the platform or using the native PCIe PME) or if the device supports
2775 * PME and one of its upstream bridges can generate wake-up events.
2776 */
pci_dev_run_wake(struct pci_dev * dev)2777 bool pci_dev_run_wake(struct pci_dev *dev)
2778 {
2779 struct pci_bus *bus = dev->bus;
2780
2781 if (!dev->pme_support)
2782 return false;
2783
2784 /* PME-capable in principle, but not from the target power state */
2785 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2786 return false;
2787
2788 if (device_can_wakeup(&dev->dev))
2789 return true;
2790
2791 while (bus->parent) {
2792 struct pci_dev *bridge = bus->self;
2793
2794 if (device_can_wakeup(&bridge->dev))
2795 return true;
2796
2797 bus = bus->parent;
2798 }
2799
2800 /* We have reached the root bus. */
2801 if (bus->bridge)
2802 return device_can_wakeup(bus->bridge);
2803
2804 return false;
2805 }
2806 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2807
2808 /**
2809 * pci_dev_need_resume - Check if it is necessary to resume the device.
2810 * @pci_dev: Device to check.
2811 *
2812 * Return 'true' if the device is not runtime-suspended or it has to be
2813 * reconfigured due to wakeup settings difference between system and runtime
2814 * suspend, or the current power state of it is not suitable for the upcoming
2815 * (system-wide) transition.
2816 */
pci_dev_need_resume(struct pci_dev * pci_dev)2817 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2818 {
2819 struct device *dev = &pci_dev->dev;
2820 pci_power_t target_state;
2821
2822 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2823 return true;
2824
2825 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2826
2827 /*
2828 * If the earlier platform check has not triggered, D3cold is just power
2829 * removal on top of D3hot, so no need to resume the device in that
2830 * case.
2831 */
2832 return target_state != pci_dev->current_state &&
2833 target_state != PCI_D3cold &&
2834 pci_dev->current_state != PCI_D3hot;
2835 }
2836
2837 /**
2838 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2839 * @pci_dev: Device to check.
2840 *
2841 * If the device is suspended and it is not configured for system wakeup,
2842 * disable PME for it to prevent it from waking up the system unnecessarily.
2843 *
2844 * Note that if the device's power state is D3cold and the platform check in
2845 * pci_dev_need_resume() has not triggered, the device's configuration need not
2846 * be changed.
2847 */
pci_dev_adjust_pme(struct pci_dev * pci_dev)2848 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2849 {
2850 struct device *dev = &pci_dev->dev;
2851
2852 spin_lock_irq(&dev->power.lock);
2853
2854 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2855 pci_dev->current_state < PCI_D3cold)
2856 __pci_pme_active(pci_dev, false);
2857
2858 spin_unlock_irq(&dev->power.lock);
2859 }
2860
2861 /**
2862 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2863 * @pci_dev: Device to handle.
2864 *
2865 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2866 * it might have been disabled during the prepare phase of system suspend if
2867 * the device was not configured for system wakeup.
2868 */
pci_dev_complete_resume(struct pci_dev * pci_dev)2869 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2870 {
2871 struct device *dev = &pci_dev->dev;
2872
2873 if (!pci_dev_run_wake(pci_dev))
2874 return;
2875
2876 spin_lock_irq(&dev->power.lock);
2877
2878 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2879 __pci_pme_active(pci_dev, true);
2880
2881 spin_unlock_irq(&dev->power.lock);
2882 }
2883
2884 /**
2885 * pci_choose_state - Choose the power state of a PCI device.
2886 * @dev: Target PCI device.
2887 * @state: Target state for the whole system.
2888 *
2889 * Returns PCI power state suitable for @dev and @state.
2890 */
pci_choose_state(struct pci_dev * dev,pm_message_t state)2891 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
2892 {
2893 if (state.event == PM_EVENT_ON)
2894 return PCI_D0;
2895
2896 return pci_target_state(dev, false);
2897 }
2898 EXPORT_SYMBOL(pci_choose_state);
2899
pci_config_pm_runtime_get(struct pci_dev * pdev)2900 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2901 {
2902 struct device *dev = &pdev->dev;
2903 struct device *parent = dev->parent;
2904
2905 if (parent)
2906 pm_runtime_get_sync(parent);
2907 pm_runtime_get_noresume(dev);
2908 /*
2909 * pdev->current_state is set to PCI_D3cold during suspending,
2910 * so wait until suspending completes
2911 */
2912 pm_runtime_barrier(dev);
2913 /*
2914 * Only need to resume devices in D3cold, because config
2915 * registers are still accessible for devices suspended but
2916 * not in D3cold.
2917 */
2918 if (pdev->current_state == PCI_D3cold)
2919 pm_runtime_resume(dev);
2920 }
2921
pci_config_pm_runtime_put(struct pci_dev * pdev)2922 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2923 {
2924 struct device *dev = &pdev->dev;
2925 struct device *parent = dev->parent;
2926
2927 pm_runtime_put(dev);
2928 if (parent)
2929 pm_runtime_put_sync(parent);
2930 }
2931
2932 static const struct dmi_system_id bridge_d3_blacklist[] = {
2933 #ifdef CONFIG_X86
2934 {
2935 /*
2936 * Gigabyte X299 root port is not marked as hotplug capable
2937 * which allows Linux to power manage it. However, this
2938 * confuses the BIOS SMI handler so don't power manage root
2939 * ports on that system.
2940 */
2941 .ident = "X299 DESIGNARE EX-CF",
2942 .matches = {
2943 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2944 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2945 },
2946 },
2947 {
2948 /*
2949 * Downstream device is not accessible after putting a root port
2950 * into D3cold and back into D0 on Elo i2.
2951 */
2952 .ident = "Elo i2",
2953 .matches = {
2954 DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
2955 DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"),
2956 DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"),
2957 },
2958 },
2959 #endif
2960 { }
2961 };
2962
2963 /**
2964 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2965 * @bridge: Bridge to check
2966 *
2967 * This function checks if it is possible to move the bridge to D3.
2968 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2969 */
pci_bridge_d3_possible(struct pci_dev * bridge)2970 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2971 {
2972 if (!pci_is_pcie(bridge))
2973 return false;
2974
2975 switch (pci_pcie_type(bridge)) {
2976 case PCI_EXP_TYPE_ROOT_PORT:
2977 case PCI_EXP_TYPE_UPSTREAM:
2978 case PCI_EXP_TYPE_DOWNSTREAM:
2979 if (pci_bridge_d3_disable)
2980 return false;
2981
2982 /*
2983 * Hotplug ports handled by firmware in System Management Mode
2984 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2985 */
2986 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2987 return false;
2988
2989 if (pci_bridge_d3_force)
2990 return true;
2991
2992 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2993 if (bridge->is_thunderbolt)
2994 return true;
2995
2996 /* Platform might know better if the bridge supports D3 */
2997 if (platform_pci_bridge_d3(bridge))
2998 return true;
2999
3000 /*
3001 * Hotplug ports handled natively by the OS were not validated
3002 * by vendors for runtime D3 at least until 2018 because there
3003 * was no OS support.
3004 */
3005 if (bridge->is_hotplug_bridge)
3006 return false;
3007
3008 if (dmi_check_system(bridge_d3_blacklist))
3009 return false;
3010
3011 /*
3012 * It should be safe to put PCIe ports from 2015 or newer
3013 * to D3.
3014 */
3015 if (dmi_get_bios_year() >= 2015)
3016 return true;
3017 break;
3018 }
3019
3020 return false;
3021 }
3022
pci_dev_check_d3cold(struct pci_dev * dev,void * data)3023 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
3024 {
3025 bool *d3cold_ok = data;
3026
3027 if (/* The device needs to be allowed to go D3cold ... */
3028 dev->no_d3cold || !dev->d3cold_allowed ||
3029
3030 /* ... and if it is wakeup capable to do so from D3cold. */
3031 (device_may_wakeup(&dev->dev) &&
3032 !pci_pme_capable(dev, PCI_D3cold)) ||
3033
3034 /* If it is a bridge it must be allowed to go to D3. */
3035 !pci_power_manageable(dev))
3036
3037 *d3cold_ok = false;
3038
3039 return !*d3cold_ok;
3040 }
3041
3042 /*
3043 * pci_bridge_d3_update - Update bridge D3 capabilities
3044 * @dev: PCI device which is changed
3045 *
3046 * Update upstream bridge PM capabilities accordingly depending on if the
3047 * device PM configuration was changed or the device is being removed. The
3048 * change is also propagated upstream.
3049 */
pci_bridge_d3_update(struct pci_dev * dev)3050 void pci_bridge_d3_update(struct pci_dev *dev)
3051 {
3052 bool remove = !device_is_registered(&dev->dev);
3053 struct pci_dev *bridge;
3054 bool d3cold_ok = true;
3055
3056 bridge = pci_upstream_bridge(dev);
3057 if (!bridge || !pci_bridge_d3_possible(bridge))
3058 return;
3059
3060 /*
3061 * If D3 is currently allowed for the bridge, removing one of its
3062 * children won't change that.
3063 */
3064 if (remove && bridge->bridge_d3)
3065 return;
3066
3067 /*
3068 * If D3 is currently allowed for the bridge and a child is added or
3069 * changed, disallowance of D3 can only be caused by that child, so
3070 * we only need to check that single device, not any of its siblings.
3071 *
3072 * If D3 is currently not allowed for the bridge, checking the device
3073 * first may allow us to skip checking its siblings.
3074 */
3075 if (!remove)
3076 pci_dev_check_d3cold(dev, &d3cold_ok);
3077
3078 /*
3079 * If D3 is currently not allowed for the bridge, this may be caused
3080 * either by the device being changed/removed or any of its siblings,
3081 * so we need to go through all children to find out if one of them
3082 * continues to block D3.
3083 */
3084 if (d3cold_ok && !bridge->bridge_d3)
3085 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3086 &d3cold_ok);
3087
3088 if (bridge->bridge_d3 != d3cold_ok) {
3089 bridge->bridge_d3 = d3cold_ok;
3090 /* Propagate change to upstream bridges */
3091 pci_bridge_d3_update(bridge);
3092 }
3093 }
3094
3095 /**
3096 * pci_d3cold_enable - Enable D3cold for device
3097 * @dev: PCI device to handle
3098 *
3099 * This function can be used in drivers to enable D3cold from the device
3100 * they handle. It also updates upstream PCI bridge PM capabilities
3101 * accordingly.
3102 */
pci_d3cold_enable(struct pci_dev * dev)3103 void pci_d3cold_enable(struct pci_dev *dev)
3104 {
3105 if (dev->no_d3cold) {
3106 dev->no_d3cold = false;
3107 pci_bridge_d3_update(dev);
3108 }
3109 }
3110 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3111
3112 /**
3113 * pci_d3cold_disable - Disable D3cold for device
3114 * @dev: PCI device to handle
3115 *
3116 * This function can be used in drivers to disable D3cold from the device
3117 * they handle. It also updates upstream PCI bridge PM capabilities
3118 * accordingly.
3119 */
pci_d3cold_disable(struct pci_dev * dev)3120 void pci_d3cold_disable(struct pci_dev *dev)
3121 {
3122 if (!dev->no_d3cold) {
3123 dev->no_d3cold = true;
3124 pci_bridge_d3_update(dev);
3125 }
3126 }
3127 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3128
3129 /**
3130 * pci_pm_init - Initialize PM functions of given PCI device
3131 * @dev: PCI device to handle.
3132 */
pci_pm_init(struct pci_dev * dev)3133 void pci_pm_init(struct pci_dev *dev)
3134 {
3135 int pm;
3136 u16 status;
3137 u16 pmc;
3138
3139 pm_runtime_forbid(&dev->dev);
3140 pm_runtime_set_active(&dev->dev);
3141 pm_runtime_enable(&dev->dev);
3142 device_enable_async_suspend(&dev->dev);
3143 dev->wakeup_prepared = false;
3144
3145 dev->pm_cap = 0;
3146 dev->pme_support = 0;
3147
3148 /* find PCI PM capability in list */
3149 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3150 if (!pm)
3151 return;
3152 /* Check device's ability to generate PME# */
3153 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3154
3155 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3156 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3157 pmc & PCI_PM_CAP_VER_MASK);
3158 return;
3159 }
3160
3161 dev->pm_cap = pm;
3162 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3163 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3164 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3165 dev->d3cold_allowed = true;
3166
3167 dev->d1_support = false;
3168 dev->d2_support = false;
3169 if (!pci_no_d1d2(dev)) {
3170 if (pmc & PCI_PM_CAP_D1)
3171 dev->d1_support = true;
3172 if (pmc & PCI_PM_CAP_D2)
3173 dev->d2_support = true;
3174
3175 if (dev->d1_support || dev->d2_support)
3176 pci_info(dev, "supports%s%s\n",
3177 dev->d1_support ? " D1" : "",
3178 dev->d2_support ? " D2" : "");
3179 }
3180
3181 pmc &= PCI_PM_CAP_PME_MASK;
3182 if (pmc) {
3183 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3184 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3185 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3186 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3187 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3188 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3189 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3190 dev->pme_poll = true;
3191 /*
3192 * Make device's PM flags reflect the wake-up capability, but
3193 * let the user space enable it to wake up the system as needed.
3194 */
3195 device_set_wakeup_capable(&dev->dev, true);
3196 /* Disable the PME# generation functionality */
3197 pci_pme_active(dev, false);
3198 }
3199
3200 pci_read_config_word(dev, PCI_STATUS, &status);
3201 if (status & PCI_STATUS_IMM_READY)
3202 dev->imm_ready = 1;
3203 }
3204
pci_ea_flags(struct pci_dev * dev,u8 prop)3205 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3206 {
3207 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3208
3209 switch (prop) {
3210 case PCI_EA_P_MEM:
3211 case PCI_EA_P_VF_MEM:
3212 flags |= IORESOURCE_MEM;
3213 break;
3214 case PCI_EA_P_MEM_PREFETCH:
3215 case PCI_EA_P_VF_MEM_PREFETCH:
3216 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3217 break;
3218 case PCI_EA_P_IO:
3219 flags |= IORESOURCE_IO;
3220 break;
3221 default:
3222 return 0;
3223 }
3224
3225 return flags;
3226 }
3227
pci_ea_get_resource(struct pci_dev * dev,u8 bei,u8 prop)3228 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3229 u8 prop)
3230 {
3231 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3232 return &dev->resource[bei];
3233 #ifdef CONFIG_PCI_IOV
3234 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3235 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3236 return &dev->resource[PCI_IOV_RESOURCES +
3237 bei - PCI_EA_BEI_VF_BAR0];
3238 #endif
3239 else if (bei == PCI_EA_BEI_ROM)
3240 return &dev->resource[PCI_ROM_RESOURCE];
3241 else
3242 return NULL;
3243 }
3244
3245 /* Read an Enhanced Allocation (EA) entry */
pci_ea_read(struct pci_dev * dev,int offset)3246 static int pci_ea_read(struct pci_dev *dev, int offset)
3247 {
3248 struct resource *res;
3249 int ent_size, ent_offset = offset;
3250 resource_size_t start, end;
3251 unsigned long flags;
3252 u32 dw0, bei, base, max_offset;
3253 u8 prop;
3254 bool support_64 = (sizeof(resource_size_t) >= 8);
3255
3256 pci_read_config_dword(dev, ent_offset, &dw0);
3257 ent_offset += 4;
3258
3259 /* Entry size field indicates DWORDs after 1st */
3260 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3261
3262 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3263 goto out;
3264
3265 bei = (dw0 & PCI_EA_BEI) >> 4;
3266 prop = (dw0 & PCI_EA_PP) >> 8;
3267
3268 /*
3269 * If the Property is in the reserved range, try the Secondary
3270 * Property instead.
3271 */
3272 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3273 prop = (dw0 & PCI_EA_SP) >> 16;
3274 if (prop > PCI_EA_P_BRIDGE_IO)
3275 goto out;
3276
3277 res = pci_ea_get_resource(dev, bei, prop);
3278 if (!res) {
3279 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3280 goto out;
3281 }
3282
3283 flags = pci_ea_flags(dev, prop);
3284 if (!flags) {
3285 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3286 goto out;
3287 }
3288
3289 /* Read Base */
3290 pci_read_config_dword(dev, ent_offset, &base);
3291 start = (base & PCI_EA_FIELD_MASK);
3292 ent_offset += 4;
3293
3294 /* Read MaxOffset */
3295 pci_read_config_dword(dev, ent_offset, &max_offset);
3296 ent_offset += 4;
3297
3298 /* Read Base MSBs (if 64-bit entry) */
3299 if (base & PCI_EA_IS_64) {
3300 u32 base_upper;
3301
3302 pci_read_config_dword(dev, ent_offset, &base_upper);
3303 ent_offset += 4;
3304
3305 flags |= IORESOURCE_MEM_64;
3306
3307 /* entry starts above 32-bit boundary, can't use */
3308 if (!support_64 && base_upper)
3309 goto out;
3310
3311 if (support_64)
3312 start |= ((u64)base_upper << 32);
3313 }
3314
3315 end = start + (max_offset | 0x03);
3316
3317 /* Read MaxOffset MSBs (if 64-bit entry) */
3318 if (max_offset & PCI_EA_IS_64) {
3319 u32 max_offset_upper;
3320
3321 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3322 ent_offset += 4;
3323
3324 flags |= IORESOURCE_MEM_64;
3325
3326 /* entry too big, can't use */
3327 if (!support_64 && max_offset_upper)
3328 goto out;
3329
3330 if (support_64)
3331 end += ((u64)max_offset_upper << 32);
3332 }
3333
3334 if (end < start) {
3335 pci_err(dev, "EA Entry crosses address boundary\n");
3336 goto out;
3337 }
3338
3339 if (ent_size != ent_offset - offset) {
3340 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3341 ent_size, ent_offset - offset);
3342 goto out;
3343 }
3344
3345 res->name = pci_name(dev);
3346 res->start = start;
3347 res->end = end;
3348 res->flags = flags;
3349
3350 if (bei <= PCI_EA_BEI_BAR5)
3351 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3352 bei, res, prop);
3353 else if (bei == PCI_EA_BEI_ROM)
3354 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3355 res, prop);
3356 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3357 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3358 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3359 else
3360 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3361 bei, res, prop);
3362
3363 out:
3364 return offset + ent_size;
3365 }
3366
3367 /* Enhanced Allocation Initialization */
pci_ea_init(struct pci_dev * dev)3368 void pci_ea_init(struct pci_dev *dev)
3369 {
3370 int ea;
3371 u8 num_ent;
3372 int offset;
3373 int i;
3374
3375 /* find PCI EA capability in list */
3376 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3377 if (!ea)
3378 return;
3379
3380 /* determine the number of entries */
3381 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3382 &num_ent);
3383 num_ent &= PCI_EA_NUM_ENT_MASK;
3384
3385 offset = ea + PCI_EA_FIRST_ENT;
3386
3387 /* Skip DWORD 2 for type 1 functions */
3388 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3389 offset += 4;
3390
3391 /* parse each EA entry */
3392 for (i = 0; i < num_ent; ++i)
3393 offset = pci_ea_read(dev, offset);
3394 }
3395
pci_add_saved_cap(struct pci_dev * pci_dev,struct pci_cap_saved_state * new_cap)3396 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3397 struct pci_cap_saved_state *new_cap)
3398 {
3399 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3400 }
3401
3402 /**
3403 * _pci_add_cap_save_buffer - allocate buffer for saving given
3404 * capability registers
3405 * @dev: the PCI device
3406 * @cap: the capability to allocate the buffer for
3407 * @extended: Standard or Extended capability ID
3408 * @size: requested size of the buffer
3409 */
_pci_add_cap_save_buffer(struct pci_dev * dev,u16 cap,bool extended,unsigned int size)3410 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3411 bool extended, unsigned int size)
3412 {
3413 int pos;
3414 struct pci_cap_saved_state *save_state;
3415
3416 if (extended)
3417 pos = pci_find_ext_capability(dev, cap);
3418 else
3419 pos = pci_find_capability(dev, cap);
3420
3421 if (!pos)
3422 return 0;
3423
3424 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3425 if (!save_state)
3426 return -ENOMEM;
3427
3428 save_state->cap.cap_nr = cap;
3429 save_state->cap.cap_extended = extended;
3430 save_state->cap.size = size;
3431 pci_add_saved_cap(dev, save_state);
3432
3433 return 0;
3434 }
3435
pci_add_cap_save_buffer(struct pci_dev * dev,char cap,unsigned int size)3436 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3437 {
3438 return _pci_add_cap_save_buffer(dev, cap, false, size);
3439 }
3440
pci_add_ext_cap_save_buffer(struct pci_dev * dev,u16 cap,unsigned int size)3441 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3442 {
3443 return _pci_add_cap_save_buffer(dev, cap, true, size);
3444 }
3445
3446 /**
3447 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3448 * @dev: the PCI device
3449 */
pci_allocate_cap_save_buffers(struct pci_dev * dev)3450 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3451 {
3452 int error;
3453
3454 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3455 PCI_EXP_SAVE_REGS * sizeof(u16));
3456 if (error)
3457 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3458
3459 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3460 if (error)
3461 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3462
3463 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3464 2 * sizeof(u16));
3465 if (error)
3466 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3467
3468 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS,
3469 2 * sizeof(u32));
3470 if (error)
3471 pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n");
3472
3473 pci_allocate_vc_save_buffers(dev);
3474 }
3475
pci_free_cap_save_buffers(struct pci_dev * dev)3476 void pci_free_cap_save_buffers(struct pci_dev *dev)
3477 {
3478 struct pci_cap_saved_state *tmp;
3479 struct hlist_node *n;
3480
3481 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3482 kfree(tmp);
3483 }
3484
3485 /**
3486 * pci_configure_ari - enable or disable ARI forwarding
3487 * @dev: the PCI device
3488 *
3489 * If @dev and its upstream bridge both support ARI, enable ARI in the
3490 * bridge. Otherwise, disable ARI in the bridge.
3491 */
pci_configure_ari(struct pci_dev * dev)3492 void pci_configure_ari(struct pci_dev *dev)
3493 {
3494 u32 cap;
3495 struct pci_dev *bridge;
3496
3497 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3498 return;
3499
3500 bridge = dev->bus->self;
3501 if (!bridge)
3502 return;
3503
3504 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3505 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3506 return;
3507
3508 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3509 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3510 PCI_EXP_DEVCTL2_ARI);
3511 bridge->ari_enabled = 1;
3512 } else {
3513 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3514 PCI_EXP_DEVCTL2_ARI);
3515 bridge->ari_enabled = 0;
3516 }
3517 }
3518
pci_acs_flags_enabled(struct pci_dev * pdev,u16 acs_flags)3519 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3520 {
3521 int pos;
3522 u16 cap, ctrl;
3523
3524 pos = pdev->acs_cap;
3525 if (!pos)
3526 return false;
3527
3528 /*
3529 * Except for egress control, capabilities are either required
3530 * or only required if controllable. Features missing from the
3531 * capability field can therefore be assumed as hard-wired enabled.
3532 */
3533 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3534 acs_flags &= (cap | PCI_ACS_EC);
3535
3536 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3537 return (ctrl & acs_flags) == acs_flags;
3538 }
3539
3540 /**
3541 * pci_acs_enabled - test ACS against required flags for a given device
3542 * @pdev: device to test
3543 * @acs_flags: required PCI ACS flags
3544 *
3545 * Return true if the device supports the provided flags. Automatically
3546 * filters out flags that are not implemented on multifunction devices.
3547 *
3548 * Note that this interface checks the effective ACS capabilities of the
3549 * device rather than the actual capabilities. For instance, most single
3550 * function endpoints are not required to support ACS because they have no
3551 * opportunity for peer-to-peer access. We therefore return 'true'
3552 * regardless of whether the device exposes an ACS capability. This makes
3553 * it much easier for callers of this function to ignore the actual type
3554 * or topology of the device when testing ACS support.
3555 */
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)3556 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3557 {
3558 int ret;
3559
3560 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3561 if (ret >= 0)
3562 return ret > 0;
3563
3564 /*
3565 * Conventional PCI and PCI-X devices never support ACS, either
3566 * effectively or actually. The shared bus topology implies that
3567 * any device on the bus can receive or snoop DMA.
3568 */
3569 if (!pci_is_pcie(pdev))
3570 return false;
3571
3572 switch (pci_pcie_type(pdev)) {
3573 /*
3574 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3575 * but since their primary interface is PCI/X, we conservatively
3576 * handle them as we would a non-PCIe device.
3577 */
3578 case PCI_EXP_TYPE_PCIE_BRIDGE:
3579 /*
3580 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3581 * applicable... must never implement an ACS Extended Capability...".
3582 * This seems arbitrary, but we take a conservative interpretation
3583 * of this statement.
3584 */
3585 case PCI_EXP_TYPE_PCI_BRIDGE:
3586 case PCI_EXP_TYPE_RC_EC:
3587 return false;
3588 /*
3589 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3590 * implement ACS in order to indicate their peer-to-peer capabilities,
3591 * regardless of whether they are single- or multi-function devices.
3592 */
3593 case PCI_EXP_TYPE_DOWNSTREAM:
3594 case PCI_EXP_TYPE_ROOT_PORT:
3595 return pci_acs_flags_enabled(pdev, acs_flags);
3596 /*
3597 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3598 * implemented by the remaining PCIe types to indicate peer-to-peer
3599 * capabilities, but only when they are part of a multifunction
3600 * device. The footnote for section 6.12 indicates the specific
3601 * PCIe types included here.
3602 */
3603 case PCI_EXP_TYPE_ENDPOINT:
3604 case PCI_EXP_TYPE_UPSTREAM:
3605 case PCI_EXP_TYPE_LEG_END:
3606 case PCI_EXP_TYPE_RC_END:
3607 if (!pdev->multifunction)
3608 break;
3609
3610 return pci_acs_flags_enabled(pdev, acs_flags);
3611 }
3612
3613 /*
3614 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3615 * to single function devices with the exception of downstream ports.
3616 */
3617 return true;
3618 }
3619
3620 /**
3621 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3622 * @start: starting downstream device
3623 * @end: ending upstream device or NULL to search to the root bus
3624 * @acs_flags: required flags
3625 *
3626 * Walk up a device tree from start to end testing PCI ACS support. If
3627 * any step along the way does not support the required flags, return false.
3628 */
pci_acs_path_enabled(struct pci_dev * start,struct pci_dev * end,u16 acs_flags)3629 bool pci_acs_path_enabled(struct pci_dev *start,
3630 struct pci_dev *end, u16 acs_flags)
3631 {
3632 struct pci_dev *pdev, *parent = start;
3633
3634 do {
3635 pdev = parent;
3636
3637 if (!pci_acs_enabled(pdev, acs_flags))
3638 return false;
3639
3640 if (pci_is_root_bus(pdev->bus))
3641 return (end == NULL);
3642
3643 parent = pdev->bus->self;
3644 } while (pdev != end);
3645
3646 return true;
3647 }
3648
3649 /**
3650 * pci_acs_init - Initialize ACS if hardware supports it
3651 * @dev: the PCI device
3652 */
pci_acs_init(struct pci_dev * dev)3653 void pci_acs_init(struct pci_dev *dev)
3654 {
3655 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3656
3657 /*
3658 * Attempt to enable ACS regardless of capability because some Root
3659 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3660 * the standard ACS capability but still support ACS via those
3661 * quirks.
3662 */
3663 pci_enable_acs(dev);
3664 }
3665
3666 /**
3667 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3668 * @pdev: PCI device
3669 * @bar: BAR to find
3670 *
3671 * Helper to find the position of the ctrl register for a BAR.
3672 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3673 * Returns -ENOENT if no ctrl register for the BAR could be found.
3674 */
pci_rebar_find_pos(struct pci_dev * pdev,int bar)3675 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3676 {
3677 unsigned int pos, nbars, i;
3678 u32 ctrl;
3679
3680 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3681 if (!pos)
3682 return -ENOTSUPP;
3683
3684 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3685 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3686 PCI_REBAR_CTRL_NBAR_SHIFT;
3687
3688 for (i = 0; i < nbars; i++, pos += 8) {
3689 int bar_idx;
3690
3691 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3692 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3693 if (bar_idx == bar)
3694 return pos;
3695 }
3696
3697 return -ENOENT;
3698 }
3699
3700 /**
3701 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3702 * @pdev: PCI device
3703 * @bar: BAR to query
3704 *
3705 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3706 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3707 */
pci_rebar_get_possible_sizes(struct pci_dev * pdev,int bar)3708 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3709 {
3710 int pos;
3711 u32 cap;
3712
3713 pos = pci_rebar_find_pos(pdev, bar);
3714 if (pos < 0)
3715 return 0;
3716
3717 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3718 cap &= PCI_REBAR_CAP_SIZES;
3719
3720 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3721 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3722 bar == 0 && cap == 0x7000)
3723 cap = 0x3f000;
3724
3725 return cap >> 4;
3726 }
3727 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3728
3729 /**
3730 * pci_rebar_get_current_size - get the current size of a BAR
3731 * @pdev: PCI device
3732 * @bar: BAR to set size to
3733 *
3734 * Read the size of a BAR from the resizable BAR config.
3735 * Returns size if found or negative error code.
3736 */
pci_rebar_get_current_size(struct pci_dev * pdev,int bar)3737 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3738 {
3739 int pos;
3740 u32 ctrl;
3741
3742 pos = pci_rebar_find_pos(pdev, bar);
3743 if (pos < 0)
3744 return pos;
3745
3746 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3747 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3748 }
3749
3750 /**
3751 * pci_rebar_set_size - set a new size for a BAR
3752 * @pdev: PCI device
3753 * @bar: BAR to set size to
3754 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3755 *
3756 * Set the new size of a BAR as defined in the spec.
3757 * Returns zero if resizing was successful, error code otherwise.
3758 */
pci_rebar_set_size(struct pci_dev * pdev,int bar,int size)3759 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3760 {
3761 int pos;
3762 u32 ctrl;
3763
3764 pos = pci_rebar_find_pos(pdev, bar);
3765 if (pos < 0)
3766 return pos;
3767
3768 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3769 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3770 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3771 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3772 return 0;
3773 }
3774
3775 /**
3776 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3777 * @dev: the PCI device
3778 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3779 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3780 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3781 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3782 *
3783 * Return 0 if all upstream bridges support AtomicOp routing, egress
3784 * blocking is disabled on all upstream ports, and the root port supports
3785 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3786 * AtomicOp completion), or negative otherwise.
3787 */
pci_enable_atomic_ops_to_root(struct pci_dev * dev,u32 cap_mask)3788 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3789 {
3790 struct pci_bus *bus = dev->bus;
3791 struct pci_dev *bridge;
3792 u32 cap, ctl2;
3793
3794 /*
3795 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3796 * in Device Control 2 is reserved in VFs and the PF value applies
3797 * to all associated VFs.
3798 */
3799 if (dev->is_virtfn)
3800 return -EINVAL;
3801
3802 if (!pci_is_pcie(dev))
3803 return -EINVAL;
3804
3805 /*
3806 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3807 * AtomicOp requesters. For now, we only support endpoints as
3808 * requesters and root ports as completers. No endpoints as
3809 * completers, and no peer-to-peer.
3810 */
3811
3812 switch (pci_pcie_type(dev)) {
3813 case PCI_EXP_TYPE_ENDPOINT:
3814 case PCI_EXP_TYPE_LEG_END:
3815 case PCI_EXP_TYPE_RC_END:
3816 break;
3817 default:
3818 return -EINVAL;
3819 }
3820
3821 while (bus->parent) {
3822 bridge = bus->self;
3823
3824 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3825
3826 switch (pci_pcie_type(bridge)) {
3827 /* Ensure switch ports support AtomicOp routing */
3828 case PCI_EXP_TYPE_UPSTREAM:
3829 case PCI_EXP_TYPE_DOWNSTREAM:
3830 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3831 return -EINVAL;
3832 break;
3833
3834 /* Ensure root port supports all the sizes we care about */
3835 case PCI_EXP_TYPE_ROOT_PORT:
3836 if ((cap & cap_mask) != cap_mask)
3837 return -EINVAL;
3838 break;
3839 }
3840
3841 /* Ensure upstream ports don't block AtomicOps on egress */
3842 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3843 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3844 &ctl2);
3845 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3846 return -EINVAL;
3847 }
3848
3849 bus = bus->parent;
3850 }
3851
3852 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3853 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3854 return 0;
3855 }
3856 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3857
3858 /**
3859 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3860 * @dev: the PCI device
3861 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3862 *
3863 * Perform INTx swizzling for a device behind one level of bridge. This is
3864 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3865 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3866 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3867 * the PCI Express Base Specification, Revision 2.1)
3868 */
pci_swizzle_interrupt_pin(const struct pci_dev * dev,u8 pin)3869 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3870 {
3871 int slot;
3872
3873 if (pci_ari_enabled(dev->bus))
3874 slot = 0;
3875 else
3876 slot = PCI_SLOT(dev->devfn);
3877
3878 return (((pin - 1) + slot) % 4) + 1;
3879 }
3880
pci_get_interrupt_pin(struct pci_dev * dev,struct pci_dev ** bridge)3881 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3882 {
3883 u8 pin;
3884
3885 pin = dev->pin;
3886 if (!pin)
3887 return -1;
3888
3889 while (!pci_is_root_bus(dev->bus)) {
3890 pin = pci_swizzle_interrupt_pin(dev, pin);
3891 dev = dev->bus->self;
3892 }
3893 *bridge = dev;
3894 return pin;
3895 }
3896
3897 /**
3898 * pci_common_swizzle - swizzle INTx all the way to root bridge
3899 * @dev: the PCI device
3900 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3901 *
3902 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3903 * bridges all the way up to a PCI root bus.
3904 */
pci_common_swizzle(struct pci_dev * dev,u8 * pinp)3905 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3906 {
3907 u8 pin = *pinp;
3908
3909 while (!pci_is_root_bus(dev->bus)) {
3910 pin = pci_swizzle_interrupt_pin(dev, pin);
3911 dev = dev->bus->self;
3912 }
3913 *pinp = pin;
3914 return PCI_SLOT(dev->devfn);
3915 }
3916 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3917
3918 /**
3919 * pci_release_region - Release a PCI bar
3920 * @pdev: PCI device whose resources were previously reserved by
3921 * pci_request_region()
3922 * @bar: BAR to release
3923 *
3924 * Releases the PCI I/O and memory resources previously reserved by a
3925 * successful call to pci_request_region(). Call this function only
3926 * after all use of the PCI regions has ceased.
3927 */
pci_release_region(struct pci_dev * pdev,int bar)3928 void pci_release_region(struct pci_dev *pdev, int bar)
3929 {
3930 struct pci_devres *dr;
3931
3932 if (pci_resource_len(pdev, bar) == 0)
3933 return;
3934 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3935 release_region(pci_resource_start(pdev, bar),
3936 pci_resource_len(pdev, bar));
3937 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3938 release_mem_region(pci_resource_start(pdev, bar),
3939 pci_resource_len(pdev, bar));
3940
3941 dr = find_pci_dr(pdev);
3942 if (dr)
3943 dr->region_mask &= ~(1 << bar);
3944 }
3945 EXPORT_SYMBOL(pci_release_region);
3946
3947 /**
3948 * __pci_request_region - Reserved PCI I/O and memory resource
3949 * @pdev: PCI device whose resources are to be reserved
3950 * @bar: BAR to be reserved
3951 * @res_name: Name to be associated with resource.
3952 * @exclusive: whether the region access is exclusive or not
3953 *
3954 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3955 * being reserved by owner @res_name. Do not access any
3956 * address inside the PCI regions unless this call returns
3957 * successfully.
3958 *
3959 * If @exclusive is set, then the region is marked so that userspace
3960 * is explicitly not allowed to map the resource via /dev/mem or
3961 * sysfs MMIO access.
3962 *
3963 * Returns 0 on success, or %EBUSY on error. A warning
3964 * message is also printed on failure.
3965 */
__pci_request_region(struct pci_dev * pdev,int bar,const char * res_name,int exclusive)3966 static int __pci_request_region(struct pci_dev *pdev, int bar,
3967 const char *res_name, int exclusive)
3968 {
3969 struct pci_devres *dr;
3970
3971 if (pci_resource_len(pdev, bar) == 0)
3972 return 0;
3973
3974 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3975 if (!request_region(pci_resource_start(pdev, bar),
3976 pci_resource_len(pdev, bar), res_name))
3977 goto err_out;
3978 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3979 if (!__request_mem_region(pci_resource_start(pdev, bar),
3980 pci_resource_len(pdev, bar), res_name,
3981 exclusive))
3982 goto err_out;
3983 }
3984
3985 dr = find_pci_dr(pdev);
3986 if (dr)
3987 dr->region_mask |= 1 << bar;
3988
3989 return 0;
3990
3991 err_out:
3992 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3993 &pdev->resource[bar]);
3994 return -EBUSY;
3995 }
3996
3997 /**
3998 * pci_request_region - Reserve PCI I/O and memory resource
3999 * @pdev: PCI device whose resources are to be reserved
4000 * @bar: BAR to be reserved
4001 * @res_name: Name to be associated with resource
4002 *
4003 * Mark the PCI region associated with PCI device @pdev BAR @bar as
4004 * being reserved by owner @res_name. Do not access any
4005 * address inside the PCI regions unless this call returns
4006 * successfully.
4007 *
4008 * Returns 0 on success, or %EBUSY on error. A warning
4009 * message is also printed on failure.
4010 */
pci_request_region(struct pci_dev * pdev,int bar,const char * res_name)4011 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
4012 {
4013 return __pci_request_region(pdev, bar, res_name, 0);
4014 }
4015 EXPORT_SYMBOL(pci_request_region);
4016
4017 /**
4018 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4019 * @pdev: PCI device whose resources were previously reserved
4020 * @bars: Bitmask of BARs to be released
4021 *
4022 * Release selected PCI I/O and memory resources previously reserved.
4023 * Call this function only after all use of the PCI regions has ceased.
4024 */
pci_release_selected_regions(struct pci_dev * pdev,int bars)4025 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
4026 {
4027 int i;
4028
4029 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4030 if (bars & (1 << i))
4031 pci_release_region(pdev, i);
4032 }
4033 EXPORT_SYMBOL(pci_release_selected_regions);
4034
__pci_request_selected_regions(struct pci_dev * pdev,int bars,const char * res_name,int excl)4035 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
4036 const char *res_name, int excl)
4037 {
4038 int i;
4039
4040 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4041 if (bars & (1 << i))
4042 if (__pci_request_region(pdev, i, res_name, excl))
4043 goto err_out;
4044 return 0;
4045
4046 err_out:
4047 while (--i >= 0)
4048 if (bars & (1 << i))
4049 pci_release_region(pdev, i);
4050
4051 return -EBUSY;
4052 }
4053
4054
4055 /**
4056 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4057 * @pdev: PCI device whose resources are to be reserved
4058 * @bars: Bitmask of BARs to be requested
4059 * @res_name: Name to be associated with resource
4060 */
pci_request_selected_regions(struct pci_dev * pdev,int bars,const char * res_name)4061 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4062 const char *res_name)
4063 {
4064 return __pci_request_selected_regions(pdev, bars, res_name, 0);
4065 }
4066 EXPORT_SYMBOL(pci_request_selected_regions);
4067
pci_request_selected_regions_exclusive(struct pci_dev * pdev,int bars,const char * res_name)4068 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4069 const char *res_name)
4070 {
4071 return __pci_request_selected_regions(pdev, bars, res_name,
4072 IORESOURCE_EXCLUSIVE);
4073 }
4074 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4075
4076 /**
4077 * pci_release_regions - Release reserved PCI I/O and memory resources
4078 * @pdev: PCI device whose resources were previously reserved by
4079 * pci_request_regions()
4080 *
4081 * Releases all PCI I/O and memory resources previously reserved by a
4082 * successful call to pci_request_regions(). Call this function only
4083 * after all use of the PCI regions has ceased.
4084 */
4085
pci_release_regions(struct pci_dev * pdev)4086 void pci_release_regions(struct pci_dev *pdev)
4087 {
4088 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4089 }
4090 EXPORT_SYMBOL(pci_release_regions);
4091
4092 /**
4093 * pci_request_regions - Reserve PCI I/O and memory resources
4094 * @pdev: PCI device whose resources are to be reserved
4095 * @res_name: Name to be associated with resource.
4096 *
4097 * Mark all PCI regions associated with PCI device @pdev as
4098 * being reserved by owner @res_name. Do not access any
4099 * address inside the PCI regions unless this call returns
4100 * successfully.
4101 *
4102 * Returns 0 on success, or %EBUSY on error. A warning
4103 * message is also printed on failure.
4104 */
pci_request_regions(struct pci_dev * pdev,const char * res_name)4105 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4106 {
4107 return pci_request_selected_regions(pdev,
4108 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4109 }
4110 EXPORT_SYMBOL(pci_request_regions);
4111
4112 /**
4113 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4114 * @pdev: PCI device whose resources are to be reserved
4115 * @res_name: Name to be associated with resource.
4116 *
4117 * Mark all PCI regions associated with PCI device @pdev as being reserved
4118 * by owner @res_name. Do not access any address inside the PCI regions
4119 * unless this call returns successfully.
4120 *
4121 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4122 * and the sysfs MMIO access will not be allowed.
4123 *
4124 * Returns 0 on success, or %EBUSY on error. A warning message is also
4125 * printed on failure.
4126 */
pci_request_regions_exclusive(struct pci_dev * pdev,const char * res_name)4127 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4128 {
4129 return pci_request_selected_regions_exclusive(pdev,
4130 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4131 }
4132 EXPORT_SYMBOL(pci_request_regions_exclusive);
4133
4134 /*
4135 * Record the PCI IO range (expressed as CPU physical address + size).
4136 * Return a negative value if an error has occurred, zero otherwise
4137 */
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)4138 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4139 resource_size_t size)
4140 {
4141 int ret = 0;
4142 #ifdef PCI_IOBASE
4143 struct logic_pio_hwaddr *range;
4144
4145 if (!size || addr + size < addr)
4146 return -EINVAL;
4147
4148 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4149 if (!range)
4150 return -ENOMEM;
4151
4152 range->fwnode = fwnode;
4153 range->size = size;
4154 range->hw_start = addr;
4155 range->flags = LOGIC_PIO_CPU_MMIO;
4156
4157 ret = logic_pio_register_range(range);
4158 if (ret)
4159 kfree(range);
4160
4161 /* Ignore duplicates due to deferred probing */
4162 if (ret == -EEXIST)
4163 ret = 0;
4164 #endif
4165
4166 return ret;
4167 }
4168
pci_pio_to_address(unsigned long pio)4169 phys_addr_t pci_pio_to_address(unsigned long pio)
4170 {
4171 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4172
4173 #ifdef PCI_IOBASE
4174 if (pio >= MMIO_UPPER_LIMIT)
4175 return address;
4176
4177 address = logic_pio_to_hwaddr(pio);
4178 #endif
4179
4180 return address;
4181 }
4182 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4183
pci_address_to_pio(phys_addr_t address)4184 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4185 {
4186 #ifdef PCI_IOBASE
4187 return logic_pio_trans_cpuaddr(address);
4188 #else
4189 if (address > IO_SPACE_LIMIT)
4190 return (unsigned long)-1;
4191
4192 return (unsigned long) address;
4193 #endif
4194 }
4195
4196 /**
4197 * pci_remap_iospace - Remap the memory mapped I/O space
4198 * @res: Resource describing the I/O space
4199 * @phys_addr: physical address of range to be mapped
4200 *
4201 * Remap the memory mapped I/O space described by the @res and the CPU
4202 * physical address @phys_addr into virtual address space. Only
4203 * architectures that have memory mapped IO functions defined (and the
4204 * PCI_IOBASE value defined) should call this function.
4205 */
4206 #ifndef pci_remap_iospace
pci_remap_iospace(const struct resource * res,phys_addr_t phys_addr)4207 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4208 {
4209 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4210 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4211
4212 if (!(res->flags & IORESOURCE_IO))
4213 return -EINVAL;
4214
4215 if (res->end > IO_SPACE_LIMIT)
4216 return -EINVAL;
4217
4218 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4219 pgprot_device(PAGE_KERNEL));
4220 #else
4221 /*
4222 * This architecture does not have memory mapped I/O space,
4223 * so this function should never be called
4224 */
4225 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4226 return -ENODEV;
4227 #endif
4228 }
4229 EXPORT_SYMBOL(pci_remap_iospace);
4230 #endif
4231
4232 /**
4233 * pci_unmap_iospace - Unmap the memory mapped I/O space
4234 * @res: resource to be unmapped
4235 *
4236 * Unmap the CPU virtual address @res from virtual address space. Only
4237 * architectures that have memory mapped IO functions defined (and the
4238 * PCI_IOBASE value defined) should call this function.
4239 */
pci_unmap_iospace(struct resource * res)4240 void pci_unmap_iospace(struct resource *res)
4241 {
4242 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4243 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4244
4245 vunmap_range(vaddr, vaddr + resource_size(res));
4246 #endif
4247 }
4248 EXPORT_SYMBOL(pci_unmap_iospace);
4249
devm_pci_unmap_iospace(struct device * dev,void * ptr)4250 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4251 {
4252 struct resource **res = ptr;
4253
4254 pci_unmap_iospace(*res);
4255 }
4256
4257 /**
4258 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4259 * @dev: Generic device to remap IO address for
4260 * @res: Resource describing the I/O space
4261 * @phys_addr: physical address of range to be mapped
4262 *
4263 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4264 * detach.
4265 */
devm_pci_remap_iospace(struct device * dev,const struct resource * res,phys_addr_t phys_addr)4266 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4267 phys_addr_t phys_addr)
4268 {
4269 const struct resource **ptr;
4270 int error;
4271
4272 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4273 if (!ptr)
4274 return -ENOMEM;
4275
4276 error = pci_remap_iospace(res, phys_addr);
4277 if (error) {
4278 devres_free(ptr);
4279 } else {
4280 *ptr = res;
4281 devres_add(dev, ptr);
4282 }
4283
4284 return error;
4285 }
4286 EXPORT_SYMBOL(devm_pci_remap_iospace);
4287
4288 /**
4289 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4290 * @dev: Generic device to remap IO address for
4291 * @offset: Resource address to map
4292 * @size: Size of map
4293 *
4294 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4295 * detach.
4296 */
devm_pci_remap_cfgspace(struct device * dev,resource_size_t offset,resource_size_t size)4297 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4298 resource_size_t offset,
4299 resource_size_t size)
4300 {
4301 void __iomem **ptr, *addr;
4302
4303 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4304 if (!ptr)
4305 return NULL;
4306
4307 addr = pci_remap_cfgspace(offset, size);
4308 if (addr) {
4309 *ptr = addr;
4310 devres_add(dev, ptr);
4311 } else
4312 devres_free(ptr);
4313
4314 return addr;
4315 }
4316 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4317
4318 /**
4319 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4320 * @dev: generic device to handle the resource for
4321 * @res: configuration space resource to be handled
4322 *
4323 * Checks that a resource is a valid memory region, requests the memory
4324 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4325 * proper PCI configuration space memory attributes are guaranteed.
4326 *
4327 * All operations are managed and will be undone on driver detach.
4328 *
4329 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4330 * on failure. Usage example::
4331 *
4332 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4333 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4334 * if (IS_ERR(base))
4335 * return PTR_ERR(base);
4336 */
devm_pci_remap_cfg_resource(struct device * dev,struct resource * res)4337 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4338 struct resource *res)
4339 {
4340 resource_size_t size;
4341 const char *name;
4342 void __iomem *dest_ptr;
4343
4344 BUG_ON(!dev);
4345
4346 if (!res || resource_type(res) != IORESOURCE_MEM) {
4347 dev_err(dev, "invalid resource\n");
4348 return IOMEM_ERR_PTR(-EINVAL);
4349 }
4350
4351 size = resource_size(res);
4352
4353 if (res->name)
4354 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4355 res->name);
4356 else
4357 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4358 if (!name)
4359 return IOMEM_ERR_PTR(-ENOMEM);
4360
4361 if (!devm_request_mem_region(dev, res->start, size, name)) {
4362 dev_err(dev, "can't request region for resource %pR\n", res);
4363 return IOMEM_ERR_PTR(-EBUSY);
4364 }
4365
4366 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4367 if (!dest_ptr) {
4368 dev_err(dev, "ioremap failed for resource %pR\n", res);
4369 devm_release_mem_region(dev, res->start, size);
4370 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4371 }
4372
4373 return dest_ptr;
4374 }
4375 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4376
__pci_set_master(struct pci_dev * dev,bool enable)4377 static void __pci_set_master(struct pci_dev *dev, bool enable)
4378 {
4379 u16 old_cmd, cmd;
4380
4381 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4382 if (enable)
4383 cmd = old_cmd | PCI_COMMAND_MASTER;
4384 else
4385 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4386 if (cmd != old_cmd) {
4387 pci_dbg(dev, "%s bus mastering\n",
4388 enable ? "enabling" : "disabling");
4389 pci_write_config_word(dev, PCI_COMMAND, cmd);
4390 }
4391 dev->is_busmaster = enable;
4392 }
4393
4394 /**
4395 * pcibios_setup - process "pci=" kernel boot arguments
4396 * @str: string used to pass in "pci=" kernel boot arguments
4397 *
4398 * Process kernel boot arguments. This is the default implementation.
4399 * Architecture specific implementations can override this as necessary.
4400 */
pcibios_setup(char * str)4401 char * __weak __init pcibios_setup(char *str)
4402 {
4403 return str;
4404 }
4405
4406 /**
4407 * pcibios_set_master - enable PCI bus-mastering for device dev
4408 * @dev: the PCI device to enable
4409 *
4410 * Enables PCI bus-mastering for the device. This is the default
4411 * implementation. Architecture specific implementations can override
4412 * this if necessary.
4413 */
pcibios_set_master(struct pci_dev * dev)4414 void __weak pcibios_set_master(struct pci_dev *dev)
4415 {
4416 u8 lat;
4417
4418 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4419 if (pci_is_pcie(dev))
4420 return;
4421
4422 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4423 if (lat < 16)
4424 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4425 else if (lat > pcibios_max_latency)
4426 lat = pcibios_max_latency;
4427 else
4428 return;
4429
4430 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4431 }
4432
4433 /**
4434 * pci_set_master - enables bus-mastering for device dev
4435 * @dev: the PCI device to enable
4436 *
4437 * Enables bus-mastering on the device and calls pcibios_set_master()
4438 * to do the needed arch specific settings.
4439 */
pci_set_master(struct pci_dev * dev)4440 void pci_set_master(struct pci_dev *dev)
4441 {
4442 __pci_set_master(dev, true);
4443 pcibios_set_master(dev);
4444 }
4445 EXPORT_SYMBOL(pci_set_master);
4446
4447 /**
4448 * pci_clear_master - disables bus-mastering for device dev
4449 * @dev: the PCI device to disable
4450 */
pci_clear_master(struct pci_dev * dev)4451 void pci_clear_master(struct pci_dev *dev)
4452 {
4453 __pci_set_master(dev, false);
4454 }
4455 EXPORT_SYMBOL(pci_clear_master);
4456
4457 /**
4458 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4459 * @dev: the PCI device for which MWI is to be enabled
4460 *
4461 * Helper function for pci_set_mwi.
4462 * Originally copied from drivers/net/acenic.c.
4463 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4464 *
4465 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4466 */
pci_set_cacheline_size(struct pci_dev * dev)4467 int pci_set_cacheline_size(struct pci_dev *dev)
4468 {
4469 u8 cacheline_size;
4470
4471 if (!pci_cache_line_size)
4472 return -EINVAL;
4473
4474 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4475 equal to or multiple of the right value. */
4476 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4477 if (cacheline_size >= pci_cache_line_size &&
4478 (cacheline_size % pci_cache_line_size) == 0)
4479 return 0;
4480
4481 /* Write the correct value. */
4482 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4483 /* Read it back. */
4484 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4485 if (cacheline_size == pci_cache_line_size)
4486 return 0;
4487
4488 pci_dbg(dev, "cache line size of %d is not supported\n",
4489 pci_cache_line_size << 2);
4490
4491 return -EINVAL;
4492 }
4493 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4494
4495 /**
4496 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4497 * @dev: the PCI device for which MWI is enabled
4498 *
4499 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4500 *
4501 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4502 */
pci_set_mwi(struct pci_dev * dev)4503 int pci_set_mwi(struct pci_dev *dev)
4504 {
4505 #ifdef PCI_DISABLE_MWI
4506 return 0;
4507 #else
4508 int rc;
4509 u16 cmd;
4510
4511 rc = pci_set_cacheline_size(dev);
4512 if (rc)
4513 return rc;
4514
4515 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4516 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4517 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4518 cmd |= PCI_COMMAND_INVALIDATE;
4519 pci_write_config_word(dev, PCI_COMMAND, cmd);
4520 }
4521 return 0;
4522 #endif
4523 }
4524 EXPORT_SYMBOL(pci_set_mwi);
4525
4526 /**
4527 * pcim_set_mwi - a device-managed pci_set_mwi()
4528 * @dev: the PCI device for which MWI is enabled
4529 *
4530 * Managed pci_set_mwi().
4531 *
4532 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4533 */
pcim_set_mwi(struct pci_dev * dev)4534 int pcim_set_mwi(struct pci_dev *dev)
4535 {
4536 struct pci_devres *dr;
4537
4538 dr = find_pci_dr(dev);
4539 if (!dr)
4540 return -ENOMEM;
4541
4542 dr->mwi = 1;
4543 return pci_set_mwi(dev);
4544 }
4545 EXPORT_SYMBOL(pcim_set_mwi);
4546
4547 /**
4548 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4549 * @dev: the PCI device for which MWI is enabled
4550 *
4551 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4552 * Callers are not required to check the return value.
4553 *
4554 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4555 */
pci_try_set_mwi(struct pci_dev * dev)4556 int pci_try_set_mwi(struct pci_dev *dev)
4557 {
4558 #ifdef PCI_DISABLE_MWI
4559 return 0;
4560 #else
4561 return pci_set_mwi(dev);
4562 #endif
4563 }
4564 EXPORT_SYMBOL(pci_try_set_mwi);
4565
4566 /**
4567 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4568 * @dev: the PCI device to disable
4569 *
4570 * Disables PCI Memory-Write-Invalidate transaction on the device
4571 */
pci_clear_mwi(struct pci_dev * dev)4572 void pci_clear_mwi(struct pci_dev *dev)
4573 {
4574 #ifndef PCI_DISABLE_MWI
4575 u16 cmd;
4576
4577 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4578 if (cmd & PCI_COMMAND_INVALIDATE) {
4579 cmd &= ~PCI_COMMAND_INVALIDATE;
4580 pci_write_config_word(dev, PCI_COMMAND, cmd);
4581 }
4582 #endif
4583 }
4584 EXPORT_SYMBOL(pci_clear_mwi);
4585
4586 /**
4587 * pci_disable_parity - disable parity checking for device
4588 * @dev: the PCI device to operate on
4589 *
4590 * Disable parity checking for device @dev
4591 */
pci_disable_parity(struct pci_dev * dev)4592 void pci_disable_parity(struct pci_dev *dev)
4593 {
4594 u16 cmd;
4595
4596 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4597 if (cmd & PCI_COMMAND_PARITY) {
4598 cmd &= ~PCI_COMMAND_PARITY;
4599 pci_write_config_word(dev, PCI_COMMAND, cmd);
4600 }
4601 }
4602
4603 /**
4604 * pci_intx - enables/disables PCI INTx for device dev
4605 * @pdev: the PCI device to operate on
4606 * @enable: boolean: whether to enable or disable PCI INTx
4607 *
4608 * Enables/disables PCI INTx for device @pdev
4609 */
pci_intx(struct pci_dev * pdev,int enable)4610 void pci_intx(struct pci_dev *pdev, int enable)
4611 {
4612 u16 pci_command, new;
4613
4614 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4615
4616 if (enable)
4617 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4618 else
4619 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4620
4621 if (new != pci_command) {
4622 struct pci_devres *dr;
4623
4624 pci_write_config_word(pdev, PCI_COMMAND, new);
4625
4626 dr = find_pci_dr(pdev);
4627 if (dr && !dr->restore_intx) {
4628 dr->restore_intx = 1;
4629 dr->orig_intx = !enable;
4630 }
4631 }
4632 }
4633 EXPORT_SYMBOL_GPL(pci_intx);
4634
pci_check_and_set_intx_mask(struct pci_dev * dev,bool mask)4635 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4636 {
4637 struct pci_bus *bus = dev->bus;
4638 bool mask_updated = true;
4639 u32 cmd_status_dword;
4640 u16 origcmd, newcmd;
4641 unsigned long flags;
4642 bool irq_pending;
4643
4644 /*
4645 * We do a single dword read to retrieve both command and status.
4646 * Document assumptions that make this possible.
4647 */
4648 BUILD_BUG_ON(PCI_COMMAND % 4);
4649 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4650
4651 raw_spin_lock_irqsave(&pci_lock, flags);
4652
4653 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4654
4655 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4656
4657 /*
4658 * Check interrupt status register to see whether our device
4659 * triggered the interrupt (when masking) or the next IRQ is
4660 * already pending (when unmasking).
4661 */
4662 if (mask != irq_pending) {
4663 mask_updated = false;
4664 goto done;
4665 }
4666
4667 origcmd = cmd_status_dword;
4668 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4669 if (mask)
4670 newcmd |= PCI_COMMAND_INTX_DISABLE;
4671 if (newcmd != origcmd)
4672 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4673
4674 done:
4675 raw_spin_unlock_irqrestore(&pci_lock, flags);
4676
4677 return mask_updated;
4678 }
4679
4680 /**
4681 * pci_check_and_mask_intx - mask INTx on pending interrupt
4682 * @dev: the PCI device to operate on
4683 *
4684 * Check if the device dev has its INTx line asserted, mask it and return
4685 * true in that case. False is returned if no interrupt was pending.
4686 */
pci_check_and_mask_intx(struct pci_dev * dev)4687 bool pci_check_and_mask_intx(struct pci_dev *dev)
4688 {
4689 return pci_check_and_set_intx_mask(dev, true);
4690 }
4691 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4692
4693 /**
4694 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4695 * @dev: the PCI device to operate on
4696 *
4697 * Check if the device dev has its INTx line asserted, unmask it if not and
4698 * return true. False is returned and the mask remains active if there was
4699 * still an interrupt pending.
4700 */
pci_check_and_unmask_intx(struct pci_dev * dev)4701 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4702 {
4703 return pci_check_and_set_intx_mask(dev, false);
4704 }
4705 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4706
4707 /**
4708 * pci_wait_for_pending_transaction - wait for pending transaction
4709 * @dev: the PCI device to operate on
4710 *
4711 * Return 0 if transaction is pending 1 otherwise.
4712 */
pci_wait_for_pending_transaction(struct pci_dev * dev)4713 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4714 {
4715 if (!pci_is_pcie(dev))
4716 return 1;
4717
4718 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4719 PCI_EXP_DEVSTA_TRPND);
4720 }
4721 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4722
4723 /**
4724 * pcie_flr - initiate a PCIe function level reset
4725 * @dev: device to reset
4726 *
4727 * Initiate a function level reset unconditionally on @dev without
4728 * checking any flags and DEVCAP
4729 */
pcie_flr(struct pci_dev * dev)4730 int pcie_flr(struct pci_dev *dev)
4731 {
4732 if (!pci_wait_for_pending_transaction(dev))
4733 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4734
4735 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4736
4737 if (dev->imm_ready)
4738 return 0;
4739
4740 /*
4741 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4742 * 100ms, but may silently discard requests while the FLR is in
4743 * progress. Wait 100ms before trying to access the device.
4744 */
4745 msleep(100);
4746
4747 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4748 }
4749 EXPORT_SYMBOL_GPL(pcie_flr);
4750
4751 /**
4752 * pcie_reset_flr - initiate a PCIe function level reset
4753 * @dev: device to reset
4754 * @probe: if true, return 0 if device can be reset this way
4755 *
4756 * Initiate a function level reset on @dev.
4757 */
pcie_reset_flr(struct pci_dev * dev,bool probe)4758 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4759 {
4760 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4761 return -ENOTTY;
4762
4763 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4764 return -ENOTTY;
4765
4766 if (probe)
4767 return 0;
4768
4769 return pcie_flr(dev);
4770 }
4771 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4772
pci_af_flr(struct pci_dev * dev,bool probe)4773 static int pci_af_flr(struct pci_dev *dev, bool probe)
4774 {
4775 int pos;
4776 u8 cap;
4777
4778 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4779 if (!pos)
4780 return -ENOTTY;
4781
4782 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4783 return -ENOTTY;
4784
4785 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4786 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4787 return -ENOTTY;
4788
4789 if (probe)
4790 return 0;
4791
4792 /*
4793 * Wait for Transaction Pending bit to clear. A word-aligned test
4794 * is used, so we use the control offset rather than status and shift
4795 * the test bit to match.
4796 */
4797 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4798 PCI_AF_STATUS_TP << 8))
4799 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4800
4801 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4802
4803 if (dev->imm_ready)
4804 return 0;
4805
4806 /*
4807 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4808 * updated 27 July 2006; a device must complete an FLR within
4809 * 100ms, but may silently discard requests while the FLR is in
4810 * progress. Wait 100ms before trying to access the device.
4811 */
4812 msleep(100);
4813
4814 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4815 }
4816
4817 /**
4818 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4819 * @dev: Device to reset.
4820 * @probe: if true, return 0 if the device can be reset this way.
4821 *
4822 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4823 * unset, it will be reinitialized internally when going from PCI_D3hot to
4824 * PCI_D0. If that's the case and the device is not in a low-power state
4825 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4826 *
4827 * NOTE: This causes the caller to sleep for twice the device power transition
4828 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4829 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4830 * Moreover, only devices in D0 can be reset by this function.
4831 */
pci_pm_reset(struct pci_dev * dev,bool probe)4832 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4833 {
4834 u16 csr;
4835
4836 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4837 return -ENOTTY;
4838
4839 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4840 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4841 return -ENOTTY;
4842
4843 if (probe)
4844 return 0;
4845
4846 if (dev->current_state != PCI_D0)
4847 return -EINVAL;
4848
4849 csr &= ~PCI_PM_CTRL_STATE_MASK;
4850 csr |= PCI_D3hot;
4851 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4852 pci_dev_d3_sleep(dev);
4853
4854 csr &= ~PCI_PM_CTRL_STATE_MASK;
4855 csr |= PCI_D0;
4856 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4857 pci_dev_d3_sleep(dev);
4858
4859 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4860 }
4861
4862 /**
4863 * pcie_wait_for_link_delay - Wait until link is active or inactive
4864 * @pdev: Bridge device
4865 * @active: waiting for active or inactive?
4866 * @delay: Delay to wait after link has become active (in ms)
4867 *
4868 * Use this to wait till link becomes active or inactive.
4869 */
pcie_wait_for_link_delay(struct pci_dev * pdev,bool active,int delay)4870 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4871 int delay)
4872 {
4873 int timeout = 1000;
4874 bool ret;
4875 u16 lnk_status;
4876
4877 /*
4878 * Some controllers might not implement link active reporting. In this
4879 * case, we wait for 1000 ms + any delay requested by the caller.
4880 */
4881 if (!pdev->link_active_reporting) {
4882 msleep(timeout + delay);
4883 return true;
4884 }
4885
4886 /*
4887 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4888 * after which we should expect an link active if the reset was
4889 * successful. If so, software must wait a minimum 100ms before sending
4890 * configuration requests to devices downstream this port.
4891 *
4892 * If the link fails to activate, either the device was physically
4893 * removed or the link is permanently failed.
4894 */
4895 if (active)
4896 msleep(20);
4897 for (;;) {
4898 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4899 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4900 if (ret == active)
4901 break;
4902 if (timeout <= 0)
4903 break;
4904 msleep(10);
4905 timeout -= 10;
4906 }
4907 if (active && ret)
4908 msleep(delay);
4909
4910 return ret == active;
4911 }
4912
4913 /**
4914 * pcie_wait_for_link - Wait until link is active or inactive
4915 * @pdev: Bridge device
4916 * @active: waiting for active or inactive?
4917 *
4918 * Use this to wait till link becomes active or inactive.
4919 */
pcie_wait_for_link(struct pci_dev * pdev,bool active)4920 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4921 {
4922 return pcie_wait_for_link_delay(pdev, active, 100);
4923 }
4924
4925 /*
4926 * Find maximum D3cold delay required by all the devices on the bus. The
4927 * spec says 100 ms, but firmware can lower it and we allow drivers to
4928 * increase it as well.
4929 *
4930 * Called with @pci_bus_sem locked for reading.
4931 */
pci_bus_max_d3cold_delay(const struct pci_bus * bus)4932 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4933 {
4934 const struct pci_dev *pdev;
4935 int min_delay = 100;
4936 int max_delay = 0;
4937
4938 list_for_each_entry(pdev, &bus->devices, bus_list) {
4939 if (pdev->d3cold_delay < min_delay)
4940 min_delay = pdev->d3cold_delay;
4941 if (pdev->d3cold_delay > max_delay)
4942 max_delay = pdev->d3cold_delay;
4943 }
4944
4945 return max(min_delay, max_delay);
4946 }
4947
4948 /**
4949 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4950 * @dev: PCI bridge
4951 *
4952 * Handle necessary delays before access to the devices on the secondary
4953 * side of the bridge are permitted after D3cold to D0 transition.
4954 *
4955 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4956 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4957 * 4.3.2.
4958 */
pci_bridge_wait_for_secondary_bus(struct pci_dev * dev)4959 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4960 {
4961 struct pci_dev *child;
4962 int delay;
4963
4964 if (pci_dev_is_disconnected(dev))
4965 return;
4966
4967 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4968 return;
4969
4970 down_read(&pci_bus_sem);
4971
4972 /*
4973 * We only deal with devices that are present currently on the bus.
4974 * For any hot-added devices the access delay is handled in pciehp
4975 * board_added(). In case of ACPI hotplug the firmware is expected
4976 * to configure the devices before OS is notified.
4977 */
4978 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4979 up_read(&pci_bus_sem);
4980 return;
4981 }
4982
4983 /* Take d3cold_delay requirements into account */
4984 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4985 if (!delay) {
4986 up_read(&pci_bus_sem);
4987 return;
4988 }
4989
4990 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4991 bus_list);
4992 up_read(&pci_bus_sem);
4993
4994 /*
4995 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4996 * accessing the device after reset (that is 1000 ms + 100 ms). In
4997 * practice this should not be needed because we don't do power
4998 * management for them (see pci_bridge_d3_possible()).
4999 */
5000 if (!pci_is_pcie(dev)) {
5001 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5002 msleep(1000 + delay);
5003 return;
5004 }
5005
5006 /*
5007 * For PCIe downstream and root ports that do not support speeds
5008 * greater than 5 GT/s need to wait minimum 100 ms. For higher
5009 * speeds (gen3) we need to wait first for the data link layer to
5010 * become active.
5011 *
5012 * However, 100 ms is the minimum and the PCIe spec says the
5013 * software must allow at least 1s before it can determine that the
5014 * device that did not respond is a broken device. There is
5015 * evidence that 100 ms is not always enough, for example certain
5016 * Titan Ridge xHCI controller does not always respond to
5017 * configuration requests if we only wait for 100 ms (see
5018 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
5019 *
5020 * Therefore we wait for 100 ms and check for the device presence.
5021 * If it is still not present give it an additional 100 ms.
5022 */
5023 if (!pcie_downstream_port(dev))
5024 return;
5025
5026 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
5027 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5028 msleep(delay);
5029 } else {
5030 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5031 delay);
5032 if (!pcie_wait_for_link_delay(dev, true, delay)) {
5033 /* Did not train, no need to wait any further */
5034 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
5035 return;
5036 }
5037 }
5038
5039 if (!pci_device_is_present(child)) {
5040 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
5041 msleep(delay);
5042 }
5043 }
5044
pci_reset_secondary_bus(struct pci_dev * dev)5045 void pci_reset_secondary_bus(struct pci_dev *dev)
5046 {
5047 u16 ctrl;
5048
5049 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5050 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
5051 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5052
5053 /*
5054 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5055 * this to 2ms to ensure that we meet the minimum requirement.
5056 */
5057 msleep(2);
5058
5059 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5060 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5061
5062 /*
5063 * Trhfa for conventional PCI is 2^25 clock cycles.
5064 * Assuming a minimum 33MHz clock this results in a 1s
5065 * delay before we can consider subordinate devices to
5066 * be re-initialized. PCIe has some ways to shorten this,
5067 * but we don't make use of them yet.
5068 */
5069 ssleep(1);
5070 }
5071
pcibios_reset_secondary_bus(struct pci_dev * dev)5072 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5073 {
5074 pci_reset_secondary_bus(dev);
5075 }
5076
5077 /**
5078 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5079 * @dev: Bridge device
5080 *
5081 * Use the bridge control register to assert reset on the secondary bus.
5082 * Devices on the secondary bus are left in power-on state.
5083 */
pci_bridge_secondary_bus_reset(struct pci_dev * dev)5084 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5085 {
5086 pcibios_reset_secondary_bus(dev);
5087
5088 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
5089 }
5090 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5091
pci_parent_bus_reset(struct pci_dev * dev,bool probe)5092 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5093 {
5094 struct pci_dev *pdev;
5095
5096 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5097 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5098 return -ENOTTY;
5099
5100 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5101 if (pdev != dev)
5102 return -ENOTTY;
5103
5104 if (probe)
5105 return 0;
5106
5107 return pci_bridge_secondary_bus_reset(dev->bus->self);
5108 }
5109
pci_reset_hotplug_slot(struct hotplug_slot * hotplug,bool probe)5110 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5111 {
5112 int rc = -ENOTTY;
5113
5114 if (!hotplug || !try_module_get(hotplug->owner))
5115 return rc;
5116
5117 if (hotplug->ops->reset_slot)
5118 rc = hotplug->ops->reset_slot(hotplug, probe);
5119
5120 module_put(hotplug->owner);
5121
5122 return rc;
5123 }
5124
pci_dev_reset_slot_function(struct pci_dev * dev,bool probe)5125 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5126 {
5127 if (dev->multifunction || dev->subordinate || !dev->slot ||
5128 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5129 return -ENOTTY;
5130
5131 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5132 }
5133
pci_reset_bus_function(struct pci_dev * dev,bool probe)5134 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5135 {
5136 int rc;
5137
5138 rc = pci_dev_reset_slot_function(dev, probe);
5139 if (rc != -ENOTTY)
5140 return rc;
5141 return pci_parent_bus_reset(dev, probe);
5142 }
5143
pci_dev_lock(struct pci_dev * dev)5144 void pci_dev_lock(struct pci_dev *dev)
5145 {
5146 /* block PM suspend, driver probe, etc. */
5147 device_lock(&dev->dev);
5148 pci_cfg_access_lock(dev);
5149 }
5150 EXPORT_SYMBOL_GPL(pci_dev_lock);
5151
5152 /* Return 1 on successful lock, 0 on contention */
pci_dev_trylock(struct pci_dev * dev)5153 int pci_dev_trylock(struct pci_dev *dev)
5154 {
5155 if (device_trylock(&dev->dev)) {
5156 if (pci_cfg_access_trylock(dev))
5157 return 1;
5158 device_unlock(&dev->dev);
5159 }
5160
5161 return 0;
5162 }
5163 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5164
pci_dev_unlock(struct pci_dev * dev)5165 void pci_dev_unlock(struct pci_dev *dev)
5166 {
5167 pci_cfg_access_unlock(dev);
5168 device_unlock(&dev->dev);
5169 }
5170 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5171
pci_dev_save_and_disable(struct pci_dev * dev)5172 static void pci_dev_save_and_disable(struct pci_dev *dev)
5173 {
5174 const struct pci_error_handlers *err_handler =
5175 dev->driver ? dev->driver->err_handler : NULL;
5176
5177 /*
5178 * dev->driver->err_handler->reset_prepare() is protected against
5179 * races with ->remove() by the device lock, which must be held by
5180 * the caller.
5181 */
5182 if (err_handler && err_handler->reset_prepare)
5183 err_handler->reset_prepare(dev);
5184
5185 /*
5186 * Wake-up device prior to save. PM registers default to D0 after
5187 * reset and a simple register restore doesn't reliably return
5188 * to a non-D0 state anyway.
5189 */
5190 pci_set_power_state(dev, PCI_D0);
5191
5192 pci_save_state(dev);
5193 /*
5194 * Disable the device by clearing the Command register, except for
5195 * INTx-disable which is set. This not only disables MMIO and I/O port
5196 * BARs, but also prevents the device from being Bus Master, preventing
5197 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5198 * compliant devices, INTx-disable prevents legacy interrupts.
5199 */
5200 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5201 }
5202
pci_dev_restore(struct pci_dev * dev)5203 static void pci_dev_restore(struct pci_dev *dev)
5204 {
5205 const struct pci_error_handlers *err_handler =
5206 dev->driver ? dev->driver->err_handler : NULL;
5207
5208 pci_restore_state(dev);
5209
5210 /*
5211 * dev->driver->err_handler->reset_done() is protected against
5212 * races with ->remove() by the device lock, which must be held by
5213 * the caller.
5214 */
5215 if (err_handler && err_handler->reset_done)
5216 err_handler->reset_done(dev);
5217 }
5218
5219 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5220 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5221 { },
5222 { pci_dev_specific_reset, .name = "device_specific" },
5223 { pci_dev_acpi_reset, .name = "acpi" },
5224 { pcie_reset_flr, .name = "flr" },
5225 { pci_af_flr, .name = "af_flr" },
5226 { pci_pm_reset, .name = "pm" },
5227 { pci_reset_bus_function, .name = "bus" },
5228 };
5229
reset_method_show(struct device * dev,struct device_attribute * attr,char * buf)5230 static ssize_t reset_method_show(struct device *dev,
5231 struct device_attribute *attr, char *buf)
5232 {
5233 struct pci_dev *pdev = to_pci_dev(dev);
5234 ssize_t len = 0;
5235 int i, m;
5236
5237 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5238 m = pdev->reset_methods[i];
5239 if (!m)
5240 break;
5241
5242 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5243 pci_reset_fn_methods[m].name);
5244 }
5245
5246 if (len)
5247 len += sysfs_emit_at(buf, len, "\n");
5248
5249 return len;
5250 }
5251
reset_method_lookup(const char * name)5252 static int reset_method_lookup(const char *name)
5253 {
5254 int m;
5255
5256 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5257 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5258 return m;
5259 }
5260
5261 return 0; /* not found */
5262 }
5263
reset_method_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)5264 static ssize_t reset_method_store(struct device *dev,
5265 struct device_attribute *attr,
5266 const char *buf, size_t count)
5267 {
5268 struct pci_dev *pdev = to_pci_dev(dev);
5269 char *options, *name;
5270 int m, n;
5271 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5272
5273 if (sysfs_streq(buf, "")) {
5274 pdev->reset_methods[0] = 0;
5275 pci_warn(pdev, "All device reset methods disabled by user");
5276 return count;
5277 }
5278
5279 if (sysfs_streq(buf, "default")) {
5280 pci_init_reset_methods(pdev);
5281 return count;
5282 }
5283
5284 options = kstrndup(buf, count, GFP_KERNEL);
5285 if (!options)
5286 return -ENOMEM;
5287
5288 n = 0;
5289 while ((name = strsep(&options, " ")) != NULL) {
5290 if (sysfs_streq(name, ""))
5291 continue;
5292
5293 name = strim(name);
5294
5295 m = reset_method_lookup(name);
5296 if (!m) {
5297 pci_err(pdev, "Invalid reset method '%s'", name);
5298 goto error;
5299 }
5300
5301 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5302 pci_err(pdev, "Unsupported reset method '%s'", name);
5303 goto error;
5304 }
5305
5306 if (n == PCI_NUM_RESET_METHODS - 1) {
5307 pci_err(pdev, "Too many reset methods\n");
5308 goto error;
5309 }
5310
5311 reset_methods[n++] = m;
5312 }
5313
5314 reset_methods[n] = 0;
5315
5316 /* Warn if dev-specific supported but not highest priority */
5317 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5318 reset_methods[0] != 1)
5319 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5320 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5321 kfree(options);
5322 return count;
5323
5324 error:
5325 /* Leave previous methods unchanged */
5326 kfree(options);
5327 return -EINVAL;
5328 }
5329 static DEVICE_ATTR_RW(reset_method);
5330
5331 static struct attribute *pci_dev_reset_method_attrs[] = {
5332 &dev_attr_reset_method.attr,
5333 NULL,
5334 };
5335
pci_dev_reset_method_attr_is_visible(struct kobject * kobj,struct attribute * a,int n)5336 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5337 struct attribute *a, int n)
5338 {
5339 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5340
5341 if (!pci_reset_supported(pdev))
5342 return 0;
5343
5344 return a->mode;
5345 }
5346
5347 const struct attribute_group pci_dev_reset_method_attr_group = {
5348 .attrs = pci_dev_reset_method_attrs,
5349 .is_visible = pci_dev_reset_method_attr_is_visible,
5350 };
5351
5352 /**
5353 * __pci_reset_function_locked - reset a PCI device function while holding
5354 * the @dev mutex lock.
5355 * @dev: PCI device to reset
5356 *
5357 * Some devices allow an individual function to be reset without affecting
5358 * other functions in the same device. The PCI device must be responsive
5359 * to PCI config space in order to use this function.
5360 *
5361 * The device function is presumed to be unused and the caller is holding
5362 * the device mutex lock when this function is called.
5363 *
5364 * Resetting the device will make the contents of PCI configuration space
5365 * random, so any caller of this must be prepared to reinitialise the
5366 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5367 * etc.
5368 *
5369 * Returns 0 if the device function was successfully reset or negative if the
5370 * device doesn't support resetting a single function.
5371 */
__pci_reset_function_locked(struct pci_dev * dev)5372 int __pci_reset_function_locked(struct pci_dev *dev)
5373 {
5374 int i, m, rc;
5375
5376 might_sleep();
5377
5378 /*
5379 * A reset method returns -ENOTTY if it doesn't support this device and
5380 * we should try the next method.
5381 *
5382 * If it returns 0 (success), we're finished. If it returns any other
5383 * error, we're also finished: this indicates that further reset
5384 * mechanisms might be broken on the device.
5385 */
5386 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5387 m = dev->reset_methods[i];
5388 if (!m)
5389 return -ENOTTY;
5390
5391 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5392 if (!rc)
5393 return 0;
5394 if (rc != -ENOTTY)
5395 return rc;
5396 }
5397
5398 return -ENOTTY;
5399 }
5400 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5401
5402 /**
5403 * pci_init_reset_methods - check whether device can be safely reset
5404 * and store supported reset mechanisms.
5405 * @dev: PCI device to check for reset mechanisms
5406 *
5407 * Some devices allow an individual function to be reset without affecting
5408 * other functions in the same device. The PCI device must be in D0-D3hot
5409 * state.
5410 *
5411 * Stores reset mechanisms supported by device in reset_methods byte array
5412 * which is a member of struct pci_dev.
5413 */
pci_init_reset_methods(struct pci_dev * dev)5414 void pci_init_reset_methods(struct pci_dev *dev)
5415 {
5416 int m, i, rc;
5417
5418 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5419
5420 might_sleep();
5421
5422 i = 0;
5423 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5424 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5425 if (!rc)
5426 dev->reset_methods[i++] = m;
5427 else if (rc != -ENOTTY)
5428 break;
5429 }
5430
5431 dev->reset_methods[i] = 0;
5432 }
5433
5434 /**
5435 * pci_reset_function - quiesce and reset a PCI device function
5436 * @dev: PCI device to reset
5437 *
5438 * Some devices allow an individual function to be reset without affecting
5439 * other functions in the same device. The PCI device must be responsive
5440 * to PCI config space in order to use this function.
5441 *
5442 * This function does not just reset the PCI portion of a device, but
5443 * clears all the state associated with the device. This function differs
5444 * from __pci_reset_function_locked() in that it saves and restores device state
5445 * over the reset and takes the PCI device lock.
5446 *
5447 * Returns 0 if the device function was successfully reset or negative if the
5448 * device doesn't support resetting a single function.
5449 */
pci_reset_function(struct pci_dev * dev)5450 int pci_reset_function(struct pci_dev *dev)
5451 {
5452 int rc;
5453
5454 if (!pci_reset_supported(dev))
5455 return -ENOTTY;
5456
5457 pci_dev_lock(dev);
5458 pci_dev_save_and_disable(dev);
5459
5460 rc = __pci_reset_function_locked(dev);
5461
5462 pci_dev_restore(dev);
5463 pci_dev_unlock(dev);
5464
5465 return rc;
5466 }
5467 EXPORT_SYMBOL_GPL(pci_reset_function);
5468
5469 /**
5470 * pci_reset_function_locked - quiesce and reset a PCI device function
5471 * @dev: PCI device to reset
5472 *
5473 * Some devices allow an individual function to be reset without affecting
5474 * other functions in the same device. The PCI device must be responsive
5475 * to PCI config space in order to use this function.
5476 *
5477 * This function does not just reset the PCI portion of a device, but
5478 * clears all the state associated with the device. This function differs
5479 * from __pci_reset_function_locked() in that it saves and restores device state
5480 * over the reset. It also differs from pci_reset_function() in that it
5481 * requires the PCI device lock to be held.
5482 *
5483 * Returns 0 if the device function was successfully reset or negative if the
5484 * device doesn't support resetting a single function.
5485 */
pci_reset_function_locked(struct pci_dev * dev)5486 int pci_reset_function_locked(struct pci_dev *dev)
5487 {
5488 int rc;
5489
5490 if (!pci_reset_supported(dev))
5491 return -ENOTTY;
5492
5493 pci_dev_save_and_disable(dev);
5494
5495 rc = __pci_reset_function_locked(dev);
5496
5497 pci_dev_restore(dev);
5498
5499 return rc;
5500 }
5501 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5502
5503 /**
5504 * pci_try_reset_function - quiesce and reset a PCI device function
5505 * @dev: PCI device to reset
5506 *
5507 * Same as above, except return -EAGAIN if unable to lock device.
5508 */
pci_try_reset_function(struct pci_dev * dev)5509 int pci_try_reset_function(struct pci_dev *dev)
5510 {
5511 int rc;
5512
5513 if (!pci_reset_supported(dev))
5514 return -ENOTTY;
5515
5516 if (!pci_dev_trylock(dev))
5517 return -EAGAIN;
5518
5519 pci_dev_save_and_disable(dev);
5520 rc = __pci_reset_function_locked(dev);
5521 pci_dev_restore(dev);
5522 pci_dev_unlock(dev);
5523
5524 return rc;
5525 }
5526 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5527
5528 /* Do any devices on or below this bus prevent a bus reset? */
pci_bus_resetable(struct pci_bus * bus)5529 static bool pci_bus_resetable(struct pci_bus *bus)
5530 {
5531 struct pci_dev *dev;
5532
5533
5534 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5535 return false;
5536
5537 list_for_each_entry(dev, &bus->devices, bus_list) {
5538 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5539 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5540 return false;
5541 }
5542
5543 return true;
5544 }
5545
5546 /* Lock devices from the top of the tree down */
pci_bus_lock(struct pci_bus * bus)5547 static void pci_bus_lock(struct pci_bus *bus)
5548 {
5549 struct pci_dev *dev;
5550
5551 list_for_each_entry(dev, &bus->devices, bus_list) {
5552 pci_dev_lock(dev);
5553 if (dev->subordinate)
5554 pci_bus_lock(dev->subordinate);
5555 }
5556 }
5557
5558 /* Unlock devices from the bottom of the tree up */
pci_bus_unlock(struct pci_bus * bus)5559 static void pci_bus_unlock(struct pci_bus *bus)
5560 {
5561 struct pci_dev *dev;
5562
5563 list_for_each_entry(dev, &bus->devices, bus_list) {
5564 if (dev->subordinate)
5565 pci_bus_unlock(dev->subordinate);
5566 pci_dev_unlock(dev);
5567 }
5568 }
5569
5570 /* Return 1 on successful lock, 0 on contention */
pci_bus_trylock(struct pci_bus * bus)5571 static int pci_bus_trylock(struct pci_bus *bus)
5572 {
5573 struct pci_dev *dev;
5574
5575 list_for_each_entry(dev, &bus->devices, bus_list) {
5576 if (!pci_dev_trylock(dev))
5577 goto unlock;
5578 if (dev->subordinate) {
5579 if (!pci_bus_trylock(dev->subordinate)) {
5580 pci_dev_unlock(dev);
5581 goto unlock;
5582 }
5583 }
5584 }
5585 return 1;
5586
5587 unlock:
5588 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5589 if (dev->subordinate)
5590 pci_bus_unlock(dev->subordinate);
5591 pci_dev_unlock(dev);
5592 }
5593 return 0;
5594 }
5595
5596 /* Do any devices on or below this slot prevent a bus reset? */
pci_slot_resetable(struct pci_slot * slot)5597 static bool pci_slot_resetable(struct pci_slot *slot)
5598 {
5599 struct pci_dev *dev;
5600
5601 if (slot->bus->self &&
5602 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5603 return false;
5604
5605 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5606 if (!dev->slot || dev->slot != slot)
5607 continue;
5608 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5609 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5610 return false;
5611 }
5612
5613 return true;
5614 }
5615
5616 /* Lock devices from the top of the tree down */
pci_slot_lock(struct pci_slot * slot)5617 static void pci_slot_lock(struct pci_slot *slot)
5618 {
5619 struct pci_dev *dev;
5620
5621 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5622 if (!dev->slot || dev->slot != slot)
5623 continue;
5624 pci_dev_lock(dev);
5625 if (dev->subordinate)
5626 pci_bus_lock(dev->subordinate);
5627 }
5628 }
5629
5630 /* Unlock devices from the bottom of the tree up */
pci_slot_unlock(struct pci_slot * slot)5631 static void pci_slot_unlock(struct pci_slot *slot)
5632 {
5633 struct pci_dev *dev;
5634
5635 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5636 if (!dev->slot || dev->slot != slot)
5637 continue;
5638 if (dev->subordinate)
5639 pci_bus_unlock(dev->subordinate);
5640 pci_dev_unlock(dev);
5641 }
5642 }
5643
5644 /* Return 1 on successful lock, 0 on contention */
pci_slot_trylock(struct pci_slot * slot)5645 static int pci_slot_trylock(struct pci_slot *slot)
5646 {
5647 struct pci_dev *dev;
5648
5649 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5650 if (!dev->slot || dev->slot != slot)
5651 continue;
5652 if (!pci_dev_trylock(dev))
5653 goto unlock;
5654 if (dev->subordinate) {
5655 if (!pci_bus_trylock(dev->subordinate)) {
5656 pci_dev_unlock(dev);
5657 goto unlock;
5658 }
5659 }
5660 }
5661 return 1;
5662
5663 unlock:
5664 list_for_each_entry_continue_reverse(dev,
5665 &slot->bus->devices, bus_list) {
5666 if (!dev->slot || dev->slot != slot)
5667 continue;
5668 if (dev->subordinate)
5669 pci_bus_unlock(dev->subordinate);
5670 pci_dev_unlock(dev);
5671 }
5672 return 0;
5673 }
5674
5675 /*
5676 * Save and disable devices from the top of the tree down while holding
5677 * the @dev mutex lock for the entire tree.
5678 */
pci_bus_save_and_disable_locked(struct pci_bus * bus)5679 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5680 {
5681 struct pci_dev *dev;
5682
5683 list_for_each_entry(dev, &bus->devices, bus_list) {
5684 pci_dev_save_and_disable(dev);
5685 if (dev->subordinate)
5686 pci_bus_save_and_disable_locked(dev->subordinate);
5687 }
5688 }
5689
5690 /*
5691 * Restore devices from top of the tree down while holding @dev mutex lock
5692 * for the entire tree. Parent bridges need to be restored before we can
5693 * get to subordinate devices.
5694 */
pci_bus_restore_locked(struct pci_bus * bus)5695 static void pci_bus_restore_locked(struct pci_bus *bus)
5696 {
5697 struct pci_dev *dev;
5698
5699 list_for_each_entry(dev, &bus->devices, bus_list) {
5700 pci_dev_restore(dev);
5701 if (dev->subordinate)
5702 pci_bus_restore_locked(dev->subordinate);
5703 }
5704 }
5705
5706 /*
5707 * Save and disable devices from the top of the tree down while holding
5708 * the @dev mutex lock for the entire tree.
5709 */
pci_slot_save_and_disable_locked(struct pci_slot * slot)5710 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5711 {
5712 struct pci_dev *dev;
5713
5714 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5715 if (!dev->slot || dev->slot != slot)
5716 continue;
5717 pci_dev_save_and_disable(dev);
5718 if (dev->subordinate)
5719 pci_bus_save_and_disable_locked(dev->subordinate);
5720 }
5721 }
5722
5723 /*
5724 * Restore devices from top of the tree down while holding @dev mutex lock
5725 * for the entire tree. Parent bridges need to be restored before we can
5726 * get to subordinate devices.
5727 */
pci_slot_restore_locked(struct pci_slot * slot)5728 static void pci_slot_restore_locked(struct pci_slot *slot)
5729 {
5730 struct pci_dev *dev;
5731
5732 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5733 if (!dev->slot || dev->slot != slot)
5734 continue;
5735 pci_dev_restore(dev);
5736 if (dev->subordinate)
5737 pci_bus_restore_locked(dev->subordinate);
5738 }
5739 }
5740
pci_slot_reset(struct pci_slot * slot,bool probe)5741 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5742 {
5743 int rc;
5744
5745 if (!slot || !pci_slot_resetable(slot))
5746 return -ENOTTY;
5747
5748 if (!probe)
5749 pci_slot_lock(slot);
5750
5751 might_sleep();
5752
5753 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5754
5755 if (!probe)
5756 pci_slot_unlock(slot);
5757
5758 return rc;
5759 }
5760
5761 /**
5762 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5763 * @slot: PCI slot to probe
5764 *
5765 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5766 */
pci_probe_reset_slot(struct pci_slot * slot)5767 int pci_probe_reset_slot(struct pci_slot *slot)
5768 {
5769 return pci_slot_reset(slot, PCI_RESET_PROBE);
5770 }
5771 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5772
5773 /**
5774 * __pci_reset_slot - Try to reset a PCI slot
5775 * @slot: PCI slot to reset
5776 *
5777 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5778 * independent of other slots. For instance, some slots may support slot power
5779 * control. In the case of a 1:1 bus to slot architecture, this function may
5780 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5781 * Generally a slot reset should be attempted before a bus reset. All of the
5782 * function of the slot and any subordinate buses behind the slot are reset
5783 * through this function. PCI config space of all devices in the slot and
5784 * behind the slot is saved before and restored after reset.
5785 *
5786 * Same as above except return -EAGAIN if the slot cannot be locked
5787 */
__pci_reset_slot(struct pci_slot * slot)5788 static int __pci_reset_slot(struct pci_slot *slot)
5789 {
5790 int rc;
5791
5792 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5793 if (rc)
5794 return rc;
5795
5796 if (pci_slot_trylock(slot)) {
5797 pci_slot_save_and_disable_locked(slot);
5798 might_sleep();
5799 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5800 pci_slot_restore_locked(slot);
5801 pci_slot_unlock(slot);
5802 } else
5803 rc = -EAGAIN;
5804
5805 return rc;
5806 }
5807
pci_bus_reset(struct pci_bus * bus,bool probe)5808 static int pci_bus_reset(struct pci_bus *bus, bool probe)
5809 {
5810 int ret;
5811
5812 if (!bus->self || !pci_bus_resetable(bus))
5813 return -ENOTTY;
5814
5815 if (probe)
5816 return 0;
5817
5818 pci_bus_lock(bus);
5819
5820 might_sleep();
5821
5822 ret = pci_bridge_secondary_bus_reset(bus->self);
5823
5824 pci_bus_unlock(bus);
5825
5826 return ret;
5827 }
5828
5829 /**
5830 * pci_bus_error_reset - reset the bridge's subordinate bus
5831 * @bridge: The parent device that connects to the bus to reset
5832 *
5833 * This function will first try to reset the slots on this bus if the method is
5834 * available. If slot reset fails or is not available, this will fall back to a
5835 * secondary bus reset.
5836 */
pci_bus_error_reset(struct pci_dev * bridge)5837 int pci_bus_error_reset(struct pci_dev *bridge)
5838 {
5839 struct pci_bus *bus = bridge->subordinate;
5840 struct pci_slot *slot;
5841
5842 if (!bus)
5843 return -ENOTTY;
5844
5845 mutex_lock(&pci_slot_mutex);
5846 if (list_empty(&bus->slots))
5847 goto bus_reset;
5848
5849 list_for_each_entry(slot, &bus->slots, list)
5850 if (pci_probe_reset_slot(slot))
5851 goto bus_reset;
5852
5853 list_for_each_entry(slot, &bus->slots, list)
5854 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
5855 goto bus_reset;
5856
5857 mutex_unlock(&pci_slot_mutex);
5858 return 0;
5859 bus_reset:
5860 mutex_unlock(&pci_slot_mutex);
5861 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5862 }
5863
5864 /**
5865 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5866 * @bus: PCI bus to probe
5867 *
5868 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5869 */
pci_probe_reset_bus(struct pci_bus * bus)5870 int pci_probe_reset_bus(struct pci_bus *bus)
5871 {
5872 return pci_bus_reset(bus, PCI_RESET_PROBE);
5873 }
5874 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5875
5876 /**
5877 * __pci_reset_bus - Try to reset a PCI bus
5878 * @bus: top level PCI bus to reset
5879 *
5880 * Same as above except return -EAGAIN if the bus cannot be locked
5881 */
__pci_reset_bus(struct pci_bus * bus)5882 static int __pci_reset_bus(struct pci_bus *bus)
5883 {
5884 int rc;
5885
5886 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
5887 if (rc)
5888 return rc;
5889
5890 if (pci_bus_trylock(bus)) {
5891 pci_bus_save_and_disable_locked(bus);
5892 might_sleep();
5893 rc = pci_bridge_secondary_bus_reset(bus->self);
5894 pci_bus_restore_locked(bus);
5895 pci_bus_unlock(bus);
5896 } else
5897 rc = -EAGAIN;
5898
5899 return rc;
5900 }
5901
5902 /**
5903 * pci_reset_bus - Try to reset a PCI bus
5904 * @pdev: top level PCI device to reset via slot/bus
5905 *
5906 * Same as above except return -EAGAIN if the bus cannot be locked
5907 */
pci_reset_bus(struct pci_dev * pdev)5908 int pci_reset_bus(struct pci_dev *pdev)
5909 {
5910 return (!pci_probe_reset_slot(pdev->slot)) ?
5911 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5912 }
5913 EXPORT_SYMBOL_GPL(pci_reset_bus);
5914
5915 /**
5916 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5917 * @dev: PCI device to query
5918 *
5919 * Returns mmrbc: maximum designed memory read count in bytes or
5920 * appropriate error value.
5921 */
pcix_get_max_mmrbc(struct pci_dev * dev)5922 int pcix_get_max_mmrbc(struct pci_dev *dev)
5923 {
5924 int cap;
5925 u32 stat;
5926
5927 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5928 if (!cap)
5929 return -EINVAL;
5930
5931 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5932 return -EINVAL;
5933
5934 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5935 }
5936 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5937
5938 /**
5939 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5940 * @dev: PCI device to query
5941 *
5942 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5943 * value.
5944 */
pcix_get_mmrbc(struct pci_dev * dev)5945 int pcix_get_mmrbc(struct pci_dev *dev)
5946 {
5947 int cap;
5948 u16 cmd;
5949
5950 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5951 if (!cap)
5952 return -EINVAL;
5953
5954 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5955 return -EINVAL;
5956
5957 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5958 }
5959 EXPORT_SYMBOL(pcix_get_mmrbc);
5960
5961 /**
5962 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5963 * @dev: PCI device to query
5964 * @mmrbc: maximum memory read count in bytes
5965 * valid values are 512, 1024, 2048, 4096
5966 *
5967 * If possible sets maximum memory read byte count, some bridges have errata
5968 * that prevent this.
5969 */
pcix_set_mmrbc(struct pci_dev * dev,int mmrbc)5970 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5971 {
5972 int cap;
5973 u32 stat, v, o;
5974 u16 cmd;
5975
5976 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5977 return -EINVAL;
5978
5979 v = ffs(mmrbc) - 10;
5980
5981 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5982 if (!cap)
5983 return -EINVAL;
5984
5985 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5986 return -EINVAL;
5987
5988 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5989 return -E2BIG;
5990
5991 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5992 return -EINVAL;
5993
5994 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5995 if (o != v) {
5996 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5997 return -EIO;
5998
5999 cmd &= ~PCI_X_CMD_MAX_READ;
6000 cmd |= v << 2;
6001 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
6002 return -EIO;
6003 }
6004 return 0;
6005 }
6006 EXPORT_SYMBOL(pcix_set_mmrbc);
6007
6008 /**
6009 * pcie_get_readrq - get PCI Express read request size
6010 * @dev: PCI device to query
6011 *
6012 * Returns maximum memory read request in bytes or appropriate error value.
6013 */
pcie_get_readrq(struct pci_dev * dev)6014 int pcie_get_readrq(struct pci_dev *dev)
6015 {
6016 u16 ctl;
6017
6018 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6019
6020 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6021 }
6022 EXPORT_SYMBOL(pcie_get_readrq);
6023
6024 /**
6025 * pcie_set_readrq - set PCI Express maximum memory read request
6026 * @dev: PCI device to query
6027 * @rq: maximum memory read count in bytes
6028 * valid values are 128, 256, 512, 1024, 2048, 4096
6029 *
6030 * If possible sets maximum memory read request in bytes
6031 */
pcie_set_readrq(struct pci_dev * dev,int rq)6032 int pcie_set_readrq(struct pci_dev *dev, int rq)
6033 {
6034 u16 v;
6035 int ret;
6036
6037 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
6038 return -EINVAL;
6039
6040 /*
6041 * If using the "performance" PCIe config, we clamp the read rq
6042 * size to the max packet size to keep the host bridge from
6043 * generating requests larger than we can cope with.
6044 */
6045 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
6046 int mps = pcie_get_mps(dev);
6047
6048 if (mps < rq)
6049 rq = mps;
6050 }
6051
6052 v = (ffs(rq) - 8) << 12;
6053
6054 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6055 PCI_EXP_DEVCTL_READRQ, v);
6056
6057 return pcibios_err_to_errno(ret);
6058 }
6059 EXPORT_SYMBOL(pcie_set_readrq);
6060
6061 /**
6062 * pcie_get_mps - get PCI Express maximum payload size
6063 * @dev: PCI device to query
6064 *
6065 * Returns maximum payload size in bytes
6066 */
pcie_get_mps(struct pci_dev * dev)6067 int pcie_get_mps(struct pci_dev *dev)
6068 {
6069 u16 ctl;
6070
6071 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6072
6073 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6074 }
6075 EXPORT_SYMBOL(pcie_get_mps);
6076
6077 /**
6078 * pcie_set_mps - set PCI Express maximum payload size
6079 * @dev: PCI device to query
6080 * @mps: maximum payload size in bytes
6081 * valid values are 128, 256, 512, 1024, 2048, 4096
6082 *
6083 * If possible sets maximum payload size
6084 */
pcie_set_mps(struct pci_dev * dev,int mps)6085 int pcie_set_mps(struct pci_dev *dev, int mps)
6086 {
6087 u16 v;
6088 int ret;
6089
6090 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6091 return -EINVAL;
6092
6093 v = ffs(mps) - 8;
6094 if (v > dev->pcie_mpss)
6095 return -EINVAL;
6096 v <<= 5;
6097
6098 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6099 PCI_EXP_DEVCTL_PAYLOAD, v);
6100
6101 return pcibios_err_to_errno(ret);
6102 }
6103 EXPORT_SYMBOL(pcie_set_mps);
6104
6105 /**
6106 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6107 * device and its bandwidth limitation
6108 * @dev: PCI device to query
6109 * @limiting_dev: storage for device causing the bandwidth limitation
6110 * @speed: storage for speed of limiting device
6111 * @width: storage for width of limiting device
6112 *
6113 * Walk up the PCI device chain and find the point where the minimum
6114 * bandwidth is available. Return the bandwidth available there and (if
6115 * limiting_dev, speed, and width pointers are supplied) information about
6116 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6117 * raw bandwidth.
6118 */
pcie_bandwidth_available(struct pci_dev * dev,struct pci_dev ** limiting_dev,enum pci_bus_speed * speed,enum pcie_link_width * width)6119 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6120 enum pci_bus_speed *speed,
6121 enum pcie_link_width *width)
6122 {
6123 u16 lnksta;
6124 enum pci_bus_speed next_speed;
6125 enum pcie_link_width next_width;
6126 u32 bw, next_bw;
6127
6128 if (speed)
6129 *speed = PCI_SPEED_UNKNOWN;
6130 if (width)
6131 *width = PCIE_LNK_WIDTH_UNKNOWN;
6132
6133 bw = 0;
6134
6135 while (dev) {
6136 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6137
6138 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
6139 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
6140 PCI_EXP_LNKSTA_NLW_SHIFT;
6141
6142 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6143
6144 /* Check if current device limits the total bandwidth */
6145 if (!bw || next_bw <= bw) {
6146 bw = next_bw;
6147
6148 if (limiting_dev)
6149 *limiting_dev = dev;
6150 if (speed)
6151 *speed = next_speed;
6152 if (width)
6153 *width = next_width;
6154 }
6155
6156 dev = pci_upstream_bridge(dev);
6157 }
6158
6159 return bw;
6160 }
6161 EXPORT_SYMBOL(pcie_bandwidth_available);
6162
6163 /**
6164 * pcie_get_speed_cap - query for the PCI device's link speed capability
6165 * @dev: PCI device to query
6166 *
6167 * Query the PCI device speed capability. Return the maximum link speed
6168 * supported by the device.
6169 */
pcie_get_speed_cap(struct pci_dev * dev)6170 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6171 {
6172 u32 lnkcap2, lnkcap;
6173
6174 /*
6175 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6176 * implementation note there recommends using the Supported Link
6177 * Speeds Vector in Link Capabilities 2 when supported.
6178 *
6179 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6180 * should use the Supported Link Speeds field in Link Capabilities,
6181 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6182 */
6183 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6184
6185 /* PCIe r3.0-compliant */
6186 if (lnkcap2)
6187 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6188
6189 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6190 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6191 return PCIE_SPEED_5_0GT;
6192 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6193 return PCIE_SPEED_2_5GT;
6194
6195 return PCI_SPEED_UNKNOWN;
6196 }
6197 EXPORT_SYMBOL(pcie_get_speed_cap);
6198
6199 /**
6200 * pcie_get_width_cap - query for the PCI device's link width capability
6201 * @dev: PCI device to query
6202 *
6203 * Query the PCI device width capability. Return the maximum link width
6204 * supported by the device.
6205 */
pcie_get_width_cap(struct pci_dev * dev)6206 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6207 {
6208 u32 lnkcap;
6209
6210 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6211 if (lnkcap)
6212 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
6213
6214 return PCIE_LNK_WIDTH_UNKNOWN;
6215 }
6216 EXPORT_SYMBOL(pcie_get_width_cap);
6217
6218 /**
6219 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6220 * @dev: PCI device
6221 * @speed: storage for link speed
6222 * @width: storage for link width
6223 *
6224 * Calculate a PCI device's link bandwidth by querying for its link speed
6225 * and width, multiplying them, and applying encoding overhead. The result
6226 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6227 */
pcie_bandwidth_capable(struct pci_dev * dev,enum pci_bus_speed * speed,enum pcie_link_width * width)6228 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6229 enum pcie_link_width *width)
6230 {
6231 *speed = pcie_get_speed_cap(dev);
6232 *width = pcie_get_width_cap(dev);
6233
6234 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6235 return 0;
6236
6237 return *width * PCIE_SPEED2MBS_ENC(*speed);
6238 }
6239
6240 /**
6241 * __pcie_print_link_status - Report the PCI device's link speed and width
6242 * @dev: PCI device to query
6243 * @verbose: Print info even when enough bandwidth is available
6244 *
6245 * If the available bandwidth at the device is less than the device is
6246 * capable of, report the device's maximum possible bandwidth and the
6247 * upstream link that limits its performance. If @verbose, always print
6248 * the available bandwidth, even if the device isn't constrained.
6249 */
__pcie_print_link_status(struct pci_dev * dev,bool verbose)6250 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6251 {
6252 enum pcie_link_width width, width_cap;
6253 enum pci_bus_speed speed, speed_cap;
6254 struct pci_dev *limiting_dev = NULL;
6255 u32 bw_avail, bw_cap;
6256
6257 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6258 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6259
6260 if (bw_avail >= bw_cap && verbose)
6261 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6262 bw_cap / 1000, bw_cap % 1000,
6263 pci_speed_string(speed_cap), width_cap);
6264 else if (bw_avail < bw_cap)
6265 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6266 bw_avail / 1000, bw_avail % 1000,
6267 pci_speed_string(speed), width,
6268 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6269 bw_cap / 1000, bw_cap % 1000,
6270 pci_speed_string(speed_cap), width_cap);
6271 }
6272
6273 /**
6274 * pcie_print_link_status - Report the PCI device's link speed and width
6275 * @dev: PCI device to query
6276 *
6277 * Report the available bandwidth at the device.
6278 */
pcie_print_link_status(struct pci_dev * dev)6279 void pcie_print_link_status(struct pci_dev *dev)
6280 {
6281 __pcie_print_link_status(dev, true);
6282 }
6283 EXPORT_SYMBOL(pcie_print_link_status);
6284
6285 /**
6286 * pci_select_bars - Make BAR mask from the type of resource
6287 * @dev: the PCI device for which BAR mask is made
6288 * @flags: resource type mask to be selected
6289 *
6290 * This helper routine makes bar mask from the type of resource.
6291 */
pci_select_bars(struct pci_dev * dev,unsigned long flags)6292 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6293 {
6294 int i, bars = 0;
6295 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6296 if (pci_resource_flags(dev, i) & flags)
6297 bars |= (1 << i);
6298 return bars;
6299 }
6300 EXPORT_SYMBOL(pci_select_bars);
6301
6302 /* Some architectures require additional programming to enable VGA */
6303 static arch_set_vga_state_t arch_set_vga_state;
6304
pci_register_set_vga_state(arch_set_vga_state_t func)6305 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6306 {
6307 arch_set_vga_state = func; /* NULL disables */
6308 }
6309
pci_set_vga_state_arch(struct pci_dev * dev,bool decode,unsigned int command_bits,u32 flags)6310 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6311 unsigned int command_bits, u32 flags)
6312 {
6313 if (arch_set_vga_state)
6314 return arch_set_vga_state(dev, decode, command_bits,
6315 flags);
6316 return 0;
6317 }
6318
6319 /**
6320 * pci_set_vga_state - set VGA decode state on device and parents if requested
6321 * @dev: the PCI device
6322 * @decode: true = enable decoding, false = disable decoding
6323 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6324 * @flags: traverse ancestors and change bridges
6325 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6326 */
pci_set_vga_state(struct pci_dev * dev,bool decode,unsigned int command_bits,u32 flags)6327 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6328 unsigned int command_bits, u32 flags)
6329 {
6330 struct pci_bus *bus;
6331 struct pci_dev *bridge;
6332 u16 cmd;
6333 int rc;
6334
6335 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6336
6337 /* ARCH specific VGA enables */
6338 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6339 if (rc)
6340 return rc;
6341
6342 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6343 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6344 if (decode)
6345 cmd |= command_bits;
6346 else
6347 cmd &= ~command_bits;
6348 pci_write_config_word(dev, PCI_COMMAND, cmd);
6349 }
6350
6351 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6352 return 0;
6353
6354 bus = dev->bus;
6355 while (bus) {
6356 bridge = bus->self;
6357 if (bridge) {
6358 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6359 &cmd);
6360 if (decode)
6361 cmd |= PCI_BRIDGE_CTL_VGA;
6362 else
6363 cmd &= ~PCI_BRIDGE_CTL_VGA;
6364 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6365 cmd);
6366 }
6367 bus = bus->parent;
6368 }
6369 return 0;
6370 }
6371
6372 #ifdef CONFIG_ACPI
pci_pr3_present(struct pci_dev * pdev)6373 bool pci_pr3_present(struct pci_dev *pdev)
6374 {
6375 struct acpi_device *adev;
6376
6377 if (acpi_disabled)
6378 return false;
6379
6380 adev = ACPI_COMPANION(&pdev->dev);
6381 if (!adev)
6382 return false;
6383
6384 return adev->power.flags.power_resources &&
6385 acpi_has_method(adev->handle, "_PR3");
6386 }
6387 EXPORT_SYMBOL_GPL(pci_pr3_present);
6388 #endif
6389
6390 /**
6391 * pci_add_dma_alias - Add a DMA devfn alias for a device
6392 * @dev: the PCI device for which alias is added
6393 * @devfn_from: alias slot and function
6394 * @nr_devfns: number of subsequent devfns to alias
6395 *
6396 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6397 * which is used to program permissible bus-devfn source addresses for DMA
6398 * requests in an IOMMU. These aliases factor into IOMMU group creation
6399 * and are useful for devices generating DMA requests beyond or different
6400 * from their logical bus-devfn. Examples include device quirks where the
6401 * device simply uses the wrong devfn, as well as non-transparent bridges
6402 * where the alias may be a proxy for devices in another domain.
6403 *
6404 * IOMMU group creation is performed during device discovery or addition,
6405 * prior to any potential DMA mapping and therefore prior to driver probing
6406 * (especially for userspace assigned devices where IOMMU group definition
6407 * cannot be left as a userspace activity). DMA aliases should therefore
6408 * be configured via quirks, such as the PCI fixup header quirk.
6409 */
pci_add_dma_alias(struct pci_dev * dev,u8 devfn_from,unsigned int nr_devfns)6410 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6411 unsigned int nr_devfns)
6412 {
6413 int devfn_to;
6414
6415 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);
6416 devfn_to = devfn_from + nr_devfns - 1;
6417
6418 if (!dev->dma_alias_mask)
6419 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6420 if (!dev->dma_alias_mask) {
6421 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6422 return;
6423 }
6424
6425 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6426
6427 if (nr_devfns == 1)
6428 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6429 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6430 else if (nr_devfns > 1)
6431 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6432 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6433 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6434 }
6435
pci_devs_are_dma_aliases(struct pci_dev * dev1,struct pci_dev * dev2)6436 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6437 {
6438 return (dev1->dma_alias_mask &&
6439 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6440 (dev2->dma_alias_mask &&
6441 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6442 pci_real_dma_dev(dev1) == dev2 ||
6443 pci_real_dma_dev(dev2) == dev1;
6444 }
6445
pci_device_is_present(struct pci_dev * pdev)6446 bool pci_device_is_present(struct pci_dev *pdev)
6447 {
6448 u32 v;
6449
6450 /* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6451 pdev = pci_physfn(pdev);
6452 if (pci_dev_is_disconnected(pdev))
6453 return false;
6454 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6455 }
6456 EXPORT_SYMBOL_GPL(pci_device_is_present);
6457
pci_ignore_hotplug(struct pci_dev * dev)6458 void pci_ignore_hotplug(struct pci_dev *dev)
6459 {
6460 struct pci_dev *bridge = dev->bus->self;
6461
6462 dev->ignore_hotplug = 1;
6463 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6464 if (bridge)
6465 bridge->ignore_hotplug = 1;
6466 }
6467 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6468
6469 /**
6470 * pci_real_dma_dev - Get PCI DMA device for PCI device
6471 * @dev: the PCI device that may have a PCI DMA alias
6472 *
6473 * Permits the platform to provide architecture-specific functionality to
6474 * devices needing to alias DMA to another PCI device on another PCI bus. If
6475 * the PCI device is on the same bus, it is recommended to use
6476 * pci_add_dma_alias(). This is the default implementation. Architecture
6477 * implementations can override this.
6478 */
pci_real_dma_dev(struct pci_dev * dev)6479 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6480 {
6481 return dev;
6482 }
6483
pcibios_default_alignment(void)6484 resource_size_t __weak pcibios_default_alignment(void)
6485 {
6486 return 0;
6487 }
6488
6489 /*
6490 * Arches that don't want to expose struct resource to userland as-is in
6491 * sysfs and /proc can implement their own pci_resource_to_user().
6492 */
pci_resource_to_user(const struct pci_dev * dev,int bar,const struct resource * rsrc,resource_size_t * start,resource_size_t * end)6493 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6494 const struct resource *rsrc,
6495 resource_size_t *start, resource_size_t *end)
6496 {
6497 *start = rsrc->start;
6498 *end = rsrc->end;
6499 }
6500
6501 static char *resource_alignment_param;
6502 static DEFINE_SPINLOCK(resource_alignment_lock);
6503
6504 /**
6505 * pci_specified_resource_alignment - get resource alignment specified by user.
6506 * @dev: the PCI device to get
6507 * @resize: whether or not to change resources' size when reassigning alignment
6508 *
6509 * RETURNS: Resource alignment if it is specified.
6510 * Zero if it is not specified.
6511 */
pci_specified_resource_alignment(struct pci_dev * dev,bool * resize)6512 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6513 bool *resize)
6514 {
6515 int align_order, count;
6516 resource_size_t align = pcibios_default_alignment();
6517 const char *p;
6518 int ret;
6519
6520 spin_lock(&resource_alignment_lock);
6521 p = resource_alignment_param;
6522 if (!p || !*p)
6523 goto out;
6524 if (pci_has_flag(PCI_PROBE_ONLY)) {
6525 align = 0;
6526 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6527 goto out;
6528 }
6529
6530 while (*p) {
6531 count = 0;
6532 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6533 p[count] == '@') {
6534 p += count + 1;
6535 if (align_order > 63) {
6536 pr_err("PCI: Invalid requested alignment (order %d)\n",
6537 align_order);
6538 align_order = PAGE_SHIFT;
6539 }
6540 } else {
6541 align_order = PAGE_SHIFT;
6542 }
6543
6544 ret = pci_dev_str_match(dev, p, &p);
6545 if (ret == 1) {
6546 *resize = true;
6547 align = 1ULL << align_order;
6548 break;
6549 } else if (ret < 0) {
6550 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6551 p);
6552 break;
6553 }
6554
6555 if (*p != ';' && *p != ',') {
6556 /* End of param or invalid format */
6557 break;
6558 }
6559 p++;
6560 }
6561 out:
6562 spin_unlock(&resource_alignment_lock);
6563 return align;
6564 }
6565
pci_request_resource_alignment(struct pci_dev * dev,int bar,resource_size_t align,bool resize)6566 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6567 resource_size_t align, bool resize)
6568 {
6569 struct resource *r = &dev->resource[bar];
6570 resource_size_t size;
6571
6572 if (!(r->flags & IORESOURCE_MEM))
6573 return;
6574
6575 if (r->flags & IORESOURCE_PCI_FIXED) {
6576 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6577 bar, r, (unsigned long long)align);
6578 return;
6579 }
6580
6581 size = resource_size(r);
6582 if (size >= align)
6583 return;
6584
6585 /*
6586 * Increase the alignment of the resource. There are two ways we
6587 * can do this:
6588 *
6589 * 1) Increase the size of the resource. BARs are aligned on their
6590 * size, so when we reallocate space for this resource, we'll
6591 * allocate it with the larger alignment. This also prevents
6592 * assignment of any other BARs inside the alignment region, so
6593 * if we're requesting page alignment, this means no other BARs
6594 * will share the page.
6595 *
6596 * The disadvantage is that this makes the resource larger than
6597 * the hardware BAR, which may break drivers that compute things
6598 * based on the resource size, e.g., to find registers at a
6599 * fixed offset before the end of the BAR.
6600 *
6601 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6602 * set r->start to the desired alignment. By itself this
6603 * doesn't prevent other BARs being put inside the alignment
6604 * region, but if we realign *every* resource of every device in
6605 * the system, none of them will share an alignment region.
6606 *
6607 * When the user has requested alignment for only some devices via
6608 * the "pci=resource_alignment" argument, "resize" is true and we
6609 * use the first method. Otherwise we assume we're aligning all
6610 * devices and we use the second.
6611 */
6612
6613 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6614 bar, r, (unsigned long long)align);
6615
6616 if (resize) {
6617 r->start = 0;
6618 r->end = align - 1;
6619 } else {
6620 r->flags &= ~IORESOURCE_SIZEALIGN;
6621 r->flags |= IORESOURCE_STARTALIGN;
6622 r->start = align;
6623 r->end = r->start + size - 1;
6624 }
6625 r->flags |= IORESOURCE_UNSET;
6626 }
6627
6628 /*
6629 * This function disables memory decoding and releases memory resources
6630 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6631 * It also rounds up size to specified alignment.
6632 * Later on, the kernel will assign page-aligned memory resource back
6633 * to the device.
6634 */
pci_reassigndev_resource_alignment(struct pci_dev * dev)6635 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6636 {
6637 int i;
6638 struct resource *r;
6639 resource_size_t align;
6640 u16 command;
6641 bool resize = false;
6642
6643 /*
6644 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6645 * 3.4.1.11. Their resources are allocated from the space
6646 * described by the VF BARx register in the PF's SR-IOV capability.
6647 * We can't influence their alignment here.
6648 */
6649 if (dev->is_virtfn)
6650 return;
6651
6652 /* check if specified PCI is target device to reassign */
6653 align = pci_specified_resource_alignment(dev, &resize);
6654 if (!align)
6655 return;
6656
6657 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6658 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6659 pci_warn(dev, "Can't reassign resources to host bridge\n");
6660 return;
6661 }
6662
6663 pci_read_config_word(dev, PCI_COMMAND, &command);
6664 command &= ~PCI_COMMAND_MEMORY;
6665 pci_write_config_word(dev, PCI_COMMAND, command);
6666
6667 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6668 pci_request_resource_alignment(dev, i, align, resize);
6669
6670 /*
6671 * Need to disable bridge's resource window,
6672 * to enable the kernel to reassign new resource
6673 * window later on.
6674 */
6675 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6676 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6677 r = &dev->resource[i];
6678 if (!(r->flags & IORESOURCE_MEM))
6679 continue;
6680 r->flags |= IORESOURCE_UNSET;
6681 r->end = resource_size(r) - 1;
6682 r->start = 0;
6683 }
6684 pci_disable_bridge_window(dev);
6685 }
6686 }
6687
resource_alignment_show(struct bus_type * bus,char * buf)6688 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6689 {
6690 size_t count = 0;
6691
6692 spin_lock(&resource_alignment_lock);
6693 if (resource_alignment_param)
6694 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6695 spin_unlock(&resource_alignment_lock);
6696
6697 return count;
6698 }
6699
resource_alignment_store(struct bus_type * bus,const char * buf,size_t count)6700 static ssize_t resource_alignment_store(struct bus_type *bus,
6701 const char *buf, size_t count)
6702 {
6703 char *param, *old, *end;
6704
6705 if (count >= (PAGE_SIZE - 1))
6706 return -EINVAL;
6707
6708 param = kstrndup(buf, count, GFP_KERNEL);
6709 if (!param)
6710 return -ENOMEM;
6711
6712 end = strchr(param, '\n');
6713 if (end)
6714 *end = '\0';
6715
6716 spin_lock(&resource_alignment_lock);
6717 old = resource_alignment_param;
6718 if (strlen(param)) {
6719 resource_alignment_param = param;
6720 } else {
6721 kfree(param);
6722 resource_alignment_param = NULL;
6723 }
6724 spin_unlock(&resource_alignment_lock);
6725
6726 kfree(old);
6727
6728 return count;
6729 }
6730
6731 static BUS_ATTR_RW(resource_alignment);
6732
pci_resource_alignment_sysfs_init(void)6733 static int __init pci_resource_alignment_sysfs_init(void)
6734 {
6735 return bus_create_file(&pci_bus_type,
6736 &bus_attr_resource_alignment);
6737 }
6738 late_initcall(pci_resource_alignment_sysfs_init);
6739
pci_no_domains(void)6740 static void pci_no_domains(void)
6741 {
6742 #ifdef CONFIG_PCI_DOMAINS
6743 pci_domains_supported = 0;
6744 #endif
6745 }
6746
6747 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6748 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6749
pci_get_new_domain_nr(void)6750 static int pci_get_new_domain_nr(void)
6751 {
6752 return atomic_inc_return(&__domain_nr);
6753 }
6754
of_pci_bus_find_domain_nr(struct device * parent)6755 static int of_pci_bus_find_domain_nr(struct device *parent)
6756 {
6757 static int use_dt_domains = -1;
6758 int domain = -1;
6759
6760 if (parent)
6761 domain = of_get_pci_domain_nr(parent->of_node);
6762
6763 /*
6764 * Check DT domain and use_dt_domains values.
6765 *
6766 * If DT domain property is valid (domain >= 0) and
6767 * use_dt_domains != 0, the DT assignment is valid since this means
6768 * we have not previously allocated a domain number by using
6769 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6770 * 1, to indicate that we have just assigned a domain number from
6771 * DT.
6772 *
6773 * If DT domain property value is not valid (ie domain < 0), and we
6774 * have not previously assigned a domain number from DT
6775 * (use_dt_domains != 1) we should assign a domain number by
6776 * using the:
6777 *
6778 * pci_get_new_domain_nr()
6779 *
6780 * API and update the use_dt_domains value to keep track of method we
6781 * are using to assign domain numbers (use_dt_domains = 0).
6782 *
6783 * All other combinations imply we have a platform that is trying
6784 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6785 * which is a recipe for domain mishandling and it is prevented by
6786 * invalidating the domain value (domain = -1) and printing a
6787 * corresponding error.
6788 */
6789 if (domain >= 0 && use_dt_domains) {
6790 use_dt_domains = 1;
6791 } else if (domain < 0 && use_dt_domains != 1) {
6792 use_dt_domains = 0;
6793 domain = pci_get_new_domain_nr();
6794 } else {
6795 if (parent)
6796 pr_err("Node %pOF has ", parent->of_node);
6797 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6798 domain = -1;
6799 }
6800
6801 return domain;
6802 }
6803
pci_bus_find_domain_nr(struct pci_bus * bus,struct device * parent)6804 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6805 {
6806 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6807 acpi_pci_bus_find_domain_nr(bus);
6808 }
6809 #endif
6810
6811 /**
6812 * pci_ext_cfg_avail - can we access extended PCI config space?
6813 *
6814 * Returns 1 if we can access PCI extended config space (offsets
6815 * greater than 0xff). This is the default implementation. Architecture
6816 * implementations can override this.
6817 */
pci_ext_cfg_avail(void)6818 int __weak pci_ext_cfg_avail(void)
6819 {
6820 return 1;
6821 }
6822
pci_fixup_cardbus(struct pci_bus * bus)6823 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6824 {
6825 }
6826 EXPORT_SYMBOL(pci_fixup_cardbus);
6827
pci_setup(char * str)6828 static int __init pci_setup(char *str)
6829 {
6830 while (str) {
6831 char *k = strchr(str, ',');
6832 if (k)
6833 *k++ = 0;
6834 if (*str && (str = pcibios_setup(str)) && *str) {
6835 if (!strcmp(str, "nomsi")) {
6836 pci_no_msi();
6837 } else if (!strncmp(str, "noats", 5)) {
6838 pr_info("PCIe: ATS is disabled\n");
6839 pcie_ats_disabled = true;
6840 } else if (!strcmp(str, "noaer")) {
6841 pci_no_aer();
6842 } else if (!strcmp(str, "earlydump")) {
6843 pci_early_dump = true;
6844 } else if (!strncmp(str, "realloc=", 8)) {
6845 pci_realloc_get_opt(str + 8);
6846 } else if (!strncmp(str, "realloc", 7)) {
6847 pci_realloc_get_opt("on");
6848 } else if (!strcmp(str, "nodomains")) {
6849 pci_no_domains();
6850 } else if (!strncmp(str, "noari", 5)) {
6851 pcie_ari_disabled = true;
6852 } else if (!strncmp(str, "cbiosize=", 9)) {
6853 pci_cardbus_io_size = memparse(str + 9, &str);
6854 } else if (!strncmp(str, "cbmemsize=", 10)) {
6855 pci_cardbus_mem_size = memparse(str + 10, &str);
6856 } else if (!strncmp(str, "resource_alignment=", 19)) {
6857 resource_alignment_param = str + 19;
6858 } else if (!strncmp(str, "ecrc=", 5)) {
6859 pcie_ecrc_get_policy(str + 5);
6860 } else if (!strncmp(str, "hpiosize=", 9)) {
6861 pci_hotplug_io_size = memparse(str + 9, &str);
6862 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6863 pci_hotplug_mmio_size = memparse(str + 11, &str);
6864 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6865 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6866 } else if (!strncmp(str, "hpmemsize=", 10)) {
6867 pci_hotplug_mmio_size = memparse(str + 10, &str);
6868 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6869 } else if (!strncmp(str, "hpbussize=", 10)) {
6870 pci_hotplug_bus_size =
6871 simple_strtoul(str + 10, &str, 0);
6872 if (pci_hotplug_bus_size > 0xff)
6873 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6874 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6875 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6876 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6877 pcie_bus_config = PCIE_BUS_SAFE;
6878 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6879 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6880 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6881 pcie_bus_config = PCIE_BUS_PEER2PEER;
6882 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6883 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6884 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6885 disable_acs_redir_param = str + 18;
6886 } else {
6887 pr_err("PCI: Unknown option `%s'\n", str);
6888 }
6889 }
6890 str = k;
6891 }
6892 return 0;
6893 }
6894 early_param("pci", pci_setup);
6895
6896 /*
6897 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6898 * in pci_setup(), above, to point to data in the __initdata section which
6899 * will be freed after the init sequence is complete. We can't allocate memory
6900 * in pci_setup() because some architectures do not have any memory allocation
6901 * service available during an early_param() call. So we allocate memory and
6902 * copy the variable here before the init section is freed.
6903 *
6904 */
pci_realloc_setup_params(void)6905 static int __init pci_realloc_setup_params(void)
6906 {
6907 resource_alignment_param = kstrdup(resource_alignment_param,
6908 GFP_KERNEL);
6909 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6910
6911 return 0;
6912 }
6913 pure_initcall(pci_realloc_setup_params);
6914