1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices Generic AXI ADC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
5 *
6 * Copyright 2012-2020 Analog Devices Inc.
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/io.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/buffer-dmaengine.h>
22
23 #include <linux/fpga/adi-axi-common.h>
24 #include <linux/iio/adc/adi-axi-adc.h>
25
26 /*
27 * Register definitions:
28 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
29 */
30
31 /* ADC controls */
32
33 #define ADI_AXI_REG_RSTN 0x0040
34 #define ADI_AXI_REG_RSTN_CE_N BIT(2)
35 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
36 #define ADI_AXI_REG_RSTN_RSTN BIT(0)
37
38 /* ADC Channel controls */
39
40 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
41 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
42 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
43 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
44 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
45 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
46 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
47 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
48 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
49 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
50
51 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
52 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
53 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
54 ADI_AXI_REG_CHAN_CTRL_ENABLE)
55
56 struct adi_axi_adc_core_info {
57 unsigned int version;
58 };
59
60 struct adi_axi_adc_state {
61 struct mutex lock;
62
63 struct adi_axi_adc_client *client;
64 void __iomem *regs;
65 };
66
67 struct adi_axi_adc_client {
68 struct list_head entry;
69 struct adi_axi_adc_conv conv;
70 struct adi_axi_adc_state *state;
71 struct device *dev;
72 const struct adi_axi_adc_core_info *info;
73 };
74
75 static LIST_HEAD(registered_clients);
76 static DEFINE_MUTEX(registered_clients_lock);
77
conv_to_client(struct adi_axi_adc_conv * conv)78 static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
79 {
80 return container_of(conv, struct adi_axi_adc_client, conv);
81 }
82
adi_axi_adc_conv_priv(struct adi_axi_adc_conv * conv)83 void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
84 {
85 struct adi_axi_adc_client *cl = conv_to_client(conv);
86
87 return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client),
88 IIO_DMA_MINALIGN);
89 }
90 EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv);
91
adi_axi_adc_write(struct adi_axi_adc_state * st,unsigned int reg,unsigned int val)92 static void adi_axi_adc_write(struct adi_axi_adc_state *st,
93 unsigned int reg,
94 unsigned int val)
95 {
96 iowrite32(val, st->regs + reg);
97 }
98
adi_axi_adc_read(struct adi_axi_adc_state * st,unsigned int reg)99 static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
100 unsigned int reg)
101 {
102 return ioread32(st->regs + reg);
103 }
104
adi_axi_adc_config_dma_buffer(struct device * dev,struct iio_dev * indio_dev)105 static int adi_axi_adc_config_dma_buffer(struct device *dev,
106 struct iio_dev *indio_dev)
107 {
108 const char *dma_name;
109
110 if (!device_property_present(dev, "dmas"))
111 return 0;
112
113 if (device_property_read_string(dev, "dma-names", &dma_name))
114 dma_name = "rx";
115
116 return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent,
117 indio_dev, dma_name);
118 }
119
adi_axi_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)120 static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
121 struct iio_chan_spec const *chan,
122 int *val, int *val2, long mask)
123 {
124 struct adi_axi_adc_state *st = iio_priv(indio_dev);
125 struct adi_axi_adc_conv *conv = &st->client->conv;
126
127 if (!conv->read_raw)
128 return -EOPNOTSUPP;
129
130 return conv->read_raw(conv, chan, val, val2, mask);
131 }
132
adi_axi_adc_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)133 static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
134 struct iio_chan_spec const *chan,
135 int val, int val2, long mask)
136 {
137 struct adi_axi_adc_state *st = iio_priv(indio_dev);
138 struct adi_axi_adc_conv *conv = &st->client->conv;
139
140 if (!conv->write_raw)
141 return -EOPNOTSUPP;
142
143 return conv->write_raw(conv, chan, val, val2, mask);
144 }
145
adi_axi_adc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)146 static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
147 const unsigned long *scan_mask)
148 {
149 struct adi_axi_adc_state *st = iio_priv(indio_dev);
150 struct adi_axi_adc_conv *conv = &st->client->conv;
151 unsigned int i, ctrl;
152
153 for (i = 0; i < conv->chip_info->num_channels; i++) {
154 ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
155
156 if (test_bit(i, scan_mask))
157 ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
158 else
159 ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
160
161 adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
162 }
163
164 return 0;
165 }
166
adi_axi_adc_conv_register(struct device * dev,size_t sizeof_priv)167 static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
168 size_t sizeof_priv)
169 {
170 struct adi_axi_adc_client *cl;
171 size_t alloc_size;
172
173 alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN);
174 if (sizeof_priv)
175 alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN);
176
177 cl = kzalloc(alloc_size, GFP_KERNEL);
178 if (!cl)
179 return ERR_PTR(-ENOMEM);
180
181 mutex_lock(®istered_clients_lock);
182
183 cl->dev = get_device(dev);
184
185 list_add_tail(&cl->entry, ®istered_clients);
186
187 mutex_unlock(®istered_clients_lock);
188
189 return &cl->conv;
190 }
191
adi_axi_adc_conv_unregister(struct adi_axi_adc_conv * conv)192 static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
193 {
194 struct adi_axi_adc_client *cl = conv_to_client(conv);
195
196 mutex_lock(®istered_clients_lock);
197
198 list_del(&cl->entry);
199 put_device(cl->dev);
200
201 mutex_unlock(®istered_clients_lock);
202
203 kfree(cl);
204 }
205
devm_adi_axi_adc_conv_release(void * conv)206 static void devm_adi_axi_adc_conv_release(void *conv)
207 {
208 adi_axi_adc_conv_unregister(conv);
209 }
210
devm_adi_axi_adc_conv_register(struct device * dev,size_t sizeof_priv)211 struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
212 size_t sizeof_priv)
213 {
214 struct adi_axi_adc_conv *conv;
215 int ret;
216
217 conv = adi_axi_adc_conv_register(dev, sizeof_priv);
218 if (IS_ERR(conv))
219 return conv;
220
221 ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release,
222 conv);
223 if (ret)
224 return ERR_PTR(ret);
225
226 return conv;
227 }
228 EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register);
229
in_voltage_scale_available_show(struct device * dev,struct device_attribute * attr,char * buf)230 static ssize_t in_voltage_scale_available_show(struct device *dev,
231 struct device_attribute *attr,
232 char *buf)
233 {
234 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
235 struct adi_axi_adc_state *st = iio_priv(indio_dev);
236 struct adi_axi_adc_conv *conv = &st->client->conv;
237 size_t len = 0;
238 int i;
239
240 for (i = 0; i < conv->chip_info->num_scales; i++) {
241 const unsigned int *s = conv->chip_info->scale_table[i];
242
243 len += scnprintf(buf + len, PAGE_SIZE - len,
244 "%u.%06u ", s[0], s[1]);
245 }
246 buf[len - 1] = '\n';
247
248 return len;
249 }
250
251 static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
252
253 enum {
254 ADI_AXI_ATTR_SCALE_AVAIL,
255 };
256
257 #define ADI_AXI_ATTR(_en_, _file_) \
258 [ADI_AXI_ATTR_##_en_] = &iio_dev_attr_##_file_.dev_attr.attr
259
260 static struct attribute *adi_axi_adc_attributes[] = {
261 ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available),
262 NULL
263 };
264
axi_adc_attr_is_visible(struct kobject * kobj,struct attribute * attr,int n)265 static umode_t axi_adc_attr_is_visible(struct kobject *kobj,
266 struct attribute *attr, int n)
267 {
268 struct device *dev = kobj_to_dev(kobj);
269 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
270 struct adi_axi_adc_state *st = iio_priv(indio_dev);
271 struct adi_axi_adc_conv *conv = &st->client->conv;
272
273 switch (n) {
274 case ADI_AXI_ATTR_SCALE_AVAIL:
275 if (!conv->chip_info->num_scales)
276 return 0;
277 return attr->mode;
278 default:
279 return attr->mode;
280 }
281 }
282
283 static const struct attribute_group adi_axi_adc_attribute_group = {
284 .attrs = adi_axi_adc_attributes,
285 .is_visible = axi_adc_attr_is_visible,
286 };
287
288 static const struct iio_info adi_axi_adc_info = {
289 .read_raw = &adi_axi_adc_read_raw,
290 .write_raw = &adi_axi_adc_write_raw,
291 .attrs = &adi_axi_adc_attribute_group,
292 .update_scan_mode = &adi_axi_adc_update_scan_mode,
293 };
294
295 static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
296 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
297 };
298
adi_axi_adc_attach_client(struct device * dev)299 static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
300 {
301 const struct adi_axi_adc_core_info *info;
302 struct adi_axi_adc_client *cl;
303 struct device_node *cln;
304
305 info = of_device_get_match_data(dev);
306 if (!info)
307 return ERR_PTR(-ENODEV);
308
309 cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
310 if (!cln) {
311 dev_err(dev, "No 'adi,adc-dev' node defined\n");
312 return ERR_PTR(-ENODEV);
313 }
314
315 mutex_lock(®istered_clients_lock);
316
317 list_for_each_entry(cl, ®istered_clients, entry) {
318 if (!cl->dev)
319 continue;
320
321 if (cl->dev->of_node != cln)
322 continue;
323
324 if (!try_module_get(cl->dev->driver->owner)) {
325 mutex_unlock(®istered_clients_lock);
326 of_node_put(cln);
327 return ERR_PTR(-ENODEV);
328 }
329
330 get_device(cl->dev);
331 cl->info = info;
332 mutex_unlock(®istered_clients_lock);
333 of_node_put(cln);
334 return cl;
335 }
336
337 mutex_unlock(®istered_clients_lock);
338 of_node_put(cln);
339
340 return ERR_PTR(-EPROBE_DEFER);
341 }
342
adi_axi_adc_setup_channels(struct device * dev,struct adi_axi_adc_state * st)343 static int adi_axi_adc_setup_channels(struct device *dev,
344 struct adi_axi_adc_state *st)
345 {
346 struct adi_axi_adc_conv *conv = &st->client->conv;
347 int i, ret;
348
349 if (conv->preenable_setup) {
350 ret = conv->preenable_setup(conv);
351 if (ret)
352 return ret;
353 }
354
355 for (i = 0; i < conv->chip_info->num_channels; i++) {
356 adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
357 ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
358 }
359
360 return 0;
361 }
362
axi_adc_reset(struct adi_axi_adc_state * st)363 static void axi_adc_reset(struct adi_axi_adc_state *st)
364 {
365 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
366 mdelay(10);
367 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
368 mdelay(10);
369 adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
370 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
371 }
372
adi_axi_adc_cleanup(void * data)373 static void adi_axi_adc_cleanup(void *data)
374 {
375 struct adi_axi_adc_client *cl = data;
376
377 put_device(cl->dev);
378 module_put(cl->dev->driver->owner);
379 }
380
adi_axi_adc_probe(struct platform_device * pdev)381 static int adi_axi_adc_probe(struct platform_device *pdev)
382 {
383 struct adi_axi_adc_conv *conv;
384 struct iio_dev *indio_dev;
385 struct adi_axi_adc_client *cl;
386 struct adi_axi_adc_state *st;
387 unsigned int ver;
388 int ret;
389
390 cl = adi_axi_adc_attach_client(&pdev->dev);
391 if (IS_ERR(cl))
392 return PTR_ERR(cl);
393
394 ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
395 if (ret)
396 return ret;
397
398 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
399 if (indio_dev == NULL)
400 return -ENOMEM;
401
402 st = iio_priv(indio_dev);
403 st->client = cl;
404 cl->state = st;
405 mutex_init(&st->lock);
406
407 st->regs = devm_platform_ioremap_resource(pdev, 0);
408 if (IS_ERR(st->regs))
409 return PTR_ERR(st->regs);
410
411 conv = &st->client->conv;
412
413 axi_adc_reset(st);
414
415 ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
416
417 if (cl->info->version > ver) {
418 dev_err(&pdev->dev,
419 "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
420 ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
421 ADI_AXI_PCORE_VER_MINOR(cl->info->version),
422 ADI_AXI_PCORE_VER_PATCH(cl->info->version),
423 ADI_AXI_PCORE_VER_MAJOR(ver),
424 ADI_AXI_PCORE_VER_MINOR(ver),
425 ADI_AXI_PCORE_VER_PATCH(ver));
426 return -ENODEV;
427 }
428
429 indio_dev->info = &adi_axi_adc_info;
430 indio_dev->name = "adi-axi-adc";
431 indio_dev->modes = INDIO_DIRECT_MODE;
432 indio_dev->num_channels = conv->chip_info->num_channels;
433 indio_dev->channels = conv->chip_info->channels;
434
435 ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
436 if (ret)
437 return ret;
438
439 ret = adi_axi_adc_setup_channels(&pdev->dev, st);
440 if (ret)
441 return ret;
442
443 ret = devm_iio_device_register(&pdev->dev, indio_dev);
444 if (ret)
445 return ret;
446
447 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
448 ADI_AXI_PCORE_VER_MAJOR(ver),
449 ADI_AXI_PCORE_VER_MINOR(ver),
450 ADI_AXI_PCORE_VER_PATCH(ver));
451
452 return 0;
453 }
454
455 /* Match table for of_platform binding */
456 static const struct of_device_id adi_axi_adc_of_match[] = {
457 { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
458 { /* end of list */ }
459 };
460 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
461
462 static struct platform_driver adi_axi_adc_driver = {
463 .driver = {
464 .name = KBUILD_MODNAME,
465 .of_match_table = adi_axi_adc_of_match,
466 },
467 .probe = adi_axi_adc_probe,
468 };
469 module_platform_driver(adi_axi_adc_driver);
470
471 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
472 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
473 MODULE_LICENSE("GPL v2");
474