1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GT_TYPES__ 7 #define __INTEL_GT_TYPES__ 8 9 #include <linux/ktime.h> 10 #include <linux/list.h> 11 #include <linux/llist.h> 12 #include <linux/mutex.h> 13 #include <linux/notifier.h> 14 #include <linux/seqlock.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 #include <linux/workqueue.h> 18 19 #include "uc/intel_uc.h" 20 #include "intel_gsc.h" 21 22 #include "i915_vma.h" 23 #include "intel_engine_types.h" 24 #include "intel_gt_buffer_pool_types.h" 25 #include "intel_hwconfig.h" 26 #include "intel_llc_types.h" 27 #include "intel_reset_types.h" 28 #include "intel_rc6_types.h" 29 #include "intel_rps_types.h" 30 #include "intel_migrate_types.h" 31 #include "intel_wakeref.h" 32 #include "pxp/intel_pxp_types.h" 33 34 struct drm_i915_private; 35 struct i915_ggtt; 36 struct intel_engine_cs; 37 struct intel_uncore; 38 39 struct intel_mmio_range { 40 u32 start; 41 u32 end; 42 }; 43 44 /* 45 * The hardware has multiple kinds of multicast register ranges that need 46 * special register steering (and future platforms are expected to add 47 * additional types). 48 * 49 * During driver startup, we initialize the steering control register to 50 * direct reads to a slice/subslice that are valid for the 'subslice' class 51 * of multicast registers. If another type of steering does not have any 52 * overlap in valid steering targets with 'subslice' style registers, we will 53 * need to explicitly re-steer reads of registers of the other type. 54 * 55 * Only the replication types that may need additional non-default steering 56 * are listed here. 57 */ 58 enum intel_steering_type { 59 L3BANK, 60 MSLICE, 61 LNCF, 62 63 /* 64 * On some platforms there are multiple types of MCR registers that 65 * will always return a non-terminated value at instance (0, 0). We'll 66 * lump those all into a single category to keep things simple. 67 */ 68 INSTANCE0, 69 70 NUM_STEERING_TYPES 71 }; 72 73 enum intel_submission_method { 74 INTEL_SUBMISSION_RING, 75 INTEL_SUBMISSION_ELSP, 76 INTEL_SUBMISSION_GUC, 77 }; 78 79 struct gt_defaults { 80 u32 min_freq; 81 u32 max_freq; 82 }; 83 84 enum intel_gt_type { 85 GT_PRIMARY, 86 GT_TILE, 87 GT_MEDIA, 88 }; 89 90 struct intel_gt { 91 struct drm_i915_private *i915; 92 const char *name; 93 enum intel_gt_type type; 94 95 struct intel_uncore *uncore; 96 struct i915_ggtt *ggtt; 97 98 struct intel_uc uc; 99 struct intel_gsc gsc; 100 101 struct { 102 /* Serialize global tlb invalidations */ 103 struct mutex invalidate_lock; 104 105 /* 106 * Batch TLB invalidations 107 * 108 * After unbinding the PTE, we need to ensure the TLB 109 * are invalidated prior to releasing the physical pages. 110 * But we only need one such invalidation for all unbinds, 111 * so we track how many TLB invalidations have been 112 * performed since unbind the PTE and only emit an extra 113 * invalidate if no full barrier has been passed. 114 */ 115 seqcount_mutex_t seqno; 116 } tlb; 117 118 struct i915_wa_list wa_list; 119 120 struct intel_gt_timelines { 121 spinlock_t lock; /* protects active_list */ 122 struct list_head active_list; 123 } timelines; 124 125 struct intel_gt_requests { 126 /** 127 * We leave the user IRQ off as much as possible, 128 * but this means that requests will finish and never 129 * be retired once the system goes idle. Set a timer to 130 * fire periodically while the ring is running. When it 131 * fires, go retire requests. 132 */ 133 struct delayed_work retire_work; 134 } requests; 135 136 struct { 137 struct llist_head list; 138 struct work_struct work; 139 } watchdog; 140 141 struct intel_wakeref wakeref; 142 atomic_t user_wakeref; 143 144 struct list_head closed_vma; 145 spinlock_t closed_lock; /* guards the list of closed_vma */ 146 147 ktime_t last_init_time; 148 struct intel_reset reset; 149 150 /** 151 * Is the GPU currently considered idle, or busy executing 152 * userspace requests? Whilst idle, we allow runtime power 153 * management to power down the hardware and display clocks. 154 * In order to reduce the effect on performance, there 155 * is a slight delay before we do so. 156 */ 157 intel_wakeref_t awake; 158 159 u32 clock_frequency; 160 u32 clock_period_ns; 161 162 struct intel_llc llc; 163 struct intel_rc6 rc6; 164 struct intel_rps rps; 165 166 spinlock_t *irq_lock; 167 u32 gt_imr; 168 u32 pm_ier; 169 u32 pm_imr; 170 171 u32 pm_guc_events; 172 173 struct { 174 bool active; 175 176 /** 177 * @lock: Lock protecting the below fields. 178 */ 179 seqcount_mutex_t lock; 180 181 /** 182 * @total: Total time this engine was busy. 183 * 184 * Accumulated time not counting the most recent block in cases 185 * where engine is currently busy (active > 0). 186 */ 187 ktime_t total; 188 189 /** 190 * @start: Timestamp of the last idle to active transition. 191 * 192 * Idle is defined as active == 0, active is active > 0. 193 */ 194 ktime_t start; 195 } stats; 196 197 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 198 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] 199 [MAX_ENGINE_INSTANCE + 1]; 200 enum intel_submission_method submission_method; 201 202 /* 203 * Default address space (either GGTT or ppGTT depending on arch). 204 * 205 * Reserved for exclusive use by the kernel. 206 */ 207 struct i915_address_space *vm; 208 209 /* 210 * A pool of objects to use as shadow copies of client batch buffers 211 * when the command parser is enabled. Prevents the client from 212 * modifying the batch contents after software parsing. 213 * 214 * Buffers older than 1s are periodically reaped from the pool, 215 * or may be reclaimed by the shrinker before then. 216 */ 217 struct intel_gt_buffer_pool buffer_pool; 218 219 struct i915_vma *scratch; 220 221 struct intel_migrate migrate; 222 223 const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES]; 224 225 struct { 226 u8 groupid; 227 u8 instanceid; 228 } default_steering; 229 230 /* 231 * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT. 232 */ 233 phys_addr_t phys_addr; 234 235 struct intel_gt_info { 236 unsigned int id; 237 238 intel_engine_mask_t engine_mask; 239 240 u32 l3bank_mask; 241 242 u8 num_engines; 243 244 /* General presence of SFC units */ 245 u8 sfc_mask; 246 247 /* Media engine access to SFC per instance */ 248 u8 vdbox_sfc_access; 249 250 /* Slice/subslice/EU info */ 251 struct sseu_dev_info sseu; 252 253 unsigned long mslice_mask; 254 255 /** @hwconfig: hardware configuration data */ 256 struct intel_hwconfig hwconfig; 257 } info; 258 259 struct { 260 u8 uc_index; 261 u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */ 262 } mocs; 263 264 struct intel_pxp pxp; 265 266 /* gt/gtN sysfs */ 267 struct kobject sysfs_gt; 268 269 /* sysfs defaults per gt */ 270 struct gt_defaults defaults; 271 struct kobject *sysfs_defaults; 272 }; 273 274 struct intel_gt_definition { 275 enum intel_gt_type type; 276 char *name; 277 u32 mapping_base; 278 u32 gsi_offset; 279 intel_engine_mask_t engine_mask; 280 }; 281 282 enum intel_gt_scratch_field { 283 /* 8 bytes */ 284 INTEL_GT_SCRATCH_FIELD_DEFAULT = 0, 285 286 /* 8 bytes */ 287 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128, 288 289 /* 8 bytes */ 290 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256, 291 292 /* 6 * 8 bytes */ 293 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048, 294 295 /* 4 bytes */ 296 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096, 297 }; 298 299 #endif /* __INTEL_GT_TYPES_H__ */ 300