1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "mcif_wb.h" 39 #include "panel_cntl.h" 40 41 #define MAX_CLOCK_SOURCES 7 42 43 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 44 uint32_t controller_id); 45 46 #include "grph_object_id.h" 47 #include "link_encoder.h" 48 #include "stream_encoder.h" 49 #include "clock_source.h" 50 #include "audio.h" 51 #include "dm_pp_smu.h" 52 #ifdef CONFIG_DRM_AMD_DC_HDCP 53 #include "dm_cp_psp.h" 54 #endif 55 #include "link_hwss.h" 56 57 /************ link *****************/ 58 struct link_init_data { 59 const struct dc *dc; 60 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 61 uint32_t connector_index; /* this will be mapped to the HPD pins */ 62 uint32_t link_index; /* this is mapped to DAL display_index 63 TODO: remove it when DC is complete. */ 64 bool is_dpia_link; 65 }; 66 67 struct dc_link *link_create(const struct link_init_data *init_params); 68 void link_destroy(struct dc_link **link); 69 70 enum dc_status dc_link_validate_mode_timing( 71 const struct dc_stream_state *stream, 72 struct dc_link *link, 73 const struct dc_crtc_timing *timing); 74 75 void core_link_resume(struct dc_link *link); 76 77 void core_link_enable_stream( 78 struct dc_state *state, 79 struct pipe_ctx *pipe_ctx); 80 81 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 82 83 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 84 /********** DAL Core*********************/ 85 #include "transform.h" 86 #include "dpp.h" 87 88 struct resource_pool; 89 struct dc_state; 90 struct resource_context; 91 struct clk_bw_params; 92 93 struct resource_funcs { 94 void (*destroy)(struct resource_pool **pool); 95 void (*link_init)(struct dc_link *link); 96 struct panel_cntl*(*panel_cntl_create)( 97 const struct panel_cntl_init_data *panel_cntl_init_data); 98 struct link_encoder *(*link_enc_create)( 99 const struct encoder_init_data *init); 100 /* Create a minimal link encoder object with no dc_link object 101 * associated with it. */ 102 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 103 104 bool (*validate_bandwidth)( 105 struct dc *dc, 106 struct dc_state *context, 107 bool fast_validate); 108 void (*calculate_wm_and_dlg)( 109 struct dc *dc, struct dc_state *context, 110 display_e2e_pipe_params_st *pipes, 111 int pipe_cnt, 112 int vlevel); 113 void (*update_soc_for_wm_a)( 114 struct dc *dc, struct dc_state *context); 115 int (*populate_dml_pipes)( 116 struct dc *dc, 117 struct dc_state *context, 118 display_e2e_pipe_params_st *pipes, 119 bool fast_validate); 120 121 /* 122 * Algorithm for assigning available link encoders to links. 123 * 124 * Update link_enc_assignments table and link_enc_avail list accordingly in 125 * struct resource_context. 126 */ 127 void (*link_encs_assign)( 128 struct dc *dc, 129 struct dc_state *state, 130 struct dc_stream_state *streams[], 131 uint8_t stream_count); 132 /* 133 * Unassign a link encoder from a stream. 134 * 135 * Update link_enc_assignments table and link_enc_avail list accordingly in 136 * struct resource_context. 137 */ 138 void (*link_enc_unassign)( 139 struct dc_state *state, 140 struct dc_stream_state *stream); 141 142 enum dc_status (*validate_global)( 143 struct dc *dc, 144 struct dc_state *context); 145 146 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 147 struct dc_state *context, 148 const struct resource_pool *pool, 149 struct dc_stream_state *stream); 150 151 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 152 153 enum dc_status (*add_stream_to_ctx)( 154 struct dc *dc, 155 struct dc_state *new_ctx, 156 struct dc_stream_state *dc_stream); 157 158 enum dc_status (*remove_stream_from_ctx)( 159 struct dc *dc, 160 struct dc_state *new_ctx, 161 struct dc_stream_state *stream); 162 enum dc_status (*patch_unknown_plane_state)( 163 struct dc_plane_state *plane_state); 164 165 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 166 struct resource_context *res_ctx, 167 const struct resource_pool *pool, 168 struct dc_stream_state *stream); 169 void (*populate_dml_writeback_from_context)( 170 struct dc *dc, 171 struct resource_context *res_ctx, 172 display_e2e_pipe_params_st *pipes); 173 174 void (*set_mcif_arb_params)( 175 struct dc *dc, 176 struct dc_state *context, 177 display_e2e_pipe_params_st *pipes, 178 int pipe_cnt); 179 void (*update_bw_bounding_box)( 180 struct dc *dc, 181 struct clk_bw_params *bw_params); 182 bool (*acquire_post_bldn_3dlut)( 183 struct resource_context *res_ctx, 184 const struct resource_pool *pool, 185 int mpcc_id, 186 struct dc_3dlut **lut, 187 struct dc_transfer_func **shaper); 188 189 bool (*release_post_bldn_3dlut)( 190 struct resource_context *res_ctx, 191 const struct resource_pool *pool, 192 struct dc_3dlut **lut, 193 struct dc_transfer_func **shaper); 194 195 enum dc_status (*add_dsc_to_stream_resource)( 196 struct dc *dc, struct dc_state *state, 197 struct dc_stream_state *stream); 198 }; 199 200 struct audio_support{ 201 bool dp_audio; 202 bool hdmi_audio_on_dongle; 203 bool hdmi_audio_native; 204 }; 205 206 #define NO_UNDERLAY_PIPE -1 207 208 struct resource_pool { 209 struct mem_input *mis[MAX_PIPES]; 210 struct hubp *hubps[MAX_PIPES]; 211 struct input_pixel_processor *ipps[MAX_PIPES]; 212 struct transform *transforms[MAX_PIPES]; 213 struct dpp *dpps[MAX_PIPES]; 214 struct output_pixel_processor *opps[MAX_PIPES]; 215 struct timing_generator *timing_generators[MAX_PIPES]; 216 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 217 struct hubbub *hubbub; 218 struct mpc *mpc; 219 struct pp_smu_funcs *pp_smu; 220 struct dce_aux *engines[MAX_PIPES]; 221 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 222 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 223 bool i2c_hw_buffer_in_use; 224 225 struct dwbc *dwbc[MAX_DWB_PIPES]; 226 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 227 struct { 228 unsigned int gsl_0:1; 229 unsigned int gsl_1:1; 230 unsigned int gsl_2:1; 231 } gsl_groups; 232 233 struct display_stream_compressor *dscs[MAX_PIPES]; 234 235 unsigned int pipe_count; 236 unsigned int underlay_pipe_index; 237 unsigned int stream_enc_count; 238 239 /* An array for accessing the link encoder objects that have been created. 240 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 241 */ 242 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 243 /* Number of DIG link encoder objects created - i.e. number of valid 244 * entries in link_encoders array. 245 */ 246 unsigned int dig_link_enc_count; 247 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 248 unsigned int usb4_dpia_count; 249 250 unsigned int hpo_dp_stream_enc_count; 251 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 252 unsigned int hpo_dp_link_enc_count; 253 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 254 struct dc_3dlut *mpc_lut[MAX_PIPES]; 255 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 256 257 struct { 258 unsigned int xtalin_clock_inKhz; 259 unsigned int dccg_ref_clock_inKhz; 260 unsigned int dchub_ref_clock_inKhz; 261 } ref_clocks; 262 unsigned int timing_generator_count; 263 unsigned int mpcc_count; 264 265 unsigned int writeback_pipe_count; 266 /* 267 * reserved clock source for DP 268 */ 269 struct clock_source *dp_clock_source; 270 271 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 272 unsigned int clk_src_count; 273 274 struct audio *audios[MAX_AUDIOS]; 275 unsigned int audio_count; 276 struct audio_support audio_support; 277 278 struct dccg *dccg; 279 struct irq_service *irqs; 280 281 struct abm *abm; 282 struct dmcu *dmcu; 283 struct dmub_psr *psr; 284 285 struct abm *multiple_abms[MAX_PIPES]; 286 287 const struct resource_funcs *funcs; 288 const struct resource_caps *res_cap; 289 290 struct ddc_service *oem_device; 291 }; 292 293 struct dcn_fe_bandwidth { 294 int dppclk_khz; 295 296 }; 297 298 struct stream_resource { 299 struct output_pixel_processor *opp; 300 struct display_stream_compressor *dsc; 301 struct timing_generator *tg; 302 struct stream_encoder *stream_enc; 303 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 304 struct audio *audio; 305 306 struct pixel_clk_params pix_clk_params; 307 struct encoder_info_frame encoder_info_frame; 308 309 struct abm *abm; 310 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 311 * otherwise it's using group number 'gsl_group-1' 312 */ 313 uint8_t gsl_group; 314 }; 315 316 struct plane_resource { 317 struct scaler_data scl_data; 318 struct hubp *hubp; 319 struct mem_input *mi; 320 struct input_pixel_processor *ipp; 321 struct transform *xfm; 322 struct dpp *dpp; 323 uint8_t mpcc_inst; 324 325 struct dcn_fe_bandwidth bw; 326 }; 327 328 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 329 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 330 331 /* all mappable hardware resources used to enable a link */ 332 struct link_resource { 333 struct hpo_dp_link_encoder *hpo_dp_link_enc; 334 }; 335 336 union pipe_update_flags { 337 struct { 338 uint32_t enable : 1; 339 uint32_t disable : 1; 340 uint32_t odm : 1; 341 uint32_t global_sync : 1; 342 uint32_t opp_changed : 1; 343 uint32_t tg_changed : 1; 344 uint32_t mpcc : 1; 345 uint32_t dppclk : 1; 346 uint32_t hubp_interdependent : 1; 347 uint32_t hubp_rq_dlg_ttu : 1; 348 uint32_t gamut_remap : 1; 349 uint32_t scaler : 1; 350 uint32_t viewport : 1; 351 uint32_t plane_changed : 1; 352 uint32_t det_size : 1; 353 } bits; 354 uint32_t raw; 355 }; 356 357 struct pipe_ctx { 358 struct dc_plane_state *plane_state; 359 struct dc_stream_state *stream; 360 361 struct plane_resource plane_res; 362 struct stream_resource stream_res; 363 struct link_resource link_res; 364 365 struct clock_source *clock_source; 366 367 struct pll_settings pll_settings; 368 369 uint8_t pipe_idx; 370 uint8_t pipe_idx_syncd; 371 372 struct pipe_ctx *top_pipe; 373 struct pipe_ctx *bottom_pipe; 374 struct pipe_ctx *next_odm_pipe; 375 struct pipe_ctx *prev_odm_pipe; 376 377 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 378 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 379 struct _vcs_dpi_display_rq_regs_st rq_regs; 380 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 381 struct _vcs_dpi_display_rq_params_st dml_rq_param; 382 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 383 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 384 int det_buffer_size_kb; 385 bool unbounded_req; 386 387 union pipe_update_flags update_flags; 388 struct dwbc *dwbc; 389 struct mcif_wb *mcif_wb; 390 bool vtp_locked; 391 }; 392 393 /* Data used for dynamic link encoder assignment. 394 * Tracks current and future assignments; available link encoders; 395 * and mode of operation (whether to use current or future assignments). 396 */ 397 struct link_enc_cfg_context { 398 enum link_enc_cfg_mode mode; 399 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 400 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 401 struct link_enc_assignment transient_assignments[MAX_PIPES]; 402 }; 403 404 struct resource_context { 405 struct pipe_ctx pipe_ctx[MAX_PIPES]; 406 bool is_stream_enc_acquired[MAX_PIPES * 2]; 407 bool is_audio_acquired[MAX_PIPES]; 408 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 409 uint8_t dp_clock_source_ref_count; 410 bool is_dsc_acquired[MAX_PIPES]; 411 struct link_enc_cfg_context link_enc_cfg_ctx; 412 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 413 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 414 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 415 bool is_mpc_3dlut_acquired[MAX_PIPES]; 416 }; 417 418 struct dce_bw_output { 419 bool cpuc_state_change_enable; 420 bool cpup_state_change_enable; 421 bool stutter_mode_enable; 422 bool nbp_state_change_enable; 423 bool all_displays_in_sync; 424 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 425 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 426 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 427 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 428 int sclk_khz; 429 int sclk_deep_sleep_khz; 430 int yclk_khz; 431 int dispclk_khz; 432 int blackout_recovery_time_us; 433 }; 434 435 struct dcn_bw_writeback { 436 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 437 }; 438 439 struct dcn_bw_output { 440 struct dc_clocks clk; 441 struct dcn_watermark_set watermarks; 442 struct dcn_bw_writeback bw_writeback; 443 int compbuf_size_kb; 444 }; 445 446 union bw_output { 447 struct dcn_bw_output dcn; 448 struct dce_bw_output dce; 449 }; 450 451 struct bw_context { 452 union bw_output bw; 453 struct display_mode_lib dml; 454 }; 455 /** 456 * struct dc_state - The full description of a state requested by a user 457 * 458 * @streams: Stream properties 459 * @stream_status: The planes on a given stream 460 * @res_ctx: Persistent state of resources 461 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 462 * @pp_display_cfg: PowerPlay clocks and settings 463 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 464 * 465 */ 466 struct dc_state { 467 struct dc_stream_state *streams[MAX_PIPES]; 468 struct dc_stream_status stream_status[MAX_PIPES]; 469 uint8_t stream_count; 470 uint8_t stream_mask; 471 472 struct resource_context res_ctx; 473 474 struct bw_context bw_ctx; 475 476 /* Note: these are big structures, do *not* put on stack! */ 477 struct dm_pp_display_configuration pp_display_cfg; 478 struct dcn_bw_internal_vars dcn_bw_vars; 479 480 struct clk_mgr *clk_mgr; 481 482 struct kref refcount; 483 484 struct { 485 unsigned int stutter_period_us; 486 } perf_params; 487 }; 488 489 struct dc_bounding_box_max_clk { 490 int max_dcfclk_mhz; 491 int max_dispclk_mhz; 492 int max_dppclk_mhz; 493 int max_phyclk_mhz; 494 }; 495 496 #endif /* _CORE_TYPES_H_ */ 497