1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "clk_mgr.h"
28 #include "resource.h"
29 #include "dcn31/dcn31_hubbub.h"
30 #include "dcn314_fpu.h"
31 #include "dml/dcn20/dcn20_fpu.h"
32 #include "dml/display_mode_vba.h"
33
34 struct _vcs_dpi_ip_params_st dcn3_14_ip = {
35 .VBlankNomDefaultUS = 668,
36 .gpuvm_enable = 1,
37 .gpuvm_max_page_table_levels = 1,
38 .hostvm_enable = 1,
39 .hostvm_max_page_table_levels = 2,
40 .rob_buffer_size_kbytes = 64,
41 .det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE,
42 .config_return_buffer_size_in_kbytes = 1792,
43 .compressed_buffer_segment_size_in_kbytes = 64,
44 .meta_fifo_size_in_kentries = 32,
45 .zero_size_buffer_entries = 512,
46 .compbuf_reserved_space_64b = 256,
47 .compbuf_reserved_space_zs = 64,
48 .dpp_output_buffer_pixels = 2560,
49 .opp_output_buffer_lines = 1,
50 .pixel_chunk_size_kbytes = 8,
51 .meta_chunk_size_kbytes = 2,
52 .min_meta_chunk_size_bytes = 256,
53 .writeback_chunk_size_kbytes = 8,
54 .ptoi_supported = false,
55 .num_dsc = 4,
56 .maximum_dsc_bits_per_component = 10,
57 .dsc422_native_support = false,
58 .is_line_buffer_bpp_fixed = true,
59 .line_buffer_fixed_bpp = 48,
60 .line_buffer_size_bits = 789504,
61 .max_line_buffer_lines = 12,
62 .writeback_interface_buffer_size_kbytes = 90,
63 .max_num_dpp = 4,
64 .max_num_otg = 4,
65 .max_num_hdmi_frl_outputs = 1,
66 .max_num_wb = 1,
67 .max_dchub_pscl_bw_pix_per_clk = 4,
68 .max_pscl_lb_bw_pix_per_clk = 2,
69 .max_lb_vscl_bw_pix_per_clk = 4,
70 .max_vscl_hscl_bw_pix_per_clk = 4,
71 .max_hscl_ratio = 6,
72 .max_vscl_ratio = 6,
73 .max_hscl_taps = 8,
74 .max_vscl_taps = 8,
75 .dpte_buffer_size_in_pte_reqs_luma = 64,
76 .dpte_buffer_size_in_pte_reqs_chroma = 34,
77 .dispclk_ramp_margin_percent = 1,
78 .max_inter_dcn_tile_repeaters = 8,
79 .cursor_buffer_size = 16,
80 .cursor_chunk_size = 2,
81 .writeback_line_buffer_buffer_size = 0,
82 .writeback_min_hscl_ratio = 1,
83 .writeback_min_vscl_ratio = 1,
84 .writeback_max_hscl_ratio = 1,
85 .writeback_max_vscl_ratio = 1,
86 .writeback_max_hscl_taps = 1,
87 .writeback_max_vscl_taps = 1,
88 .dppclk_delay_subtotal = 46,
89 .dppclk_delay_scl = 50,
90 .dppclk_delay_scl_lb_only = 16,
91 .dppclk_delay_cnvc_formatter = 27,
92 .dppclk_delay_cnvc_cursor = 6,
93 .dispclk_delay_subtotal = 119,
94 .dynamic_metadata_vm_enabled = false,
95 .odm_combine_4to1_supported = false,
96 .dcc_supported = true,
97 };
98
99 struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {
100 /*TODO: correct dispclk/dppclk voltage level determination*/
101 .clock_limits = {
102 {
103 .state = 0,
104 .dispclk_mhz = 1200.0,
105 .dppclk_mhz = 1200.0,
106 .phyclk_mhz = 600.0,
107 .phyclk_d18_mhz = 667.0,
108 .dscclk_mhz = 186.0,
109 .dtbclk_mhz = 600.0,
110 },
111 {
112 .state = 1,
113 .dispclk_mhz = 1200.0,
114 .dppclk_mhz = 1200.0,
115 .phyclk_mhz = 810.0,
116 .phyclk_d18_mhz = 667.0,
117 .dscclk_mhz = 209.0,
118 .dtbclk_mhz = 600.0,
119 },
120 {
121 .state = 2,
122 .dispclk_mhz = 1200.0,
123 .dppclk_mhz = 1200.0,
124 .phyclk_mhz = 810.0,
125 .phyclk_d18_mhz = 667.0,
126 .dscclk_mhz = 209.0,
127 .dtbclk_mhz = 600.0,
128 },
129 {
130 .state = 3,
131 .dispclk_mhz = 1200.0,
132 .dppclk_mhz = 1200.0,
133 .phyclk_mhz = 810.0,
134 .phyclk_d18_mhz = 667.0,
135 .dscclk_mhz = 371.0,
136 .dtbclk_mhz = 600.0,
137 },
138 {
139 .state = 4,
140 .dispclk_mhz = 1200.0,
141 .dppclk_mhz = 1200.0,
142 .phyclk_mhz = 810.0,
143 .phyclk_d18_mhz = 667.0,
144 .dscclk_mhz = 417.0,
145 .dtbclk_mhz = 600.0,
146 },
147 },
148 .num_states = 5,
149 .sr_exit_time_us = 16.5,
150 .sr_enter_plus_exit_time_us = 18.5,
151 .sr_exit_z8_time_us = 442.0,
152 .sr_enter_plus_exit_z8_time_us = 560.0,
153 .writeback_latency_us = 12.0,
154 .dram_channel_width_bytes = 4,
155 .round_trip_ping_latency_dcfclk_cycles = 106,
156 .urgent_latency_pixel_data_only_us = 4.0,
157 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
158 .urgent_latency_vm_data_only_us = 4.0,
159 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
160 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
161 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
162 .pct_ideal_sdp_bw_after_urgent = 80.0,
163 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
164 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
165 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
166 .max_avg_sdp_bw_use_normal_percent = 60.0,
167 .max_avg_dram_bw_use_normal_percent = 60.0,
168 .fabric_datapath_to_dcn_data_return_bytes = 32,
169 .return_bus_width_bytes = 64,
170 .downspread_percent = 0.38,
171 .dcn_downspread_percent = 0.5,
172 .gpuvm_min_page_size_bytes = 4096,
173 .hostvm_min_page_size_bytes = 4096,
174 .do_urgent_latency_adjustment = false,
175 .urgent_latency_adjustment_fabric_clock_component_us = 0,
176 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
177 };
178
179
dcn314_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params)180 void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
181 {
182 struct clk_limit_table *clk_table = &bw_params->clk_table;
183 struct _vcs_dpi_voltage_scaling_st *clock_limits =
184 dcn3_14_soc.clock_limits;
185 unsigned int i, closest_clk_lvl;
186 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
187 int j;
188
189 dc_assert_fp_enabled();
190
191 // Default clock levels are used for diags, which may lead to overclocking.
192 if (!IS_DIAG_DC(dc->ctx->dce_environment) && dc->config.use_default_clock_table == false) {
193
194 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
195 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;
196
197 if (bw_params->dram_channel_width_bytes > 0)
198 dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes;
199
200 if (bw_params->num_channels > 0)
201 dcn3_14_soc.num_chans = bw_params->num_channels;
202
203 ASSERT(dcn3_14_soc.num_chans);
204 ASSERT(clk_table->num_entries);
205
206 /* Prepass to find max clocks independent of voltage level. */
207 for (i = 0; i < clk_table->num_entries; ++i) {
208 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
209 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
210 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
211 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
212 }
213
214 for (i = 0; i < clk_table->num_entries; i++) {
215 /* loop backwards*/
216 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) {
217 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
218 closest_clk_lvl = j;
219 break;
220 }
221 }
222 if (clk_table->num_entries == 1) {
223 /*smu gives one DPM level, let's take the highest one*/
224 closest_clk_lvl = dcn3_14_soc.num_states - 1;
225 }
226
227 clock_limits[i].state = i;
228
229 /* Clocks dependent on voltage level. */
230 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
231 if (clk_table->num_entries == 1 &&
232 clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
233 /*SMU fix not released yet*/
234 clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
235 }
236 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
237 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
238
239 if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio)
240 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
241
242 /* Clocks independent of voltage level. */
243 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
244 dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
245
246 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
247 dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
248
249 clock_limits[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
250 clock_limits[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
251 clock_limits[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
252 clock_limits[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
253 clock_limits[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
254 }
255 for (i = 0; i < clk_table->num_entries; i++)
256 dcn3_14_soc.clock_limits[i] = clock_limits[i];
257 if (clk_table->num_entries) {
258 dcn3_14_soc.num_states = clk_table->num_entries;
259 }
260 }
261
262 if (max_dispclk_mhz) {
263 dcn3_14_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
264 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
265 }
266
267 if ((int)(dcn3_14_soc.dram_clock_change_latency_us * 1000)
268 != dc->debug.dram_clock_change_latency_ns
269 && dc->debug.dram_clock_change_latency_ns) {
270 dcn3_14_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;
271 }
272 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
273 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314);
274 else
275 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA);
276 }
277
is_dual_plane(enum surface_pixel_format format)278 static bool is_dual_plane(enum surface_pixel_format format)
279 {
280 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
281 }
282
dcn314_populate_dml_pipes_from_context_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)283 int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,
284 display_e2e_pipe_params_st *pipes,
285 bool fast_validate)
286 {
287 int i, pipe_cnt;
288 struct resource_context *res_ctx = &context->res_ctx;
289 struct pipe_ctx *pipe;
290 bool upscaled = false;
291
292 dc_assert_fp_enabled();
293
294 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
295
296 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
297 struct dc_crtc_timing *timing;
298
299 if (!res_ctx->pipe_ctx[i].stream)
300 continue;
301 pipe = &res_ctx->pipe_ctx[i];
302 timing = &pipe->stream->timing;
303
304 if (dc_extended_blank_supported(dc) && pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min
305 && pipe->stream->adjust.v_total_min > timing->v_total)
306 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min;
307
308 if (pipe->plane_state &&
309 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
310 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
311 upscaled = true;
312
313 /*
314 * Immediate flip can be set dynamically after enabling the plane.
315 * We need to require support for immediate flip or underflow can be
316 * intermittently experienced depending on peak b/w requirements.
317 */
318 pipes[pipe_cnt].pipe.src.immediate_flip = true;
319
320 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
321 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
322 pipes[pipe_cnt].pipe.src.gpuvm = true;
323 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
324 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
325 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
326 pipes[pipe_cnt].pipe.dest.vblank_nom =
327 dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0));
328 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
329 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
330
331 if (pipes[pipe_cnt].dout.dsc_enable) {
332 switch (timing->display_color_depth) {
333 case COLOR_DEPTH_888:
334 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
335 break;
336 case COLOR_DEPTH_101010:
337 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
338 break;
339 case COLOR_DEPTH_121212:
340 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
341 break;
342 default:
343 ASSERT(0);
344 break;
345 }
346 }
347
348 pipe_cnt++;
349 }
350 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE;
351
352 dc->config.enable_4to1MPC = false;
353 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
354 if (is_dual_plane(pipe->plane_state->format)
355 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
356 dc->config.enable_4to1MPC = true;
357 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
358 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
359 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
360 pipes[0].pipe.src.unbounded_req_mode = true;
361 }
362 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
363 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
364 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
365 } else if (context->stream_count >= 3 && upscaled) {
366 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
367 }
368
369 for (i = 0; i < dc->res_pool->pipe_count; i++) {
370 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
371
372 if (!pipe->stream)
373 continue;
374
375 if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine &&
376 pipe->stream->apply_seamless_boot_optimization) {
377
378 if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) {
379 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1;
380 break;
381 }
382 }
383 }
384
385 return pipe_cnt;
386 }
387