1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 #include "dcn32_fpu.h"
27 #include "dc_link_dp.h"
28 #include "dcn32/dcn32_resource.h"
29 #include "dcn20/dcn20_resource.h"
30 #include "display_mode_vba_util_32.h"
31 // We need this includes for WATERMARKS_* defines
32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
33 #include "dcn30/dcn30_resource.h"
34 
35 #define DC_LOGGER_INIT(logger)
36 
37 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
38 	.gpuvm_enable = 0,
39 	.gpuvm_max_page_table_levels = 4,
40 	.hostvm_enable = 0,
41 	.rob_buffer_size_kbytes = 128,
42 	.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
43 	.config_return_buffer_size_in_kbytes = 1280,
44 	.compressed_buffer_segment_size_in_kbytes = 64,
45 	.meta_fifo_size_in_kentries = 22,
46 	.zero_size_buffer_entries = 512,
47 	.compbuf_reserved_space_64b = 256,
48 	.compbuf_reserved_space_zs = 64,
49 	.dpp_output_buffer_pixels = 2560,
50 	.opp_output_buffer_lines = 1,
51 	.pixel_chunk_size_kbytes = 8,
52 	.alpha_pixel_chunk_size_kbytes = 4,
53 	.min_pixel_chunk_size_bytes = 1024,
54 	.dcc_meta_buffer_size_bytes = 6272,
55 	.meta_chunk_size_kbytes = 2,
56 	.min_meta_chunk_size_bytes = 256,
57 	.writeback_chunk_size_kbytes = 8,
58 	.ptoi_supported = false,
59 	.num_dsc = 4,
60 	.maximum_dsc_bits_per_component = 12,
61 	.maximum_pixels_per_line_per_dsc_unit = 6016,
62 	.dsc422_native_support = true,
63 	.is_line_buffer_bpp_fixed = true,
64 	.line_buffer_fixed_bpp = 57,
65 	.line_buffer_size_bits = 1171920,
66 	.max_line_buffer_lines = 32,
67 	.writeback_interface_buffer_size_kbytes = 90,
68 	.max_num_dpp = 4,
69 	.max_num_otg = 4,
70 	.max_num_hdmi_frl_outputs = 1,
71 	.max_num_wb = 1,
72 	.max_dchub_pscl_bw_pix_per_clk = 4,
73 	.max_pscl_lb_bw_pix_per_clk = 2,
74 	.max_lb_vscl_bw_pix_per_clk = 4,
75 	.max_vscl_hscl_bw_pix_per_clk = 4,
76 	.max_hscl_ratio = 6,
77 	.max_vscl_ratio = 6,
78 	.max_hscl_taps = 8,
79 	.max_vscl_taps = 8,
80 	.dpte_buffer_size_in_pte_reqs_luma = 64,
81 	.dpte_buffer_size_in_pte_reqs_chroma = 34,
82 	.dispclk_ramp_margin_percent = 1,
83 	.max_inter_dcn_tile_repeaters = 8,
84 	.cursor_buffer_size = 16,
85 	.cursor_chunk_size = 2,
86 	.writeback_line_buffer_buffer_size = 0,
87 	.writeback_min_hscl_ratio = 1,
88 	.writeback_min_vscl_ratio = 1,
89 	.writeback_max_hscl_ratio = 1,
90 	.writeback_max_vscl_ratio = 1,
91 	.writeback_max_hscl_taps = 1,
92 	.writeback_max_vscl_taps = 1,
93 	.dppclk_delay_subtotal = 47,
94 	.dppclk_delay_scl = 50,
95 	.dppclk_delay_scl_lb_only = 16,
96 	.dppclk_delay_cnvc_formatter = 28,
97 	.dppclk_delay_cnvc_cursor = 6,
98 	.dispclk_delay_subtotal = 125,
99 	.dynamic_metadata_vm_enabled = false,
100 	.odm_combine_4to1_supported = false,
101 	.dcc_supported = true,
102 	.max_num_dp2p0_outputs = 2,
103 	.max_num_dp2p0_streams = 4,
104 };
105 
106 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
107 	.clock_limits = {
108 		{
109 			.state = 0,
110 			.dcfclk_mhz = 1564.0,
111 			.fabricclk_mhz = 400.0,
112 			.dispclk_mhz = 2150.0,
113 			.dppclk_mhz = 2150.0,
114 			.phyclk_mhz = 810.0,
115 			.phyclk_d18_mhz = 667.0,
116 			.phyclk_d32_mhz = 625.0,
117 			.socclk_mhz = 1200.0,
118 			.dscclk_mhz = 716.667,
119 			.dram_speed_mts = 16000.0,
120 			.dtbclk_mhz = 1564.0,
121 		},
122 	},
123 	.num_states = 1,
124 	.sr_exit_time_us = 42.97,
125 	.sr_enter_plus_exit_time_us = 49.94,
126 	.sr_exit_z8_time_us = 285.0,
127 	.sr_enter_plus_exit_z8_time_us = 320,
128 	.writeback_latency_us = 12.0,
129 	.round_trip_ping_latency_dcfclk_cycles = 263,
130 	.urgent_latency_pixel_data_only_us = 4.0,
131 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
132 	.urgent_latency_vm_data_only_us = 4.0,
133 	.fclk_change_latency_us = 20,
134 	.usr_retraining_latency_us = 2,
135 	.smn_latency_us = 2,
136 	.mall_allocated_for_dcn_mbytes = 64,
137 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
138 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
139 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
140 	.pct_ideal_sdp_bw_after_urgent = 100.0,
141 	.pct_ideal_fabric_bw_after_urgent = 67.0,
142 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
143 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
144 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
145 	.pct_ideal_dram_bw_after_urgent_strobe = 67.0,
146 	.max_avg_sdp_bw_use_normal_percent = 80.0,
147 	.max_avg_fabric_bw_use_normal_percent = 60.0,
148 	.max_avg_dram_bw_use_normal_strobe_percent = 50.0,
149 	.max_avg_dram_bw_use_normal_percent = 15.0,
150 	.num_chans = 8,
151 	.dram_channel_width_bytes = 2,
152 	.fabric_datapath_to_dcn_data_return_bytes = 64,
153 	.return_bus_width_bytes = 64,
154 	.downspread_percent = 0.38,
155 	.dcn_downspread_percent = 0.5,
156 	.dram_clock_change_latency_us = 400,
157 	.dispclk_dppclk_vco_speed_mhz = 4300.0,
158 	.do_urgent_latency_adjustment = true,
159 	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
160 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
161 };
162 
dcn32_build_wm_range_table_fpu(struct clk_mgr_internal * clk_mgr)163 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
164 {
165 	/* defaults */
166 	double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
167 	double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
168 	double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
169 	double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
170 	/* For min clocks use as reported by PM FW and report those as min */
171 	uint16_t min_uclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
172 	uint16_t min_dcfclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
173 	uint16_t setb_min_uclk_mhz		= min_uclk_mhz;
174 	uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
175 
176 	dc_assert_fp_enabled();
177 
178 	/* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
179 	if (dcfclk_mhz_for_the_second_state)
180 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
181 	else
182 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
183 
184 	if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
185 		setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
186 
187 	/* Set A - Normal - default values */
188 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
189 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
190 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
191 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
192 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
193 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
194 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
195 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
196 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
197 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
198 
199 	/* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
200 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
201 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
202 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
203 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
204 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
205 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
206 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
207 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
208 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
209 
210 	/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
211 	/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
212 	if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
213 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
214 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;
215 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
216 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
217 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
218 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
219 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
220 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
221 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
222 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
223 		clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
224 		clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;
225 		clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
226 		clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
227 		clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
228 		clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
229 		clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
230 		clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
231 	}
232 	/* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
233 	/* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
234 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
235 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
236 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
237 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
238 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
239 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
240 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
241 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
242 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
243 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
244 }
245 
246 /*
247  * Finds dummy_latency_index when MCLK switching using firmware based
248  * vblank stretch is enabled. This function will iterate through the
249  * table of dummy pstate latencies until the lowest value that allows
250  * dm_allow_self_refresh_and_mclk_switch to happen is found
251  */
dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)252 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
253 							    struct dc_state *context,
254 							    display_e2e_pipe_params_st *pipes,
255 							    int pipe_cnt,
256 							    int vlevel)
257 {
258 	const int max_latency_table_entries = 4;
259 	const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
260 	int dummy_latency_index = 0;
261 
262 	dc_assert_fp_enabled();
263 
264 	while (dummy_latency_index < max_latency_table_entries) {
265 		context->bw_ctx.dml.soc.dram_clock_change_latency_us =
266 				dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
267 		dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
268 
269 		if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
270 				vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
271 			break;
272 
273 		dummy_latency_index++;
274 	}
275 
276 	if (dummy_latency_index == max_latency_table_entries) {
277 		ASSERT(dummy_latency_index != max_latency_table_entries);
278 		/* If the execution gets here, it means dummy p_states are
279 		 * not possible. This should never happen and would mean
280 		 * something is severely wrong.
281 		 * Here we reset dummy_latency_index to 3, because it is
282 		 * better to have underflows than system crashes.
283 		 */
284 		dummy_latency_index = max_latency_table_entries - 1;
285 	}
286 
287 	return dummy_latency_index;
288 }
289 
290 /**
291  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
292  * and populate pipe_ctx with those params.
293  * @dc: [in] current dc state
294  * @context: [in] new dc state
295  * @pipes: [in] DML pipe params array
296  * @pipe_cnt: [in] DML pipe count
297  *
298  * This function must be called AFTER the phantom pipes are added to context
299  * and run through DML (so that the DLG params for the phantom pipes can be
300  * populated), and BEFORE we program the timing for the phantom pipes.
301  */
dcn32_helper_populate_phantom_dlg_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)302 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
303 					      struct dc_state *context,
304 					      display_e2e_pipe_params_st *pipes,
305 					      int pipe_cnt)
306 {
307 	uint32_t i, pipe_idx;
308 
309 	dc_assert_fp_enabled();
310 
311 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
312 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
313 
314 		if (!pipe->stream)
315 			continue;
316 
317 		if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
318 			pipes[pipe_idx].pipe.dest.vstartup_start =
319 				get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
320 			pipes[pipe_idx].pipe.dest.vupdate_offset =
321 				get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
322 			pipes[pipe_idx].pipe.dest.vupdate_width =
323 				get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
324 			pipes[pipe_idx].pipe.dest.vready_offset =
325 				get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
326 			pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
327 		}
328 		pipe_idx++;
329 	}
330 }
331 
332 /**
333  * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe
334  * @context: [in] New DC state to be programmed
335  * @pipe_e2e: [in] DML pipe end to end context
336  *
337  * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both
338  * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is
339  * determined by DPPClk requirements
340  *
341  * This function follows the same policy as DML:
342  * - Check for ODM combine requirements / policy first
343  * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and
344  *   MPC is required
345  *
346  * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits).
347  */
dcn32_predict_pipe_split(struct dc_state * context,display_e2e_pipe_params_st * pipe_e2e)348 uint8_t dcn32_predict_pipe_split(struct dc_state *context,
349 				  display_e2e_pipe_params_st *pipe_e2e)
350 {
351 	double pscl_throughput;
352 	double pscl_throughput_chroma;
353 	double dpp_clk_single_dpp, clock;
354 	double clk_frequency = 0.0;
355 	double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;
356 	bool total_available_pipes_support = false;
357 	uint32_t number_of_dpp = 0;
358 	enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled;
359 	double req_dispclk_per_surface = 0;
360 	uint8_t num_splits = 0;
361 
362 	dc_assert_fp_enabled();
363 
364 	dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit,
365 			pipe_e2e->pipe.dest.hactive,
366 			pipe_e2e->dout.output_format,
367 			pipe_e2e->dout.output_type,
368 			pipe_e2e->pipe.dest.odm_combine_policy,
369 			context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,
370 			context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz,
371 			pipe_e2e->dout.dsc_enable != 0,
372 			0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */
373 			context->bw_ctx.dml.ip.max_num_dpp,
374 			pipe_e2e->pipe.dest.pixel_rate_mhz,
375 			context->bw_ctx.dml.soc.dcn_downspread_percent,
376 			context->bw_ctx.dml.ip.dispclk_ramp_margin_percent,
377 			context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz,
378 			pipe_e2e->dout.dsc_slices,
379 			/* Output */
380 			&total_available_pipes_support,
381 			&number_of_dpp,
382 			&odm_mode,
383 			&req_dispclk_per_surface);
384 
385 	dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio,
386 			pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c,
387 			pipe_e2e->pipe.scale_ratio_depth.vscl_ratio,
388 			pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c,
389 			context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,
390 			context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,
391 			pipe_e2e->pipe.dest.pixel_rate_mhz,
392 			pipe_e2e->pipe.src.source_format,
393 			pipe_e2e->pipe.scale_taps.htaps,
394 			pipe_e2e->pipe.scale_taps.htaps_c,
395 			pipe_e2e->pipe.scale_taps.vtaps,
396 			pipe_e2e->pipe.scale_taps.vtaps_c,
397 			/* Output */
398 			&pscl_throughput, &pscl_throughput_chroma,
399 			&dpp_clk_single_dpp);
400 
401 	clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100);
402 
403 	if (clock > 0)
404 		clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock);
405 
406 	if (odm_mode == dm_odm_combine_mode_2to1)
407 		num_splits = 1;
408 	else if (odm_mode == dm_odm_combine_mode_4to1)
409 		num_splits = 3;
410 	else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz)
411 		num_splits = 1;
412 
413 	return num_splits;
414 }
415 
calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st * entry)416 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
417 {
418 	float memory_bw_kbytes_sec;
419 	float fabric_bw_kbytes_sec;
420 	float sdp_bw_kbytes_sec;
421 	float limiting_bw_kbytes_sec;
422 
423 	memory_bw_kbytes_sec = entry->dram_speed_mts *
424 				dcn3_2_soc.num_chans *
425 				dcn3_2_soc.dram_channel_width_bytes *
426 				((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
427 
428 	fabric_bw_kbytes_sec = entry->fabricclk_mhz *
429 				dcn3_2_soc.return_bus_width_bytes *
430 				((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
431 
432 	sdp_bw_kbytes_sec = entry->dcfclk_mhz *
433 				dcn3_2_soc.return_bus_width_bytes *
434 				((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
435 
436 	limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
437 
438 	if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
439 		limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
440 
441 	if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
442 		limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
443 
444 	return limiting_bw_kbytes_sec;
445 }
446 
get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st * entry)447 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
448 {
449 	if (entry->dcfclk_mhz > 0) {
450 		float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
451 
452 		entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
453 		entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
454 				dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
455 	} else if (entry->fabricclk_mhz > 0) {
456 		float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
457 
458 		entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
459 		entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
460 				dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
461 	} else if (entry->dram_speed_mts > 0) {
462 		float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
463 				dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
464 
465 		entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
466 		entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
467 	}
468 }
469 
insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st * table,unsigned int * num_entries,struct _vcs_dpi_voltage_scaling_st * entry)470 void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
471 				    unsigned int *num_entries,
472 				    struct _vcs_dpi_voltage_scaling_st *entry)
473 {
474 	int i = 0;
475 	int index = 0;
476 	float net_bw_of_new_state = 0;
477 
478 	dc_assert_fp_enabled();
479 
480 	get_optimal_ntuple(entry);
481 
482 	if (*num_entries == 0) {
483 		table[0] = *entry;
484 		(*num_entries)++;
485 	} else {
486 		net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry);
487 		while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) {
488 			index++;
489 			if (index >= *num_entries)
490 				break;
491 		}
492 
493 		for (i = *num_entries; i > index; i--)
494 			table[i] = table[i - 1];
495 
496 		table[index] = *entry;
497 		(*num_entries)++;
498 	}
499 }
500 
501 /**
502  * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream
503  * @dc: current dc state
504  * @context: new dc state
505  * @ref_pipe: Main pipe for the phantom stream
506  * @phantom_stream: target phantom stream state
507  * @pipes: DML pipe params
508  * @pipe_cnt: number of DML pipes
509  * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
510  *
511  * Set timing params of the phantom stream based on calculated output from DML.
512  * This function first gets the DML pipe index using the DC pipe index, then
513  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
514  * lines required for SubVP MCLK switching and assigns to the phantom stream
515  * accordingly.
516  *
517  * - The number of SubVP lines calculated in DML does not take into account
518  * FW processing delays and required pstate allow width, so we must include
519  * that separately.
520  *
521  * - Set phantom backporch = vstartup of main pipe
522  */
dcn32_set_phantom_stream_timing(struct dc * dc,struct dc_state * context,struct pipe_ctx * ref_pipe,struct dc_stream_state * phantom_stream,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int dc_pipe_idx)523 void dcn32_set_phantom_stream_timing(struct dc *dc,
524 				     struct dc_state *context,
525 				     struct pipe_ctx *ref_pipe,
526 				     struct dc_stream_state *phantom_stream,
527 				     display_e2e_pipe_params_st *pipes,
528 				     unsigned int pipe_cnt,
529 				     unsigned int dc_pipe_idx)
530 {
531 	unsigned int i, pipe_idx;
532 	struct pipe_ctx *pipe;
533 	uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
534 	unsigned int num_dpp;
535 	unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
536 	unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
537 	unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
538 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
539 
540 	dc_assert_fp_enabled();
541 
542 	// Find DML pipe index (pipe_idx) using dc_pipe_idx
543 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
544 		pipe = &context->res_ctx.pipe_ctx[i];
545 
546 		if (!pipe->stream)
547 			continue;
548 
549 		if (i == dc_pipe_idx)
550 			break;
551 
552 		pipe_idx++;
553 	}
554 
555 	// Calculate lines required for pstate allow width and FW processing delays
556 	pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
557 			dc->caps.subvp_pstate_allow_width_us) / 1000000) *
558 			(ref_pipe->stream->timing.pix_clk_100hz * 100) /
559 			(double)ref_pipe->stream->timing.h_total;
560 
561 	// Update clks_cfg for calling into recalculate
562 	pipes[0].clks_cfg.voltage = vlevel;
563 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
564 	pipes[0].clks_cfg.socclk_mhz = socclk;
565 
566 	// DML calculation for MALL region doesn't take into account FW delay
567 	// and required pstate allow width for multi-display cases
568 	/* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned
569 	 * to 2 swaths (i.e. 16 lines)
570 	 */
571 	phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
572 				pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines;
573 
574 	// W/A for DCC corruption with certain high resolution timings.
575 	// Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive.
576 	num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]];
577 	phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0;
578 
579 	// For backporch of phantom pipe, use vstartup of the main pipe
580 	phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
581 
582 	phantom_stream->dst.y = 0;
583 	phantom_stream->dst.height = phantom_vactive;
584 	phantom_stream->src.y = 0;
585 	phantom_stream->src.height = phantom_vactive;
586 
587 	phantom_stream->timing.v_addressable = phantom_vactive;
588 	phantom_stream->timing.v_front_porch = 1;
589 	phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
590 						phantom_stream->timing.v_front_porch +
591 						phantom_stream->timing.v_sync_width +
592 						phantom_bp;
593 	phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
594 }
595 
596 /**
597  * dcn32_get_num_free_pipes - Calculate number of free pipes
598  * @dc: current dc state
599  * @context: new dc state
600  *
601  * This function assumes that a "used" pipe is a pipe that has
602  * both a stream and a plane assigned to it.
603  *
604  * Return: Number of free pipes available in the context
605  */
dcn32_get_num_free_pipes(struct dc * dc,struct dc_state * context)606 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
607 {
608 	unsigned int i;
609 	unsigned int free_pipes = 0;
610 	unsigned int num_pipes = 0;
611 
612 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
613 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
614 
615 		if (pipe->stream && !pipe->top_pipe) {
616 			while (pipe) {
617 				num_pipes++;
618 				pipe = pipe->bottom_pipe;
619 			}
620 		}
621 	}
622 
623 	free_pipes = dc->res_pool->pipe_count - num_pipes;
624 	return free_pipes;
625 }
626 
627 /**
628  * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP.
629  * @dc: current dc state
630  * @context: new dc state
631  * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
632  *
633  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
634  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
635  * we are forcing SubVP P-State switching on the current config.
636  *
637  * The number of pipes used for the chosen surface must be less than or equal to the
638  * number of free pipes available.
639  *
640  * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK).
641  * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own
642  * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't
643  * support MCLK switching naturally [i.e. ACTIVE or VBLANK]).
644  *
645  * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
646  */
dcn32_assign_subvp_pipe(struct dc * dc,struct dc_state * context,unsigned int * index)647 static bool dcn32_assign_subvp_pipe(struct dc *dc,
648 				    struct dc_state *context,
649 				    unsigned int *index)
650 {
651 	unsigned int i, pipe_idx;
652 	unsigned int max_frame_time = 0;
653 	bool valid_assignment_found = false;
654 	unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
655 	bool current_assignment_freesync = false;
656 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
657 
658 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
659 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
660 		unsigned int num_pipes = 0;
661 		unsigned int refresh_rate = 0;
662 
663 		if (!pipe->stream)
664 			continue;
665 
666 		// Round up
667 		refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
668 				pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
669 				/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
670 		/* SubVP pipe candidate requirements:
671 		 * - Refresh rate < 120hz
672 		 * - Not able to switch in vactive naturally (switching in active means the
673 		 *   DET provides enough buffer to hide the P-State switch latency -- trying
674 		 *   to combine this with SubVP can cause issues with the scheduling).
675 		 * - Not TMZ surface
676 		 */
677 		if (pipe->plane_state && !pipe->top_pipe &&
678 				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&
679 				vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
680 			while (pipe) {
681 				num_pipes++;
682 				pipe = pipe->bottom_pipe;
683 			}
684 
685 			pipe = &context->res_ctx.pipe_ctx[i];
686 			if (num_pipes <= free_pipes) {
687 				struct dc_stream_state *stream = pipe->stream;
688 				unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
689 						(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
690 				if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
691 					*index = i;
692 					max_frame_time = frame_us;
693 					valid_assignment_found = true;
694 					current_assignment_freesync = false;
695 				/* For the 2-Freesync display case, still choose the one with the
696 			     * longest frame time
697 			     */
698 				} else if (stream->ignore_msa_timing_param && (!valid_assignment_found ||
699 						(current_assignment_freesync && frame_us > max_frame_time))) {
700 					*index = i;
701 					valid_assignment_found = true;
702 					current_assignment_freesync = true;
703 				}
704 			}
705 		}
706 		pipe_idx++;
707 	}
708 	return valid_assignment_found;
709 }
710 
711 /**
712  * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP.
713  * @dc: current dc state
714  * @context: new dc state
715  *
716  * This function returns true if there are enough free pipes
717  * to create the required phantom pipes for any given stream
718  * (that does not already have phantom pipe assigned).
719  *
720  * e.g. For a 2 stream config where the first stream uses one
721  * pipe and the second stream uses 2 pipes (i.e. pipe split),
722  * this function will return true because there is 1 remaining
723  * pipe which can be used as the phantom pipe for the non pipe
724  * split pipe.
725  *
726  * Return:
727  * True if there are enough free pipes to assign phantom pipes to at least one
728  * stream that does not already have phantom pipes assigned. Otherwise false.
729  */
dcn32_enough_pipes_for_subvp(struct dc * dc,struct dc_state * context)730 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
731 {
732 	unsigned int i, split_cnt, free_pipes;
733 	unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
734 	bool subvp_possible = false;
735 
736 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
737 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
738 
739 		// Find the minimum pipe split count for non SubVP pipes
740 		if (pipe->stream && !pipe->top_pipe &&
741 		    pipe->stream->mall_stream_config.type == SUBVP_NONE) {
742 			split_cnt = 0;
743 			while (pipe) {
744 				split_cnt++;
745 				pipe = pipe->bottom_pipe;
746 			}
747 
748 			if (split_cnt < min_pipe_split)
749 				min_pipe_split = split_cnt;
750 		}
751 	}
752 
753 	free_pipes = dcn32_get_num_free_pipes(dc, context);
754 
755 	// SubVP only possible if at least one pipe is being used (i.e. free_pipes
756 	// should not equal to the pipe_count)
757 	if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
758 		subvp_possible = true;
759 
760 	return subvp_possible;
761 }
762 
763 /**
764  * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable
765  * @dc: current dc state
766  * @context: new dc state
767  *
768  * High level algorithm:
769  * 1. Find longest microschedule length (in us) between the two SubVP pipes
770  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
771  * pipes still allows for the maximum microschedule to fit in the active
772  * region for both pipes.
773  *
774  * Return: True if the SubVP + SubVP config is schedulable, false otherwise
775  */
subvp_subvp_schedulable(struct dc * dc,struct dc_state * context)776 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
777 {
778 	struct pipe_ctx *subvp_pipes[2];
779 	struct dc_stream_state *phantom = NULL;
780 	uint32_t microschedule_lines = 0;
781 	uint32_t index = 0;
782 	uint32_t i;
783 	uint32_t max_microschedule_us = 0;
784 	int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
785 
786 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
787 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
788 		uint32_t time_us = 0;
789 
790 		/* Loop to calculate the maximum microschedule time between the two SubVP pipes,
791 		 * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
792 		 */
793 		if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
794 		    pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
795 			phantom = pipe->stream->mall_stream_config.paired_stream;
796 			microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
797 					phantom->timing.v_addressable;
798 
799 			// Round up when calculating microschedule time (+ 1 at the end)
800 			time_us = (microschedule_lines * phantom->timing.h_total) /
801 					(double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
802 						dc->caps.subvp_prefetch_end_to_mall_start_us +
803 						dc->caps.subvp_fw_processing_delay_us + 1;
804 			if (time_us > max_microschedule_us)
805 				max_microschedule_us = time_us;
806 
807 			subvp_pipes[index] = pipe;
808 			index++;
809 
810 			// Maximum 2 SubVP pipes
811 			if (index == 2)
812 				break;
813 		}
814 	}
815 	vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
816 			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
817 	vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
818 				(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
819 	vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
820 			subvp_pipes[0]->stream->timing.h_total) /
821 			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
822 	vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
823 			subvp_pipes[1]->stream->timing.h_total) /
824 			(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
825 
826 	if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
827 	    (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
828 		return true;
829 
830 	return false;
831 }
832 
833 /**
834  * subvp_drr_schedulable - Determine if SubVP + DRR config is schedulable
835  * @dc: current dc state
836  * @context: new dc state
837  * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config
838  *
839  * High level algorithm:
840  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
841  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
842  * (the margin is equal to the MALL region + DRR margin (500us))
843  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
844  * then report the configuration as supported
845  *
846  * Return: True if the SubVP + DRR config is schedulable, false otherwise
847  */
subvp_drr_schedulable(struct dc * dc,struct dc_state * context,struct pipe_ctx * drr_pipe)848 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
849 {
850 	bool schedulable = false;
851 	uint32_t i;
852 	struct pipe_ctx *pipe = NULL;
853 	struct dc_crtc_timing *main_timing = NULL;
854 	struct dc_crtc_timing *phantom_timing = NULL;
855 	struct dc_crtc_timing *drr_timing = NULL;
856 	int16_t prefetch_us = 0;
857 	int16_t mall_region_us = 0;
858 	int16_t drr_frame_us = 0;	// nominal frame time
859 	int16_t subvp_active_us = 0;
860 	int16_t stretched_drr_us = 0;
861 	int16_t drr_stretched_vblank_us = 0;
862 	int16_t max_vblank_mallregion = 0;
863 
864 	// Find SubVP pipe
865 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
866 		pipe = &context->res_ctx.pipe_ctx[i];
867 
868 		// We check for master pipe, but it shouldn't matter since we only need
869 		// the pipe for timing info (stream should be same for any pipe splits)
870 		if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
871 			continue;
872 
873 		// Find the SubVP pipe
874 		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
875 			break;
876 	}
877 
878 	main_timing = &pipe->stream->timing;
879 	phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
880 	drr_timing = &drr_pipe->stream->timing;
881 	prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
882 			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
883 			dc->caps.subvp_prefetch_end_to_mall_start_us;
884 	subvp_active_us = main_timing->v_addressable * main_timing->h_total /
885 			(double)(main_timing->pix_clk_100hz * 100) * 1000000;
886 	drr_frame_us = drr_timing->v_total * drr_timing->h_total /
887 			(double)(drr_timing->pix_clk_100hz * 100) * 1000000;
888 	// P-State allow width and FW delays already included phantom_timing->v_addressable
889 	mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
890 			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
891 	stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
892 	drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
893 			(double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
894 	max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
895 
896 	/* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
897 	 * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
898 	 * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
899 	 * and the max of (VBLANK blanking time, MALL region)).
900 	 */
901 	if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
902 			subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
903 		schedulable = true;
904 
905 	return schedulable;
906 }
907 
908 
909 /**
910  * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable
911  * @dc: current dc state
912  * @context: new dc state
913  *
914  * High level algorithm:
915  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
916  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
917  * then report the configuration as supported
918  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
919  *
920  * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
921  */
subvp_vblank_schedulable(struct dc * dc,struct dc_state * context)922 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
923 {
924 	struct pipe_ctx *pipe = NULL;
925 	struct pipe_ctx *subvp_pipe = NULL;
926 	bool found = false;
927 	bool schedulable = false;
928 	uint32_t i = 0;
929 	uint8_t vblank_index = 0;
930 	uint16_t prefetch_us = 0;
931 	uint16_t mall_region_us = 0;
932 	uint16_t vblank_frame_us = 0;
933 	uint16_t subvp_active_us = 0;
934 	uint16_t vblank_blank_us = 0;
935 	uint16_t max_vblank_mallregion = 0;
936 	struct dc_crtc_timing *main_timing = NULL;
937 	struct dc_crtc_timing *phantom_timing = NULL;
938 	struct dc_crtc_timing *vblank_timing = NULL;
939 
940 	/* For SubVP + VBLANK/DRR cases, we assume there can only be
941 	 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
942 	 * is supported, it is either a single VBLANK case or two VBLANK
943 	 * displays which are synchronized (in which case they have identical
944 	 * timings).
945 	 */
946 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
947 		pipe = &context->res_ctx.pipe_ctx[i];
948 
949 		// We check for master pipe, but it shouldn't matter since we only need
950 		// the pipe for timing info (stream should be same for any pipe splits)
951 		if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
952 			continue;
953 
954 		if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
955 			// Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
956 			vblank_index = i;
957 			found = true;
958 		}
959 
960 		if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
961 			subvp_pipe = pipe;
962 	}
963 	// Use ignore_msa_timing_param flag to identify as DRR
964 	if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {
965 		// SUBVP + DRR case
966 		schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
967 	} else if (found) {
968 		main_timing = &subvp_pipe->stream->timing;
969 		phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
970 		vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
971 		// Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
972 		// Also include the prefetch end to mallstart delay time
973 		prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
974 				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
975 				dc->caps.subvp_prefetch_end_to_mall_start_us;
976 		// P-State allow width and FW delays already included phantom_timing->v_addressable
977 		mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
978 				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
979 		vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
980 				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
981 		vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
982 				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
983 		subvp_active_us = main_timing->v_addressable * main_timing->h_total /
984 				(double)(main_timing->pix_clk_100hz * 100) * 1000000;
985 		max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
986 
987 		// Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
988 		// and the max of (VBLANK blanking time, MALL region)
989 		// TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
990 		if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
991 			schedulable = true;
992 	}
993 	return schedulable;
994 }
995 
996 /**
997  * subvp_validate_static_schedulability - Check which SubVP case is calculated
998  * and handle static analysis based on the case.
999  * @dc: current dc state
1000  * @context: new dc state
1001  * @vlevel: Voltage level calculated by DML
1002  *
1003  * Three cases:
1004  * 1. SubVP + SubVP
1005  * 2. SubVP + VBLANK (DRR checked internally)
1006  * 3. SubVP + VACTIVE (currently unsupported)
1007  *
1008  * Return: True if statically schedulable, false otherwise
1009  */
subvp_validate_static_schedulability(struct dc * dc,struct dc_state * context,int vlevel)1010 static bool subvp_validate_static_schedulability(struct dc *dc,
1011 				struct dc_state *context,
1012 				int vlevel)
1013 {
1014 	bool schedulable = true;	// true by default for single display case
1015 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1016 	uint32_t i, pipe_idx;
1017 	uint8_t subvp_count = 0;
1018 	uint8_t vactive_count = 0;
1019 
1020 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1021 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1022 
1023 		if (!pipe->stream)
1024 			continue;
1025 
1026 		if (pipe->plane_state && !pipe->top_pipe &&
1027 				pipe->stream->mall_stream_config.type == SUBVP_MAIN)
1028 			subvp_count++;
1029 
1030 		// Count how many planes that aren't SubVP/phantom are capable of VACTIVE
1031 		// switching (SubVP + VACTIVE unsupported). In situations where we force
1032 		// SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
1033 		if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
1034 		    pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1035 			vactive_count++;
1036 		}
1037 		pipe_idx++;
1038 	}
1039 
1040 	if (subvp_count == 2) {
1041 		// Static schedulability check for SubVP + SubVP case
1042 		schedulable = subvp_subvp_schedulable(dc, context);
1043 	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
1044 		// Static schedulability check for SubVP + VBLANK case. Also handle the case where
1045 		// DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
1046 		if (vactive_count > 0)
1047 			schedulable = false;
1048 		else
1049 			schedulable = subvp_vblank_schedulable(dc, context);
1050 	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
1051 			vactive_count > 0) {
1052 		// For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default.
1053 		// We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count.
1054 		// SubVP + VACTIVE currently unsupported
1055 		schedulable = false;
1056 	}
1057 	return schedulable;
1058 }
1059 
dcn32_full_validate_bw_helper(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * vlevel,int * split,bool * merge,int * pipe_cnt)1060 static void dcn32_full_validate_bw_helper(struct dc *dc,
1061 				   struct dc_state *context,
1062 				   display_e2e_pipe_params_st *pipes,
1063 				   int *vlevel,
1064 				   int *split,
1065 				   bool *merge,
1066 				   int *pipe_cnt)
1067 {
1068 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1069 	unsigned int dc_pipe_idx = 0;
1070 	bool found_supported_config = false;
1071 	struct pipe_ctx *pipe = NULL;
1072 	uint32_t non_subvp_pipes = 0;
1073 	bool drr_pipe_found = false;
1074 	uint32_t drr_pipe_index = 0;
1075 	uint32_t i = 0;
1076 
1077 	dc_assert_fp_enabled();
1078 
1079 	/*
1080 	 * DML favors voltage over p-state, but we're more interested in
1081 	 * supporting p-state over voltage. We can't support p-state in
1082 	 * prefetch mode > 0 so try capping the prefetch mode to start.
1083 	 * Override present for testing.
1084 	 */
1085 	if (dc->debug.dml_disallow_alternate_prefetch_modes)
1086 		context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1087 			dm_prefetch_support_uclk_fclk_and_stutter;
1088 	else
1089 		context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1090 			dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
1091 
1092 	*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1093 	/* This may adjust vlevel and maxMpcComb */
1094 	if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1095 		*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1096 		vba->VoltageLevel = *vlevel;
1097 	}
1098 
1099 	/* Conditions for setting up phantom pipes for SubVP:
1100 	 * 1. Not force disable SubVP
1101 	 * 2. Full update (i.e. !fast_validate)
1102 	 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
1103 	 * 4. Display configuration passes validation
1104 	 * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
1105 	 */
1106 	if (!dc->debug.force_disable_subvp && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
1107 	    !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) &&
1108 		(*vlevel == context->bw_ctx.dml.soc.num_states ||
1109 	    vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
1110 	    dc->debug.force_subvp_mclk_switch)) {
1111 
1112 		dcn32_merge_pipes_for_subvp(dc, context);
1113 		memset(merge, 0, MAX_PIPES * sizeof(bool));
1114 
1115 		/* to re-initialize viewport after the pipe merge */
1116 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
1117 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1118 
1119 			if (!pipe_ctx->plane_state || !pipe_ctx->stream)
1120 				continue;
1121 
1122 			resource_build_scaling_params(pipe_ctx);
1123 		}
1124 
1125 		while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
1126 			dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
1127 			/* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
1128 			 * Adding phantom pipes won't change the validation result, so change the DML input param
1129 			 * for P-State support before adding phantom pipes and recalculating the DML result.
1130 			 * However, this case is only applicable for SubVP + DRR cases because the prefetch mode
1131 			 * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched
1132 			 * enough to support MCLK switching.
1133 			 */
1134 			if (*vlevel == context->bw_ctx.dml.soc.num_states &&
1135 				context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final ==
1136 					dm_prefetch_support_uclk_fclk_and_stutter) {
1137 				context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1138 								dm_prefetch_support_stutter;
1139 				/* There are params (such as FabricClock) that need to be recalculated
1140 				 * after validation fails (otherwise it will be 0). Calculation for
1141 				 * phantom vactive requires call into DML, so we must ensure all the
1142 				 * vba params are valid otherwise we'll get incorrect phantom vactive.
1143 				 */
1144 				*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1145 			}
1146 
1147 			dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1148 
1149 			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1150 			// Populate dppclk to trigger a recalculate in dml_get_voltage_level
1151 			// so the phantom pipe DLG params can be assigned correctly.
1152 			pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
1153 			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1154 
1155 			if (*vlevel < context->bw_ctx.dml.soc.num_states &&
1156 			    vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
1157 			    && subvp_validate_static_schedulability(dc, context, *vlevel)) {
1158 				found_supported_config = true;
1159 			} else if (*vlevel < context->bw_ctx.dml.soc.num_states &&
1160 					vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1161 				/* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles
1162 				 * the case for SubVP + DRR, where the DRR display does not support MCLK switch
1163 				 * at it's native refresh rate / timing.
1164 				 */
1165 				for (i = 0; i < dc->res_pool->pipe_count; i++) {
1166 					pipe = &context->res_ctx.pipe_ctx[i];
1167 					if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
1168 					    pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1169 						non_subvp_pipes++;
1170 						// Use ignore_msa_timing_param flag to identify as DRR
1171 						if (pipe->stream->ignore_msa_timing_param) {
1172 							drr_pipe_found = true;
1173 							drr_pipe_index = i;
1174 						}
1175 					}
1176 				}
1177 				// If there is only 1 remaining non SubVP pipe that is DRR, check static
1178 				// schedulability for SubVP + DRR.
1179 				if (non_subvp_pipes == 1 && drr_pipe_found) {
1180 					found_supported_config = subvp_drr_schedulable(dc, context,
1181 										       &context->res_ctx.pipe_ctx[drr_pipe_index]);
1182 				}
1183 			}
1184 		}
1185 
1186 		// If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
1187 		// remove phantom pipes and repopulate dml pipes
1188 		if (!found_supported_config) {
1189 			dc->res_pool->funcs->remove_phantom_pipes(dc, context);
1190 			vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1191 			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1192 
1193 			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1194 			/* This may adjust vlevel and maxMpcComb */
1195 			if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1196 				*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1197 				vba->VoltageLevel = *vlevel;
1198 			}
1199 		} else {
1200 			// Most populate phantom DLG params before programming hardware / timing for phantom pipe
1201 			DC_FP_START();
1202 			dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
1203 			DC_FP_END();
1204 
1205 			/* Call validate_apply_pipe_split flags after calling DML getters for
1206 			 * phantom dlg params, or some of the VBA params indicating pipe split
1207 			 * can be overwritten by the getters.
1208 			 *
1209 			 * When setting up SubVP config, all pipes are merged before attempting to
1210 			 * add phantom pipes. If pipe split (ODM / MPC) is required, both the main
1211 			 * and phantom pipes will be split in the regular pipe splitting sequence.
1212 			 */
1213 			memset(split, 0, MAX_PIPES * sizeof(int));
1214 			memset(merge, 0, MAX_PIPES * sizeof(bool));
1215 			*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1216 			vba->VoltageLevel = *vlevel;
1217 			// Note: We can't apply the phantom pipes to hardware at this time. We have to wait
1218 			// until driver has acquired the DMCUB lock to do it safely.
1219 		}
1220 	}
1221 }
1222 
is_dtbclk_required(struct dc * dc,struct dc_state * context)1223 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
1224 {
1225 	int i;
1226 
1227 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1228 		if (!context->res_ctx.pipe_ctx[i].stream)
1229 			continue;
1230 		if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
1231 			return true;
1232 	}
1233 	return false;
1234 }
1235 
dcn32_calculate_dlg_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1236 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
1237 				       display_e2e_pipe_params_st *pipes,
1238 				       int pipe_cnt, int vlevel)
1239 {
1240 	int i, pipe_idx;
1241 	bool usr_retraining_support = false;
1242 	bool unbounded_req_enabled = false;
1243 
1244 	dc_assert_fp_enabled();
1245 
1246 	/* Writeback MCIF_WB arbitration parameters */
1247 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1248 
1249 	context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1250 	context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1251 	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1252 	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1253 	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1254 	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1255 	context->bw_ctx.bw.dcn.clk.p_state_change_support =
1256 			context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1257 					!= dm_dram_clock_change_unsupported;
1258 	context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);
1259 
1260 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1261 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1262 	context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
1263 	if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
1264 		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
1265 	else
1266 		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1267 
1268 	usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1269 	ASSERT(usr_retraining_support);
1270 
1271 	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1272 		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1273 
1274 	unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
1275 
1276 	if (unbounded_req_enabled && pipe_cnt > 1) {
1277 		// Unbounded requesting should not ever be used when more than 1 pipe is enabled.
1278 		ASSERT(false);
1279 		unbounded_req_enabled = false;
1280 	}
1281 
1282 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1283 		if (!context->res_ctx.pipe_ctx[i].stream)
1284 			continue;
1285 		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
1286 				pipe_idx);
1287 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1288 				pipe_idx);
1289 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
1290 				pipe_idx);
1291 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1292 				pipe_idx);
1293 
1294 		if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1295 			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1296 			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1297 			context->res_ctx.pipe_ctx[i].unbounded_req = false;
1298 		} else {
1299 			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,
1300 							pipe_idx);
1301 			context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;
1302 		}
1303 
1304 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1305 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1306 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1307 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1308 		pipe_idx++;
1309 	}
1310 	/*save a original dppclock copy*/
1311 	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1312 	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1313 	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
1314 			* 1000;
1315 	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
1316 			* 1000;
1317 
1318 	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes;
1319 
1320 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1321 		if (context->res_ctx.pipe_ctx[i].stream)
1322 			context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;
1323 	}
1324 
1325 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1326 
1327 		if (!context->res_ctx.pipe_ctx[i].stream)
1328 			continue;
1329 
1330 		context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
1331 				&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
1332 				pipe_cnt, pipe_idx);
1333 
1334 		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
1335 				&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1336 		pipe_idx++;
1337 	}
1338 }
1339 
dcn32_find_split_pipe(struct dc * dc,struct dc_state * context,int old_index)1340 static struct pipe_ctx *dcn32_find_split_pipe(
1341 		struct dc *dc,
1342 		struct dc_state *context,
1343 		int old_index)
1344 {
1345 	struct pipe_ctx *pipe = NULL;
1346 	int i;
1347 
1348 	if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1349 		pipe = &context->res_ctx.pipe_ctx[old_index];
1350 		pipe->pipe_idx = old_index;
1351 	}
1352 
1353 	if (!pipe)
1354 		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1355 			if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1356 					&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1357 				if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1358 					pipe = &context->res_ctx.pipe_ctx[i];
1359 					pipe->pipe_idx = i;
1360 					break;
1361 				}
1362 			}
1363 		}
1364 
1365 	/*
1366 	 * May need to fix pipes getting tossed from 1 opp to another on flip
1367 	 * Add for debugging transient underflow during topology updates:
1368 	 * ASSERT(pipe);
1369 	 */
1370 	if (!pipe)
1371 		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1372 			if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1373 				pipe = &context->res_ctx.pipe_ctx[i];
1374 				pipe->pipe_idx = i;
1375 				break;
1376 			}
1377 		}
1378 
1379 	return pipe;
1380 }
1381 
dcn32_split_stream_for_mpc_or_odm(const struct dc * dc,struct resource_context * res_ctx,struct pipe_ctx * pri_pipe,struct pipe_ctx * sec_pipe,bool odm)1382 static bool dcn32_split_stream_for_mpc_or_odm(
1383 		const struct dc *dc,
1384 		struct resource_context *res_ctx,
1385 		struct pipe_ctx *pri_pipe,
1386 		struct pipe_ctx *sec_pipe,
1387 		bool odm)
1388 {
1389 	int pipe_idx = sec_pipe->pipe_idx;
1390 	const struct resource_pool *pool = dc->res_pool;
1391 
1392 	DC_LOGGER_INIT(dc->ctx->logger);
1393 
1394 	if (odm && pri_pipe->plane_state) {
1395 		/* ODM + window MPO, where MPO window is on left half only */
1396 		if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
1397 				pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) {
1398 
1399 			DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n",
1400 					__func__,
1401 					pri_pipe->pipe_idx);
1402 			return true;
1403 		}
1404 
1405 		/* ODM + window MPO, where MPO window is on right half only */
1406 		if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x +  pri_pipe->stream->src.width/2) {
1407 
1408 			DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n",
1409 					__func__,
1410 					pri_pipe->pipe_idx);
1411 			return true;
1412 		}
1413 	}
1414 
1415 	*sec_pipe = *pri_pipe;
1416 
1417 	sec_pipe->pipe_idx = pipe_idx;
1418 	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1419 	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1420 	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1421 	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1422 	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1423 	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1424 	sec_pipe->stream_res.dsc = NULL;
1425 	if (odm) {
1426 		if (pri_pipe->next_odm_pipe) {
1427 			ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1428 			sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1429 			sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1430 		}
1431 		if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1432 			pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1433 			sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1434 		}
1435 		if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1436 			pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1437 			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1438 		}
1439 		pri_pipe->next_odm_pipe = sec_pipe;
1440 		sec_pipe->prev_odm_pipe = pri_pipe;
1441 		ASSERT(sec_pipe->top_pipe == NULL);
1442 
1443 		if (!sec_pipe->top_pipe)
1444 			sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1445 		else
1446 			sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1447 		if (sec_pipe->stream->timing.flags.DSC == 1) {
1448 			dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1449 			ASSERT(sec_pipe->stream_res.dsc);
1450 			if (sec_pipe->stream_res.dsc == NULL)
1451 				return false;
1452 		}
1453 	} else {
1454 		if (pri_pipe->bottom_pipe) {
1455 			ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1456 			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1457 			sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1458 		}
1459 		pri_pipe->bottom_pipe = sec_pipe;
1460 		sec_pipe->top_pipe = pri_pipe;
1461 
1462 		ASSERT(pri_pipe->plane_state);
1463 	}
1464 
1465 	return true;
1466 }
1467 
dcn32_internal_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * vlevel_out,bool fast_validate)1468 bool dcn32_internal_validate_bw(struct dc *dc,
1469 				struct dc_state *context,
1470 				display_e2e_pipe_params_st *pipes,
1471 				int *pipe_cnt_out,
1472 				int *vlevel_out,
1473 				bool fast_validate)
1474 {
1475 	bool out = false;
1476 	bool repopulate_pipes = false;
1477 	int split[MAX_PIPES] = { 0 };
1478 	bool merge[MAX_PIPES] = { false };
1479 	bool newly_split[MAX_PIPES] = { false };
1480 	int pipe_cnt, i, pipe_idx;
1481 	int vlevel = context->bw_ctx.dml.soc.num_states;
1482 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1483 
1484 	dc_assert_fp_enabled();
1485 
1486 	ASSERT(pipes);
1487 	if (!pipes)
1488 		return false;
1489 
1490 	// For each full update, remove all existing phantom pipes first
1491 	dc->res_pool->funcs->remove_phantom_pipes(dc, context);
1492 
1493 	dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1494 
1495 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1496 
1497 	if (!pipe_cnt) {
1498 		out = true;
1499 		goto validate_out;
1500 	}
1501 
1502 	dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1503 
1504 	if (!fast_validate) {
1505 		DC_FP_START();
1506 		dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
1507 		DC_FP_END();
1508 	}
1509 
1510 	if (fast_validate ||
1511 			(dc->debug.dml_disallow_alternate_prefetch_modes &&
1512 			(vlevel == context->bw_ctx.dml.soc.num_states ||
1513 				vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) {
1514 		/*
1515 		 * If dml_disallow_alternate_prefetch_modes is false, then we have already
1516 		 * tried alternate prefetch modes during full validation.
1517 		 *
1518 		 * If mode is unsupported or there is no p-state support, then
1519 		 * fall back to favouring voltage.
1520 		 *
1521 		 * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try
1522 		 * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)
1523 		 */
1524 		context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1525 			dm_prefetch_support_fclk_and_stutter;
1526 
1527 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1528 
1529 		/* Last attempt with Prefetch mode 2 (dm_prefetch_support_stutter == 3) */
1530 		if (vlevel == context->bw_ctx.dml.soc.num_states) {
1531 			context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1532 				dm_prefetch_support_stutter;
1533 			vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1534 		}
1535 
1536 		if (vlevel < context->bw_ctx.dml.soc.num_states) {
1537 			memset(split, 0, sizeof(split));
1538 			memset(merge, 0, sizeof(merge));
1539 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1540 			// dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML
1541 			vba->VoltageLevel = vlevel;
1542 		}
1543 	}
1544 
1545 	dml_log_mode_support_params(&context->bw_ctx.dml);
1546 
1547 	if (vlevel == context->bw_ctx.dml.soc.num_states)
1548 		goto validate_fail;
1549 
1550 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1551 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1552 		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1553 
1554 		if (!pipe->stream)
1555 			continue;
1556 
1557 		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1558 				&& !dc->config.enable_windowed_mpo_odm
1559 				&& pipe->plane_state && mpo_pipe
1560 				&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
1561 						&pipe->plane_res.scl_data.recout,
1562 						sizeof(struct rect)) != 0) {
1563 			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1564 			goto validate_fail;
1565 		}
1566 		pipe_idx++;
1567 	}
1568 
1569 	/* merge pipes if necessary */
1570 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1571 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1572 
1573 		/*skip pipes that don't need merging*/
1574 		if (!merge[i])
1575 			continue;
1576 
1577 		/* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1578 		if (pipe->prev_odm_pipe) {
1579 			/*split off odm pipe*/
1580 			pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1581 			if (pipe->next_odm_pipe)
1582 				pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1583 
1584 			/*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/
1585 			if (pipe->bottom_pipe) {
1586 				if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) {
1587 					/*MPC split rules will handle this case*/
1588 					pipe->bottom_pipe->top_pipe = NULL;
1589 				} else {
1590 					/* when merging an ODM pipes, the bottom MPC pipe must now point to
1591 					 * the previous ODM pipe and its associated stream assets
1592 					 */
1593 					if (pipe->prev_odm_pipe->bottom_pipe) {
1594 						/* 3 plane MPO*/
1595 						pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe;
1596 						pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe;
1597 					} else {
1598 						/* 2 plane MPO*/
1599 						pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe;
1600 						pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe;
1601 					}
1602 
1603 					memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource));
1604 				}
1605 			}
1606 
1607 			if (pipe->top_pipe) {
1608 				pipe->top_pipe->bottom_pipe = NULL;
1609 			}
1610 
1611 			pipe->bottom_pipe = NULL;
1612 			pipe->next_odm_pipe = NULL;
1613 			pipe->plane_state = NULL;
1614 			pipe->stream = NULL;
1615 			pipe->top_pipe = NULL;
1616 			pipe->prev_odm_pipe = NULL;
1617 			if (pipe->stream_res.dsc)
1618 				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1619 			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1620 			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1621 			repopulate_pipes = true;
1622 		} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1623 			struct pipe_ctx *top_pipe = pipe->top_pipe;
1624 			struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1625 
1626 			top_pipe->bottom_pipe = bottom_pipe;
1627 			if (bottom_pipe)
1628 				bottom_pipe->top_pipe = top_pipe;
1629 
1630 			pipe->top_pipe = NULL;
1631 			pipe->bottom_pipe = NULL;
1632 			pipe->plane_state = NULL;
1633 			pipe->stream = NULL;
1634 			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1635 			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1636 			repopulate_pipes = true;
1637 		} else
1638 			ASSERT(0); /* Should never try to merge master pipe */
1639 
1640 	}
1641 
1642 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1643 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1644 		struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1645 		struct pipe_ctx *hsplit_pipe = NULL;
1646 		bool odm;
1647 		int old_index = -1;
1648 
1649 		if (!pipe->stream || newly_split[i])
1650 			continue;
1651 
1652 		pipe_idx++;
1653 		odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1654 
1655 		if (!pipe->plane_state && !odm)
1656 			continue;
1657 
1658 		if (split[i]) {
1659 			if (odm) {
1660 				if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1661 					old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1662 				else if (old_pipe->next_odm_pipe)
1663 					old_index = old_pipe->next_odm_pipe->pipe_idx;
1664 			} else {
1665 				if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1666 						old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1667 					old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1668 				else if (old_pipe->bottom_pipe &&
1669 						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1670 					old_index = old_pipe->bottom_pipe->pipe_idx;
1671 			}
1672 			hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
1673 			ASSERT(hsplit_pipe);
1674 			if (!hsplit_pipe)
1675 				goto validate_fail;
1676 
1677 			if (!dcn32_split_stream_for_mpc_or_odm(
1678 					dc, &context->res_ctx,
1679 					pipe, hsplit_pipe, odm))
1680 				goto validate_fail;
1681 
1682 			newly_split[hsplit_pipe->pipe_idx] = true;
1683 			repopulate_pipes = true;
1684 		}
1685 		if (split[i] == 4) {
1686 			struct pipe_ctx *pipe_4to1;
1687 
1688 			if (odm && old_pipe->next_odm_pipe)
1689 				old_index = old_pipe->next_odm_pipe->pipe_idx;
1690 			else if (!odm && old_pipe->bottom_pipe &&
1691 						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1692 				old_index = old_pipe->bottom_pipe->pipe_idx;
1693 			else
1694 				old_index = -1;
1695 			pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
1696 			ASSERT(pipe_4to1);
1697 			if (!pipe_4to1)
1698 				goto validate_fail;
1699 			if (!dcn32_split_stream_for_mpc_or_odm(
1700 					dc, &context->res_ctx,
1701 					pipe, pipe_4to1, odm))
1702 				goto validate_fail;
1703 			newly_split[pipe_4to1->pipe_idx] = true;
1704 
1705 			if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1706 					&& old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1707 				old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1708 			else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1709 					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1710 					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1711 				old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1712 			else
1713 				old_index = -1;
1714 			pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
1715 			ASSERT(pipe_4to1);
1716 			if (!pipe_4to1)
1717 				goto validate_fail;
1718 			if (!dcn32_split_stream_for_mpc_or_odm(
1719 					dc, &context->res_ctx,
1720 					hsplit_pipe, pipe_4to1, odm))
1721 				goto validate_fail;
1722 			newly_split[pipe_4to1->pipe_idx] = true;
1723 		}
1724 		if (odm)
1725 			dcn20_build_mapped_resource(dc, context, pipe->stream);
1726 	}
1727 
1728 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1729 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1730 
1731 		if (pipe->plane_state) {
1732 			if (!resource_build_scaling_params(pipe))
1733 				goto validate_fail;
1734 		}
1735 	}
1736 
1737 	/* Actual dsc count per stream dsc validation*/
1738 	if (!dcn20_validate_dsc(dc, context)) {
1739 		vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1740 		goto validate_fail;
1741 	}
1742 
1743 	if (repopulate_pipes) {
1744 		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1745 
1746 		/* repopulate_pipes = 1 means the pipes were either split or merged. In this case
1747 		 * we have to re-calculate the DET allocation and run through DML once more to
1748 		 * ensure all the params are calculated correctly. We do not need to run the
1749 		 * pipe split check again after this call (pipes are already split / merged).
1750 		 * */
1751 		if (!fast_validate) {
1752 			context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1753 						dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
1754 			vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1755 		}
1756 	}
1757 	*vlevel_out = vlevel;
1758 	*pipe_cnt_out = pipe_cnt;
1759 
1760 	out = true;
1761 	goto validate_out;
1762 
1763 validate_fail:
1764 	out = false;
1765 
1766 validate_out:
1767 	return out;
1768 }
1769 
1770 
dcn32_calculate_wm_and_dlg_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1771 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
1772 				display_e2e_pipe_params_st *pipes,
1773 				int pipe_cnt,
1774 				int vlevel)
1775 {
1776 	int i, pipe_idx, vlevel_temp = 0;
1777 	double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
1778 	double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1779 	double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;
1780 	bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
1781 			dm_dram_clock_change_unsupported;
1782 	unsigned int dummy_latency_index = 0;
1783 	int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
1784 	unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
1785 	unsigned int min_dram_speed_mts_margin;
1786 
1787 	dc_assert_fp_enabled();
1788 
1789 	// Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK
1790 	if (!pstate_en && dcn32_subvp_in_use(dc, context)) {
1791 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
1792 		pstate_en = true;
1793 	}
1794 
1795 	context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
1796 
1797 	if (!pstate_en) {
1798 		/* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */
1799 		context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =
1800 			dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
1801 
1802 		if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
1803 			dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
1804 				context, pipes, pipe_cnt, vlevel);
1805 
1806 			/* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch
1807 			 * we reinstate the original dram_clock_change_latency_us on the context
1808 			 * and all variables that may have changed up to this point, except the
1809 			 * newly found dummy_latency_index
1810 			 */
1811 			context->bw_ctx.dml.soc.dram_clock_change_latency_us =
1812 					dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
1813 			/* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so
1814 			 * prefetch is scheduled correctly to account for dummy pstate.
1815 			 */
1816 			if (dummy_latency_index == 0)
1817 				context->bw_ctx.dml.soc.fclk_change_latency_us =
1818 						dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
1819 			dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
1820 			maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
1821 			dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1822 			pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=
1823 					dm_dram_clock_change_unsupported;
1824 		}
1825 	}
1826 
1827 	/* Set B:
1828 	 * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
1829 	 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
1830 	 * calculations to cover bootup clocks.
1831 	 * DCFCLK: soc.clock_limits[2] when available
1832 	 * UCLK: soc.clock_limits[2] when available
1833 	 */
1834 	if (dcn3_2_soc.num_states > 2) {
1835 		vlevel_temp = 2;
1836 		dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
1837 	} else
1838 		dcfclk = 615; //DCFCLK Vmin_lv
1839 
1840 	pipes[0].clks_cfg.voltage = vlevel_temp;
1841 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1842 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
1843 
1844 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
1845 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
1846 		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
1847 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
1848 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
1849 	}
1850 	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1851 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1852 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1853 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1854 	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1855 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1856 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1857 	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1858 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1859 	context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1860 
1861 	/* Set D:
1862 	 * All clocks min.
1863 	 * DCFCLK: Min, as reported by PM FW when available
1864 	 * UCLK  : Min, as reported by PM FW when available
1865 	 * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
1866 	 */
1867 
1868 	if (dcn3_2_soc.num_states > 2) {
1869 		vlevel_temp = 0;
1870 		dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
1871 	} else
1872 		dcfclk = 615; //DCFCLK Vmin_lv
1873 
1874 	pipes[0].clks_cfg.voltage = vlevel_temp;
1875 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1876 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
1877 
1878 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
1879 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
1880 		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
1881 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
1882 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
1883 	}
1884 	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1885 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1886 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1887 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1888 	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1889 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1890 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1891 	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1892 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1893 	context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1894 
1895 	/* Set C, for Dummy P-State:
1896 	 * All clocks min.
1897 	 * DCFCLK: Min, as reported by PM FW, when available
1898 	 * UCLK  : Min,  as reported by PM FW, when available
1899 	 * pstate latency as per UCLK state dummy pstate latency
1900 	 */
1901 
1902 	// For Set A and Set C use values from validation
1903 	pipes[0].clks_cfg.voltage = vlevel;
1904 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
1905 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1906 
1907 	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
1908 		pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching;
1909 	}
1910 
1911 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
1912 		min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
1913 		min_dram_speed_mts_margin = 160;
1914 
1915 		context->bw_ctx.dml.soc.dram_clock_change_latency_us =
1916 			dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
1917 
1918 		if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
1919 			dm_dram_clock_change_unsupported) {
1920 			int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;
1921 
1922 			min_dram_speed_mts =
1923 				dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;
1924 		}
1925 
1926 		if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
1927 			/* find largest table entry that is lower than dram speed,
1928 			 * but lower than DPM0 still uses DPM0
1929 			 */
1930 			for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--)
1931 				if (min_dram_speed_mts + min_dram_speed_mts_margin >
1932 					dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
1933 					break;
1934 		}
1935 
1936 		context->bw_ctx.dml.soc.dram_clock_change_latency_us =
1937 			dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
1938 
1939 		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
1940 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
1941 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
1942 	}
1943 
1944 	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1945 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1946 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1947 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1948 	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1949 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1950 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1951 	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1952 	/* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state.
1953 	 * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM
1954 	 * value.
1955 	 */
1956 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1957 	context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1958 
1959 	if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
1960 		/* The only difference between A and C is p-state latency, if p-state is not supported
1961 		 * with full p-state latency we want to calculate DLG based on dummy p-state latency,
1962 		 * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30.
1963 		 */
1964 		context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
1965 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
1966 	} else {
1967 		/* Set A:
1968 		 * All clocks min.
1969 		 * DCFCLK: Min, as reported by PM FW, when available
1970 		 * UCLK: Min, as reported by PM FW, when available
1971 		 */
1972 		dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1973 		context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1974 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1975 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1976 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1977 		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1978 		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1979 		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1980 		context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1981 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1982 		context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1983 	}
1984 
1985 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1986 		if (!context->res_ctx.pipe_ctx[i].stream)
1987 			continue;
1988 
1989 		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1990 		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1991 
1992 		if (dc->config.forced_clocks) {
1993 			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1994 			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1995 		}
1996 		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1997 			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1998 		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1999 			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2000 
2001 		pipe_idx++;
2002 	}
2003 
2004 	context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2005 
2006 	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && dummy_latency_index == 0)
2007 		context->bw_ctx.dml.soc.fclk_change_latency_us =
2008 				dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2009 
2010 	dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2011 
2012 	if (!pstate_en)
2013 		/* Restore full p-state latency */
2014 		context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2015 				dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2016 
2017 	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2018 		dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context);
2019 		if (dummy_latency_index == 0)
2020 			context->bw_ctx.dml.soc.fclk_change_latency_us =
2021 					dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2022 	}
2023 }
2024 
dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,unsigned int * optimal_dcfclk,unsigned int * optimal_fclk)2025 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2026 		unsigned int *optimal_dcfclk,
2027 		unsigned int *optimal_fclk)
2028 {
2029 	double bw_from_dram, bw_from_dram1, bw_from_dram2;
2030 
2031 	bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
2032 		dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
2033 	bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
2034 		dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
2035 
2036 	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2037 
2038 	if (optimal_fclk)
2039 		*optimal_fclk = bw_from_dram /
2040 		(dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2041 
2042 	if (optimal_dcfclk)
2043 		*optimal_dcfclk =  bw_from_dram /
2044 		(dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2045 }
2046 
remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st * table,unsigned int * num_entries,unsigned int index)2047 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
2048 		unsigned int index)
2049 {
2050 	int i;
2051 
2052 	if (*num_entries == 0)
2053 		return;
2054 
2055 	for (i = index; i < *num_entries - 1; i++) {
2056 		table[i] = table[i + 1];
2057 	}
2058 	memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
2059 }
2060 
dcn32_patch_dpm_table(struct clk_bw_params * bw_params)2061 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params)
2062 {
2063 	int i;
2064 	unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
2065 			max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
2066 
2067 	for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2068 		if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2069 			max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2070 		if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
2071 			max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2072 		if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
2073 			max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2074 		if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2075 			max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2076 		if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2077 			max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2078 		if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2079 			max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2080 		if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
2081 			max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2082 	}
2083 
2084 	/* Scan through clock values we currently have and if they are 0,
2085 	 *  then populate it with dcn3_2_soc.clock_limits[] value.
2086 	 *
2087 	 * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being
2088 	 *  0, will cause it to skip building the clock table.
2089 	 */
2090 	if (max_dcfclk_mhz == 0)
2091 		bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2092 	if (max_dispclk_mhz == 0)
2093 		bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2094 	if (max_dtbclk_mhz == 0)
2095 		bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz;
2096 	if (max_uclk_mhz == 0)
2097 		bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16;
2098 }
2099 
build_synthetic_soc_states(struct clk_bw_params * bw_params,struct _vcs_dpi_voltage_scaling_st * table,unsigned int * num_entries)2100 static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
2101 		struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2102 {
2103 	int i, j;
2104 	struct _vcs_dpi_voltage_scaling_st entry = {0};
2105 
2106 	unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
2107 			max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
2108 
2109 	unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
2110 
2111 	static const unsigned int num_dcfclk_stas = 5;
2112 	unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2113 
2114 	unsigned int num_uclk_dpms = 0;
2115 	unsigned int num_fclk_dpms = 0;
2116 	unsigned int num_dcfclk_dpms = 0;
2117 
2118 	for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2119 		if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2120 			max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2121 		if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
2122 			max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2123 		if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
2124 			max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2125 		if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2126 			max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2127 		if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2128 			max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2129 		if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2130 			max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2131 		if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
2132 			max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2133 
2134 		if (bw_params->clk_table.entries[i].memclk_mhz > 0)
2135 			num_uclk_dpms++;
2136 		if (bw_params->clk_table.entries[i].fclk_mhz > 0)
2137 			num_fclk_dpms++;
2138 		if (bw_params->clk_table.entries[i].dcfclk_mhz > 0)
2139 			num_dcfclk_dpms++;
2140 	}
2141 
2142 	if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)
2143 		return -1;
2144 
2145 	if (max_dppclk_mhz == 0)
2146 		max_dppclk_mhz = max_dispclk_mhz;
2147 
2148 	if (max_fclk_mhz == 0)
2149 		max_fclk_mhz = max_dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;
2150 
2151 	if (max_phyclk_mhz == 0)
2152 		max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2153 
2154 	*num_entries = 0;
2155 	entry.dispclk_mhz = max_dispclk_mhz;
2156 	entry.dscclk_mhz = max_dispclk_mhz / 3;
2157 	entry.dppclk_mhz = max_dppclk_mhz;
2158 	entry.dtbclk_mhz = max_dtbclk_mhz;
2159 	entry.phyclk_mhz = max_phyclk_mhz;
2160 	entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2161 	entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2162 
2163 	// Insert all the DCFCLK STAs
2164 	for (i = 0; i < num_dcfclk_stas; i++) {
2165 		entry.dcfclk_mhz = dcfclk_sta_targets[i];
2166 		entry.fabricclk_mhz = 0;
2167 		entry.dram_speed_mts = 0;
2168 
2169 		DC_FP_START();
2170 		insert_entry_into_table_sorted(table, num_entries, &entry);
2171 		DC_FP_END();
2172 	}
2173 
2174 	// Insert the max DCFCLK
2175 	entry.dcfclk_mhz = max_dcfclk_mhz;
2176 	entry.fabricclk_mhz = 0;
2177 	entry.dram_speed_mts = 0;
2178 
2179 	DC_FP_START();
2180 	insert_entry_into_table_sorted(table, num_entries, &entry);
2181 	DC_FP_END();
2182 
2183 	// Insert the UCLK DPMS
2184 	for (i = 0; i < num_uclk_dpms; i++) {
2185 		entry.dcfclk_mhz = 0;
2186 		entry.fabricclk_mhz = 0;
2187 		entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
2188 
2189 		DC_FP_START();
2190 		insert_entry_into_table_sorted(table, num_entries, &entry);
2191 		DC_FP_END();
2192 	}
2193 
2194 	// If FCLK is coarse grained, insert individual DPMs.
2195 	if (num_fclk_dpms > 2) {
2196 		for (i = 0; i < num_fclk_dpms; i++) {
2197 			entry.dcfclk_mhz = 0;
2198 			entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2199 			entry.dram_speed_mts = 0;
2200 
2201 			DC_FP_START();
2202 			insert_entry_into_table_sorted(table, num_entries, &entry);
2203 			DC_FP_END();
2204 		}
2205 	}
2206 	// If FCLK fine grained, only insert max
2207 	else {
2208 		entry.dcfclk_mhz = 0;
2209 		entry.fabricclk_mhz = max_fclk_mhz;
2210 		entry.dram_speed_mts = 0;
2211 
2212 		DC_FP_START();
2213 		insert_entry_into_table_sorted(table, num_entries, &entry);
2214 		DC_FP_END();
2215 	}
2216 
2217 	// At this point, the table contains all "points of interest" based on
2218 	// DPMs from PMFW, and STAs.  Table is sorted by BW, and all clock
2219 	// ratios (by derate, are exact).
2220 
2221 	// Remove states that require higher clocks than are supported
2222 	for (i = *num_entries - 1; i >= 0 ; i--) {
2223 		if (table[i].dcfclk_mhz > max_dcfclk_mhz ||
2224 				table[i].fabricclk_mhz > max_fclk_mhz ||
2225 				table[i].dram_speed_mts > max_uclk_mhz * 16)
2226 			remove_entry_from_table_at_index(table, num_entries, i);
2227 	}
2228 
2229 	// At this point, the table only contains supported points of interest
2230 	// it could be used as is, but some states may be redundant due to
2231 	// coarse grained nature of some clocks, so we want to round up to
2232 	// coarse grained DPMs and remove duplicates.
2233 
2234 	// Round up UCLKs
2235 	for (i = *num_entries - 1; i >= 0 ; i--) {
2236 		for (j = 0; j < num_uclk_dpms; j++) {
2237 			if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
2238 				table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
2239 				break;
2240 			}
2241 		}
2242 	}
2243 
2244 	// If FCLK is coarse grained, round up to next DPMs
2245 	if (num_fclk_dpms > 2) {
2246 		for (i = *num_entries - 1; i >= 0 ; i--) {
2247 			for (j = 0; j < num_fclk_dpms; j++) {
2248 				if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
2249 					table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
2250 					break;
2251 				}
2252 			}
2253 		}
2254 	}
2255 	// Otherwise, round up to minimum.
2256 	else {
2257 		for (i = *num_entries - 1; i >= 0 ; i--) {
2258 			if (table[i].fabricclk_mhz < min_fclk_mhz) {
2259 				table[i].fabricclk_mhz = min_fclk_mhz;
2260 				break;
2261 			}
2262 		}
2263 	}
2264 
2265 	// Round DCFCLKs up to minimum
2266 	for (i = *num_entries - 1; i >= 0 ; i--) {
2267 		if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
2268 			table[i].dcfclk_mhz = min_dcfclk_mhz;
2269 			break;
2270 		}
2271 	}
2272 
2273 	// Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
2274 	i = 0;
2275 	while (i < *num_entries - 1) {
2276 		if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
2277 				table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
2278 				table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
2279 			remove_entry_from_table_at_index(table, num_entries, i + 1);
2280 		else
2281 			i++;
2282 	}
2283 
2284 	// Fix up the state indicies
2285 	for (i = *num_entries - 1; i >= 0 ; i--) {
2286 		table[i].state = i;
2287 	}
2288 
2289 	return 0;
2290 }
2291 
2292 /*
2293  * dcn32_update_bw_bounding_box
2294  *
2295  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from
2296  * spreadsheet with actual values as per dGPU SKU:
2297  * - with passed few options from dc->config
2298  * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
2299  *   need to get it from PM FW)
2300  * - with passed latency values (passed in ns units) in dc-> bb override for
2301  *   debugging purposes
2302  * - with passed latencies from VBIOS (in 100_ns units) if available for
2303  *   certain dGPU SKU
2304  * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
2305  *   of the same ASIC)
2306  * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
2307  *   FW for different clocks (which might differ for certain dGPU SKU of the
2308  *   same ASIC)
2309  */
dcn32_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params)2310 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
2311 {
2312 	dc_assert_fp_enabled();
2313 
2314 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2315 		/* Overrides from dc->config options */
2316 		dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
2317 
2318 		/* Override from passed dc->bb_overrides if available*/
2319 		if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2320 				&& dc->bb_overrides.sr_exit_time_ns) {
2321 			dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2322 		}
2323 
2324 		if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
2325 				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
2326 				&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2327 			dcn3_2_soc.sr_enter_plus_exit_time_us =
2328 				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2329 		}
2330 
2331 		if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2332 			&& dc->bb_overrides.urgent_latency_ns) {
2333 			dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2334 			dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2335 		}
2336 
2337 		if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
2338 				!= dc->bb_overrides.dram_clock_change_latency_ns
2339 				&& dc->bb_overrides.dram_clock_change_latency_ns) {
2340 			dcn3_2_soc.dram_clock_change_latency_us =
2341 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2342 		}
2343 
2344 		if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000)
2345 				!= dc->bb_overrides.fclk_clock_change_latency_ns
2346 				&& dc->bb_overrides.fclk_clock_change_latency_ns) {
2347 			dcn3_2_soc.fclk_change_latency_us =
2348 				dc->bb_overrides.fclk_clock_change_latency_ns / 1000;
2349 		}
2350 
2351 		if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
2352 				!= dc->bb_overrides.dummy_clock_change_latency_ns
2353 				&& dc->bb_overrides.dummy_clock_change_latency_ns) {
2354 			dcn3_2_soc.dummy_pstate_latency_us =
2355 				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
2356 		}
2357 
2358 		/* Override from VBIOS if VBIOS bb_info available */
2359 		if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
2360 			struct bp_soc_bb_info bb_info = {0};
2361 
2362 			if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
2363 				if (bb_info.dram_clock_change_latency_100ns > 0)
2364 					dcn3_2_soc.dram_clock_change_latency_us =
2365 						bb_info.dram_clock_change_latency_100ns * 10;
2366 
2367 				if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
2368 					dcn3_2_soc.sr_enter_plus_exit_time_us =
2369 						bb_info.dram_sr_enter_exit_latency_100ns * 10;
2370 
2371 				if (bb_info.dram_sr_exit_latency_100ns > 0)
2372 					dcn3_2_soc.sr_exit_time_us =
2373 						bb_info.dram_sr_exit_latency_100ns * 10;
2374 			}
2375 		}
2376 
2377 		/* Override from VBIOS for num_chan */
2378 		if (dc->ctx->dc_bios->vram_info.num_chans)
2379 			dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2380 
2381 		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2382 			dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2383 	}
2384 
2385 	/* DML DSC delay factor workaround */
2386 	dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
2387 
2388 	dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
2389 
2390 	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
2391 	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2392 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2393 
2394 	/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
2395 	if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
2396 		if (dc->debug.use_legacy_soc_bb_mechanism) {
2397 			unsigned int i = 0, j = 0, num_states = 0;
2398 
2399 			unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2400 			unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2401 			unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2402 			unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2403 			unsigned int min_dcfclk = UINT_MAX;
2404 			/* Set 199 as first value in STA target array to have a minimum DCFCLK value.
2405 			 * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */
2406 			unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2407 			unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
2408 			unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
2409 
2410 			for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2411 				if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2412 					max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2413 				if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&
2414 						bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)
2415 					min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;
2416 				if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2417 					max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2418 				if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2419 					max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2420 				if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2421 					max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2422 			}
2423 			if (min_dcfclk > dcfclk_sta_targets[0])
2424 				dcfclk_sta_targets[0] = min_dcfclk;
2425 			if (!max_dcfclk_mhz)
2426 				max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2427 			if (!max_dispclk_mhz)
2428 				max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2429 			if (!max_dppclk_mhz)
2430 				max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
2431 			if (!max_phyclk_mhz)
2432 				max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2433 
2434 			if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2435 				// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2436 				dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2437 				num_dcfclk_sta_targets++;
2438 			} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2439 				// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2440 				for (i = 0; i < num_dcfclk_sta_targets; i++) {
2441 					if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2442 						dcfclk_sta_targets[i] = max_dcfclk_mhz;
2443 						break;
2444 					}
2445 				}
2446 				// Update size of array since we "removed" duplicates
2447 				num_dcfclk_sta_targets = i + 1;
2448 			}
2449 
2450 			num_uclk_states = bw_params->clk_table.num_entries;
2451 
2452 			// Calculate optimal dcfclk for each uclk
2453 			for (i = 0; i < num_uclk_states; i++) {
2454 				dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2455 						&optimal_dcfclk_for_uclk[i], NULL);
2456 				if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2457 					optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2458 				}
2459 			}
2460 
2461 			// Calculate optimal uclk for each dcfclk sta target
2462 			for (i = 0; i < num_dcfclk_sta_targets; i++) {
2463 				for (j = 0; j < num_uclk_states; j++) {
2464 					if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2465 						optimal_uclk_for_dcfclk_sta_targets[i] =
2466 								bw_params->clk_table.entries[j].memclk_mhz * 16;
2467 						break;
2468 					}
2469 				}
2470 			}
2471 
2472 			i = 0;
2473 			j = 0;
2474 			// create the final dcfclk and uclk table
2475 			while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2476 				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2477 					dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2478 					dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2479 				} else {
2480 					if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2481 						dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2482 						dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2483 					} else {
2484 						j = num_uclk_states;
2485 					}
2486 				}
2487 			}
2488 
2489 			while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2490 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2491 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2492 			}
2493 
2494 			while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2495 					optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2496 				dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2497 				dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2498 			}
2499 
2500 			dcn3_2_soc.num_states = num_states;
2501 			for (i = 0; i < dcn3_2_soc.num_states; i++) {
2502 				dcn3_2_soc.clock_limits[i].state = i;
2503 				dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2504 				dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2505 
2506 				/* Fill all states with max values of all these clocks */
2507 				dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
2508 				dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
2509 				dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
2510 				dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
2511 
2512 				/* Populate from bw_params for DTBCLK, SOCCLK */
2513 				if (i > 0) {
2514 					if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
2515 						dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
2516 					} else {
2517 						dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
2518 					}
2519 				} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
2520 					dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
2521 				}
2522 
2523 				if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
2524 					dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
2525 				else
2526 					dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
2527 
2528 				if (!dram_speed_mts[i] && i > 0)
2529 					dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
2530 				else
2531 					dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2532 
2533 				/* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
2534 				/* PHYCLK_D18, PHYCLK_D32 */
2535 				dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2536 				dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2537 			}
2538 		} else {
2539 			build_synthetic_soc_states(bw_params, dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states);
2540 		}
2541 
2542 		/* Re-init DML with updated bb */
2543 		dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2544 		if (dc->current_state)
2545 			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2546 	}
2547 }
2548 
dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st * pipes,int pipe_cnt)2549 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
2550 				  int pipe_cnt)
2551 {
2552 	dc_assert_fp_enabled();
2553 
2554 	pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
2555 	pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
2556 }
2557