1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn31_resource.h"
35
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38
39 #include "dml/dcn30/dcn30_fpu.h"
40
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn30/dcn30_hubbub.h"
43 #include "dcn31/dcn31_hubbub.h"
44 #include "dcn30/dcn30_mpc.h"
45 #include "dcn31/dcn31_hubp.h"
46 #include "irq/dcn31/irq_service_dcn31.h"
47 #include "dcn30/dcn30_dpp.h"
48 #include "dcn31/dcn31_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hw_sequencer.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
59 #include "dcn31/dcn31_apg.h"
60 #include "dcn31/dcn31_dio_link_encoder.h"
61 #include "dcn31/dcn31_vpg.h"
62 #include "dcn31/dcn31_afmt.h"
63 #include "dce/dce_clock_source.h"
64 #include "dce/dce_audio.h"
65 #include "dce/dce_hwseq.h"
66 #include "clk_mgr.h"
67 #include "virtual/virtual_stream_encoder.h"
68 #include "dce110/dce110_resource.h"
69 #include "dml/display_mode_vba.h"
70 #include "dml/dcn31/dcn31_fpu.h"
71 #include "dcn31/dcn31_dccg.h"
72 #include "dcn10/dcn10_resource.h"
73 #include "dcn31_panel_cntl.h"
74
75 #include "dcn30/dcn30_dwb.h"
76 #include "dcn30/dcn30_mmhubbub.h"
77
78 // TODO: change include headers /amd/include/asic_reg after upstream
79 #include "yellow_carp_offset.h"
80 #include "dcn/dcn_3_1_2_offset.h"
81 #include "dcn/dcn_3_1_2_sh_mask.h"
82 #include "nbio/nbio_7_2_0_offset.h"
83 #include "dpcs/dpcs_4_2_0_offset.h"
84 #include "dpcs/dpcs_4_2_0_sh_mask.h"
85 #include "mmhub/mmhub_2_3_0_offset.h"
86 #include "mmhub/mmhub_2_3_0_sh_mask.h"
87
88
89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
93
94 #include "reg_helper.h"
95 #include "dce/dmub_abm.h"
96 #include "dce/dmub_psr.h"
97 #include "dce/dce_aux.h"
98 #include "dce/dce_i2c.h"
99
100 #include "dml/dcn30/display_mode_vba_30.h"
101 #include "vm_helper.h"
102 #include "dcn20/dcn20_vmid.h"
103
104 #include "link_enc_cfg.h"
105
106 #define DC_LOGGER_INIT(logger)
107
108 enum dcn31_clk_src_array_id {
109 DCN31_CLK_SRC_PLL0,
110 DCN31_CLK_SRC_PLL1,
111 DCN31_CLK_SRC_PLL2,
112 DCN31_CLK_SRC_PLL3,
113 DCN31_CLK_SRC_PLL4,
114 DCN30_CLK_SRC_TOTAL
115 };
116
117 /* begin *********************
118 * macros to expend register list macro defined in HW object header file
119 */
120
121 /* DCN */
122 /* TODO awful hack. fixup dcn20_dwb.h */
123 #undef BASE_INNER
124 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
125
126 #define BASE(seg) BASE_INNER(seg)
127
128 #define SR(reg_name)\
129 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
130 reg ## reg_name
131
132 #define SRI(reg_name, block, id)\
133 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 reg ## block ## id ## _ ## reg_name
135
136 #define SRI2(reg_name, block, id)\
137 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
138 reg ## reg_name
139
140 #define SRIR(var_name, reg_name, block, id)\
141 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 reg ## block ## id ## _ ## reg_name
143
144 #define SRII(reg_name, block, id)\
145 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 reg ## block ## id ## _ ## reg_name
147
148 #define SRII_MPC_RMU(reg_name, block, id)\
149 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 reg ## block ## id ## _ ## reg_name
151
152 #define SRII_DWB(reg_name, temp_name, block, id)\
153 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## temp_name
155
156 #define DCCG_SRII(reg_name, block, id)\
157 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define VUPDATE_SRII(reg_name, block, id)\
161 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
162 reg ## reg_name ## _ ## block ## id
163
164 /* NBIO */
165 #define NBIO_BASE_INNER(seg) \
166 NBIO_BASE__INST0_SEG ## seg
167
168 #define NBIO_BASE(seg) \
169 NBIO_BASE_INNER(seg)
170
171 #define NBIO_SR(reg_name)\
172 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
173 regBIF_BX1_ ## reg_name
174
175 /* MMHUB */
176 #define MMHUB_BASE_INNER(seg) \
177 MMHUB_BASE__INST0_SEG ## seg
178
179 #define MMHUB_BASE(seg) \
180 MMHUB_BASE_INNER(seg)
181
182 #define MMHUB_SR(reg_name)\
183 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
184 mm ## reg_name
185
186 /* CLOCK */
187 #define CLK_BASE_INNER(seg) \
188 CLK_BASE__INST0_SEG ## seg
189
190 #define CLK_BASE(seg) \
191 CLK_BASE_INNER(seg)
192
193 #define CLK_SRI(reg_name, block, inst)\
194 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
195 reg ## block ## _ ## inst ## _ ## reg_name
196
197
198 static const struct bios_registers bios_regs = {
199 NBIO_SR(BIOS_SCRATCH_3),
200 NBIO_SR(BIOS_SCRATCH_6)
201 };
202
203 #define clk_src_regs(index, pllid)\
204 [index] = {\
205 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
206 }
207
208 static const struct dce110_clk_src_regs clk_src_regs[] = {
209 clk_src_regs(0, A),
210 clk_src_regs(1, B),
211 clk_src_regs(2, C),
212 clk_src_regs(3, D),
213 clk_src_regs(4, E)
214 };
215 /*pll_id being rempped in dmub, in driver it is logical instance*/
216 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
217 clk_src_regs(0, A),
218 clk_src_regs(1, B),
219 clk_src_regs(2, F),
220 clk_src_regs(3, G),
221 clk_src_regs(4, E)
222 };
223
224 static const struct dce110_clk_src_shift cs_shift = {
225 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
226 };
227
228 static const struct dce110_clk_src_mask cs_mask = {
229 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
230 };
231
232 #define abm_regs(id)\
233 [id] = {\
234 ABM_DCN302_REG_LIST(id)\
235 }
236
237 static const struct dce_abm_registers abm_regs[] = {
238 abm_regs(0),
239 abm_regs(1),
240 abm_regs(2),
241 abm_regs(3),
242 };
243
244 static const struct dce_abm_shift abm_shift = {
245 ABM_MASK_SH_LIST_DCN30(__SHIFT)
246 };
247
248 static const struct dce_abm_mask abm_mask = {
249 ABM_MASK_SH_LIST_DCN30(_MASK)
250 };
251
252 #define audio_regs(id)\
253 [id] = {\
254 AUD_COMMON_REG_LIST(id)\
255 }
256
257 static const struct dce_audio_registers audio_regs[] = {
258 audio_regs(0),
259 audio_regs(1),
260 audio_regs(2),
261 audio_regs(3),
262 audio_regs(4),
263 audio_regs(5),
264 audio_regs(6)
265 };
266
267 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
268 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
269 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
270 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
271
272 static const struct dce_audio_shift audio_shift = {
273 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
274 };
275
276 static const struct dce_audio_mask audio_mask = {
277 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
278 };
279
280 #define vpg_regs(id)\
281 [id] = {\
282 VPG_DCN31_REG_LIST(id)\
283 }
284
285 static const struct dcn31_vpg_registers vpg_regs[] = {
286 vpg_regs(0),
287 vpg_regs(1),
288 vpg_regs(2),
289 vpg_regs(3),
290 vpg_regs(4),
291 vpg_regs(5),
292 vpg_regs(6),
293 vpg_regs(7),
294 vpg_regs(8),
295 vpg_regs(9),
296 };
297
298 static const struct dcn31_vpg_shift vpg_shift = {
299 DCN31_VPG_MASK_SH_LIST(__SHIFT)
300 };
301
302 static const struct dcn31_vpg_mask vpg_mask = {
303 DCN31_VPG_MASK_SH_LIST(_MASK)
304 };
305
306 #define afmt_regs(id)\
307 [id] = {\
308 AFMT_DCN31_REG_LIST(id)\
309 }
310
311 static const struct dcn31_afmt_registers afmt_regs[] = {
312 afmt_regs(0),
313 afmt_regs(1),
314 afmt_regs(2),
315 afmt_regs(3),
316 afmt_regs(4),
317 afmt_regs(5)
318 };
319
320 static const struct dcn31_afmt_shift afmt_shift = {
321 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
322 };
323
324 static const struct dcn31_afmt_mask afmt_mask = {
325 DCN31_AFMT_MASK_SH_LIST(_MASK)
326 };
327
328 #define apg_regs(id)\
329 [id] = {\
330 APG_DCN31_REG_LIST(id)\
331 }
332
333 static const struct dcn31_apg_registers apg_regs[] = {
334 apg_regs(0),
335 apg_regs(1),
336 apg_regs(2),
337 apg_regs(3)
338 };
339
340 static const struct dcn31_apg_shift apg_shift = {
341 DCN31_APG_MASK_SH_LIST(__SHIFT)
342 };
343
344 static const struct dcn31_apg_mask apg_mask = {
345 DCN31_APG_MASK_SH_LIST(_MASK)
346 };
347
348 #define stream_enc_regs(id)\
349 [id] = {\
350 SE_DCN3_REG_LIST(id)\
351 }
352
353 /* Some encoders won't be initialized here - but they're logical, not physical. */
354 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
355 stream_enc_regs(0),
356 stream_enc_regs(1),
357 stream_enc_regs(2),
358 stream_enc_regs(3),
359 stream_enc_regs(4)
360 };
361
362 static const struct dcn10_stream_encoder_shift se_shift = {
363 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
364 };
365
366 static const struct dcn10_stream_encoder_mask se_mask = {
367 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
368 };
369
370
371 #define aux_regs(id)\
372 [id] = {\
373 DCN2_AUX_REG_LIST(id)\
374 }
375
376 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
377 aux_regs(0),
378 aux_regs(1),
379 aux_regs(2),
380 aux_regs(3),
381 aux_regs(4)
382 };
383
384 #define hpd_regs(id)\
385 [id] = {\
386 HPD_REG_LIST(id)\
387 }
388
389 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
390 hpd_regs(0),
391 hpd_regs(1),
392 hpd_regs(2),
393 hpd_regs(3),
394 hpd_regs(4)
395 };
396
397 #define link_regs(id, phyid)\
398 [id] = {\
399 LE_DCN31_REG_LIST(id), \
400 UNIPHY_DCN2_REG_LIST(phyid), \
401 DPCS_DCN31_REG_LIST(id), \
402 }
403
404 static const struct dce110_aux_registers_shift aux_shift = {
405 DCN_AUX_MASK_SH_LIST(__SHIFT)
406 };
407
408 static const struct dce110_aux_registers_mask aux_mask = {
409 DCN_AUX_MASK_SH_LIST(_MASK)
410 };
411
412 static const struct dcn10_link_enc_registers link_enc_regs[] = {
413 link_regs(0, A),
414 link_regs(1, B),
415 link_regs(2, C),
416 link_regs(3, D),
417 link_regs(4, E)
418 };
419
420 static const struct dcn10_link_enc_shift le_shift = {
421 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
422 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
423 };
424
425 static const struct dcn10_link_enc_mask le_mask = {
426 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
427 DPCS_DCN31_MASK_SH_LIST(_MASK)
428 };
429
430 #define hpo_dp_stream_encoder_reg_list(id)\
431 [id] = {\
432 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
433 }
434
435 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
436 hpo_dp_stream_encoder_reg_list(0),
437 hpo_dp_stream_encoder_reg_list(1),
438 hpo_dp_stream_encoder_reg_list(2),
439 hpo_dp_stream_encoder_reg_list(3),
440 };
441
442 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
443 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
444 };
445
446 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
447 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
448 };
449
450 #define hpo_dp_link_encoder_reg_list(id)\
451 [id] = {\
452 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
453 DCN3_1_RDPCSTX_REG_LIST(0),\
454 DCN3_1_RDPCSTX_REG_LIST(1),\
455 DCN3_1_RDPCSTX_REG_LIST(2),\
456 DCN3_1_RDPCSTX_REG_LIST(3),\
457 DCN3_1_RDPCSTX_REG_LIST(4)\
458 }
459
460 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
461 hpo_dp_link_encoder_reg_list(0),
462 hpo_dp_link_encoder_reg_list(1),
463 };
464
465 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
466 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
467 };
468
469 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
470 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
471 };
472
473 #define dpp_regs(id)\
474 [id] = {\
475 DPP_REG_LIST_DCN30(id),\
476 }
477
478 static const struct dcn3_dpp_registers dpp_regs[] = {
479 dpp_regs(0),
480 dpp_regs(1),
481 dpp_regs(2),
482 dpp_regs(3)
483 };
484
485 static const struct dcn3_dpp_shift tf_shift = {
486 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
487 };
488
489 static const struct dcn3_dpp_mask tf_mask = {
490 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
491 };
492
493 #define opp_regs(id)\
494 [id] = {\
495 OPP_REG_LIST_DCN30(id),\
496 }
497
498 static const struct dcn20_opp_registers opp_regs[] = {
499 opp_regs(0),
500 opp_regs(1),
501 opp_regs(2),
502 opp_regs(3)
503 };
504
505 static const struct dcn20_opp_shift opp_shift = {
506 OPP_MASK_SH_LIST_DCN20(__SHIFT)
507 };
508
509 static const struct dcn20_opp_mask opp_mask = {
510 OPP_MASK_SH_LIST_DCN20(_MASK)
511 };
512
513 #define aux_engine_regs(id)\
514 [id] = {\
515 AUX_COMMON_REG_LIST0(id), \
516 .AUXN_IMPCAL = 0, \
517 .AUXP_IMPCAL = 0, \
518 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
519 }
520
521 static const struct dce110_aux_registers aux_engine_regs[] = {
522 aux_engine_regs(0),
523 aux_engine_regs(1),
524 aux_engine_regs(2),
525 aux_engine_regs(3),
526 aux_engine_regs(4)
527 };
528
529 #define dwbc_regs_dcn3(id)\
530 [id] = {\
531 DWBC_COMMON_REG_LIST_DCN30(id),\
532 }
533
534 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
535 dwbc_regs_dcn3(0),
536 };
537
538 static const struct dcn30_dwbc_shift dwbc30_shift = {
539 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
540 };
541
542 static const struct dcn30_dwbc_mask dwbc30_mask = {
543 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
544 };
545
546 #define mcif_wb_regs_dcn3(id)\
547 [id] = {\
548 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
549 }
550
551 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
552 mcif_wb_regs_dcn3(0)
553 };
554
555 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
556 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
557 };
558
559 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
560 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
561 };
562
563 #define dsc_regsDCN20(id)\
564 [id] = {\
565 DSC_REG_LIST_DCN20(id)\
566 }
567
568 static const struct dcn20_dsc_registers dsc_regs[] = {
569 dsc_regsDCN20(0),
570 dsc_regsDCN20(1),
571 dsc_regsDCN20(2)
572 };
573
574 static const struct dcn20_dsc_shift dsc_shift = {
575 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
576 };
577
578 static const struct dcn20_dsc_mask dsc_mask = {
579 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
580 };
581
582 static const struct dcn30_mpc_registers mpc_regs = {
583 MPC_REG_LIST_DCN3_0(0),
584 MPC_REG_LIST_DCN3_0(1),
585 MPC_REG_LIST_DCN3_0(2),
586 MPC_REG_LIST_DCN3_0(3),
587 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
588 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
589 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
590 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
591 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
592 MPC_RMU_REG_LIST_DCN3AG(0),
593 MPC_RMU_REG_LIST_DCN3AG(1),
594 //MPC_RMU_REG_LIST_DCN3AG(2),
595 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
596 };
597
598 static const struct dcn30_mpc_shift mpc_shift = {
599 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
600 };
601
602 static const struct dcn30_mpc_mask mpc_mask = {
603 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
604 };
605
606 #define optc_regs(id)\
607 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
608
609 static const struct dcn_optc_registers optc_regs[] = {
610 optc_regs(0),
611 optc_regs(1),
612 optc_regs(2),
613 optc_regs(3)
614 };
615
616 static const struct dcn_optc_shift optc_shift = {
617 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
618 };
619
620 static const struct dcn_optc_mask optc_mask = {
621 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
622 };
623
624 #define hubp_regs(id)\
625 [id] = {\
626 HUBP_REG_LIST_DCN30(id)\
627 }
628
629 static const struct dcn_hubp2_registers hubp_regs[] = {
630 hubp_regs(0),
631 hubp_regs(1),
632 hubp_regs(2),
633 hubp_regs(3)
634 };
635
636
637 static const struct dcn_hubp2_shift hubp_shift = {
638 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
639 };
640
641 static const struct dcn_hubp2_mask hubp_mask = {
642 HUBP_MASK_SH_LIST_DCN31(_MASK)
643 };
644 static const struct dcn_hubbub_registers hubbub_reg = {
645 HUBBUB_REG_LIST_DCN31(0)
646 };
647
648 static const struct dcn_hubbub_shift hubbub_shift = {
649 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
650 };
651
652 static const struct dcn_hubbub_mask hubbub_mask = {
653 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
654 };
655
656 static const struct dccg_registers dccg_regs = {
657 DCCG_REG_LIST_DCN31()
658 };
659
660 static const struct dccg_shift dccg_shift = {
661 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
662 };
663
664 static const struct dccg_mask dccg_mask = {
665 DCCG_MASK_SH_LIST_DCN31(_MASK)
666 };
667
668
669 #define SRII2(reg_name_pre, reg_name_post, id)\
670 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
671 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
672 reg ## reg_name_pre ## id ## _ ## reg_name_post
673
674
675 #define HWSEQ_DCN31_REG_LIST()\
676 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
677 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
678 SR(DIO_MEM_PWR_CTRL), \
679 SR(ODM_MEM_PWR_CTRL3), \
680 SR(DMU_MEM_PWR_CNTL), \
681 SR(MMHUBBUB_MEM_PWR_CNTL), \
682 SR(DCCG_GATE_DISABLE_CNTL), \
683 SR(DCCG_GATE_DISABLE_CNTL2), \
684 SR(DCFCLK_CNTL),\
685 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
686 SRII(PIXEL_RATE_CNTL, OTG, 0), \
687 SRII(PIXEL_RATE_CNTL, OTG, 1),\
688 SRII(PIXEL_RATE_CNTL, OTG, 2),\
689 SRII(PIXEL_RATE_CNTL, OTG, 3),\
690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
694 SR(MICROSECOND_TIME_BASE_DIV), \
695 SR(MILLISECOND_TIME_BASE_DIV), \
696 SR(DISPCLK_FREQ_CHANGE_CNTL), \
697 SR(RBBMIF_TIMEOUT_DIS), \
698 SR(RBBMIF_TIMEOUT_DIS_2), \
699 SR(DCHUBBUB_CRC_CTRL), \
700 SR(DPP_TOP0_DPP_CRC_CTRL), \
701 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
702 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
703 SR(MPC_CRC_CTRL), \
704 SR(MPC_CRC_RESULT_GB), \
705 SR(MPC_CRC_RESULT_C), \
706 SR(MPC_CRC_RESULT_AR), \
707 SR(DOMAIN0_PG_CONFIG), \
708 SR(DOMAIN1_PG_CONFIG), \
709 SR(DOMAIN2_PG_CONFIG), \
710 SR(DOMAIN3_PG_CONFIG), \
711 SR(DOMAIN16_PG_CONFIG), \
712 SR(DOMAIN17_PG_CONFIG), \
713 SR(DOMAIN18_PG_CONFIG), \
714 SR(DOMAIN0_PG_STATUS), \
715 SR(DOMAIN1_PG_STATUS), \
716 SR(DOMAIN2_PG_STATUS), \
717 SR(DOMAIN3_PG_STATUS), \
718 SR(DOMAIN16_PG_STATUS), \
719 SR(DOMAIN17_PG_STATUS), \
720 SR(DOMAIN18_PG_STATUS), \
721 SR(D1VGA_CONTROL), \
722 SR(D2VGA_CONTROL), \
723 SR(D3VGA_CONTROL), \
724 SR(D4VGA_CONTROL), \
725 SR(D5VGA_CONTROL), \
726 SR(D6VGA_CONTROL), \
727 SR(DC_IP_REQUEST_CNTL), \
728 SR(AZALIA_AUDIO_DTO), \
729 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
730 SR(HPO_TOP_HW_CONTROL)
731
732 static const struct dce_hwseq_registers hwseq_reg = {
733 HWSEQ_DCN31_REG_LIST()
734 };
735
736 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
737 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
738 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
739 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
740 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
741 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
742 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
743 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
744 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
745 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
746 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
747 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
748 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
749 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
750 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
751 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
752 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
753 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
754 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
755 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
756 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
757 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
758 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
759 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
760 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
761 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
762 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
763 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
764 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
765 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
766 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
767 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
768 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
769 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
770
771 static const struct dce_hwseq_shift hwseq_shift = {
772 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
773 };
774
775 static const struct dce_hwseq_mask hwseq_mask = {
776 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
777 };
778 #define vmid_regs(id)\
779 [id] = {\
780 DCN20_VMID_REG_LIST(id)\
781 }
782
783 static const struct dcn_vmid_registers vmid_regs[] = {
784 vmid_regs(0),
785 vmid_regs(1),
786 vmid_regs(2),
787 vmid_regs(3),
788 vmid_regs(4),
789 vmid_regs(5),
790 vmid_regs(6),
791 vmid_regs(7),
792 vmid_regs(8),
793 vmid_regs(9),
794 vmid_regs(10),
795 vmid_regs(11),
796 vmid_regs(12),
797 vmid_regs(13),
798 vmid_regs(14),
799 vmid_regs(15)
800 };
801
802 static const struct dcn20_vmid_shift vmid_shifts = {
803 DCN20_VMID_MASK_SH_LIST(__SHIFT)
804 };
805
806 static const struct dcn20_vmid_mask vmid_masks = {
807 DCN20_VMID_MASK_SH_LIST(_MASK)
808 };
809
810 static const struct resource_caps res_cap_dcn31 = {
811 .num_timing_generator = 4,
812 .num_opp = 4,
813 .num_video_plane = 4,
814 .num_audio = 5,
815 .num_stream_encoder = 5,
816 .num_dig_link_enc = 5,
817 .num_hpo_dp_stream_encoder = 4,
818 .num_hpo_dp_link_encoder = 2,
819 .num_pll = 5,
820 .num_dwb = 1,
821 .num_ddc = 5,
822 .num_vmid = 16,
823 .num_mpc_3dlut = 2,
824 .num_dsc = 3,
825 };
826
827 static const struct dc_plane_cap plane_cap = {
828 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
829 .blends_with_above = true,
830 .blends_with_below = true,
831 .per_pixel_alpha = true,
832
833 .pixel_format_support = {
834 .argb8888 = true,
835 .nv12 = true,
836 .fp16 = true,
837 .p010 = true,
838 .ayuv = false,
839 },
840
841 .max_upscale_factor = {
842 .argb8888 = 16000,
843 .nv12 = 16000,
844 .fp16 = 16000
845 },
846
847 // 6:1 downscaling ratio: 1000/6 = 166.666
848 .max_downscale_factor = {
849 .argb8888 = 167,
850 .nv12 = 167,
851 .fp16 = 167
852 },
853 64,
854 64
855 };
856
857 static const struct dc_debug_options debug_defaults_drv = {
858 .disable_dmcu = true,
859 .force_abm_enable = false,
860 .timing_trace = false,
861 .clock_trace = true,
862 .disable_pplib_clock_request = false,
863 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
864 .force_single_disp_pipe_split = false,
865 .disable_dcc = DCC_ENABLE,
866 .vsr_support = true,
867 .performance_trace = false,
868 .max_downscale_src_width = 4096,/*upto true 4K*/
869 .disable_pplib_wm_range = false,
870 .scl_reset_length10 = true,
871 .sanity_checks = true,
872 .underflow_assert_delay_us = 0xFFFFFFFF,
873 .dwb_fi_phase = -1, // -1 = disable,
874 .dmub_command_table = true,
875 .pstate_enabled = true,
876 .use_max_lb = true,
877 .enable_mem_low_power = {
878 .bits = {
879 .vga = true,
880 .i2c = true,
881 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
882 .dscl = true,
883 .cm = true,
884 .mpc = true,
885 .optc = true,
886 .vpg = true,
887 .afmt = true,
888 }
889 },
890 .disable_z10 = true,
891 .optimize_edp_link_rate = true,
892 .enable_sw_cntl_psr = true,
893 .apply_vendor_specific_lttpr_wa = true,
894 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
895 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
896 };
897
898 static const struct dc_debug_options debug_defaults_diags = {
899 .disable_dmcu = true,
900 .force_abm_enable = false,
901 .timing_trace = true,
902 .clock_trace = true,
903 .disable_dpp_power_gate = true,
904 .disable_hubp_power_gate = true,
905 .disable_clock_gate = true,
906 .disable_pplib_clock_request = true,
907 .disable_pplib_wm_range = true,
908 .disable_stutter = false,
909 .scl_reset_length10 = true,
910 .dwb_fi_phase = -1, // -1 = disable
911 .dmub_command_table = true,
912 .enable_tri_buf = true,
913 .use_max_lb = true
914 };
915
dcn31_dpp_destroy(struct dpp ** dpp)916 static void dcn31_dpp_destroy(struct dpp **dpp)
917 {
918 kfree(TO_DCN20_DPP(*dpp));
919 *dpp = NULL;
920 }
921
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)922 static struct dpp *dcn31_dpp_create(
923 struct dc_context *ctx,
924 uint32_t inst)
925 {
926 struct dcn3_dpp *dpp =
927 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
928
929 if (!dpp)
930 return NULL;
931
932 if (dpp3_construct(dpp, ctx, inst,
933 &dpp_regs[inst], &tf_shift, &tf_mask))
934 return &dpp->base;
935
936 BREAK_TO_DEBUGGER();
937 kfree(dpp);
938 return NULL;
939 }
940
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)941 static struct output_pixel_processor *dcn31_opp_create(
942 struct dc_context *ctx, uint32_t inst)
943 {
944 struct dcn20_opp *opp =
945 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
946
947 if (!opp) {
948 BREAK_TO_DEBUGGER();
949 return NULL;
950 }
951
952 dcn20_opp_construct(opp, ctx, inst,
953 &opp_regs[inst], &opp_shift, &opp_mask);
954 return &opp->base;
955 }
956
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)957 static struct dce_aux *dcn31_aux_engine_create(
958 struct dc_context *ctx,
959 uint32_t inst)
960 {
961 struct aux_engine_dce110 *aux_engine =
962 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
963
964 if (!aux_engine)
965 return NULL;
966
967 dce110_aux_engine_construct(aux_engine, ctx, inst,
968 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
969 &aux_engine_regs[inst],
970 &aux_mask,
971 &aux_shift,
972 ctx->dc->caps.extended_aux_timeout_support);
973
974 return &aux_engine->base;
975 }
976 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
977
978 static const struct dce_i2c_registers i2c_hw_regs[] = {
979 i2c_inst_regs(1),
980 i2c_inst_regs(2),
981 i2c_inst_regs(3),
982 i2c_inst_regs(4),
983 i2c_inst_regs(5),
984 };
985
986 static const struct dce_i2c_shift i2c_shifts = {
987 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
988 };
989
990 static const struct dce_i2c_mask i2c_masks = {
991 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
992 };
993
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)994 static struct dce_i2c_hw *dcn31_i2c_hw_create(
995 struct dc_context *ctx,
996 uint32_t inst)
997 {
998 struct dce_i2c_hw *dce_i2c_hw =
999 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1000
1001 if (!dce_i2c_hw)
1002 return NULL;
1003
1004 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1005 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1006
1007 return dce_i2c_hw;
1008 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1009 static struct mpc *dcn31_mpc_create(
1010 struct dc_context *ctx,
1011 int num_mpcc,
1012 int num_rmu)
1013 {
1014 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1015 GFP_KERNEL);
1016
1017 if (!mpc30)
1018 return NULL;
1019
1020 dcn30_mpc_construct(mpc30, ctx,
1021 &mpc_regs,
1022 &mpc_shift,
1023 &mpc_mask,
1024 num_mpcc,
1025 num_rmu);
1026
1027 return &mpc30->base;
1028 }
1029
dcn31_hubbub_create(struct dc_context * ctx)1030 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1031 {
1032 int i;
1033
1034 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1035 GFP_KERNEL);
1036
1037 if (!hubbub3)
1038 return NULL;
1039
1040 hubbub31_construct(hubbub3, ctx,
1041 &hubbub_reg,
1042 &hubbub_shift,
1043 &hubbub_mask,
1044 dcn3_1_ip.det_buffer_size_kbytes,
1045 dcn3_1_ip.pixel_chunk_size_kbytes,
1046 dcn3_1_ip.config_return_buffer_size_in_kbytes);
1047
1048
1049 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1050 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1051
1052 vmid->ctx = ctx;
1053
1054 vmid->regs = &vmid_regs[i];
1055 vmid->shifts = &vmid_shifts;
1056 vmid->masks = &vmid_masks;
1057 }
1058
1059 return &hubbub3->base;
1060 }
1061
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1062 static struct timing_generator *dcn31_timing_generator_create(
1063 struct dc_context *ctx,
1064 uint32_t instance)
1065 {
1066 struct optc *tgn10 =
1067 kzalloc(sizeof(struct optc), GFP_KERNEL);
1068
1069 if (!tgn10)
1070 return NULL;
1071
1072 tgn10->base.inst = instance;
1073 tgn10->base.ctx = ctx;
1074
1075 tgn10->tg_regs = &optc_regs[instance];
1076 tgn10->tg_shift = &optc_shift;
1077 tgn10->tg_mask = &optc_mask;
1078
1079 dcn31_timing_generator_init(tgn10);
1080
1081 return &tgn10->base;
1082 }
1083
1084 static const struct encoder_feature_support link_enc_feature = {
1085 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1086 .max_hdmi_pixel_clock = 600000,
1087 .hdmi_ycbcr420_supported = true,
1088 .dp_ycbcr420_supported = true,
1089 .fec_supported = true,
1090 .flags.bits.IS_HBR2_CAPABLE = true,
1091 .flags.bits.IS_HBR3_CAPABLE = true,
1092 .flags.bits.IS_TPS3_CAPABLE = true,
1093 .flags.bits.IS_TPS4_CAPABLE = true
1094 };
1095
dcn31_link_encoder_create(const struct encoder_init_data * enc_init_data)1096 static struct link_encoder *dcn31_link_encoder_create(
1097 const struct encoder_init_data *enc_init_data)
1098 {
1099 struct dcn20_link_encoder *enc20 =
1100 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1101
1102 if (!enc20)
1103 return NULL;
1104
1105 dcn31_link_encoder_construct(enc20,
1106 enc_init_data,
1107 &link_enc_feature,
1108 &link_enc_regs[enc_init_data->transmitter],
1109 &link_enc_aux_regs[enc_init_data->channel - 1],
1110 &link_enc_hpd_regs[enc_init_data->hpd_source],
1111 &le_shift,
1112 &le_mask);
1113
1114 return &enc20->enc10.base;
1115 }
1116
1117 /* Create a minimal link encoder object not associated with a particular
1118 * physical connector.
1119 * resource_funcs.link_enc_create_minimal
1120 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1121 static struct link_encoder *dcn31_link_enc_create_minimal(
1122 struct dc_context *ctx, enum engine_id eng_id)
1123 {
1124 struct dcn20_link_encoder *enc20;
1125
1126 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1127 return NULL;
1128
1129 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1130 if (!enc20)
1131 return NULL;
1132
1133 dcn31_link_encoder_construct_minimal(
1134 enc20,
1135 ctx,
1136 &link_enc_feature,
1137 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1138 eng_id);
1139
1140 return &enc20->enc10.base;
1141 }
1142
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1143 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1144 {
1145 struct dcn31_panel_cntl *panel_cntl =
1146 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1147
1148 if (!panel_cntl)
1149 return NULL;
1150
1151 dcn31_panel_cntl_construct(panel_cntl, init_data);
1152
1153 return &panel_cntl->base;
1154 }
1155
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1156 static void read_dce_straps(
1157 struct dc_context *ctx,
1158 struct resource_straps *straps)
1159 {
1160 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1161 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1162
1163 }
1164
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1165 static struct audio *dcn31_create_audio(
1166 struct dc_context *ctx, unsigned int inst)
1167 {
1168 return dce_audio_create(ctx, inst,
1169 &audio_regs[inst], &audio_shift, &audio_mask);
1170 }
1171
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1172 static struct vpg *dcn31_vpg_create(
1173 struct dc_context *ctx,
1174 uint32_t inst)
1175 {
1176 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1177
1178 if (!vpg31)
1179 return NULL;
1180
1181 vpg31_construct(vpg31, ctx, inst,
1182 &vpg_regs[inst],
1183 &vpg_shift,
1184 &vpg_mask);
1185
1186 return &vpg31->base;
1187 }
1188
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1189 static struct afmt *dcn31_afmt_create(
1190 struct dc_context *ctx,
1191 uint32_t inst)
1192 {
1193 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1194
1195 if (!afmt31)
1196 return NULL;
1197
1198 afmt31_construct(afmt31, ctx, inst,
1199 &afmt_regs[inst],
1200 &afmt_shift,
1201 &afmt_mask);
1202
1203 // Light sleep by default, no need to power down here
1204
1205 return &afmt31->base;
1206 }
1207
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1208 static struct apg *dcn31_apg_create(
1209 struct dc_context *ctx,
1210 uint32_t inst)
1211 {
1212 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1213
1214 if (!apg31)
1215 return NULL;
1216
1217 apg31_construct(apg31, ctx, inst,
1218 &apg_regs[inst],
1219 &apg_shift,
1220 &apg_mask);
1221
1222 return &apg31->base;
1223 }
1224
dcn31_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1225 static struct stream_encoder *dcn31_stream_encoder_create(
1226 enum engine_id eng_id,
1227 struct dc_context *ctx)
1228 {
1229 struct dcn10_stream_encoder *enc1;
1230 struct vpg *vpg;
1231 struct afmt *afmt;
1232 int vpg_inst;
1233 int afmt_inst;
1234
1235 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1236 if (eng_id <= ENGINE_ID_DIGF) {
1237 vpg_inst = eng_id;
1238 afmt_inst = eng_id;
1239 } else
1240 return NULL;
1241
1242 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1243 vpg = dcn31_vpg_create(ctx, vpg_inst);
1244 afmt = dcn31_afmt_create(ctx, afmt_inst);
1245
1246 if (!enc1 || !vpg || !afmt) {
1247 kfree(enc1);
1248 kfree(vpg);
1249 kfree(afmt);
1250 return NULL;
1251 }
1252
1253 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1254 eng_id, vpg, afmt,
1255 &stream_enc_regs[eng_id],
1256 &se_shift, &se_mask);
1257
1258 return &enc1->base;
1259 }
1260
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1261 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1262 enum engine_id eng_id,
1263 struct dc_context *ctx)
1264 {
1265 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1266 struct vpg *vpg;
1267 struct apg *apg;
1268 uint32_t hpo_dp_inst;
1269 uint32_t vpg_inst;
1270 uint32_t apg_inst;
1271
1272 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1273 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1274
1275 /* Mapping of VPG register blocks to HPO DP block instance:
1276 * VPG[6] -> HPO_DP[0]
1277 * VPG[7] -> HPO_DP[1]
1278 * VPG[8] -> HPO_DP[2]
1279 * VPG[9] -> HPO_DP[3]
1280 */
1281 vpg_inst = hpo_dp_inst + 6;
1282
1283 /* Mapping of APG register blocks to HPO DP block instance:
1284 * APG[0] -> HPO_DP[0]
1285 * APG[1] -> HPO_DP[1]
1286 * APG[2] -> HPO_DP[2]
1287 * APG[3] -> HPO_DP[3]
1288 */
1289 apg_inst = hpo_dp_inst;
1290
1291 /* allocate HPO stream encoder and create VPG sub-block */
1292 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1293 vpg = dcn31_vpg_create(ctx, vpg_inst);
1294 apg = dcn31_apg_create(ctx, apg_inst);
1295
1296 if (!hpo_dp_enc31 || !vpg || !apg) {
1297 kfree(hpo_dp_enc31);
1298 kfree(vpg);
1299 kfree(apg);
1300 return NULL;
1301 }
1302
1303 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1304 hpo_dp_inst, eng_id, vpg, apg,
1305 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1306 &hpo_dp_se_shift, &hpo_dp_se_mask);
1307
1308 return &hpo_dp_enc31->base;
1309 }
1310
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1311 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1312 uint8_t inst,
1313 struct dc_context *ctx)
1314 {
1315 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1316
1317 /* allocate HPO link encoder */
1318 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1319
1320 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1321 &hpo_dp_link_enc_regs[inst],
1322 &hpo_dp_le_shift, &hpo_dp_le_mask);
1323
1324 return &hpo_dp_enc31->base;
1325 }
1326
dcn31_hwseq_create(struct dc_context * ctx)1327 static struct dce_hwseq *dcn31_hwseq_create(
1328 struct dc_context *ctx)
1329 {
1330 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1331
1332 if (hws) {
1333 hws->ctx = ctx;
1334 hws->regs = &hwseq_reg;
1335 hws->shifts = &hwseq_shift;
1336 hws->masks = &hwseq_mask;
1337 /* DCN3.1 FPGA Workaround
1338 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1339 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1340 * function core_link_enable_stream
1341 */
1342 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1343 hws->wa.dp_hpo_and_otg_sequence = true;
1344 }
1345 return hws;
1346 }
1347 static const struct resource_create_funcs res_create_funcs = {
1348 .read_dce_straps = read_dce_straps,
1349 .create_audio = dcn31_create_audio,
1350 .create_stream_encoder = dcn31_stream_encoder_create,
1351 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1352 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1353 .create_hwseq = dcn31_hwseq_create,
1354 };
1355
1356 static const struct resource_create_funcs res_create_maximus_funcs = {
1357 .read_dce_straps = NULL,
1358 .create_audio = NULL,
1359 .create_stream_encoder = NULL,
1360 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1361 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1362 .create_hwseq = dcn31_hwseq_create,
1363 };
1364
dcn31_resource_destruct(struct dcn31_resource_pool * pool)1365 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1366 {
1367 unsigned int i;
1368
1369 for (i = 0; i < pool->base.stream_enc_count; i++) {
1370 if (pool->base.stream_enc[i] != NULL) {
1371 if (pool->base.stream_enc[i]->vpg != NULL) {
1372 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1373 pool->base.stream_enc[i]->vpg = NULL;
1374 }
1375 if (pool->base.stream_enc[i]->afmt != NULL) {
1376 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1377 pool->base.stream_enc[i]->afmt = NULL;
1378 }
1379 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1380 pool->base.stream_enc[i] = NULL;
1381 }
1382 }
1383
1384 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1385 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1386 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1387 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1388 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1389 }
1390 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1391 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1392 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1393 }
1394 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1395 pool->base.hpo_dp_stream_enc[i] = NULL;
1396 }
1397 }
1398
1399 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1400 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1401 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1402 pool->base.hpo_dp_link_enc[i] = NULL;
1403 }
1404 }
1405
1406 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1407 if (pool->base.dscs[i] != NULL)
1408 dcn20_dsc_destroy(&pool->base.dscs[i]);
1409 }
1410
1411 if (pool->base.mpc != NULL) {
1412 kfree(TO_DCN20_MPC(pool->base.mpc));
1413 pool->base.mpc = NULL;
1414 }
1415 if (pool->base.hubbub != NULL) {
1416 kfree(pool->base.hubbub);
1417 pool->base.hubbub = NULL;
1418 }
1419 for (i = 0; i < pool->base.pipe_count; i++) {
1420 if (pool->base.dpps[i] != NULL)
1421 dcn31_dpp_destroy(&pool->base.dpps[i]);
1422
1423 if (pool->base.ipps[i] != NULL)
1424 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1425
1426 if (pool->base.hubps[i] != NULL) {
1427 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1428 pool->base.hubps[i] = NULL;
1429 }
1430
1431 if (pool->base.irqs != NULL) {
1432 dal_irq_service_destroy(&pool->base.irqs);
1433 }
1434 }
1435
1436 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1437 if (pool->base.engines[i] != NULL)
1438 dce110_engine_destroy(&pool->base.engines[i]);
1439 if (pool->base.hw_i2cs[i] != NULL) {
1440 kfree(pool->base.hw_i2cs[i]);
1441 pool->base.hw_i2cs[i] = NULL;
1442 }
1443 if (pool->base.sw_i2cs[i] != NULL) {
1444 kfree(pool->base.sw_i2cs[i]);
1445 pool->base.sw_i2cs[i] = NULL;
1446 }
1447 }
1448
1449 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1450 if (pool->base.opps[i] != NULL)
1451 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1452 }
1453
1454 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1455 if (pool->base.timing_generators[i] != NULL) {
1456 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1457 pool->base.timing_generators[i] = NULL;
1458 }
1459 }
1460
1461 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1462 if (pool->base.dwbc[i] != NULL) {
1463 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1464 pool->base.dwbc[i] = NULL;
1465 }
1466 if (pool->base.mcif_wb[i] != NULL) {
1467 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1468 pool->base.mcif_wb[i] = NULL;
1469 }
1470 }
1471
1472 for (i = 0; i < pool->base.audio_count; i++) {
1473 if (pool->base.audios[i])
1474 dce_aud_destroy(&pool->base.audios[i]);
1475 }
1476
1477 for (i = 0; i < pool->base.clk_src_count; i++) {
1478 if (pool->base.clock_sources[i] != NULL) {
1479 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1480 pool->base.clock_sources[i] = NULL;
1481 }
1482 }
1483
1484 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1485 if (pool->base.mpc_lut[i] != NULL) {
1486 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1487 pool->base.mpc_lut[i] = NULL;
1488 }
1489 if (pool->base.mpc_shaper[i] != NULL) {
1490 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1491 pool->base.mpc_shaper[i] = NULL;
1492 }
1493 }
1494
1495 if (pool->base.dp_clock_source != NULL) {
1496 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1497 pool->base.dp_clock_source = NULL;
1498 }
1499
1500 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1501 if (pool->base.multiple_abms[i] != NULL)
1502 dce_abm_destroy(&pool->base.multiple_abms[i]);
1503 }
1504
1505 if (pool->base.psr != NULL)
1506 dmub_psr_destroy(&pool->base.psr);
1507
1508 if (pool->base.dccg != NULL)
1509 dcn_dccg_destroy(&pool->base.dccg);
1510 }
1511
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1512 static struct hubp *dcn31_hubp_create(
1513 struct dc_context *ctx,
1514 uint32_t inst)
1515 {
1516 struct dcn20_hubp *hubp2 =
1517 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1518
1519 if (!hubp2)
1520 return NULL;
1521
1522 if (hubp31_construct(hubp2, ctx, inst,
1523 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1524 return &hubp2->base;
1525
1526 BREAK_TO_DEBUGGER();
1527 kfree(hubp2);
1528 return NULL;
1529 }
1530
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1531 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1532 {
1533 int i;
1534 uint32_t pipe_count = pool->res_cap->num_dwb;
1535
1536 for (i = 0; i < pipe_count; i++) {
1537 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1538 GFP_KERNEL);
1539
1540 if (!dwbc30) {
1541 dm_error("DC: failed to create dwbc30!\n");
1542 return false;
1543 }
1544
1545 dcn30_dwbc_construct(dwbc30, ctx,
1546 &dwbc30_regs[i],
1547 &dwbc30_shift,
1548 &dwbc30_mask,
1549 i);
1550
1551 pool->dwbc[i] = &dwbc30->base;
1552 }
1553 return true;
1554 }
1555
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1556 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1557 {
1558 int i;
1559 uint32_t pipe_count = pool->res_cap->num_dwb;
1560
1561 for (i = 0; i < pipe_count; i++) {
1562 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1563 GFP_KERNEL);
1564
1565 if (!mcif_wb30) {
1566 dm_error("DC: failed to create mcif_wb30!\n");
1567 return false;
1568 }
1569
1570 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1571 &mcif_wb30_regs[i],
1572 &mcif_wb30_shift,
1573 &mcif_wb30_mask,
1574 i);
1575
1576 pool->mcif_wb[i] = &mcif_wb30->base;
1577 }
1578 return true;
1579 }
1580
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1581 static struct display_stream_compressor *dcn31_dsc_create(
1582 struct dc_context *ctx, uint32_t inst)
1583 {
1584 struct dcn20_dsc *dsc =
1585 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1586
1587 if (!dsc) {
1588 BREAK_TO_DEBUGGER();
1589 return NULL;
1590 }
1591
1592 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1593 return &dsc->base;
1594 }
1595
dcn31_destroy_resource_pool(struct resource_pool ** pool)1596 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1597 {
1598 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1599
1600 dcn31_resource_destruct(dcn31_pool);
1601 kfree(dcn31_pool);
1602 *pool = NULL;
1603 }
1604
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1605 static struct clock_source *dcn31_clock_source_create(
1606 struct dc_context *ctx,
1607 struct dc_bios *bios,
1608 enum clock_source_id id,
1609 const struct dce110_clk_src_regs *regs,
1610 bool dp_clk_src)
1611 {
1612 struct dce110_clk_src *clk_src =
1613 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1614
1615 if (!clk_src)
1616 return NULL;
1617
1618 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1619 regs, &cs_shift, &cs_mask)) {
1620 clk_src->base.dp_clk_src = dp_clk_src;
1621 return &clk_src->base;
1622 }
1623
1624 BREAK_TO_DEBUGGER();
1625 return NULL;
1626 }
1627
is_dual_plane(enum surface_pixel_format format)1628 static bool is_dual_plane(enum surface_pixel_format format)
1629 {
1630 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1631 }
1632
dcn31_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1633 int dcn31_populate_dml_pipes_from_context(
1634 struct dc *dc, struct dc_state *context,
1635 display_e2e_pipe_params_st *pipes,
1636 bool fast_validate)
1637 {
1638 int i, pipe_cnt;
1639 struct resource_context *res_ctx = &context->res_ctx;
1640 struct pipe_ctx *pipe;
1641 bool upscaled = false;
1642
1643 DC_FP_START();
1644 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1645 DC_FP_END();
1646
1647 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1648 struct dc_crtc_timing *timing;
1649
1650 if (!res_ctx->pipe_ctx[i].stream)
1651 continue;
1652 pipe = &res_ctx->pipe_ctx[i];
1653 timing = &pipe->stream->timing;
1654
1655 if (pipe->plane_state &&
1656 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1657 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1658 upscaled = true;
1659
1660 /*
1661 * Immediate flip can be set dynamically after enabling the plane.
1662 * We need to require support for immediate flip or underflow can be
1663 * intermittently experienced depending on peak b/w requirements.
1664 */
1665 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1666 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1667 pipes[pipe_cnt].pipe.src.gpuvm = true;
1668 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1669 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1670 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1671 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1672 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1673
1674 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)
1675 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1676 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
1677 pipes[pipe_cnt].pipe.src.hostvm = false;
1678 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
1679 pipes[pipe_cnt].pipe.src.hostvm = true;
1680
1681 if (pipes[pipe_cnt].dout.dsc_enable) {
1682 switch (timing->display_color_depth) {
1683 case COLOR_DEPTH_888:
1684 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1685 break;
1686 case COLOR_DEPTH_101010:
1687 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1688 break;
1689 case COLOR_DEPTH_121212:
1690 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1691 break;
1692 default:
1693 ASSERT(0);
1694 break;
1695 }
1696 }
1697
1698 pipe_cnt++;
1699 }
1700 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1701 dc->config.enable_4to1MPC = false;
1702 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1703 if (is_dual_plane(pipe->plane_state->format)
1704 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1705 dc->config.enable_4to1MPC = true;
1706 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1707 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1708 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1709 pipes[0].pipe.src.unbounded_req_mode = true;
1710 }
1711 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1712 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1713 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1714 } else if (context->stream_count >= 3 && upscaled) {
1715 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1716 }
1717
1718 return pipe_cnt;
1719 }
1720
dcn31_update_soc_for_wm_a(struct dc * dc,struct dc_state * context)1721 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
1722 {
1723 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
1724 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
1725 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
1726 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
1727 }
1728 }
1729
dcn31_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1730 void dcn31_calculate_wm_and_dlg(
1731 struct dc *dc, struct dc_state *context,
1732 display_e2e_pipe_params_st *pipes,
1733 int pipe_cnt,
1734 int vlevel)
1735 {
1736 DC_FP_START();
1737 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1738 DC_FP_END();
1739 }
1740
1741 void
dcn31_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1742 dcn31_populate_dml_writeback_from_context(struct dc *dc,
1743 struct resource_context *res_ctx,
1744 display_e2e_pipe_params_st *pipes)
1745 {
1746 DC_FP_START();
1747 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1748 DC_FP_END();
1749 }
1750
1751 void
dcn31_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1752 dcn31_set_mcif_arb_params(struct dc *dc,
1753 struct dc_state *context,
1754 display_e2e_pipe_params_st *pipes,
1755 int pipe_cnt)
1756 {
1757 DC_FP_START();
1758 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1759 DC_FP_END();
1760 }
1761
dcn31_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1762 bool dcn31_validate_bandwidth(struct dc *dc,
1763 struct dc_state *context,
1764 bool fast_validate)
1765 {
1766 bool out = false;
1767
1768 BW_VAL_TRACE_SETUP();
1769
1770 int vlevel = 0;
1771 int pipe_cnt = 0;
1772 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1773 DC_LOGGER_INIT(dc->ctx->logger);
1774
1775 BW_VAL_TRACE_COUNT();
1776
1777 DC_FP_START();
1778 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1779 DC_FP_END();
1780
1781 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
1782 if (pipe_cnt == 0)
1783 fast_validate = false;
1784
1785 if (!out)
1786 goto validate_fail;
1787
1788 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1789
1790 if (fast_validate) {
1791 BW_VAL_TRACE_SKIP(fast);
1792 goto validate_out;
1793 }
1794
1795 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1796
1797 BW_VAL_TRACE_END_WATERMARKS();
1798
1799 goto validate_out;
1800
1801 validate_fail:
1802 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1803 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1804
1805 BW_VAL_TRACE_SKIP(fail);
1806 out = false;
1807
1808 validate_out:
1809 kfree(pipes);
1810
1811 BW_VAL_TRACE_FINISH();
1812
1813 return out;
1814 }
1815
1816 static struct dc_cap_funcs cap_funcs = {
1817 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1818 };
1819
1820 static struct resource_funcs dcn31_res_pool_funcs = {
1821 .destroy = dcn31_destroy_resource_pool,
1822 .link_enc_create = dcn31_link_encoder_create,
1823 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1824 .link_encs_assign = link_enc_cfg_link_encs_assign,
1825 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1826 .panel_cntl_create = dcn31_panel_cntl_create,
1827 .validate_bandwidth = dcn31_validate_bandwidth,
1828 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1829 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1830 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1831 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1832 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1833 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1834 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1835 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1836 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1837 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1838 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1839 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1840 .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1841 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1842 };
1843
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1844 static struct clock_source *dcn30_clock_source_create(
1845 struct dc_context *ctx,
1846 struct dc_bios *bios,
1847 enum clock_source_id id,
1848 const struct dce110_clk_src_regs *regs,
1849 bool dp_clk_src)
1850 {
1851 struct dce110_clk_src *clk_src =
1852 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1853
1854 if (!clk_src)
1855 return NULL;
1856
1857 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1858 regs, &cs_shift, &cs_mask)) {
1859 clk_src->base.dp_clk_src = dp_clk_src;
1860 return &clk_src->base;
1861 }
1862
1863 BREAK_TO_DEBUGGER();
1864 return NULL;
1865 }
1866
dcn31_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn31_resource_pool * pool)1867 static bool dcn31_resource_construct(
1868 uint8_t num_virtual_links,
1869 struct dc *dc,
1870 struct dcn31_resource_pool *pool)
1871 {
1872 int i;
1873 struct dc_context *ctx = dc->ctx;
1874 struct irq_service_init_data init_data;
1875
1876 DC_FP_START();
1877
1878 ctx->dc_bios->regs = &bios_regs;
1879
1880 pool->base.res_cap = &res_cap_dcn31;
1881
1882 pool->base.funcs = &dcn31_res_pool_funcs;
1883
1884 /*************************************************
1885 * Resource + asic cap harcoding *
1886 *************************************************/
1887 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1888 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1889 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1890 dc->caps.max_downscale_ratio = 600;
1891 dc->caps.i2c_speed_in_khz = 100;
1892 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1893 dc->caps.max_cursor_size = 256;
1894 dc->caps.min_horizontal_blanking_period = 80;
1895 dc->caps.dmdata_alloc_size = 2048;
1896
1897 dc->caps.max_slave_planes = 2;
1898 dc->caps.max_slave_yuv_planes = 2;
1899 dc->caps.max_slave_rgb_planes = 2;
1900 dc->caps.post_blend_color_processing = true;
1901 dc->caps.force_dp_tps4_for_cp2520 = true;
1902 dc->caps.dp_hpo = true;
1903 dc->caps.hdmi_frl_pcon_support = true;
1904 dc->caps.edp_dsc_support = true;
1905 dc->caps.extended_aux_timeout_support = true;
1906 dc->caps.dmcub_support = true;
1907 dc->caps.is_apu = true;
1908 dc->caps.zstate_support = true;
1909
1910 /* Color pipeline capabilities */
1911 dc->caps.color.dpp.dcn_arch = 1;
1912 dc->caps.color.dpp.input_lut_shared = 0;
1913 dc->caps.color.dpp.icsc = 1;
1914 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1915 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1916 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1917 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1918 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1919 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1920 dc->caps.color.dpp.post_csc = 1;
1921 dc->caps.color.dpp.gamma_corr = 1;
1922 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1923
1924 dc->caps.color.dpp.hw_3d_lut = 1;
1925 dc->caps.color.dpp.ogam_ram = 1;
1926 // no OGAM ROM on DCN301
1927 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1928 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1929 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1930 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1931 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1932 dc->caps.color.dpp.ocsc = 0;
1933
1934 dc->caps.color.mpc.gamut_remap = 1;
1935 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1936 dc->caps.color.mpc.ogam_ram = 1;
1937 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1938 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1939 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1940 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1941 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1942 dc->caps.color.mpc.ocsc = 1;
1943
1944 /* Use pipe context based otg sync logic */
1945 dc->config.use_pipe_ctx_sync_logic = true;
1946
1947 /* read VBIOS LTTPR caps */
1948 {
1949 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1950 enum bp_result bp_query_result;
1951 uint8_t is_vbios_lttpr_enable = 0;
1952
1953 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1954 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1955 }
1956
1957 /* interop bit is implicit */
1958 {
1959 dc->caps.vbios_lttpr_aware = true;
1960 }
1961 }
1962
1963 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1964 dc->debug = debug_defaults_drv;
1965 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1966 dc->debug = debug_defaults_diags;
1967 } else
1968 dc->debug = debug_defaults_diags;
1969 // Init the vm_helper
1970 if (dc->vm_helper)
1971 vm_helper_init(dc->vm_helper, 16);
1972
1973 /*************************************************
1974 * Create resources *
1975 *************************************************/
1976
1977 /* Clock Sources for Pixel Clock*/
1978 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1979 dcn30_clock_source_create(ctx, ctx->dc_bios,
1980 CLOCK_SOURCE_COMBO_PHY_PLL0,
1981 &clk_src_regs[0], false);
1982 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1983 dcn30_clock_source_create(ctx, ctx->dc_bios,
1984 CLOCK_SOURCE_COMBO_PHY_PLL1,
1985 &clk_src_regs[1], false);
1986 /*move phypllx_pixclk_resync to dmub next*/
1987 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1988 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1989 dcn30_clock_source_create(ctx, ctx->dc_bios,
1990 CLOCK_SOURCE_COMBO_PHY_PLL2,
1991 &clk_src_regs_b0[2], false);
1992 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1993 dcn30_clock_source_create(ctx, ctx->dc_bios,
1994 CLOCK_SOURCE_COMBO_PHY_PLL3,
1995 &clk_src_regs_b0[3], false);
1996 } else {
1997 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1998 dcn30_clock_source_create(ctx, ctx->dc_bios,
1999 CLOCK_SOURCE_COMBO_PHY_PLL2,
2000 &clk_src_regs[2], false);
2001 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2002 dcn30_clock_source_create(ctx, ctx->dc_bios,
2003 CLOCK_SOURCE_COMBO_PHY_PLL3,
2004 &clk_src_regs[3], false);
2005 }
2006
2007 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2008 dcn30_clock_source_create(ctx, ctx->dc_bios,
2009 CLOCK_SOURCE_COMBO_PHY_PLL4,
2010 &clk_src_regs[4], false);
2011
2012 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2013
2014 /* todo: not reuse phy_pll registers */
2015 pool->base.dp_clock_source =
2016 dcn31_clock_source_create(ctx, ctx->dc_bios,
2017 CLOCK_SOURCE_ID_DP_DTO,
2018 &clk_src_regs[0], true);
2019
2020 for (i = 0; i < pool->base.clk_src_count; i++) {
2021 if (pool->base.clock_sources[i] == NULL) {
2022 dm_error("DC: failed to create clock sources!\n");
2023 BREAK_TO_DEBUGGER();
2024 goto create_fail;
2025 }
2026 }
2027
2028 /* TODO: DCCG */
2029 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2030 if (pool->base.dccg == NULL) {
2031 dm_error("DC: failed to create dccg!\n");
2032 BREAK_TO_DEBUGGER();
2033 goto create_fail;
2034 }
2035
2036 /* TODO: IRQ */
2037 init_data.ctx = dc->ctx;
2038 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2039 if (!pool->base.irqs)
2040 goto create_fail;
2041
2042 /* HUBBUB */
2043 pool->base.hubbub = dcn31_hubbub_create(ctx);
2044 if (pool->base.hubbub == NULL) {
2045 BREAK_TO_DEBUGGER();
2046 dm_error("DC: failed to create hubbub!\n");
2047 goto create_fail;
2048 }
2049
2050 /* HUBPs, DPPs, OPPs and TGs */
2051 for (i = 0; i < pool->base.pipe_count; i++) {
2052 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2053 if (pool->base.hubps[i] == NULL) {
2054 BREAK_TO_DEBUGGER();
2055 dm_error(
2056 "DC: failed to create hubps!\n");
2057 goto create_fail;
2058 }
2059
2060 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2061 if (pool->base.dpps[i] == NULL) {
2062 BREAK_TO_DEBUGGER();
2063 dm_error(
2064 "DC: failed to create dpps!\n");
2065 goto create_fail;
2066 }
2067 }
2068
2069 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2070 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2071 if (pool->base.opps[i] == NULL) {
2072 BREAK_TO_DEBUGGER();
2073 dm_error(
2074 "DC: failed to create output pixel processor!\n");
2075 goto create_fail;
2076 }
2077 }
2078
2079 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2080 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2081 ctx, i);
2082 if (pool->base.timing_generators[i] == NULL) {
2083 BREAK_TO_DEBUGGER();
2084 dm_error("DC: failed to create tg!\n");
2085 goto create_fail;
2086 }
2087 }
2088 pool->base.timing_generator_count = i;
2089
2090 /* PSR */
2091 pool->base.psr = dmub_psr_create(ctx);
2092 if (pool->base.psr == NULL) {
2093 dm_error("DC: failed to create psr obj!\n");
2094 BREAK_TO_DEBUGGER();
2095 goto create_fail;
2096 }
2097
2098 /* ABM */
2099 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2100 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2101 &abm_regs[i],
2102 &abm_shift,
2103 &abm_mask);
2104 if (pool->base.multiple_abms[i] == NULL) {
2105 dm_error("DC: failed to create abm for pipe %d!\n", i);
2106 BREAK_TO_DEBUGGER();
2107 goto create_fail;
2108 }
2109 }
2110
2111 /* MPC and DSC */
2112 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2113 if (pool->base.mpc == NULL) {
2114 BREAK_TO_DEBUGGER();
2115 dm_error("DC: failed to create mpc!\n");
2116 goto create_fail;
2117 }
2118
2119 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2120 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2121 if (pool->base.dscs[i] == NULL) {
2122 BREAK_TO_DEBUGGER();
2123 dm_error("DC: failed to create display stream compressor %d!\n", i);
2124 goto create_fail;
2125 }
2126 }
2127
2128 /* DWB and MMHUBBUB */
2129 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2130 BREAK_TO_DEBUGGER();
2131 dm_error("DC: failed to create dwbc!\n");
2132 goto create_fail;
2133 }
2134
2135 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2136 BREAK_TO_DEBUGGER();
2137 dm_error("DC: failed to create mcif_wb!\n");
2138 goto create_fail;
2139 }
2140
2141 /* AUX and I2C */
2142 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2143 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2144 if (pool->base.engines[i] == NULL) {
2145 BREAK_TO_DEBUGGER();
2146 dm_error(
2147 "DC:failed to create aux engine!!\n");
2148 goto create_fail;
2149 }
2150 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2151 if (pool->base.hw_i2cs[i] == NULL) {
2152 BREAK_TO_DEBUGGER();
2153 dm_error(
2154 "DC:failed to create hw i2c!!\n");
2155 goto create_fail;
2156 }
2157 pool->base.sw_i2cs[i] = NULL;
2158 }
2159
2160 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2161 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2162 !dc->debug.dpia_debug.bits.disable_dpia) {
2163 /* YELLOW CARP B0 has 4 DPIA's */
2164 pool->base.usb4_dpia_count = 4;
2165 }
2166
2167 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2168 if (!resource_construct(num_virtual_links, dc, &pool->base,
2169 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2170 &res_create_funcs : &res_create_maximus_funcs)))
2171 goto create_fail;
2172
2173 /* HW Sequencer and Plane caps */
2174 dcn31_hw_sequencer_construct(dc);
2175
2176 dc->caps.max_planes = pool->base.pipe_count;
2177
2178 for (i = 0; i < dc->caps.max_planes; ++i)
2179 dc->caps.planes[i] = plane_cap;
2180
2181 dc->cap_funcs = cap_funcs;
2182
2183 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2184
2185 DC_FP_END();
2186
2187 return true;
2188
2189 create_fail:
2190
2191 DC_FP_END();
2192 dcn31_resource_destruct(pool);
2193
2194 return false;
2195 }
2196
dcn31_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2197 struct resource_pool *dcn31_create_resource_pool(
2198 const struct dc_init_data *init_data,
2199 struct dc *dc)
2200 {
2201 struct dcn31_resource_pool *pool =
2202 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2203
2204 if (!pool)
2205 return NULL;
2206
2207 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2208 return &pool->base;
2209
2210 BREAK_TO_DEBUGGER();
2211 kfree(pool);
2212 return NULL;
2213 }
2214