1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33
34 // For dcn20_update_clocks_update_dpp_dto
35 #include "dcn20/dcn20_clk_mgr.h"
36
37
38
39 #include "dcn31_clk_mgr.h"
40
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn31_smu.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48
49 #include "dc_dmub_srv.h"
50
51 #include "logger_types.h"
52 #undef DC_LOGGER
53 #define DC_LOGGER \
54 clk_mgr->base.base.ctx->logger
55
56 #include "yellow_carp_offset.h"
57
58 #define regCLK1_CLK_PLL_REQ 0x0237
59 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
60
61 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
62 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
63 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
64 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
65 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
66 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
67
68 #define REG(reg_name) \
69 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
70
71 #define TO_CLK_MGR_DCN31(clk_mgr)\
72 container_of(clk_mgr, struct clk_mgr_dcn31, base)
73
dcn31_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)74 static int dcn31_get_active_display_cnt_wa(
75 struct dc *dc,
76 struct dc_state *context)
77 {
78 int i, display_count;
79 bool tmds_present = false;
80
81 display_count = 0;
82 for (i = 0; i < context->stream_count; i++) {
83 const struct dc_stream_state *stream = context->streams[i];
84
85 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
86 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
87 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
88 tmds_present = true;
89 }
90
91 for (i = 0; i < dc->link_count; i++) {
92 const struct dc_link *link = dc->links[i];
93
94 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
95 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
96 link->link_enc->funcs->is_dig_enabled(link->link_enc))
97 display_count++;
98 }
99
100 /* WA for hang on HDMI after display off back back on*/
101 if (display_count == 0 && tmds_present)
102 display_count = 1;
103
104 return display_count;
105 }
106
dcn31_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool disable)107 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
108 {
109 struct dc *dc = clk_mgr_base->ctx->dc;
110 int i;
111
112 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
113 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
114
115 if (pipe->top_pipe || pipe->prev_odm_pipe)
116 continue;
117 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
118 if (disable) {
119 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
120 reset_sync_context_for_pipe(dc, context, i);
121 } else
122 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
123 }
124 }
125 }
126
dcn31_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)127 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
128 struct dc_state *context,
129 bool safe_to_lower)
130 {
131 union dmub_rb_cmd cmd;
132 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
133 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
134 struct dc *dc = clk_mgr_base->ctx->dc;
135 int display_count;
136 bool update_dppclk = false;
137 bool update_dispclk = false;
138 bool dpp_clock_lowered = false;
139
140 if (dc->work_arounds.skip_clock_update)
141 return;
142
143 /*
144 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
145 * also if safe to lower is false, we just go in the higher state
146 */
147 if (safe_to_lower) {
148 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
149 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
150 dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
151 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
152 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
153 }
154
155 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
156 dcn31_smu_set_dtbclk(clk_mgr, false);
157 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
158 }
159 /* check that we're not already in lower */
160 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
161 display_count = dcn31_get_active_display_cnt_wa(dc, context);
162 /* if we can go lower, go lower */
163 if (display_count == 0) {
164 union display_idle_optimization_u idle_info = { 0 };
165 idle_info.idle_info.df_request_disabled = 1;
166 idle_info.idle_info.phy_ref_clk_off = 1;
167 idle_info.idle_info.s0i2_rdy = 1;
168 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
169 /* update power state */
170 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
171 }
172 }
173 } else {
174 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
175 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
176 dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
177 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
178 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
179 }
180
181 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
182 dcn31_smu_set_dtbclk(clk_mgr, true);
183 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
184 }
185
186 /* check that we're not already in D0 */
187 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
188 union display_idle_optimization_u idle_info = { 0 };
189 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
190 /* update power state */
191 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
192 }
193 }
194
195 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
196 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
197 dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
198 }
199
200 if (should_set_clock(safe_to_lower,
201 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
202 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
203 dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
204 }
205
206 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
207 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
208 if (new_clocks->dppclk_khz < 100000)
209 new_clocks->dppclk_khz = 100000;
210 }
211
212 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
213 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
214 dpp_clock_lowered = true;
215 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
216 update_dppclk = true;
217 }
218
219 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
220 dcn31_disable_otg_wa(clk_mgr_base, context, true);
221
222 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
223 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
224 dcn31_disable_otg_wa(clk_mgr_base, context, false);
225
226 update_dispclk = true;
227 }
228
229 if (dpp_clock_lowered) {
230 // increase per DPP DTO before lowering global dppclk
231 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
232 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
233 } else {
234 // increase global DPPCLK before lowering per DPP DTO
235 if (update_dppclk || update_dispclk)
236 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
237 // always update dtos unless clock is lowered and not safe to lower
238 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
239 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
240 }
241
242 // notify DMCUB of latest clocks
243 memset(&cmd, 0, sizeof(cmd));
244 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
245 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
246 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
247 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
248 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
249 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
250 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
251
252 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
253 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
254 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
255 }
256
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)257 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
258 {
259 /* get FbMult value */
260 struct fixed31_32 pll_req;
261 unsigned int fbmult_frac_val = 0;
262 unsigned int fbmult_int_val = 0;
263
264 /*
265 * Register value of fbmult is in 8.16 format, we are converting to 31.32
266 * to leverage the fix point operations available in driver
267 */
268
269 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
270 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
271
272 pll_req = dc_fixpt_from_int(fbmult_int_val);
273
274 /*
275 * since fractional part is only 16 bit in register definition but is 32 bit
276 * in our fix point definiton, need to shift left by 16 to obtain correct value
277 */
278 pll_req.value |= fbmult_frac_val << 16;
279
280 /* multiply by REFCLK period */
281 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
282
283 /* integer part is now VCO frequency in kHz */
284 return dc_fixpt_floor(pll_req);
285 }
286
dcn31_enable_pme_wa(struct clk_mgr * clk_mgr_base)287 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
288 {
289 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
290
291 dcn31_smu_enable_pme_wa(clk_mgr);
292 }
293
dcn31_init_clocks(struct clk_mgr * clk_mgr)294 void dcn31_init_clocks(struct clk_mgr *clk_mgr)
295 {
296 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
297
298 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
299 // Assumption is that boot state always supports pstate
300 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
301 clk_mgr->clks.p_state_change_support = true;
302 clk_mgr->clks.prev_p_state_change_support = true;
303 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
304 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
305 }
306
dcn31_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)307 bool dcn31_are_clock_states_equal(struct dc_clocks *a,
308 struct dc_clocks *b)
309 {
310 if (a->dispclk_khz != b->dispclk_khz)
311 return false;
312 else if (a->dppclk_khz != b->dppclk_khz)
313 return false;
314 else if (a->dcfclk_khz != b->dcfclk_khz)
315 return false;
316 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
317 return false;
318 else if (a->zstate_support != b->zstate_support)
319 return false;
320 else if (a->dtbclk_en != b->dtbclk_en)
321 return false;
322
323 return true;
324 }
325
dcn31_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)326 static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
327 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
328 {
329 return;
330 }
331
332 static struct clk_bw_params dcn31_bw_params = {
333 .vram_type = Ddr4MemType,
334 .num_channels = 1,
335 .clk_table = {
336 .num_entries = 4,
337 },
338
339 };
340
341 static struct wm_table ddr5_wm_table = {
342 .entries = {
343 {
344 .wm_inst = WM_A,
345 .wm_type = WM_TYPE_PSTATE_CHG,
346 .pstate_latency_us = 11.72,
347 .sr_exit_time_us = 9,
348 .sr_enter_plus_exit_time_us = 11,
349 .valid = true,
350 },
351 {
352 .wm_inst = WM_B,
353 .wm_type = WM_TYPE_PSTATE_CHG,
354 .pstate_latency_us = 11.72,
355 .sr_exit_time_us = 9,
356 .sr_enter_plus_exit_time_us = 11,
357 .valid = true,
358 },
359 {
360 .wm_inst = WM_C,
361 .wm_type = WM_TYPE_PSTATE_CHG,
362 .pstate_latency_us = 11.72,
363 .sr_exit_time_us = 9,
364 .sr_enter_plus_exit_time_us = 11,
365 .valid = true,
366 },
367 {
368 .wm_inst = WM_D,
369 .wm_type = WM_TYPE_PSTATE_CHG,
370 .pstate_latency_us = 11.72,
371 .sr_exit_time_us = 9,
372 .sr_enter_plus_exit_time_us = 11,
373 .valid = true,
374 },
375 }
376 };
377
378 static struct wm_table lpddr5_wm_table = {
379 .entries = {
380 {
381 .wm_inst = WM_A,
382 .wm_type = WM_TYPE_PSTATE_CHG,
383 .pstate_latency_us = 11.65333,
384 .sr_exit_time_us = 11.5,
385 .sr_enter_plus_exit_time_us = 14.5,
386 .valid = true,
387 },
388 {
389 .wm_inst = WM_B,
390 .wm_type = WM_TYPE_PSTATE_CHG,
391 .pstate_latency_us = 11.65333,
392 .sr_exit_time_us = 11.5,
393 .sr_enter_plus_exit_time_us = 14.5,
394 .valid = true,
395 },
396 {
397 .wm_inst = WM_C,
398 .wm_type = WM_TYPE_PSTATE_CHG,
399 .pstate_latency_us = 11.65333,
400 .sr_exit_time_us = 11.5,
401 .sr_enter_plus_exit_time_us = 14.5,
402 .valid = true,
403 },
404 {
405 .wm_inst = WM_D,
406 .wm_type = WM_TYPE_PSTATE_CHG,
407 .pstate_latency_us = 11.65333,
408 .sr_exit_time_us = 11.5,
409 .sr_enter_plus_exit_time_us = 14.5,
410 .valid = true,
411 },
412 }
413 };
414
415 static DpmClocks_t dummy_clocks;
416
417 static struct dcn31_watermarks dummy_wms = { 0 };
418
dcn31_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn31_watermarks * table)419 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
420 {
421 int i, num_valid_sets;
422
423 num_valid_sets = 0;
424
425 for (i = 0; i < WM_SET_COUNT; i++) {
426 /* skip empty entries, the smu array has no holes*/
427 if (!bw_params->wm_table.entries[i].valid)
428 continue;
429
430 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
431 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
432 /* We will not select WM based on fclk, so leave it as unconstrained */
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
434 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
435
436 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
437 if (i == 0)
438 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
439 else {
440 /* add 1 to make it non-overlapping with next lvl */
441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
442 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
443 }
444 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
445 bw_params->clk_table.entries[i].dcfclk_mhz;
446
447 } else {
448 /* unconstrained for memory retraining */
449 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
451
452 /* Modify previous watermark range to cover up to max */
453 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
454 }
455 num_valid_sets++;
456 }
457
458 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
459
460 /* modify the min and max to make sure we cover the whole range*/
461 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
462 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
463 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
464 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
465
466 /* This is for writeback only, does not matter currently as no writeback support*/
467 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
468 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
469 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
470 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
471 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
472 }
473
dcn31_notify_wm_ranges(struct clk_mgr * clk_mgr_base)474 static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
475 {
476 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
477 struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);
478 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
479
480 if (!clk_mgr->smu_ver)
481 return;
482
483 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
484 return;
485
486 memset(table, 0, sizeof(*table));
487
488 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
489
490 dcn31_smu_set_dram_addr_high(clk_mgr,
491 clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
492 dcn31_smu_set_dram_addr_low(clk_mgr,
493 clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
494 dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);
495 }
496
dcn31_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn31_smu_dpm_clks * smu_dpm_clks)497 static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
498 struct dcn31_smu_dpm_clks *smu_dpm_clks)
499 {
500 DpmClocks_t *table = smu_dpm_clks->dpm_clks;
501
502 if (!clk_mgr->smu_ver)
503 return;
504
505 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
506 return;
507
508 memset(table, 0, sizeof(*table));
509
510 dcn31_smu_set_dram_addr_high(clk_mgr,
511 smu_dpm_clks->mc_address.high_part);
512 dcn31_smu_set_dram_addr_low(clk_mgr,
513 smu_dpm_clks->mc_address.low_part);
514 dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
515 }
516
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)517 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
518 {
519 uint32_t max = 0;
520 int i;
521
522 for (i = 0; i < num_clocks; ++i) {
523 if (clocks[i] > max)
524 max = clocks[i];
525 }
526
527 return max;
528 }
529
find_clk_for_voltage(const DpmClocks_t * clock_table,const uint32_t clocks[],unsigned int voltage)530 static unsigned int find_clk_for_voltage(
531 const DpmClocks_t *clock_table,
532 const uint32_t clocks[],
533 unsigned int voltage)
534 {
535 int i;
536 int max_voltage = 0;
537 int clock = 0;
538
539 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
540 if (clock_table->SocVoltage[i] == voltage) {
541 return clocks[i];
542 } else if (clock_table->SocVoltage[i] >= max_voltage &&
543 clock_table->SocVoltage[i] < voltage) {
544 max_voltage = clock_table->SocVoltage[i];
545 clock = clocks[i];
546 }
547 }
548
549 ASSERT(clock);
550 return clock;
551 }
552
dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_t * clock_table)553 static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
554 struct integrated_info *bios_info,
555 const DpmClocks_t *clock_table)
556 {
557 int i, j;
558 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
559 uint32_t max_dispclk = 0, max_dppclk = 0;
560
561 j = -1;
562
563 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
564
565 /* Find lowest DPM, FCLK is filled in reverse order*/
566
567 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
568 if (clock_table->DfPstateTable[i].FClk != 0) {
569 j = i;
570 break;
571 }
572 }
573
574 if (j == -1) {
575 /* clock table is all 0s, just use our own hardcode */
576 ASSERT(0);
577 return;
578 }
579
580 bw_params->clk_table.num_entries = j + 1;
581
582 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
583 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
584 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
585 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
586 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
587 } else {
588 ASSERT(0);
589 }
590
591 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
592 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
593 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
594 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
595 switch (clock_table->DfPstateTable[j].WckRatio) {
596 case WCK_RATIO_1_2:
597 bw_params->clk_table.entries[i].wck_ratio = 2;
598 break;
599 case WCK_RATIO_1_4:
600 bw_params->clk_table.entries[i].wck_ratio = 4;
601 break;
602 default:
603 bw_params->clk_table.entries[i].wck_ratio = 1;
604 }
605 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
606 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
607 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
608 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
609 }
610
611 bw_params->vram_type = bios_info->memory_type;
612 bw_params->num_channels = bios_info->ma_channel_number;
613
614 for (i = 0; i < WM_SET_COUNT; i++) {
615 bw_params->wm_table.entries[i].wm_inst = i;
616
617 if (i >= bw_params->clk_table.num_entries) {
618 bw_params->wm_table.entries[i].valid = false;
619 continue;
620 }
621
622 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
623 bw_params->wm_table.entries[i].valid = true;
624 }
625 }
626
dcn31_set_low_power_state(struct clk_mgr * clk_mgr_base)627 static void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)
628 {
629 int display_count;
630 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
631 struct dc *dc = clk_mgr_base->ctx->dc;
632 struct dc_state *context = dc->current_state;
633
634 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
635 display_count = dcn31_get_active_display_cnt_wa(dc, context);
636 /* if we can go lower, go lower */
637 if (display_count == 0) {
638 union display_idle_optimization_u idle_info = { 0 };
639
640 idle_info.idle_info.df_request_disabled = 1;
641 idle_info.idle_info.phy_ref_clk_off = 1;
642 idle_info.idle_info.s0i2_rdy = 1;
643 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
644 /* update power state */
645 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
646 }
647 }
648 }
649
dcn31_get_dtb_ref_freq_khz(struct clk_mgr * clk_mgr_base)650 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
651 {
652 return clk_mgr_base->clks.ref_dtbclk_khz;
653 }
654
655 static struct clk_mgr_funcs dcn31_funcs = {
656 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
657 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
658 .update_clocks = dcn31_update_clocks,
659 .init_clocks = dcn31_init_clocks,
660 .enable_pme_wa = dcn31_enable_pme_wa,
661 .are_clock_states_equal = dcn31_are_clock_states_equal,
662 .notify_wm_ranges = dcn31_notify_wm_ranges,
663 .set_low_power_state = dcn31_set_low_power_state
664 };
665 extern struct clk_mgr_funcs dcn3_fpga_funcs;
666
dcn31_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn31 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)667 void dcn31_clk_mgr_construct(
668 struct dc_context *ctx,
669 struct clk_mgr_dcn31 *clk_mgr,
670 struct pp_smu_funcs *pp_smu,
671 struct dccg *dccg)
672 {
673 struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
674
675 clk_mgr->base.base.ctx = ctx;
676 clk_mgr->base.base.funcs = &dcn31_funcs;
677
678 clk_mgr->base.pp_smu = pp_smu;
679
680 clk_mgr->base.dccg = dccg;
681 clk_mgr->base.dfs_bypass_disp_clk = 0;
682
683 clk_mgr->base.dprefclk_ss_percentage = 0;
684 clk_mgr->base.dprefclk_ss_divider = 1000;
685 clk_mgr->base.ss_on_dprefclk = false;
686 clk_mgr->base.dfs_ref_freq_khz = 48000;
687
688 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
689 clk_mgr->base.base.ctx,
690 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
691 sizeof(struct dcn31_watermarks),
692 &clk_mgr->smu_wm_set.mc_address.quad_part);
693
694 if (!clk_mgr->smu_wm_set.wm_set) {
695 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
696 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
697 }
698 ASSERT(clk_mgr->smu_wm_set.wm_set);
699
700 smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
701 clk_mgr->base.base.ctx,
702 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
703 sizeof(DpmClocks_t),
704 &smu_dpm_clks.mc_address.quad_part);
705
706 if (smu_dpm_clks.dpm_clks == NULL) {
707 smu_dpm_clks.dpm_clks = &dummy_clocks;
708 smu_dpm_clks.mc_address.quad_part = 0;
709 }
710
711 ASSERT(smu_dpm_clks.dpm_clks);
712
713 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
714 clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
715 } else {
716 struct clk_log_info log_info = {0};
717
718 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
719
720 if (clk_mgr->base.smu_ver)
721 clk_mgr->base.smu_present = true;
722
723 /* TODO: Check we get what we expect during bringup */
724 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
725
726 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
727 dcn31_bw_params.wm_table = lpddr5_wm_table;
728 } else {
729 dcn31_bw_params.wm_table = ddr5_wm_table;
730 }
731 /* Saved clocks configured at boot for debug purposes */
732 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
733 &clk_mgr->base.base, &log_info);
734
735 }
736
737 clk_mgr->base.base.dprefclk_khz = 600000;
738 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
739 dce_clock_read_ss_info(&clk_mgr->base);
740 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
741 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);
742
743 clk_mgr->base.base.bw_params = &dcn31_bw_params;
744
745 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
746 int i;
747
748 dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
749
750 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
751 "NumDispClkLevelsEnabled: %d\n"
752 "NumSocClkLevelsEnabled: %d\n"
753 "VcnClkLevelsEnabled: %d\n"
754 "NumDfPst atesEnabled: %d\n"
755 "MinGfxClk: %d\n"
756 "MaxGfxClk: %d\n",
757 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
758 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
759 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
760 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
761 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
762 smu_dpm_clks.dpm_clks->MinGfxClk,
763 smu_dpm_clks.dpm_clks->MaxGfxClk);
764 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
765 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
766 i,
767 smu_dpm_clks.dpm_clks->DcfClocks[i]);
768 }
769 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
770 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
771 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
772 }
773 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
774 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
775 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
776 }
777 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
778 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
779 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
780
781 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
782 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
783 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
784 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
785 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
786 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
787 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
788 }
789 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
790 dcn31_clk_mgr_helper_populate_bw_params(
791 &clk_mgr->base,
792 ctx->dc_bios->integrated_info,
793 smu_dpm_clks.dpm_clks);
794 }
795 }
796
797 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
798 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
799 smu_dpm_clks.dpm_clks);
800 }
801
dcn31_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)802 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
803 {
804 struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);
805
806 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
807 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
808 clk_mgr->smu_wm_set.wm_set);
809 }
810