1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33 // For dcn20_update_clocks_update_dpp_dto
34 #include "dcn20/dcn20_clk_mgr.h"
35 #include "dcn31/dcn31_clk_mgr.h"
36 #include "dcn316_clk_mgr.h"
37 #include "reg_helper.h"
38 #include "core_types.h"
39 #include "dcn316_smu.h"
40 #include "dm_helpers.h"
41 #include "dc_dmub_srv.h"
42 #include "dc_link_dp.h"
43
44 // DCN316 this is CLK1 instance
45 #define MAX_INSTANCE 7
46 #define MAX_SEGMENT 6
47
48 struct IP_BASE_INSTANCE
49 {
50 unsigned int segment[MAX_SEGMENT];
51 };
52
53 struct IP_BASE
54 {
55 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
56 };
57
58 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
59 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
60 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
61 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
62 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
63 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
64 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } };
65
66 #define regCLK1_CLK_PLL_REQ 0x0237
67 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
68
69 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
70 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
71 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
72 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
73 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
74 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
75
76 #define REG(reg_name) \
77 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
78
79 #define TO_CLK_MGR_DCN316(clk_mgr)\
80 container_of(clk_mgr, struct clk_mgr_dcn316, base)
81
dcn316_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)82 static int dcn316_get_active_display_cnt_wa(
83 struct dc *dc,
84 struct dc_state *context)
85 {
86 int i, display_count;
87 bool tmds_present = false;
88
89 display_count = 0;
90 for (i = 0; i < context->stream_count; i++) {
91 const struct dc_stream_state *stream = context->streams[i];
92
93 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
94 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
95 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
96 tmds_present = true;
97 }
98
99 for (i = 0; i < dc->link_count; i++) {
100 const struct dc_link *link = dc->links[i];
101
102 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
103 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
104 link->link_enc->funcs->is_dig_enabled(link->link_enc))
105 display_count++;
106 }
107
108 /* WA for hang on HDMI after display off back back on*/
109 if (display_count == 0 && tmds_present)
110 display_count = 1;
111
112 return display_count;
113 }
114
dcn316_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool disable)115 static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
116 {
117 struct dc *dc = clk_mgr_base->ctx->dc;
118 int i;
119
120 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
121 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
122
123 if (pipe->top_pipe || pipe->prev_odm_pipe)
124 continue;
125 if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
126 dc_is_virtual_signal(pipe->stream->signal))) {
127 if (disable) {
128 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
129 reset_sync_context_for_pipe(dc, context, i);
130 } else
131 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
132 }
133 }
134 }
135
dcn316_enable_pme_wa(struct clk_mgr * clk_mgr_base)136 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base)
137 {
138 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
139
140 dcn316_smu_enable_pme_wa(clk_mgr);
141 }
142
dcn316_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)143 static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
144 struct dc_state *context,
145 bool safe_to_lower)
146 {
147 union dmub_rb_cmd cmd;
148 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
149 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
150 struct dc *dc = clk_mgr_base->ctx->dc;
151 int display_count;
152 bool update_dppclk = false;
153 bool update_dispclk = false;
154 bool dpp_clock_lowered = false;
155
156 if (dc->work_arounds.skip_clock_update)
157 return;
158
159 /*
160 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
161 * also if safe to lower is false, we just go in the higher state
162 */
163 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
164 if (safe_to_lower) {
165 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
166 dcn316_smu_set_dtbclk(clk_mgr, false);
167 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
168 }
169 /* check that we're not already in lower */
170 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
171 display_count = dcn316_get_active_display_cnt_wa(dc, context);
172 /* if we can go lower, go lower */
173 if (display_count == 0) {
174 union display_idle_optimization_u idle_info = { 0 };
175 idle_info.idle_info.df_request_disabled = 1;
176 idle_info.idle_info.phy_ref_clk_off = 1;
177 idle_info.idle_info.s0i2_rdy = 1;
178 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
179 /* update power state */
180 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
181 }
182 }
183 } else {
184 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
185 dcn316_smu_set_dtbclk(clk_mgr, true);
186 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
187 }
188
189 /* check that we're not already in D0 */
190 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
191 union display_idle_optimization_u idle_info = { 0 };
192 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
193 /* update power state */
194 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
195 }
196 }
197
198 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
199 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
200 dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
201 }
202
203 if (should_set_clock(safe_to_lower,
204 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
205 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
206 dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
207 }
208
209 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
210 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
211 if (new_clocks->dppclk_khz < 100000)
212 new_clocks->dppclk_khz = 100000;
213 if (new_clocks->dispclk_khz < 100000)
214 new_clocks->dispclk_khz = 100000;
215 }
216
217 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
218 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
219 dpp_clock_lowered = true;
220 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
221 update_dppclk = true;
222 }
223
224 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
225 dcn316_disable_otg_wa(clk_mgr_base, context, true);
226
227 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
228 dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
229 dcn316_disable_otg_wa(clk_mgr_base, context, false);
230
231 update_dispclk = true;
232 }
233
234 if (dpp_clock_lowered) {
235 // increase per DPP DTO before lowering global dppclk
236 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
237 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
238 } else {
239 // increase global DPPCLK before lowering per DPP DTO
240 if (update_dppclk || update_dispclk)
241 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
242 // always update dtos unless clock is lowered and not safe to lower
243 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
244 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
245 }
246
247 // notify DMCUB of latest clocks
248 memset(&cmd, 0, sizeof(cmd));
249 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
250 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
251 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
252 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
253 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
254 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
255 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
256
257 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
258 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
259 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
260 }
261
dcn316_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)262 static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
263 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
264 {
265 return;
266 }
267
268 static struct clk_bw_params dcn316_bw_params = {
269 .vram_type = Ddr4MemType,
270 .num_channels = 1,
271 .clk_table = {
272 .num_entries = 5,
273 },
274
275 };
276
277 static struct wm_table ddr4_wm_table = {
278 .entries = {
279 {
280 .wm_inst = WM_A,
281 .wm_type = WM_TYPE_PSTATE_CHG,
282 .pstate_latency_us = 11.72,
283 .sr_exit_time_us = 6.09,
284 .sr_enter_plus_exit_time_us = 7.14,
285 .valid = true,
286 },
287 {
288 .wm_inst = WM_B,
289 .wm_type = WM_TYPE_PSTATE_CHG,
290 .pstate_latency_us = 11.72,
291 .sr_exit_time_us = 10.12,
292 .sr_enter_plus_exit_time_us = 11.48,
293 .valid = true,
294 },
295 {
296 .wm_inst = WM_C,
297 .wm_type = WM_TYPE_PSTATE_CHG,
298 .pstate_latency_us = 11.72,
299 .sr_exit_time_us = 10.12,
300 .sr_enter_plus_exit_time_us = 11.48,
301 .valid = true,
302 },
303 {
304 .wm_inst = WM_D,
305 .wm_type = WM_TYPE_PSTATE_CHG,
306 .pstate_latency_us = 11.72,
307 .sr_exit_time_us = 10.12,
308 .sr_enter_plus_exit_time_us = 11.48,
309 .valid = true,
310 },
311 }
312 };
313
314 static struct wm_table lpddr5_wm_table = {
315 .entries = {
316 {
317 .wm_inst = WM_A,
318 .wm_type = WM_TYPE_PSTATE_CHG,
319 .pstate_latency_us = 11.65333,
320 .sr_exit_time_us = 11.5,
321 .sr_enter_plus_exit_time_us = 14.5,
322 .valid = true,
323 },
324 {
325 .wm_inst = WM_B,
326 .wm_type = WM_TYPE_PSTATE_CHG,
327 .pstate_latency_us = 11.65333,
328 .sr_exit_time_us = 11.5,
329 .sr_enter_plus_exit_time_us = 14.5,
330 .valid = true,
331 },
332 {
333 .wm_inst = WM_C,
334 .wm_type = WM_TYPE_PSTATE_CHG,
335 .pstate_latency_us = 11.65333,
336 .sr_exit_time_us = 11.5,
337 .sr_enter_plus_exit_time_us = 14.5,
338 .valid = true,
339 },
340 {
341 .wm_inst = WM_D,
342 .wm_type = WM_TYPE_PSTATE_CHG,
343 .pstate_latency_us = 11.65333,
344 .sr_exit_time_us = 11.5,
345 .sr_enter_plus_exit_time_us = 14.5,
346 .valid = true,
347 },
348 }
349 };
350
351 static DpmClocks_316_t dummy_clocks;
352
353 static struct dcn316_watermarks dummy_wms = { 0 };
354
dcn316_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn316_watermarks * table)355 static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
356 {
357 int i, num_valid_sets;
358
359 num_valid_sets = 0;
360
361 for (i = 0; i < WM_SET_COUNT; i++) {
362 /* skip empty entries, the smu array has no holes*/
363 if (!bw_params->wm_table.entries[i].valid)
364 continue;
365
366 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
367 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
368 /* We will not select WM based on fclk, so leave it as unconstrained */
369 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
370 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
371
372 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
373 if (i == 0)
374 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
375 else {
376 /* add 1 to make it non-overlapping with next lvl */
377 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
378 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
379 }
380 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
381 bw_params->clk_table.entries[i].dcfclk_mhz;
382
383 } else {
384 /* unconstrained for memory retraining */
385 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
386 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
387
388 /* Modify previous watermark range to cover up to max */
389 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
390 }
391 num_valid_sets++;
392 }
393
394 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
395
396 /* modify the min and max to make sure we cover the whole range*/
397 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
398 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
399 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
401
402 /* This is for writeback only, does not matter currently as no writeback support*/
403 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
404 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
405 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
406 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
407 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
408 }
409
dcn316_notify_wm_ranges(struct clk_mgr * clk_mgr_base)410 static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
411 {
412 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
413 struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr);
414 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set;
415
416 if (!clk_mgr->smu_ver)
417 return;
418
419 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0)
420 return;
421
422 memset(table, 0, sizeof(*table));
423
424 dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table);
425
426 dcn316_smu_set_dram_addr_high(clk_mgr,
427 clk_mgr_dcn316->smu_wm_set.mc_address.high_part);
428 dcn316_smu_set_dram_addr_low(clk_mgr,
429 clk_mgr_dcn316->smu_wm_set.mc_address.low_part);
430 dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr);
431 }
432
dcn316_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn316_smu_dpm_clks * smu_dpm_clks)433 static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
434 struct dcn316_smu_dpm_clks *smu_dpm_clks)
435 {
436 DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;
437
438 if (!clk_mgr->smu_ver)
439 return;
440
441 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
442 return;
443
444 memset(table, 0, sizeof(*table));
445
446 dcn316_smu_set_dram_addr_high(clk_mgr,
447 smu_dpm_clks->mc_address.high_part);
448 dcn316_smu_set_dram_addr_low(clk_mgr,
449 smu_dpm_clks->mc_address.low_part);
450 dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
451 }
452
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)453 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
454 {
455 uint32_t max = 0;
456 int i;
457
458 for (i = 0; i < num_clocks; ++i) {
459 if (clocks[i] > max)
460 max = clocks[i];
461 }
462
463 return max;
464 }
465
find_clk_for_voltage(const DpmClocks_316_t * clock_table,const uint32_t clocks[],unsigned int voltage)466 static unsigned int find_clk_for_voltage(
467 const DpmClocks_316_t *clock_table,
468 const uint32_t clocks[],
469 unsigned int voltage)
470 {
471 int i;
472 int max_voltage = 0;
473 int clock = 0;
474
475 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
476 if (clock_table->SocVoltage[i] == voltage) {
477 return clocks[i];
478 } else if (clock_table->SocVoltage[i] >= max_voltage &&
479 clock_table->SocVoltage[i] < voltage) {
480 max_voltage = clock_table->SocVoltage[i];
481 clock = clocks[i];
482 }
483 }
484
485 ASSERT(clock);
486 return clock;
487 }
488
dcn316_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_316_t * clock_table)489 static void dcn316_clk_mgr_helper_populate_bw_params(
490 struct clk_mgr_internal *clk_mgr,
491 struct integrated_info *bios_info,
492 const DpmClocks_316_t *clock_table)
493 {
494 int i, j;
495 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
496 uint32_t max_dispclk = 0, max_dppclk = 0;
497
498 j = -1;
499
500 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
501
502 /* Find lowest DPM, FCLK is filled in reverse order*/
503
504 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
505 if (clock_table->DfPstateTable[i].FClk != 0) {
506 j = i;
507 break;
508 }
509 }
510
511 if (j == -1) {
512 /* clock table is all 0s, just use our own hardcode */
513 ASSERT(0);
514 return;
515 }
516
517 bw_params->clk_table.num_entries = j + 1;
518
519 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
520 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
521 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
522 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
523 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
524 } else {
525 ASSERT(0);
526 }
527
528 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
529 int temp;
530
531 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
532 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
533 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
534 switch (clock_table->DfPstateTable[j].WckRatio) {
535 case WCK_RATIO_1_2:
536 bw_params->clk_table.entries[i].wck_ratio = 2;
537 break;
538 case WCK_RATIO_1_4:
539 bw_params->clk_table.entries[i].wck_ratio = 4;
540 break;
541 default:
542 bw_params->clk_table.entries[i].wck_ratio = 1;
543 }
544 temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
545 if (temp)
546 bw_params->clk_table.entries[i].dcfclk_mhz = temp;
547 temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
548 if (temp)
549 bw_params->clk_table.entries[i].socclk_mhz = temp;
550 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
551 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
552 }
553
554 bw_params->vram_type = bios_info->memory_type;
555 bw_params->num_channels = bios_info->ma_channel_number;
556
557 for (i = 0; i < WM_SET_COUNT; i++) {
558 bw_params->wm_table.entries[i].wm_inst = i;
559
560 if (i >= bw_params->clk_table.num_entries) {
561 bw_params->wm_table.entries[i].valid = false;
562 continue;
563 }
564
565 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
566 bw_params->wm_table.entries[i].valid = true;
567 }
568 }
569
570
571
572 static struct clk_mgr_funcs dcn316_funcs = {
573 .enable_pme_wa = dcn316_enable_pme_wa,
574 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
575 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
576 .update_clocks = dcn316_update_clocks,
577 .init_clocks = dcn31_init_clocks,
578 .are_clock_states_equal = dcn31_are_clock_states_equal,
579 .notify_wm_ranges = dcn316_notify_wm_ranges
580 };
581 extern struct clk_mgr_funcs dcn3_fpga_funcs;
582
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)583 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
584 {
585 /* get FbMult value */
586 struct fixed31_32 pll_req;
587 unsigned int fbmult_frac_val = 0;
588 unsigned int fbmult_int_val = 0;
589
590 /*
591 * Register value of fbmult is in 8.16 format, we are converting to 31.32
592 * to leverage the fix point operations available in driver
593 */
594
595 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
596 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
597
598 pll_req = dc_fixpt_from_int(fbmult_int_val);
599
600 /*
601 * since fractional part is only 16 bit in register definition but is 32 bit
602 * in our fix point definiton, need to shift left by 16 to obtain correct value
603 */
604 pll_req.value |= fbmult_frac_val << 16;
605
606 /* multiply by REFCLK period */
607 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
608
609 /* integer part is now VCO frequency in kHz */
610 return dc_fixpt_floor(pll_req);
611 }
612
dcn316_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn316 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)613 void dcn316_clk_mgr_construct(
614 struct dc_context *ctx,
615 struct clk_mgr_dcn316 *clk_mgr,
616 struct pp_smu_funcs *pp_smu,
617 struct dccg *dccg)
618 {
619 struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };
620
621 clk_mgr->base.base.ctx = ctx;
622 clk_mgr->base.base.funcs = &dcn316_funcs;
623
624 clk_mgr->base.pp_smu = pp_smu;
625
626 clk_mgr->base.dccg = dccg;
627 clk_mgr->base.dfs_bypass_disp_clk = 0;
628
629 clk_mgr->base.dprefclk_ss_percentage = 0;
630 clk_mgr->base.dprefclk_ss_divider = 1000;
631 clk_mgr->base.ss_on_dprefclk = false;
632 clk_mgr->base.dfs_ref_freq_khz = 48000;
633
634 clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem(
635 clk_mgr->base.base.ctx,
636 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
637 sizeof(struct dcn316_watermarks),
638 &clk_mgr->smu_wm_set.mc_address.quad_part);
639
640 if (!clk_mgr->smu_wm_set.wm_set) {
641 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
642 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
643 }
644 ASSERT(clk_mgr->smu_wm_set.wm_set);
645
646 smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(
647 clk_mgr->base.base.ctx,
648 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
649 sizeof(DpmClocks_316_t),
650 &smu_dpm_clks.mc_address.quad_part);
651
652 if (smu_dpm_clks.dpm_clks == NULL) {
653 smu_dpm_clks.dpm_clks = &dummy_clocks;
654 smu_dpm_clks.mc_address.quad_part = 0;
655 }
656
657 ASSERT(smu_dpm_clks.dpm_clks);
658
659 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
660 clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
661 clk_mgr->base.base.dentist_vco_freq_khz = 2500000;
662 } else {
663 struct clk_log_info log_info = {0};
664
665 clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base);
666
667 if (clk_mgr->base.smu_ver > 0)
668 clk_mgr->base.smu_present = true;
669
670 // Skip this for now as it did not work on DCN315, renable during bring up
671 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
672
673 /* in case we don't get a value from the register, use default */
674 if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
675 clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */
676
677
678 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
679 dcn316_bw_params.wm_table = lpddr5_wm_table;
680 } else {
681 dcn316_bw_params.wm_table = ddr4_wm_table;
682 }
683 /* Saved clocks configured at boot for debug purposes */
684 dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
685 &clk_mgr->base.base, &log_info);
686
687 }
688
689 clk_mgr->base.base.dprefclk_khz = 600000;
690 clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
691 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
692 dce_clock_read_ss_info(&clk_mgr->base);
693 /*clk_mgr->base.dccg->ref_dtbclk_khz =
694 dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/
695
696 clk_mgr->base.base.bw_params = &dcn316_bw_params;
697
698 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
699 dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
700
701 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
702 dcn316_clk_mgr_helper_populate_bw_params(
703 &clk_mgr->base,
704 ctx->dc_bios->integrated_info,
705 smu_dpm_clks.dpm_clks);
706 }
707 }
708
709 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
710 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
711 smu_dpm_clks.dpm_clks);
712 }
713
dcn316_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)714 void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
715 {
716 struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int);
717
718 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
719 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
720 clk_mgr->smu_wm_set.wm_set);
721 }
722