1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn30_optc.h"
28 #include "dc.h"
29 #include "dcn_calc_math.h"
30
31 #include "dml/dcn30/dcn30_fpu.h"
32
33 #define REG(reg)\
34 optc1->tg_regs->reg
35
36 #define CTX \
37 optc1->base.ctx
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
42
optc3_triplebuffer_lock(struct timing_generator * optc)43 void optc3_triplebuffer_lock(struct timing_generator *optc)
44 {
45 struct optc *optc1 = DCN10TG_FROM_TG(optc);
46
47 REG_UPDATE(OTG_GLOBAL_CONTROL2,
48 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
49
50 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
51 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
52
53 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
54 OTG_MASTER_UPDATE_LOCK, 1);
55
56 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
57 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
58 UPDATE_LOCK_STATUS, 1,
59 1, 10);
60 }
61
optc3_lock_doublebuffer_enable(struct timing_generator * optc)62 void optc3_lock_doublebuffer_enable(struct timing_generator *optc)
63 {
64 struct optc *optc1 = DCN10TG_FROM_TG(optc);
65 uint32_t v_blank_start = 0;
66 uint32_t v_blank_end = 0;
67 uint32_t h_blank_start = 0;
68 uint32_t h_blank_end = 0;
69
70 REG_GET_2(OTG_V_BLANK_START_END,
71 OTG_V_BLANK_START, &v_blank_start,
72 OTG_V_BLANK_END, &v_blank_end);
73 REG_GET_2(OTG_H_BLANK_START_END,
74 OTG_H_BLANK_START, &h_blank_start,
75 OTG_H_BLANK_END, &h_blank_end);
76
77 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
78 MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start - 1,
79 MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start);
80 REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
81 DIG_UPDATE_POSITION_X, h_blank_start - 180 - 1,
82 DIG_UPDATE_POSITION_Y, v_blank_start - 1);
83 // there is a DIG_UPDATE_VCOUNT_MODE and it is 0.
84
85 REG_UPDATE_3(OTG_GLOBAL_CONTROL0,
86 MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1,
87 MASTER_UPDATE_LOCK_DB_END_X, h_blank_start - 180,
88 MASTER_UPDATE_LOCK_DB_EN, 1);
89 REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
90
91 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
92 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
93 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
94 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
95 }
96
optc3_lock_doublebuffer_disable(struct timing_generator * optc)97 void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
98 {
99 struct optc *optc1 = DCN10TG_FROM_TG(optc);
100
101 REG_UPDATE_2(OTG_GLOBAL_CONTROL0,
102 MASTER_UPDATE_LOCK_DB_START_X, 0,
103 MASTER_UPDATE_LOCK_DB_END_X, 0);
104 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
105 MASTER_UPDATE_LOCK_DB_START_Y, 0,
106 MASTER_UPDATE_LOCK_DB_END_Y, 0);
107
108 REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
109 REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);
110 }
111
optc3_lock(struct timing_generator * optc)112 void optc3_lock(struct timing_generator *optc)
113 {
114 struct optc *optc1 = DCN10TG_FROM_TG(optc);
115
116 REG_UPDATE(OTG_GLOBAL_CONTROL2,
117 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
118 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
119 OTG_MASTER_UPDATE_LOCK, 1);
120
121 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
122 UPDATE_LOCK_STATUS, 1,
123 1, 10);
124 }
125
optc3_set_out_mux(struct timing_generator * optc,enum otg_out_mux_dest dest)126 void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)
127 {
128 struct optc *optc1 = DCN10TG_FROM_TG(optc);
129
130 REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);
131 }
132
optc3_program_blank_color(struct timing_generator * optc,const struct tg_color * blank_color)133 void optc3_program_blank_color(struct timing_generator *optc,
134 const struct tg_color *blank_color)
135 {
136 struct optc *optc1 = DCN10TG_FROM_TG(optc);
137
138 REG_SET_3(OTG_BLANK_DATA_COLOR, 0,
139 OTG_BLANK_DATA_COLOR_BLUE_CB, blank_color->color_b_cb,
140 OTG_BLANK_DATA_COLOR_GREEN_Y, blank_color->color_g_y,
141 OTG_BLANK_DATA_COLOR_RED_CR, blank_color->color_r_cr);
142
143 REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0,
144 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, blank_color->color_b_cb >> 10,
145 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, blank_color->color_g_y >> 10,
146 OTG_BLANK_DATA_COLOR_RED_CR_EXT, blank_color->color_r_cr >> 10);
147 }
148
optc3_set_drr_trigger_window(struct timing_generator * optc,uint32_t window_start,uint32_t window_end)149 void optc3_set_drr_trigger_window(struct timing_generator *optc,
150 uint32_t window_start, uint32_t window_end)
151 {
152 struct optc *optc1 = DCN10TG_FROM_TG(optc);
153
154 REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0,
155 OTG_DRR_TRIGGER_WINDOW_START_X, window_start,
156 OTG_DRR_TRIGGER_WINDOW_END_X, window_end);
157 }
158
optc3_set_vtotal_change_limit(struct timing_generator * optc,uint32_t limit)159 void optc3_set_vtotal_change_limit(struct timing_generator *optc,
160 uint32_t limit)
161 {
162 struct optc *optc1 = DCN10TG_FROM_TG(optc);
163
164
165 REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,
166 OTG_DRR_V_TOTAL_CHANGE_LIMIT, limit);
167 }
168
169
170 /* Set DSC-related configuration.
171 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
172 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format
173 * dsc_slice_width: Slice width in pixels
174 */
optc3_set_dsc_config(struct timing_generator * optc,enum optc_dsc_mode dsc_mode,uint32_t dsc_bytes_per_pixel,uint32_t dsc_slice_width)175 void optc3_set_dsc_config(struct timing_generator *optc,
176 enum optc_dsc_mode dsc_mode,
177 uint32_t dsc_bytes_per_pixel,
178 uint32_t dsc_slice_width)
179 {
180 struct optc *optc1 = DCN10TG_FROM_TG(optc);
181
182 optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel,
183 dsc_slice_width);
184
185 REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
186
187 }
188
optc3_set_vrr_m_const(struct timing_generator * optc,double vtotal_avg)189 void optc3_set_vrr_m_const(struct timing_generator *optc,
190 double vtotal_avg)
191 {
192 DC_FP_START();
193 optc3_fpu_set_vrr_m_const(optc, vtotal_avg);
194 DC_FP_END();
195 }
196
optc3_set_odm_bypass(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing)197 void optc3_set_odm_bypass(struct timing_generator *optc,
198 const struct dc_crtc_timing *dc_crtc_timing)
199 {
200 struct optc *optc1 = DCN10TG_FROM_TG(optc);
201 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
202
203 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
204 OPTC_NUM_OF_INPUT_SEGMENT, 0,
205 OPTC_SEG0_SRC_SEL, optc->inst,
206 OPTC_SEG1_SRC_SEL, 0xf,
207 OPTC_SEG2_SRC_SEL, 0xf,
208 OPTC_SEG3_SRC_SEL, 0xf
209 );
210
211 h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
212 REG_SET(OTG_H_TIMING_CNTL, 0,
213 OTG_H_TIMING_DIV_MODE, h_div);
214
215 REG_SET(OPTC_MEMORY_CONFIG, 0,
216 OPTC_MEM_SEL, 0);
217 optc1->opp_count = 1;
218 }
219
optc3_set_odm_combine(struct timing_generator * optc,int * opp_id,int opp_cnt,struct dc_crtc_timing * timing)220 static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
221 struct dc_crtc_timing *timing)
222 {
223 struct optc *optc1 = DCN10TG_FROM_TG(optc);
224 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
225 / opp_cnt;
226 uint32_t memory_mask = 0;
227
228 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
229 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
230 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
231 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
232 * MASTER_UPDATE_LOCK_DB_X, 160,
233 * MASTER_UPDATE_LOCK_DB_Y, 240);
234 */
235
236 ASSERT(opp_cnt == 2 || opp_cnt == 4);
237
238 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
239 * however, for ODM combine we can simplify by always using 4.
240 */
241 if (opp_cnt == 2) {
242 /* To make sure there's no memory overlap, each instance "reserves" 2
243 * memories and they are uniquely combined here.
244 */
245 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
246 } else if (opp_cnt == 4) {
247 /* To make sure there's no memory overlap, each instance "reserves" 1
248 * memory and they are uniquely combined here.
249 */
250 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2);
251 }
252
253 if (REG(OPTC_MEMORY_CONFIG))
254 REG_SET(OPTC_MEMORY_CONFIG, 0,
255 OPTC_MEM_SEL, memory_mask);
256
257 if (opp_cnt == 2) {
258 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
259 OPTC_NUM_OF_INPUT_SEGMENT, 1,
260 OPTC_SEG0_SRC_SEL, opp_id[0],
261 OPTC_SEG1_SRC_SEL, opp_id[1]);
262 } else if (opp_cnt == 4) {
263 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
264 OPTC_NUM_OF_INPUT_SEGMENT, 3,
265 OPTC_SEG0_SRC_SEL, opp_id[0],
266 OPTC_SEG1_SRC_SEL, opp_id[1],
267 OPTC_SEG2_SRC_SEL, opp_id[2],
268 OPTC_SEG3_SRC_SEL, opp_id[3]);
269 }
270
271 REG_UPDATE(OPTC_WIDTH_CONTROL,
272 OPTC_SEGMENT_WIDTH, mpcc_hactive);
273
274 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
275 optc1->opp_count = opp_cnt;
276 }
277
278 /**
279 * optc3_set_timing_double_buffer() - DRR double buffering control
280 *
281 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
282 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
283 *
284 * Options: any time, start of frame, dp start of frame (range timing)
285 */
optc3_set_timing_double_buffer(struct timing_generator * optc,bool enable)286 static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
287 {
288 struct optc *optc1 = DCN10TG_FROM_TG(optc);
289 uint32_t mode = enable ? 2 : 0;
290
291 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
292 OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode);
293 }
294
optc3_tg_init(struct timing_generator * optc)295 void optc3_tg_init(struct timing_generator *optc)
296 {
297 optc3_set_timing_double_buffer(optc, true);
298 optc1_clear_optc_underflow(optc);
299 }
300
301 static struct timing_generator_funcs dcn30_tg_funcs = {
302 .validate_timing = optc1_validate_timing,
303 .program_timing = optc1_program_timing,
304 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
305 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
306 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
307 .program_global_sync = optc1_program_global_sync,
308 .enable_crtc = optc2_enable_crtc,
309 .disable_crtc = optc1_disable_crtc,
310 /* used by enable_timing_synchronization. Not need for FPGA */
311 .is_counter_moving = optc1_is_counter_moving,
312 .get_position = optc1_get_position,
313 .get_frame_count = optc1_get_vblank_counter,
314 .get_scanoutpos = optc1_get_crtc_scanoutpos,
315 .get_otg_active_size = optc1_get_otg_active_size,
316 .set_early_control = optc1_set_early_control,
317 /* used by enable_timing_synchronization. Not need for FPGA */
318 .wait_for_state = optc1_wait_for_state,
319 .set_blank_color = optc3_program_blank_color,
320 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
321 .triplebuffer_lock = optc3_triplebuffer_lock,
322 .triplebuffer_unlock = optc2_triplebuffer_unlock,
323 .enable_reset_trigger = optc1_enable_reset_trigger,
324 .enable_crtc_reset = optc1_enable_crtc_reset,
325 .disable_reset_trigger = optc1_disable_reset_trigger,
326 .lock = optc3_lock,
327 .is_locked = optc1_is_locked,
328 .unlock = optc1_unlock,
329 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
330 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
331 .enable_optc_clock = optc1_enable_optc_clock,
332 .set_drr = optc1_set_drr,
333 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
334 .set_static_screen_control = optc1_set_static_screen_control,
335 .program_stereo = optc1_program_stereo,
336 .is_stereo_left_eye = optc1_is_stereo_left_eye,
337 .tg_init = optc3_tg_init,
338 .is_tg_enabled = optc1_is_tg_enabled,
339 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
340 .clear_optc_underflow = optc1_clear_optc_underflow,
341 .setup_global_swap_lock = NULL,
342 .get_crc = optc1_get_crc,
343 .configure_crc = optc2_configure_crc,
344 .set_dsc_config = optc3_set_dsc_config,
345 .get_dsc_status = optc2_get_dsc_status,
346 .set_dwb_source = NULL,
347 .set_odm_bypass = optc3_set_odm_bypass,
348 .set_odm_combine = optc3_set_odm_combine,
349 .get_optc_source = optc2_get_optc_source,
350 .set_out_mux = optc3_set_out_mux,
351 .set_drr_trigger_window = optc3_set_drr_trigger_window,
352 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
353 .set_gsl = optc2_set_gsl,
354 .set_gsl_source_select = optc2_set_gsl_source_select,
355 .set_vtg_params = optc1_set_vtg_params,
356 .program_manual_trigger = optc2_program_manual_trigger,
357 .setup_manual_trigger = optc2_setup_manual_trigger,
358 .get_hw_timing = optc1_get_hw_timing,
359 };
360
dcn30_timing_generator_init(struct optc * optc1)361 void dcn30_timing_generator_init(struct optc *optc1)
362 {
363 optc1->base.funcs = &dcn30_tg_funcs;
364
365 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
366 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
367
368 optc1->min_h_blank = 32;
369 optc1->min_v_blank = 3;
370 optc1->min_v_blank_interlace = 5;
371 optc1->min_h_sync_width = 4;
372 optc1->min_v_sync_width = 1;
373 }
374
375