1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2021 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "resource.h"
28 #include "clk_mgr.h"
29 #include "dc_link_dp.h"
30 #include "dchubbub.h"
31 #include "dcn20/dcn20_resource.h"
32 #include "dcn21/dcn21_resource.h"
33
34 #include "dcn20_fpu.h"
35
36 #define DC_LOGGER_INIT(logger)
37
38 #ifndef MAX
39 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
40 #endif
41 #ifndef MIN
42 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
43 #endif
44
45 /**
46 * DOC: DCN2x FPU manipulation Overview
47 *
48 * The DCN architecture relies on FPU operations, which require special
49 * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
50 * want to avoid spreading FPU access across multiple files. With this idea in
51 * mind, this file aims to centralize all DCN20 and DCN2.1 (DCN2x) functions
52 * that require FPU access in a single place. Code in this file follows the
53 * following code pattern:
54 *
55 * 1. Functions that use FPU operations should be isolated in static functions.
56 * 2. The FPU functions should have the noinline attribute to ensure anything
57 * that deals with FP register is contained within this call.
58 * 3. All function that needs to be accessed outside this file requires a
59 * public interface that not uses any FPU reference.
60 * 4. Developers **must not** use DC_FP_START/END in this file, but they need
61 * to ensure that the caller invokes it before access any function available
62 * in this file. For this reason, public functions in this file must invoke
63 * dc_assert_fp_enabled();
64 *
65 * Let's expand a little bit more the idea in the code pattern. To fully
66 * isolate FPU operations in a single place, we must avoid situations where
67 * compilers spill FP values to registers due to FP enable in a specific C
68 * file. Note that even if we isolate all FPU functions in a single file and
69 * call its interface from other files, the compiler might enable the use of
70 * FPU before we call DC_FP_START. Nevertheless, it is the programmer's
71 * responsibility to invoke DC_FP_START/END in the correct place. To highlight
72 * situations where developers forgot to use the FP protection before calling
73 * the DC FPU interface functions, we introduce a helper that checks if the
74 * function is invoked under FP protection. If not, it will trigger a kernel
75 * warning.
76 */
77
78 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
79 .odm_capable = 1,
80 .gpuvm_enable = 0,
81 .hostvm_enable = 0,
82 .gpuvm_max_page_table_levels = 4,
83 .hostvm_max_page_table_levels = 4,
84 .hostvm_cached_page_table_levels = 0,
85 .pte_group_size_bytes = 2048,
86 .num_dsc = 6,
87 .rob_buffer_size_kbytes = 168,
88 .det_buffer_size_kbytes = 164,
89 .dpte_buffer_size_in_pte_reqs_luma = 84,
90 .pde_proc_buffer_size_64k_reqs = 48,
91 .dpp_output_buffer_pixels = 2560,
92 .opp_output_buffer_lines = 1,
93 .pixel_chunk_size_kbytes = 8,
94 .pte_chunk_size_kbytes = 2,
95 .meta_chunk_size_kbytes = 2,
96 .writeback_chunk_size_kbytes = 2,
97 .line_buffer_size_bits = 789504,
98 .is_line_buffer_bpp_fixed = 0,
99 .line_buffer_fixed_bpp = 0,
100 .dcc_supported = true,
101 .max_line_buffer_lines = 12,
102 .writeback_luma_buffer_size_kbytes = 12,
103 .writeback_chroma_buffer_size_kbytes = 8,
104 .writeback_chroma_line_buffer_width_pixels = 4,
105 .writeback_max_hscl_ratio = 1,
106 .writeback_max_vscl_ratio = 1,
107 .writeback_min_hscl_ratio = 1,
108 .writeback_min_vscl_ratio = 1,
109 .writeback_max_hscl_taps = 12,
110 .writeback_max_vscl_taps = 12,
111 .writeback_line_buffer_luma_buffer_size = 0,
112 .writeback_line_buffer_chroma_buffer_size = 14643,
113 .cursor_buffer_size = 8,
114 .cursor_chunk_size = 2,
115 .max_num_otg = 6,
116 .max_num_dpp = 6,
117 .max_num_wb = 1,
118 .max_dchub_pscl_bw_pix_per_clk = 4,
119 .max_pscl_lb_bw_pix_per_clk = 2,
120 .max_lb_vscl_bw_pix_per_clk = 4,
121 .max_vscl_hscl_bw_pix_per_clk = 4,
122 .max_hscl_ratio = 8,
123 .max_vscl_ratio = 8,
124 .hscl_mults = 4,
125 .vscl_mults = 4,
126 .max_hscl_taps = 8,
127 .max_vscl_taps = 8,
128 .dispclk_ramp_margin_percent = 1,
129 .underscan_factor = 1.10,
130 .min_vblank_lines = 32, //
131 .dppclk_delay_subtotal = 77, //
132 .dppclk_delay_scl_lb_only = 16,
133 .dppclk_delay_scl = 50,
134 .dppclk_delay_cnvc_formatter = 8,
135 .dppclk_delay_cnvc_cursor = 6,
136 .dispclk_delay_subtotal = 87, //
137 .dcfclk_cstate_latency = 10, // SRExitTime
138 .max_inter_dcn_tile_repeaters = 8,
139 .xfc_supported = true,
140 .xfc_fill_bw_overhead_percent = 10.0,
141 .xfc_fill_constant_bytes = 0,
142 .number_of_cursors = 1,
143 };
144
145 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
146 .odm_capable = 1,
147 .gpuvm_enable = 0,
148 .hostvm_enable = 0,
149 .gpuvm_max_page_table_levels = 4,
150 .hostvm_max_page_table_levels = 4,
151 .hostvm_cached_page_table_levels = 0,
152 .num_dsc = 5,
153 .rob_buffer_size_kbytes = 168,
154 .det_buffer_size_kbytes = 164,
155 .dpte_buffer_size_in_pte_reqs_luma = 84,
156 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
157 .dpp_output_buffer_pixels = 2560,
158 .opp_output_buffer_lines = 1,
159 .pixel_chunk_size_kbytes = 8,
160 .pte_enable = 1,
161 .max_page_table_levels = 4,
162 .pte_chunk_size_kbytes = 2,
163 .meta_chunk_size_kbytes = 2,
164 .writeback_chunk_size_kbytes = 2,
165 .line_buffer_size_bits = 789504,
166 .is_line_buffer_bpp_fixed = 0,
167 .line_buffer_fixed_bpp = 0,
168 .dcc_supported = true,
169 .max_line_buffer_lines = 12,
170 .writeback_luma_buffer_size_kbytes = 12,
171 .writeback_chroma_buffer_size_kbytes = 8,
172 .writeback_chroma_line_buffer_width_pixels = 4,
173 .writeback_max_hscl_ratio = 1,
174 .writeback_max_vscl_ratio = 1,
175 .writeback_min_hscl_ratio = 1,
176 .writeback_min_vscl_ratio = 1,
177 .writeback_max_hscl_taps = 12,
178 .writeback_max_vscl_taps = 12,
179 .writeback_line_buffer_luma_buffer_size = 0,
180 .writeback_line_buffer_chroma_buffer_size = 14643,
181 .cursor_buffer_size = 8,
182 .cursor_chunk_size = 2,
183 .max_num_otg = 5,
184 .max_num_dpp = 5,
185 .max_num_wb = 1,
186 .max_dchub_pscl_bw_pix_per_clk = 4,
187 .max_pscl_lb_bw_pix_per_clk = 2,
188 .max_lb_vscl_bw_pix_per_clk = 4,
189 .max_vscl_hscl_bw_pix_per_clk = 4,
190 .max_hscl_ratio = 8,
191 .max_vscl_ratio = 8,
192 .hscl_mults = 4,
193 .vscl_mults = 4,
194 .max_hscl_taps = 8,
195 .max_vscl_taps = 8,
196 .dispclk_ramp_margin_percent = 1,
197 .underscan_factor = 1.10,
198 .min_vblank_lines = 32, //
199 .dppclk_delay_subtotal = 77, //
200 .dppclk_delay_scl_lb_only = 16,
201 .dppclk_delay_scl = 50,
202 .dppclk_delay_cnvc_formatter = 8,
203 .dppclk_delay_cnvc_cursor = 6,
204 .dispclk_delay_subtotal = 87, //
205 .dcfclk_cstate_latency = 10, // SRExitTime
206 .max_inter_dcn_tile_repeaters = 8,
207 .xfc_supported = true,
208 .xfc_fill_bw_overhead_percent = 10.0,
209 .xfc_fill_constant_bytes = 0,
210 .ptoi_supported = 0,
211 .number_of_cursors = 1,
212 };
213
214 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
215 /* Defaults that get patched on driver load from firmware. */
216 .clock_limits = {
217 {
218 .state = 0,
219 .dcfclk_mhz = 560.0,
220 .fabricclk_mhz = 560.0,
221 .dispclk_mhz = 513.0,
222 .dppclk_mhz = 513.0,
223 .phyclk_mhz = 540.0,
224 .socclk_mhz = 560.0,
225 .dscclk_mhz = 171.0,
226 .dram_speed_mts = 8960.0,
227 },
228 {
229 .state = 1,
230 .dcfclk_mhz = 694.0,
231 .fabricclk_mhz = 694.0,
232 .dispclk_mhz = 642.0,
233 .dppclk_mhz = 642.0,
234 .phyclk_mhz = 600.0,
235 .socclk_mhz = 694.0,
236 .dscclk_mhz = 214.0,
237 .dram_speed_mts = 11104.0,
238 },
239 {
240 .state = 2,
241 .dcfclk_mhz = 875.0,
242 .fabricclk_mhz = 875.0,
243 .dispclk_mhz = 734.0,
244 .dppclk_mhz = 734.0,
245 .phyclk_mhz = 810.0,
246 .socclk_mhz = 875.0,
247 .dscclk_mhz = 245.0,
248 .dram_speed_mts = 14000.0,
249 },
250 {
251 .state = 3,
252 .dcfclk_mhz = 1000.0,
253 .fabricclk_mhz = 1000.0,
254 .dispclk_mhz = 1100.0,
255 .dppclk_mhz = 1100.0,
256 .phyclk_mhz = 810.0,
257 .socclk_mhz = 1000.0,
258 .dscclk_mhz = 367.0,
259 .dram_speed_mts = 16000.0,
260 },
261 {
262 .state = 4,
263 .dcfclk_mhz = 1200.0,
264 .fabricclk_mhz = 1200.0,
265 .dispclk_mhz = 1284.0,
266 .dppclk_mhz = 1284.0,
267 .phyclk_mhz = 810.0,
268 .socclk_mhz = 1200.0,
269 .dscclk_mhz = 428.0,
270 .dram_speed_mts = 16000.0,
271 },
272 /*Extra state, no dispclk ramping*/
273 {
274 .state = 5,
275 .dcfclk_mhz = 1200.0,
276 .fabricclk_mhz = 1200.0,
277 .dispclk_mhz = 1284.0,
278 .dppclk_mhz = 1284.0,
279 .phyclk_mhz = 810.0,
280 .socclk_mhz = 1200.0,
281 .dscclk_mhz = 428.0,
282 .dram_speed_mts = 16000.0,
283 },
284 },
285 .num_states = 5,
286 .sr_exit_time_us = 8.6,
287 .sr_enter_plus_exit_time_us = 10.9,
288 .urgent_latency_us = 4.0,
289 .urgent_latency_pixel_data_only_us = 4.0,
290 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
291 .urgent_latency_vm_data_only_us = 4.0,
292 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
293 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
294 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
295 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
296 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
297 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
298 .max_avg_sdp_bw_use_normal_percent = 40.0,
299 .max_avg_dram_bw_use_normal_percent = 40.0,
300 .writeback_latency_us = 12.0,
301 .ideal_dram_bw_after_urgent_percent = 40.0,
302 .max_request_size_bytes = 256,
303 .dram_channel_width_bytes = 2,
304 .fabric_datapath_to_dcn_data_return_bytes = 64,
305 .dcn_downspread_percent = 0.5,
306 .downspread_percent = 0.38,
307 .dram_page_open_time_ns = 50.0,
308 .dram_rw_turnaround_time_ns = 17.5,
309 .dram_return_buffer_per_channel_bytes = 8192,
310 .round_trip_ping_latency_dcfclk_cycles = 131,
311 .urgent_out_of_order_return_per_channel_bytes = 256,
312 .channel_interleave_bytes = 256,
313 .num_banks = 8,
314 .num_chans = 16,
315 .vmm_page_size_bytes = 4096,
316 .dram_clock_change_latency_us = 404.0,
317 .dummy_pstate_latency_us = 5.0,
318 .writeback_dram_clock_change_latency_us = 23.0,
319 .return_bus_width_bytes = 64,
320 .dispclk_dppclk_vco_speed_mhz = 3850,
321 .xfc_bus_transport_time_us = 20,
322 .xfc_xbuf_latency_tolerance_us = 4,
323 .use_urgent_burst_bw = 0
324 };
325
326 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
327 .clock_limits = {
328 {
329 .state = 0,
330 .dcfclk_mhz = 560.0,
331 .fabricclk_mhz = 560.0,
332 .dispclk_mhz = 513.0,
333 .dppclk_mhz = 513.0,
334 .phyclk_mhz = 540.0,
335 .socclk_mhz = 560.0,
336 .dscclk_mhz = 171.0,
337 .dram_speed_mts = 8960.0,
338 },
339 {
340 .state = 1,
341 .dcfclk_mhz = 694.0,
342 .fabricclk_mhz = 694.0,
343 .dispclk_mhz = 642.0,
344 .dppclk_mhz = 642.0,
345 .phyclk_mhz = 600.0,
346 .socclk_mhz = 694.0,
347 .dscclk_mhz = 214.0,
348 .dram_speed_mts = 11104.0,
349 },
350 {
351 .state = 2,
352 .dcfclk_mhz = 875.0,
353 .fabricclk_mhz = 875.0,
354 .dispclk_mhz = 734.0,
355 .dppclk_mhz = 734.0,
356 .phyclk_mhz = 810.0,
357 .socclk_mhz = 875.0,
358 .dscclk_mhz = 245.0,
359 .dram_speed_mts = 14000.0,
360 },
361 {
362 .state = 3,
363 .dcfclk_mhz = 1000.0,
364 .fabricclk_mhz = 1000.0,
365 .dispclk_mhz = 1100.0,
366 .dppclk_mhz = 1100.0,
367 .phyclk_mhz = 810.0,
368 .socclk_mhz = 1000.0,
369 .dscclk_mhz = 367.0,
370 .dram_speed_mts = 16000.0,
371 },
372 {
373 .state = 4,
374 .dcfclk_mhz = 1200.0,
375 .fabricclk_mhz = 1200.0,
376 .dispclk_mhz = 1284.0,
377 .dppclk_mhz = 1284.0,
378 .phyclk_mhz = 810.0,
379 .socclk_mhz = 1200.0,
380 .dscclk_mhz = 428.0,
381 .dram_speed_mts = 16000.0,
382 },
383 /*Extra state, no dispclk ramping*/
384 {
385 .state = 5,
386 .dcfclk_mhz = 1200.0,
387 .fabricclk_mhz = 1200.0,
388 .dispclk_mhz = 1284.0,
389 .dppclk_mhz = 1284.0,
390 .phyclk_mhz = 810.0,
391 .socclk_mhz = 1200.0,
392 .dscclk_mhz = 428.0,
393 .dram_speed_mts = 16000.0,
394 },
395 },
396 .num_states = 5,
397 .sr_exit_time_us = 11.6,
398 .sr_enter_plus_exit_time_us = 13.9,
399 .urgent_latency_us = 4.0,
400 .urgent_latency_pixel_data_only_us = 4.0,
401 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
402 .urgent_latency_vm_data_only_us = 4.0,
403 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
404 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
405 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
406 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
407 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
408 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
409 .max_avg_sdp_bw_use_normal_percent = 40.0,
410 .max_avg_dram_bw_use_normal_percent = 40.0,
411 .writeback_latency_us = 12.0,
412 .ideal_dram_bw_after_urgent_percent = 40.0,
413 .max_request_size_bytes = 256,
414 .dram_channel_width_bytes = 2,
415 .fabric_datapath_to_dcn_data_return_bytes = 64,
416 .dcn_downspread_percent = 0.5,
417 .downspread_percent = 0.38,
418 .dram_page_open_time_ns = 50.0,
419 .dram_rw_turnaround_time_ns = 17.5,
420 .dram_return_buffer_per_channel_bytes = 8192,
421 .round_trip_ping_latency_dcfclk_cycles = 131,
422 .urgent_out_of_order_return_per_channel_bytes = 256,
423 .channel_interleave_bytes = 256,
424 .num_banks = 8,
425 .num_chans = 8,
426 .vmm_page_size_bytes = 4096,
427 .dram_clock_change_latency_us = 404.0,
428 .dummy_pstate_latency_us = 5.0,
429 .writeback_dram_clock_change_latency_us = 23.0,
430 .return_bus_width_bytes = 64,
431 .dispclk_dppclk_vco_speed_mhz = 3850,
432 .xfc_bus_transport_time_us = 20,
433 .xfc_xbuf_latency_tolerance_us = 4,
434 .use_urgent_burst_bw = 0
435 };
436
437 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
438
439 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
440 .odm_capable = 1,
441 .gpuvm_enable = 1,
442 .hostvm_enable = 1,
443 .gpuvm_max_page_table_levels = 1,
444 .hostvm_max_page_table_levels = 4,
445 .hostvm_cached_page_table_levels = 2,
446 .num_dsc = 3,
447 .rob_buffer_size_kbytes = 168,
448 .det_buffer_size_kbytes = 164,
449 .dpte_buffer_size_in_pte_reqs_luma = 44,
450 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
451 .dpp_output_buffer_pixels = 2560,
452 .opp_output_buffer_lines = 1,
453 .pixel_chunk_size_kbytes = 8,
454 .pte_enable = 1,
455 .max_page_table_levels = 4,
456 .pte_chunk_size_kbytes = 2,
457 .meta_chunk_size_kbytes = 2,
458 .min_meta_chunk_size_bytes = 256,
459 .writeback_chunk_size_kbytes = 2,
460 .line_buffer_size_bits = 789504,
461 .is_line_buffer_bpp_fixed = 0,
462 .line_buffer_fixed_bpp = 0,
463 .dcc_supported = true,
464 .max_line_buffer_lines = 12,
465 .writeback_luma_buffer_size_kbytes = 12,
466 .writeback_chroma_buffer_size_kbytes = 8,
467 .writeback_chroma_line_buffer_width_pixels = 4,
468 .writeback_max_hscl_ratio = 1,
469 .writeback_max_vscl_ratio = 1,
470 .writeback_min_hscl_ratio = 1,
471 .writeback_min_vscl_ratio = 1,
472 .writeback_max_hscl_taps = 12,
473 .writeback_max_vscl_taps = 12,
474 .writeback_line_buffer_luma_buffer_size = 0,
475 .writeback_line_buffer_chroma_buffer_size = 14643,
476 .cursor_buffer_size = 8,
477 .cursor_chunk_size = 2,
478 .max_num_otg = 4,
479 .max_num_dpp = 4,
480 .max_num_wb = 1,
481 .max_dchub_pscl_bw_pix_per_clk = 4,
482 .max_pscl_lb_bw_pix_per_clk = 2,
483 .max_lb_vscl_bw_pix_per_clk = 4,
484 .max_vscl_hscl_bw_pix_per_clk = 4,
485 .max_hscl_ratio = 4,
486 .max_vscl_ratio = 4,
487 .hscl_mults = 4,
488 .vscl_mults = 4,
489 .max_hscl_taps = 8,
490 .max_vscl_taps = 8,
491 .dispclk_ramp_margin_percent = 1,
492 .underscan_factor = 1.10,
493 .min_vblank_lines = 32, //
494 .dppclk_delay_subtotal = 77, //
495 .dppclk_delay_scl_lb_only = 16,
496 .dppclk_delay_scl = 50,
497 .dppclk_delay_cnvc_formatter = 8,
498 .dppclk_delay_cnvc_cursor = 6,
499 .dispclk_delay_subtotal = 87, //
500 .dcfclk_cstate_latency = 10, // SRExitTime
501 .max_inter_dcn_tile_repeaters = 8,
502
503 .xfc_supported = false,
504 .xfc_fill_bw_overhead_percent = 10.0,
505 .xfc_fill_constant_bytes = 0,
506 .ptoi_supported = 0,
507 .number_of_cursors = 1,
508 };
509
510 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
511 .clock_limits = {
512 {
513 .state = 0,
514 .dcfclk_mhz = 400.0,
515 .fabricclk_mhz = 400.0,
516 .dispclk_mhz = 600.0,
517 .dppclk_mhz = 400.00,
518 .phyclk_mhz = 600.0,
519 .socclk_mhz = 278.0,
520 .dscclk_mhz = 205.67,
521 .dram_speed_mts = 1600.0,
522 },
523 {
524 .state = 1,
525 .dcfclk_mhz = 464.52,
526 .fabricclk_mhz = 800.0,
527 .dispclk_mhz = 654.55,
528 .dppclk_mhz = 626.09,
529 .phyclk_mhz = 600.0,
530 .socclk_mhz = 278.0,
531 .dscclk_mhz = 205.67,
532 .dram_speed_mts = 1600.0,
533 },
534 {
535 .state = 2,
536 .dcfclk_mhz = 514.29,
537 .fabricclk_mhz = 933.0,
538 .dispclk_mhz = 757.89,
539 .dppclk_mhz = 685.71,
540 .phyclk_mhz = 600.0,
541 .socclk_mhz = 278.0,
542 .dscclk_mhz = 287.67,
543 .dram_speed_mts = 1866.0,
544 },
545 {
546 .state = 3,
547 .dcfclk_mhz = 576.00,
548 .fabricclk_mhz = 1067.0,
549 .dispclk_mhz = 847.06,
550 .dppclk_mhz = 757.89,
551 .phyclk_mhz = 600.0,
552 .socclk_mhz = 715.0,
553 .dscclk_mhz = 318.334,
554 .dram_speed_mts = 2134.0,
555 },
556 {
557 .state = 4,
558 .dcfclk_mhz = 626.09,
559 .fabricclk_mhz = 1200.0,
560 .dispclk_mhz = 900.00,
561 .dppclk_mhz = 847.06,
562 .phyclk_mhz = 810.0,
563 .socclk_mhz = 953.0,
564 .dscclk_mhz = 489.0,
565 .dram_speed_mts = 2400.0,
566 },
567 {
568 .state = 5,
569 .dcfclk_mhz = 685.71,
570 .fabricclk_mhz = 1333.0,
571 .dispclk_mhz = 1028.57,
572 .dppclk_mhz = 960.00,
573 .phyclk_mhz = 810.0,
574 .socclk_mhz = 278.0,
575 .dscclk_mhz = 287.67,
576 .dram_speed_mts = 2666.0,
577 },
578 {
579 .state = 6,
580 .dcfclk_mhz = 757.89,
581 .fabricclk_mhz = 1467.0,
582 .dispclk_mhz = 1107.69,
583 .dppclk_mhz = 1028.57,
584 .phyclk_mhz = 810.0,
585 .socclk_mhz = 715.0,
586 .dscclk_mhz = 318.334,
587 .dram_speed_mts = 3200.0,
588 },
589 {
590 .state = 7,
591 .dcfclk_mhz = 847.06,
592 .fabricclk_mhz = 1600.0,
593 .dispclk_mhz = 1395.0,
594 .dppclk_mhz = 1285.00,
595 .phyclk_mhz = 1325.0,
596 .socclk_mhz = 953.0,
597 .dscclk_mhz = 489.0,
598 .dram_speed_mts = 4266.0,
599 },
600 /*Extra state, no dispclk ramping*/
601 {
602 .state = 8,
603 .dcfclk_mhz = 847.06,
604 .fabricclk_mhz = 1600.0,
605 .dispclk_mhz = 1395.0,
606 .dppclk_mhz = 1285.0,
607 .phyclk_mhz = 1325.0,
608 .socclk_mhz = 953.0,
609 .dscclk_mhz = 489.0,
610 .dram_speed_mts = 4266.0,
611 },
612
613 },
614
615 .sr_exit_time_us = 12.5,
616 .sr_enter_plus_exit_time_us = 17.0,
617 .urgent_latency_us = 4.0,
618 .urgent_latency_pixel_data_only_us = 4.0,
619 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
620 .urgent_latency_vm_data_only_us = 4.0,
621 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
622 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
623 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
624 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
625 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
626 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
627 .max_avg_sdp_bw_use_normal_percent = 60.0,
628 .max_avg_dram_bw_use_normal_percent = 100.0,
629 .writeback_latency_us = 12.0,
630 .max_request_size_bytes = 256,
631 .dram_channel_width_bytes = 4,
632 .fabric_datapath_to_dcn_data_return_bytes = 32,
633 .dcn_downspread_percent = 0.5,
634 .downspread_percent = 0.38,
635 .dram_page_open_time_ns = 50.0,
636 .dram_rw_turnaround_time_ns = 17.5,
637 .dram_return_buffer_per_channel_bytes = 8192,
638 .round_trip_ping_latency_dcfclk_cycles = 128,
639 .urgent_out_of_order_return_per_channel_bytes = 4096,
640 .channel_interleave_bytes = 256,
641 .num_banks = 8,
642 .num_chans = 4,
643 .vmm_page_size_bytes = 4096,
644 .dram_clock_change_latency_us = 23.84,
645 .return_bus_width_bytes = 64,
646 .dispclk_dppclk_vco_speed_mhz = 3600,
647 .xfc_bus_transport_time_us = 4,
648 .xfc_xbuf_latency_tolerance_us = 4,
649 .use_urgent_burst_bw = 1,
650 .num_states = 8
651 };
652
dcn20_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)653 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
654 struct resource_context *res_ctx,
655 display_e2e_pipe_params_st *pipes)
656 {
657 int pipe_cnt, i;
658
659 dc_assert_fp_enabled();
660
661 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
662 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
663
664 if (!res_ctx->pipe_ctx[i].stream)
665 continue;
666
667 /* Set writeback information */
668 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
669 pipes[pipe_cnt].dout.num_active_wb++;
670 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
671 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
672 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
673 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
674 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
675 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
676 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
677 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
678 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
679 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
680 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
681 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
682 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
683 else
684 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
685 } else {
686 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
687 }
688
689 pipe_cnt++;
690 }
691 }
692
dcn20_fpu_set_wb_arb_params(struct mcif_arb_params * wb_arb_params,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int i)693 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
694 struct dc_state *context,
695 display_e2e_pipe_params_st *pipes,
696 int pipe_cnt, int i)
697 {
698 int k;
699
700 dc_assert_fp_enabled();
701
702 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
703 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
704 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
705 }
706 wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
707 }
708
is_dtbclk_required(struct dc * dc,struct dc_state * context)709 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
710 {
711 int i;
712 for (i = 0; i < dc->res_pool->pipe_count; i++) {
713 if (!context->res_ctx.pipe_ctx[i].stream)
714 continue;
715 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
716 return true;
717 }
718 return false;
719 }
720
decide_zstate_support(struct dc * dc,struct dc_state * context)721 static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context)
722 {
723 int plane_count;
724 int i;
725 unsigned int optimized_min_dst_y_next_start_us;
726
727 plane_count = 0;
728 optimized_min_dst_y_next_start_us = 0;
729 for (i = 0; i < dc->res_pool->pipe_count; i++) {
730 if (context->res_ctx.pipe_ctx[i].plane_state)
731 plane_count++;
732 }
733
734 /*
735 * Z9 and Z10 allowed cases:
736 * 1. 0 Planes enabled
737 * 2. single eDP, on link 0, 1 plane and stutter period > 5ms
738 * Z10 only cases:
739 * 1. single eDP, on link 0, 1 plane and stutter period >= 5ms
740 * Zstate not allowed cases:
741 * 1. Everything else
742 */
743 if (plane_count == 0)
744 return DCN_ZSTATE_SUPPORT_ALLOW;
745 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
746 struct dc_link *link = context->streams[0]->sink->link;
747 struct dc_stream_status *stream_status = &context->stream_status[0];
748
749 if (dc_extended_blank_supported(dc)) {
750 for (i = 0; i < dc->res_pool->pipe_count; i++) {
751 if (context->res_ctx.pipe_ctx[i].stream == context->streams[0]
752 && context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min == context->res_ctx.pipe_ctx[i].stream->adjust.v_total_max
753 && context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min > context->res_ctx.pipe_ctx[i].stream->timing.v_total) {
754 optimized_min_dst_y_next_start_us =
755 context->res_ctx.pipe_ctx[i].dlg_regs.optimized_min_dst_y_next_start_us;
756 break;
757 }
758 }
759 }
760 /* zstate only supported on PWRSEQ0 and when there's <2 planes*/
761 if (link->link_index != 0 || stream_status->plane_count > 1)
762 return DCN_ZSTATE_SUPPORT_DISALLOW;
763
764 if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000)
765 return DCN_ZSTATE_SUPPORT_ALLOW;
766 else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !dc->debug.disable_psr)
767 return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
768 else
769 return DCN_ZSTATE_SUPPORT_DISALLOW;
770 } else
771 return DCN_ZSTATE_SUPPORT_DISALLOW;
772 }
773
dcn20_calculate_dlg_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)774 void dcn20_calculate_dlg_params(
775 struct dc *dc, struct dc_state *context,
776 display_e2e_pipe_params_st *pipes,
777 int pipe_cnt,
778 int vlevel)
779 {
780 int i, pipe_idx;
781
782 dc_assert_fp_enabled();
783
784 /* Writeback MCIF_WB arbitration parameters */
785 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
786
787 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
788 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
789 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
790 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
791
792 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
793 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
794
795 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
796 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
797 context->bw_ctx.bw.dcn.clk.p_state_change_support =
798 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
799 != dm_dram_clock_change_unsupported;
800 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
801
802 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
803
804 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
805 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
806
807 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
808 if (!context->res_ctx.pipe_ctx[i].stream)
809 continue;
810 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
811 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
812 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
813 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
814 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
815 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
816
817 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
818 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
819 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
820 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
821 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
822 pipe_idx++;
823 }
824 /*save a original dppclock copy*/
825 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
826 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
827 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
828 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
829
830 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
831 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
832
833 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
834 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
835
836 if (!context->res_ctx.pipe_ctx[i].stream)
837 continue;
838
839 if (dc->ctx->dce_version == DCN_VERSION_2_01)
840 cstate_en = false;
841
842 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
843 &context->res_ctx.pipe_ctx[i].dlg_regs,
844 &context->res_ctx.pipe_ctx[i].ttu_regs,
845 pipes,
846 pipe_cnt,
847 pipe_idx,
848 cstate_en,
849 context->bw_ctx.bw.dcn.clk.p_state_change_support,
850 false, false, true);
851
852 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
853 &context->res_ctx.pipe_ctx[i].rq_regs,
854 &pipes[pipe_idx].pipe);
855 pipe_idx++;
856 }
857 context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
858 }
859
swizzle_to_dml_params(enum swizzle_mode_values swizzle,unsigned int * sw_mode)860 static void swizzle_to_dml_params(
861 enum swizzle_mode_values swizzle,
862 unsigned int *sw_mode)
863 {
864 switch (swizzle) {
865 case DC_SW_LINEAR:
866 *sw_mode = dm_sw_linear;
867 break;
868 case DC_SW_4KB_S:
869 *sw_mode = dm_sw_4kb_s;
870 break;
871 case DC_SW_4KB_S_X:
872 *sw_mode = dm_sw_4kb_s_x;
873 break;
874 case DC_SW_4KB_D:
875 *sw_mode = dm_sw_4kb_d;
876 break;
877 case DC_SW_4KB_D_X:
878 *sw_mode = dm_sw_4kb_d_x;
879 break;
880 case DC_SW_64KB_S:
881 *sw_mode = dm_sw_64kb_s;
882 break;
883 case DC_SW_64KB_S_X:
884 *sw_mode = dm_sw_64kb_s_x;
885 break;
886 case DC_SW_64KB_S_T:
887 *sw_mode = dm_sw_64kb_s_t;
888 break;
889 case DC_SW_64KB_D:
890 *sw_mode = dm_sw_64kb_d;
891 break;
892 case DC_SW_64KB_D_X:
893 *sw_mode = dm_sw_64kb_d_x;
894 break;
895 case DC_SW_64KB_D_T:
896 *sw_mode = dm_sw_64kb_d_t;
897 break;
898 case DC_SW_64KB_R_X:
899 *sw_mode = dm_sw_64kb_r_x;
900 break;
901 case DC_SW_VAR_S:
902 *sw_mode = dm_sw_var_s;
903 break;
904 case DC_SW_VAR_S_X:
905 *sw_mode = dm_sw_var_s_x;
906 break;
907 case DC_SW_VAR_D:
908 *sw_mode = dm_sw_var_d;
909 break;
910 case DC_SW_VAR_D_X:
911 *sw_mode = dm_sw_var_d_x;
912 break;
913 case DC_SW_VAR_R_X:
914 *sw_mode = dm_sw_var_r_x;
915 break;
916 default:
917 ASSERT(0); /* Not supported */
918 break;
919 }
920 }
921
dcn20_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)922 int dcn20_populate_dml_pipes_from_context(
923 struct dc *dc,
924 struct dc_state *context,
925 display_e2e_pipe_params_st *pipes,
926 bool fast_validate)
927 {
928 int pipe_cnt, i;
929 bool synchronized_vblank = true;
930 struct resource_context *res_ctx = &context->res_ctx;
931
932 dc_assert_fp_enabled();
933
934 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
935 if (!res_ctx->pipe_ctx[i].stream)
936 continue;
937
938 if (pipe_cnt < 0) {
939 pipe_cnt = i;
940 continue;
941 }
942
943 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
944 continue;
945
946 if (dc->debug.disable_timing_sync ||
947 (!resource_are_streams_timing_synchronizable(
948 res_ctx->pipe_ctx[pipe_cnt].stream,
949 res_ctx->pipe_ctx[i].stream) &&
950 !resource_are_vblanks_synchronizable(
951 res_ctx->pipe_ctx[pipe_cnt].stream,
952 res_ctx->pipe_ctx[i].stream))) {
953 synchronized_vblank = false;
954 break;
955 }
956 }
957
958 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
959 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
960 unsigned int v_total;
961 unsigned int front_porch;
962 int output_bpc;
963 struct audio_check aud_check = {0};
964
965 if (!res_ctx->pipe_ctx[i].stream)
966 continue;
967
968 v_total = timing->v_total;
969 front_porch = timing->v_front_porch;
970
971 /* todo:
972 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
973 pipes[pipe_cnt].pipe.src.dcc = 0;
974 pipes[pipe_cnt].pipe.src.vm = 0;*/
975
976 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
977
978 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
979 /* todo: rotation?*/
980 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
981 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
982 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
983 /* 1/2 vblank */
984 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
985 (v_total - timing->v_addressable
986 - timing->v_border_top - timing->v_border_bottom) / 2;
987 /* 36 bytes dp, 32 hdmi */
988 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
989 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
990 }
991 pipes[pipe_cnt].pipe.src.dcc = false;
992 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
993 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
994 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
995 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
996 - timing->h_addressable
997 - timing->h_border_left
998 - timing->h_border_right;
999 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
1000 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1001 - timing->v_addressable
1002 - timing->v_border_top
1003 - timing->v_border_bottom;
1004 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1005 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
1006 pipes[pipe_cnt].pipe.dest.hactive =
1007 timing->h_addressable + timing->h_border_left + timing->h_border_right;
1008 pipes[pipe_cnt].pipe.dest.vactive =
1009 timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1010 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1011 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1012 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1013 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1014 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1015 pipes[pipe_cnt].dout.dp_lanes = 4;
1016 pipes[pipe_cnt].dout.is_virtual = 0;
1017 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1018 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1019 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
1020 case 1:
1021 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
1022 break;
1023 case 3:
1024 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
1025 break;
1026 default:
1027 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
1028 }
1029 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1030 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1031 == res_ctx->pipe_ctx[i].plane_state) {
1032 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
1033 int split_idx = 0;
1034
1035 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
1036 == res_ctx->pipe_ctx[i].plane_state) {
1037 first_pipe = first_pipe->top_pipe;
1038 split_idx++;
1039 }
1040 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
1041 if (split_idx == 0)
1042 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1043 else if (split_idx == 1)
1044 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1045 else if (split_idx == 2)
1046 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1047 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1048 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1049
1050 while (first_pipe->prev_odm_pipe)
1051 first_pipe = first_pipe->prev_odm_pipe;
1052 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1053 }
1054
1055 switch (res_ctx->pipe_ctx[i].stream->signal) {
1056 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1057 case SIGNAL_TYPE_DISPLAY_PORT:
1058 pipes[pipe_cnt].dout.output_type = dm_dp;
1059 break;
1060 case SIGNAL_TYPE_EDP:
1061 pipes[pipe_cnt].dout.output_type = dm_edp;
1062 break;
1063 case SIGNAL_TYPE_HDMI_TYPE_A:
1064 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1065 case SIGNAL_TYPE_DVI_DUAL_LINK:
1066 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1067 break;
1068 default:
1069 /* In case there is no signal, set dp with 4 lanes to allow max config */
1070 pipes[pipe_cnt].dout.is_virtual = 1;
1071 pipes[pipe_cnt].dout.output_type = dm_dp;
1072 pipes[pipe_cnt].dout.dp_lanes = 4;
1073 }
1074
1075 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1076 case COLOR_DEPTH_666:
1077 output_bpc = 6;
1078 break;
1079 case COLOR_DEPTH_888:
1080 output_bpc = 8;
1081 break;
1082 case COLOR_DEPTH_101010:
1083 output_bpc = 10;
1084 break;
1085 case COLOR_DEPTH_121212:
1086 output_bpc = 12;
1087 break;
1088 case COLOR_DEPTH_141414:
1089 output_bpc = 14;
1090 break;
1091 case COLOR_DEPTH_161616:
1092 output_bpc = 16;
1093 break;
1094 case COLOR_DEPTH_999:
1095 output_bpc = 9;
1096 break;
1097 case COLOR_DEPTH_111111:
1098 output_bpc = 11;
1099 break;
1100 default:
1101 output_bpc = 8;
1102 break;
1103 }
1104
1105 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1106 case PIXEL_ENCODING_RGB:
1107 case PIXEL_ENCODING_YCBCR444:
1108 pipes[pipe_cnt].dout.output_format = dm_444;
1109 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1110 break;
1111 case PIXEL_ENCODING_YCBCR420:
1112 pipes[pipe_cnt].dout.output_format = dm_420;
1113 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
1114 break;
1115 case PIXEL_ENCODING_YCBCR422:
1116 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
1117 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
1118 pipes[pipe_cnt].dout.output_format = dm_n422;
1119 else
1120 pipes[pipe_cnt].dout.output_format = dm_s422;
1121 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1122 break;
1123 default:
1124 pipes[pipe_cnt].dout.output_format = dm_444;
1125 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1126 }
1127
1128 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
1129 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
1130
1131 /* todo: default max for now, until there is logic reflecting this in dc*/
1132 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1133 /*fill up the audio sample rate (unit in kHz)*/
1134 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
1135 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
1136 /*
1137 * For graphic plane, cursor number is 1, nv12 is 0
1138 * bw calculations due to cursor on/off
1139 */
1140 if (res_ctx->pipe_ctx[i].plane_state &&
1141 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
1142 pipes[pipe_cnt].pipe.src.num_cursors = 0;
1143 else
1144 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
1145
1146 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1147 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1148
1149 if (!res_ctx->pipe_ctx[i].plane_state) {
1150 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1151 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1152 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
1153 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1154 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1155 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1156 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1157 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1158 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1159 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1160 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
1161 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
1162 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
1163 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
1164 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
1165 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1166 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1167 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1168 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
1169 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1170 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1171 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1172 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1173 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1174 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1175 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1176 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
1177 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
1178
1179 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
1180 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
1181 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
1182 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
1183 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
1184 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
1185 }
1186 } else {
1187 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1188 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1189
1190 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1191 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1192 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
1193 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1194
1195 /* stereo is not split */
1196 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
1197 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
1198 pipes[pipe_cnt].pipe.src.is_hsplit = false;
1199 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1200 }
1201
1202 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1203 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1204 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1205 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1206 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1207 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1208 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1209 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1210 pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
1211 pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
1212 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
1213 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
1214 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
1215 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
1216 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
1217 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1218 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1219 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1220 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1221 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
1222 } else {
1223 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1224 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1225 }
1226 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1227 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1228 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1229 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1230 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1231 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
1232 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
1233 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
1234 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
1235 else {
1236 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
1237
1238 while (split_pipe && split_pipe->plane_state == pln) {
1239 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1240 split_pipe = split_pipe->bottom_pipe;
1241 }
1242 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
1243 while (split_pipe && split_pipe->plane_state == pln) {
1244 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1245 split_pipe = split_pipe->top_pipe;
1246 }
1247 }
1248
1249 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1250 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1251 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1252 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1253 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1254 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1255 scl->ratios.vert.value != dc_fixpt_one.value
1256 || scl->ratios.horz.value != dc_fixpt_one.value
1257 || scl->ratios.vert_c.value != dc_fixpt_one.value
1258 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1259 || dc->debug.always_scale; /*support always scale*/
1260 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1261 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1262 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1263 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1264
1265 pipes[pipe_cnt].pipe.src.macro_tile_size =
1266 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
1267 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1268 &pipes[pipe_cnt].pipe.src.sw_mode);
1269
1270 switch (pln->format) {
1271 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1272 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1273 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1274 break;
1275 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1276 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1277 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1278 break;
1279 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1280 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
1281 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1282 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1283 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1284 break;
1285 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1286 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1287 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1288 break;
1289 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1290 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1291 break;
1292 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
1293 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
1294 break;
1295 default:
1296 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1297 break;
1298 }
1299 }
1300
1301 pipe_cnt++;
1302 }
1303
1304 /* populate writeback information */
1305 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1306
1307 return pipe_cnt;
1308 }
1309
dcn20_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel,bool fast_validate)1310 void dcn20_calculate_wm(
1311 struct dc *dc, struct dc_state *context,
1312 display_e2e_pipe_params_st *pipes,
1313 int *out_pipe_cnt,
1314 int *pipe_split_from,
1315 int vlevel,
1316 bool fast_validate)
1317 {
1318 int pipe_cnt, i, pipe_idx;
1319
1320 dc_assert_fp_enabled();
1321
1322 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1323 if (!context->res_ctx.pipe_ctx[i].stream)
1324 continue;
1325
1326 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1327 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1328
1329 if (pipe_split_from[i] < 0) {
1330 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1331 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1332 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1333 pipes[pipe_cnt].pipe.dest.odm_combine =
1334 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
1335 else
1336 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1337 pipe_idx++;
1338 } else {
1339 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1340 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1341 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1342 pipes[pipe_cnt].pipe.dest.odm_combine =
1343 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
1344 else
1345 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1346 }
1347
1348 if (dc->config.forced_clocks) {
1349 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1350 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1351 }
1352 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
1353 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1354 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
1355 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1356
1357 pipe_cnt++;
1358 }
1359
1360 if (pipe_cnt != pipe_idx) {
1361 if (dc->res_pool->funcs->populate_dml_pipes)
1362 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1363 context, pipes, fast_validate);
1364 else
1365 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
1366 context, pipes, fast_validate);
1367 }
1368
1369 *out_pipe_cnt = pipe_cnt;
1370
1371 pipes[0].clks_cfg.voltage = vlevel;
1372 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1373 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1374
1375 /* only pipe 0 is read for voltage and dcf/soc clocks */
1376 if (vlevel < 1) {
1377 pipes[0].clks_cfg.voltage = 1;
1378 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
1379 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
1380 }
1381 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1382 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1383 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1384 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1385 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1386 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1387 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1388 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1389
1390 if (vlevel < 2) {
1391 pipes[0].clks_cfg.voltage = 2;
1392 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1393 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1394 }
1395 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1396 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1397 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1398 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1399 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1400 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1401 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1402
1403 if (vlevel < 3) {
1404 pipes[0].clks_cfg.voltage = 3;
1405 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1406 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1407 }
1408 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1409 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1410 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1411 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1412 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1413 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1414 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1415
1416 pipes[0].clks_cfg.voltage = vlevel;
1417 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1418 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1419 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1420 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1421 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1422 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1423 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1424 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1425 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1426 }
1427
dcn20_update_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb,struct pp_smu_nv_clock_table * max_clocks,unsigned int * uclk_states,unsigned int num_states)1428 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
1429 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
1430 {
1431 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
1432 int i;
1433 int num_calculated_states = 0;
1434 int min_dcfclk = 0;
1435
1436 dc_assert_fp_enabled();
1437
1438 if (num_states == 0)
1439 return;
1440
1441 memset(calculated_states, 0, sizeof(calculated_states));
1442
1443 if (dc->bb_overrides.min_dcfclk_mhz > 0)
1444 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
1445 else {
1446 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
1447 min_dcfclk = 310;
1448 else
1449 // Accounting for SOC/DCF relationship, we can go as high as
1450 // 506Mhz in Vmin.
1451 min_dcfclk = 506;
1452 }
1453
1454 for (i = 0; i < num_states; i++) {
1455 int min_fclk_required_by_uclk;
1456 calculated_states[i].state = i;
1457 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
1458
1459 // FCLK:UCLK ratio is 1.08
1460 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
1461 1000000);
1462
1463 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
1464 min_dcfclk : min_fclk_required_by_uclk;
1465
1466 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
1467 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
1468
1469 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
1470 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
1471
1472 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
1473 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
1474 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
1475
1476 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
1477
1478 num_calculated_states++;
1479 }
1480
1481 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
1482 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
1483 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
1484
1485 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
1486 bb->num_states = num_calculated_states;
1487
1488 // Duplicate the last state, DML always an extra state identical to max state to work
1489 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
1490 bb->clock_limits[num_calculated_states].state = bb->num_states;
1491 }
1492
dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st * bb,struct pp_smu_nv_clock_table max_clocks)1493 void dcn20_cap_soc_clocks(
1494 struct _vcs_dpi_soc_bounding_box_st *bb,
1495 struct pp_smu_nv_clock_table max_clocks)
1496 {
1497 int i;
1498
1499 dc_assert_fp_enabled();
1500
1501 // First pass - cap all clocks higher than the reported max
1502 for (i = 0; i < bb->num_states; i++) {
1503 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
1504 && max_clocks.dcfClockInKhz != 0)
1505 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
1506
1507 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
1508 && max_clocks.uClockInKhz != 0)
1509 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
1510
1511 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
1512 && max_clocks.fabricClockInKhz != 0)
1513 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
1514
1515 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
1516 && max_clocks.displayClockInKhz != 0)
1517 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
1518
1519 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
1520 && max_clocks.dppClockInKhz != 0)
1521 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
1522
1523 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
1524 && max_clocks.phyClockInKhz != 0)
1525 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
1526
1527 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
1528 && max_clocks.socClockInKhz != 0)
1529 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
1530
1531 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
1532 && max_clocks.dscClockInKhz != 0)
1533 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
1534 }
1535
1536 // Second pass - remove all duplicate clock states
1537 for (i = bb->num_states - 1; i > 1; i--) {
1538 bool duplicate = true;
1539
1540 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
1541 duplicate = false;
1542 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
1543 duplicate = false;
1544 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
1545 duplicate = false;
1546 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
1547 duplicate = false;
1548 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
1549 duplicate = false;
1550 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
1551 duplicate = false;
1552 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
1553 duplicate = false;
1554 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
1555 duplicate = false;
1556
1557 if (duplicate)
1558 bb->num_states--;
1559 }
1560 }
1561
dcn20_patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)1562 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1563 {
1564 dc_assert_fp_enabled();
1565
1566 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
1567 && dc->bb_overrides.sr_exit_time_ns) {
1568 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
1569 }
1570
1571 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
1572 != dc->bb_overrides.sr_enter_plus_exit_time_ns
1573 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1574 bb->sr_enter_plus_exit_time_us =
1575 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1576 }
1577
1578 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
1579 && dc->bb_overrides.urgent_latency_ns) {
1580 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1581 }
1582
1583 if ((int)(bb->dram_clock_change_latency_us * 1000)
1584 != dc->bb_overrides.dram_clock_change_latency_ns
1585 && dc->bb_overrides.dram_clock_change_latency_ns) {
1586 bb->dram_clock_change_latency_us =
1587 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1588 }
1589
1590 if ((int)(bb->dummy_pstate_latency_us * 1000)
1591 != dc->bb_overrides.dummy_clock_change_latency_ns
1592 && dc->bb_overrides.dummy_clock_change_latency_ns) {
1593 bb->dummy_pstate_latency_us =
1594 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
1595 }
1596 }
1597
dcn20_validate_bandwidth_internal(struct dc * dc,struct dc_state * context,bool fast_validate)1598 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
1599 bool fast_validate)
1600 {
1601 bool out = false;
1602
1603 BW_VAL_TRACE_SETUP();
1604
1605 int vlevel = 0;
1606 int pipe_split_from[MAX_PIPES];
1607 int pipe_cnt = 0;
1608 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1609 DC_LOGGER_INIT(dc->ctx->logger);
1610
1611 BW_VAL_TRACE_COUNT();
1612
1613 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1614
1615 if (pipe_cnt == 0)
1616 goto validate_out;
1617
1618 if (!out)
1619 goto validate_fail;
1620
1621 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1622
1623 if (fast_validate) {
1624 BW_VAL_TRACE_SKIP(fast);
1625 goto validate_out;
1626 }
1627
1628 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1629 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1630
1631 BW_VAL_TRACE_END_WATERMARKS();
1632
1633 goto validate_out;
1634
1635 validate_fail:
1636 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1637 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1638
1639 BW_VAL_TRACE_SKIP(fail);
1640 out = false;
1641
1642 validate_out:
1643 kfree(pipes);
1644
1645 BW_VAL_TRACE_FINISH();
1646
1647 return out;
1648 }
1649
dcn20_validate_bandwidth_fp(struct dc * dc,struct dc_state * context,bool fast_validate)1650 bool dcn20_validate_bandwidth_fp(struct dc *dc,
1651 struct dc_state *context,
1652 bool fast_validate)
1653 {
1654 bool voltage_supported = false;
1655 bool full_pstate_supported = false;
1656 bool dummy_pstate_supported = false;
1657 double p_state_latency_us;
1658
1659 dc_assert_fp_enabled();
1660
1661 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
1662 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
1663 dc->debug.disable_dram_clock_change_vactive_support;
1664 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
1665 dc->debug.enable_dram_clock_change_one_display_vactive;
1666
1667 /*Unsafe due to current pipe merge and split logic*/
1668 ASSERT(context != dc->current_state);
1669
1670 if (fast_validate) {
1671 return dcn20_validate_bandwidth_internal(dc, context, true);
1672 }
1673
1674 // Best case, we support full UCLK switch latency
1675 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
1676 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1677
1678 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
1679 (voltage_supported && full_pstate_supported)) {
1680 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
1681 goto restore_dml_state;
1682 }
1683
1684 // Fallback: Try to only support G6 temperature read latency
1685 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
1686
1687 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
1688 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1689
1690 if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
1691 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1692 goto restore_dml_state;
1693 }
1694
1695 // ERROR: fallback is supposed to always work.
1696 ASSERT(false);
1697
1698 restore_dml_state:
1699 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
1700 return voltage_supported;
1701 }
1702
dcn20_fpu_set_wm_ranges(int i,struct pp_smu_wm_range_sets * ranges,struct _vcs_dpi_soc_bounding_box_st * loaded_bb)1703 void dcn20_fpu_set_wm_ranges(int i,
1704 struct pp_smu_wm_range_sets *ranges,
1705 struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1706 {
1707 dc_assert_fp_enabled();
1708
1709 ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
1710 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
1711 }
1712
dcn20_fpu_adjust_dppclk(struct vba_vars_st * v,int vlevel,int max_mpc_comb,int pipe_idx,bool is_validating_bw)1713 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
1714 int vlevel,
1715 int max_mpc_comb,
1716 int pipe_idx,
1717 bool is_validating_bw)
1718 {
1719 dc_assert_fp_enabled();
1720
1721 if (is_validating_bw)
1722 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2;
1723 else
1724 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
1725 }
1726
dcn21_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1727 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
1728 struct dc_state *context,
1729 display_e2e_pipe_params_st *pipes,
1730 bool fast_validate)
1731 {
1732 uint32_t pipe_cnt;
1733 int i;
1734
1735 dc_assert_fp_enabled();
1736
1737 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1738
1739 for (i = 0; i < pipe_cnt; i++) {
1740
1741 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1742 pipes[i].pipe.src.gpuvm = 1;
1743 }
1744
1745 return pipe_cnt;
1746 }
1747
patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)1748 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1749 {
1750 int i;
1751
1752 if (dc->bb_overrides.sr_exit_time_ns) {
1753 for (i = 0; i < WM_SET_COUNT; i++) {
1754 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1755 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1756 }
1757 }
1758
1759 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1760 for (i = 0; i < WM_SET_COUNT; i++) {
1761 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1762 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1763 }
1764 }
1765
1766 if (dc->bb_overrides.urgent_latency_ns) {
1767 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1768 }
1769
1770 if (dc->bb_overrides.dram_clock_change_latency_ns) {
1771 for (i = 0; i < WM_SET_COUNT; i++) {
1772 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1773 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1774 }
1775 }
1776 }
1777
calculate_wm_set_for_vlevel(int vlevel,struct wm_range_table_entry * table_entry,struct dcn_watermarks * wm_set,struct display_mode_lib * dml,display_e2e_pipe_params_st * pipes,int pipe_cnt)1778 static void calculate_wm_set_for_vlevel(int vlevel,
1779 struct wm_range_table_entry *table_entry,
1780 struct dcn_watermarks *wm_set,
1781 struct display_mode_lib *dml,
1782 display_e2e_pipe_params_st *pipes,
1783 int pipe_cnt)
1784 {
1785 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1786
1787 ASSERT(vlevel < dml->soc.num_states);
1788 /* only pipe 0 is read for voltage and dcf/soc clocks */
1789 pipes[0].clks_cfg.voltage = vlevel;
1790 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1791 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1792
1793 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1794 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1795 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1796
1797 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1798 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1799 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1800 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1801 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1802 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1803 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1804 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1805 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1806 }
1807
dcn21_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel_req,bool fast_validate)1808 static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,
1809 display_e2e_pipe_params_st *pipes,
1810 int *out_pipe_cnt,
1811 int *pipe_split_from,
1812 int vlevel_req,
1813 bool fast_validate)
1814 {
1815 int pipe_cnt, i, pipe_idx;
1816 int vlevel, vlevel_max;
1817 struct wm_range_table_entry *table_entry;
1818 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1819
1820 ASSERT(bw_params);
1821
1822 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1823
1824 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1825 if (!context->res_ctx.pipe_ctx[i].stream)
1826 continue;
1827
1828 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1829 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1830
1831 if (pipe_split_from[i] < 0) {
1832 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1833 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1834 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1835 pipes[pipe_cnt].pipe.dest.odm_combine =
1836 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1837 else
1838 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1839 pipe_idx++;
1840 } else {
1841 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1842 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1843 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1844 pipes[pipe_cnt].pipe.dest.odm_combine =
1845 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1846 else
1847 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1848 }
1849 pipe_cnt++;
1850 }
1851
1852 if (pipe_cnt != pipe_idx) {
1853 if (dc->res_pool->funcs->populate_dml_pipes)
1854 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1855 context, pipes, fast_validate);
1856 else
1857 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1858 context, pipes, fast_validate);
1859 }
1860
1861 *out_pipe_cnt = pipe_cnt;
1862
1863 vlevel_max = bw_params->clk_table.num_entries - 1;
1864
1865
1866 /* WM Set D */
1867 table_entry = &bw_params->wm_table.entries[WM_D];
1868 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1869 vlevel = 0;
1870 else
1871 vlevel = vlevel_max;
1872 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1873 &context->bw_ctx.dml, pipes, pipe_cnt);
1874 /* WM Set C */
1875 table_entry = &bw_params->wm_table.entries[WM_C];
1876 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
1877 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1878 &context->bw_ctx.dml, pipes, pipe_cnt);
1879 /* WM Set B */
1880 table_entry = &bw_params->wm_table.entries[WM_B];
1881 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1882 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1883 &context->bw_ctx.dml, pipes, pipe_cnt);
1884
1885 /* WM Set A */
1886 table_entry = &bw_params->wm_table.entries[WM_A];
1887 vlevel = MIN(vlevel_req, vlevel_max);
1888 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1889 &context->bw_ctx.dml, pipes, pipe_cnt);
1890 }
1891
dcn21_validate_bandwidth_fp(struct dc * dc,struct dc_state * context,bool fast_validate)1892 bool dcn21_validate_bandwidth_fp(struct dc *dc,
1893 struct dc_state *context,
1894 bool fast_validate)
1895 {
1896 bool out = false;
1897
1898 BW_VAL_TRACE_SETUP();
1899
1900 int vlevel = 0;
1901 int pipe_split_from[MAX_PIPES];
1902 int pipe_cnt = 0;
1903 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1904 DC_LOGGER_INIT(dc->ctx->logger);
1905
1906 BW_VAL_TRACE_COUNT();
1907
1908 dc_assert_fp_enabled();
1909
1910 /*Unsafe due to current pipe merge and split logic*/
1911 ASSERT(context != dc->current_state);
1912
1913 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1914
1915 if (pipe_cnt == 0)
1916 goto validate_out;
1917
1918 if (!out)
1919 goto validate_fail;
1920
1921 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1922
1923 if (fast_validate) {
1924 BW_VAL_TRACE_SKIP(fast);
1925 goto validate_out;
1926 }
1927
1928 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1929 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1930
1931 BW_VAL_TRACE_END_WATERMARKS();
1932
1933 goto validate_out;
1934
1935 validate_fail:
1936 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1937 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1938
1939 BW_VAL_TRACE_SKIP(fail);
1940 out = false;
1941
1942 validate_out:
1943 kfree(pipes);
1944
1945 BW_VAL_TRACE_FINISH();
1946
1947 return out;
1948 }
1949
construct_low_pstate_lvl(struct clk_limit_table * clk_table,unsigned int high_voltage_lvl)1950 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
1951 {
1952 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
1953 int i;
1954
1955 low_pstate_lvl.state = 1;
1956 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1957 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1958 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
1959 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1960
1961 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
1962 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
1963 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
1964 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
1965 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
1966 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
1967 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
1968
1969 for (i = clk_table->num_entries; i > 1; i--)
1970 clk_table->entries[i] = clk_table->entries[i-1];
1971 clk_table->entries[1] = clk_table->entries[0];
1972 clk_table->num_entries++;
1973
1974 return low_pstate_lvl;
1975 }
1976
dcn21_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1977 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1978 {
1979 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1980 struct clk_limit_table *clk_table = &bw_params->clk_table;
1981 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1982 unsigned int i, closest_clk_lvl = 0, k = 0;
1983 int j;
1984
1985 dc_assert_fp_enabled();
1986
1987 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1988 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1989 dcn2_1_soc.num_chans = bw_params->num_channels;
1990
1991 ASSERT(clk_table->num_entries);
1992 /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
1993 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
1994 clock_limits[i] = dcn2_1_soc.clock_limits[i];
1995 }
1996
1997 for (i = 0; i < clk_table->num_entries; i++) {
1998 /* loop backwards*/
1999 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
2000 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2001 closest_clk_lvl = j;
2002 break;
2003 }
2004 }
2005
2006 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */
2007 if (i == 1)
2008 k++;
2009
2010 clock_limits[k].state = k;
2011 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2012 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2013 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
2014 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
2015
2016 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2017 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2018 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2019 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2020 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2021 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2022 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2023
2024 k++;
2025 }
2026 for (i = 0; i < clk_table->num_entries + 1; i++)
2027 dcn2_1_soc.clock_limits[i] = clock_limits[i];
2028 if (clk_table->num_entries) {
2029 dcn2_1_soc.num_states = clk_table->num_entries + 1;
2030 /* fill in min DF PState */
2031 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
2032 /* duplicate last level */
2033 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
2034 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
2035 }
2036
2037 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2038 }
2039