1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2021 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include "resource.h"
28 #include "clk_mgr.h"
29 #include "dchubbub.h"
30 #include "dcn20/dcn20_resource.h"
31 #include "dcn21/dcn21_resource.h"
32 #include "clk_mgr/dcn21/rn_clk_mgr.h"
33 
34 #include "link.h"
35 #include "dcn20_fpu.h"
36 
37 #define DC_LOGGER_INIT(logger)
38 
39 #ifndef MAX
40 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
41 #endif
42 #ifndef MIN
43 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
44 #endif
45 
46 /* Constant */
47 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
48 
49 /**
50  * DOC: DCN2x FPU manipulation Overview
51  *
52  * The DCN architecture relies on FPU operations, which require special
53  * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
54  * want to avoid spreading FPU access across multiple files. With this idea in
55  * mind, this file aims to centralize all DCN20 and DCN2.1 (DCN2x) functions
56  * that require FPU access in a single place. Code in this file follows the
57  * following code pattern:
58  *
59  * 1. Functions that use FPU operations should be isolated in static functions.
60  * 2. The FPU functions should have the noinline attribute to ensure anything
61  *    that deals with FP register is contained within this call.
62  * 3. All function that needs to be accessed outside this file requires a
63  *    public interface that not uses any FPU reference.
64  * 4. Developers **must not** use DC_FP_START/END in this file, but they need
65  *    to ensure that the caller invokes it before access any function available
66  *    in this file. For this reason, public functions in this file must invoke
67  *    dc_assert_fp_enabled();
68  *
69  * Let's expand a little bit more the idea in the code pattern. To fully
70  * isolate FPU operations in a single place, we must avoid situations where
71  * compilers spill FP values to registers due to FP enable in a specific C
72  * file. Note that even if we isolate all FPU functions in a single file and
73  * call its interface from other files, the compiler might enable the use of
74  * FPU before we call DC_FP_START. Nevertheless, it is the programmer's
75  * responsibility to invoke DC_FP_START/END in the correct place. To highlight
76  * situations where developers forgot to use the FP protection before calling
77  * the DC FPU interface functions, we introduce a helper that checks if the
78  * function is invoked under FP protection. If not, it will trigger a kernel
79  * warning.
80  */
81 
82 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
83 	.odm_capable = 1,
84 	.gpuvm_enable = 0,
85 	.hostvm_enable = 0,
86 	.gpuvm_max_page_table_levels = 4,
87 	.hostvm_max_page_table_levels = 4,
88 	.hostvm_cached_page_table_levels = 0,
89 	.pte_group_size_bytes = 2048,
90 	.num_dsc = 6,
91 	.rob_buffer_size_kbytes = 168,
92 	.det_buffer_size_kbytes = 164,
93 	.dpte_buffer_size_in_pte_reqs_luma = 84,
94 	.pde_proc_buffer_size_64k_reqs = 48,
95 	.dpp_output_buffer_pixels = 2560,
96 	.opp_output_buffer_lines = 1,
97 	.pixel_chunk_size_kbytes = 8,
98 	.pte_chunk_size_kbytes = 2,
99 	.meta_chunk_size_kbytes = 2,
100 	.writeback_chunk_size_kbytes = 2,
101 	.line_buffer_size_bits = 789504,
102 	.is_line_buffer_bpp_fixed = 0,
103 	.line_buffer_fixed_bpp = 0,
104 	.dcc_supported = true,
105 	.max_line_buffer_lines = 12,
106 	.writeback_luma_buffer_size_kbytes = 12,
107 	.writeback_chroma_buffer_size_kbytes = 8,
108 	.writeback_chroma_line_buffer_width_pixels = 4,
109 	.writeback_max_hscl_ratio = 1,
110 	.writeback_max_vscl_ratio = 1,
111 	.writeback_min_hscl_ratio = 1,
112 	.writeback_min_vscl_ratio = 1,
113 	.writeback_max_hscl_taps = 12,
114 	.writeback_max_vscl_taps = 12,
115 	.writeback_line_buffer_luma_buffer_size = 0,
116 	.writeback_line_buffer_chroma_buffer_size = 14643,
117 	.cursor_buffer_size = 8,
118 	.cursor_chunk_size = 2,
119 	.max_num_otg = 6,
120 	.max_num_dpp = 6,
121 	.max_num_wb = 1,
122 	.max_dchub_pscl_bw_pix_per_clk = 4,
123 	.max_pscl_lb_bw_pix_per_clk = 2,
124 	.max_lb_vscl_bw_pix_per_clk = 4,
125 	.max_vscl_hscl_bw_pix_per_clk = 4,
126 	.max_hscl_ratio = 8,
127 	.max_vscl_ratio = 8,
128 	.hscl_mults = 4,
129 	.vscl_mults = 4,
130 	.max_hscl_taps = 8,
131 	.max_vscl_taps = 8,
132 	.dispclk_ramp_margin_percent = 1,
133 	.underscan_factor = 1.10,
134 	.min_vblank_lines = 32, //
135 	.dppclk_delay_subtotal = 77, //
136 	.dppclk_delay_scl_lb_only = 16,
137 	.dppclk_delay_scl = 50,
138 	.dppclk_delay_cnvc_formatter = 8,
139 	.dppclk_delay_cnvc_cursor = 6,
140 	.dispclk_delay_subtotal = 87, //
141 	.dcfclk_cstate_latency = 10, // SRExitTime
142 	.max_inter_dcn_tile_repeaters = 8,
143 	.xfc_supported = true,
144 	.xfc_fill_bw_overhead_percent = 10.0,
145 	.xfc_fill_constant_bytes = 0,
146 	.number_of_cursors = 1,
147 };
148 
149 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
150 	.odm_capable = 1,
151 	.gpuvm_enable = 0,
152 	.hostvm_enable = 0,
153 	.gpuvm_max_page_table_levels = 4,
154 	.hostvm_max_page_table_levels = 4,
155 	.hostvm_cached_page_table_levels = 0,
156 	.num_dsc = 5,
157 	.rob_buffer_size_kbytes = 168,
158 	.det_buffer_size_kbytes = 164,
159 	.dpte_buffer_size_in_pte_reqs_luma = 84,
160 	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
161 	.dpp_output_buffer_pixels = 2560,
162 	.opp_output_buffer_lines = 1,
163 	.pixel_chunk_size_kbytes = 8,
164 	.pte_enable = 1,
165 	.max_page_table_levels = 4,
166 	.pte_chunk_size_kbytes = 2,
167 	.meta_chunk_size_kbytes = 2,
168 	.writeback_chunk_size_kbytes = 2,
169 	.line_buffer_size_bits = 789504,
170 	.is_line_buffer_bpp_fixed = 0,
171 	.line_buffer_fixed_bpp = 0,
172 	.dcc_supported = true,
173 	.max_line_buffer_lines = 12,
174 	.writeback_luma_buffer_size_kbytes = 12,
175 	.writeback_chroma_buffer_size_kbytes = 8,
176 	.writeback_chroma_line_buffer_width_pixels = 4,
177 	.writeback_max_hscl_ratio = 1,
178 	.writeback_max_vscl_ratio = 1,
179 	.writeback_min_hscl_ratio = 1,
180 	.writeback_min_vscl_ratio = 1,
181 	.writeback_max_hscl_taps = 12,
182 	.writeback_max_vscl_taps = 12,
183 	.writeback_line_buffer_luma_buffer_size = 0,
184 	.writeback_line_buffer_chroma_buffer_size = 14643,
185 	.cursor_buffer_size = 8,
186 	.cursor_chunk_size = 2,
187 	.max_num_otg = 5,
188 	.max_num_dpp = 5,
189 	.max_num_wb = 1,
190 	.max_dchub_pscl_bw_pix_per_clk = 4,
191 	.max_pscl_lb_bw_pix_per_clk = 2,
192 	.max_lb_vscl_bw_pix_per_clk = 4,
193 	.max_vscl_hscl_bw_pix_per_clk = 4,
194 	.max_hscl_ratio = 8,
195 	.max_vscl_ratio = 8,
196 	.hscl_mults = 4,
197 	.vscl_mults = 4,
198 	.max_hscl_taps = 8,
199 	.max_vscl_taps = 8,
200 	.dispclk_ramp_margin_percent = 1,
201 	.underscan_factor = 1.10,
202 	.min_vblank_lines = 32, //
203 	.dppclk_delay_subtotal = 77, //
204 	.dppclk_delay_scl_lb_only = 16,
205 	.dppclk_delay_scl = 50,
206 	.dppclk_delay_cnvc_formatter = 8,
207 	.dppclk_delay_cnvc_cursor = 6,
208 	.dispclk_delay_subtotal = 87, //
209 	.dcfclk_cstate_latency = 10, // SRExitTime
210 	.max_inter_dcn_tile_repeaters = 8,
211 	.xfc_supported = true,
212 	.xfc_fill_bw_overhead_percent = 10.0,
213 	.xfc_fill_constant_bytes = 0,
214 	.ptoi_supported = 0,
215 	.number_of_cursors = 1,
216 };
217 
218 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
219 	/* Defaults that get patched on driver load from firmware. */
220 	.clock_limits = {
221 			{
222 				.state = 0,
223 				.dcfclk_mhz = 560.0,
224 				.fabricclk_mhz = 560.0,
225 				.dispclk_mhz = 513.0,
226 				.dppclk_mhz = 513.0,
227 				.phyclk_mhz = 540.0,
228 				.socclk_mhz = 560.0,
229 				.dscclk_mhz = 171.0,
230 				.dram_speed_mts = 8960.0,
231 			},
232 			{
233 				.state = 1,
234 				.dcfclk_mhz = 694.0,
235 				.fabricclk_mhz = 694.0,
236 				.dispclk_mhz = 642.0,
237 				.dppclk_mhz = 642.0,
238 				.phyclk_mhz = 600.0,
239 				.socclk_mhz = 694.0,
240 				.dscclk_mhz = 214.0,
241 				.dram_speed_mts = 11104.0,
242 			},
243 			{
244 				.state = 2,
245 				.dcfclk_mhz = 875.0,
246 				.fabricclk_mhz = 875.0,
247 				.dispclk_mhz = 734.0,
248 				.dppclk_mhz = 734.0,
249 				.phyclk_mhz = 810.0,
250 				.socclk_mhz = 875.0,
251 				.dscclk_mhz = 245.0,
252 				.dram_speed_mts = 14000.0,
253 			},
254 			{
255 				.state = 3,
256 				.dcfclk_mhz = 1000.0,
257 				.fabricclk_mhz = 1000.0,
258 				.dispclk_mhz = 1100.0,
259 				.dppclk_mhz = 1100.0,
260 				.phyclk_mhz = 810.0,
261 				.socclk_mhz = 1000.0,
262 				.dscclk_mhz = 367.0,
263 				.dram_speed_mts = 16000.0,
264 			},
265 			{
266 				.state = 4,
267 				.dcfclk_mhz = 1200.0,
268 				.fabricclk_mhz = 1200.0,
269 				.dispclk_mhz = 1284.0,
270 				.dppclk_mhz = 1284.0,
271 				.phyclk_mhz = 810.0,
272 				.socclk_mhz = 1200.0,
273 				.dscclk_mhz = 428.0,
274 				.dram_speed_mts = 16000.0,
275 			},
276 			/*Extra state, no dispclk ramping*/
277 			{
278 				.state = 5,
279 				.dcfclk_mhz = 1200.0,
280 				.fabricclk_mhz = 1200.0,
281 				.dispclk_mhz = 1284.0,
282 				.dppclk_mhz = 1284.0,
283 				.phyclk_mhz = 810.0,
284 				.socclk_mhz = 1200.0,
285 				.dscclk_mhz = 428.0,
286 				.dram_speed_mts = 16000.0,
287 			},
288 		},
289 	.num_states = 5,
290 	.sr_exit_time_us = 8.6,
291 	.sr_enter_plus_exit_time_us = 10.9,
292 	.urgent_latency_us = 4.0,
293 	.urgent_latency_pixel_data_only_us = 4.0,
294 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
295 	.urgent_latency_vm_data_only_us = 4.0,
296 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
297 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
298 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
299 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
300 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
301 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
302 	.max_avg_sdp_bw_use_normal_percent = 40.0,
303 	.max_avg_dram_bw_use_normal_percent = 40.0,
304 	.writeback_latency_us = 12.0,
305 	.ideal_dram_bw_after_urgent_percent = 40.0,
306 	.max_request_size_bytes = 256,
307 	.dram_channel_width_bytes = 2,
308 	.fabric_datapath_to_dcn_data_return_bytes = 64,
309 	.dcn_downspread_percent = 0.5,
310 	.downspread_percent = 0.38,
311 	.dram_page_open_time_ns = 50.0,
312 	.dram_rw_turnaround_time_ns = 17.5,
313 	.dram_return_buffer_per_channel_bytes = 8192,
314 	.round_trip_ping_latency_dcfclk_cycles = 131,
315 	.urgent_out_of_order_return_per_channel_bytes = 256,
316 	.channel_interleave_bytes = 256,
317 	.num_banks = 8,
318 	.num_chans = 16,
319 	.vmm_page_size_bytes = 4096,
320 	.dram_clock_change_latency_us = 404.0,
321 	.dummy_pstate_latency_us = 5.0,
322 	.writeback_dram_clock_change_latency_us = 23.0,
323 	.return_bus_width_bytes = 64,
324 	.dispclk_dppclk_vco_speed_mhz = 3850,
325 	.xfc_bus_transport_time_us = 20,
326 	.xfc_xbuf_latency_tolerance_us = 4,
327 	.use_urgent_burst_bw = 0
328 };
329 
330 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
331 	.clock_limits = {
332 			{
333 				.state = 0,
334 				.dcfclk_mhz = 560.0,
335 				.fabricclk_mhz = 560.0,
336 				.dispclk_mhz = 513.0,
337 				.dppclk_mhz = 513.0,
338 				.phyclk_mhz = 540.0,
339 				.socclk_mhz = 560.0,
340 				.dscclk_mhz = 171.0,
341 				.dram_speed_mts = 8960.0,
342 			},
343 			{
344 				.state = 1,
345 				.dcfclk_mhz = 694.0,
346 				.fabricclk_mhz = 694.0,
347 				.dispclk_mhz = 642.0,
348 				.dppclk_mhz = 642.0,
349 				.phyclk_mhz = 600.0,
350 				.socclk_mhz = 694.0,
351 				.dscclk_mhz = 214.0,
352 				.dram_speed_mts = 11104.0,
353 			},
354 			{
355 				.state = 2,
356 				.dcfclk_mhz = 875.0,
357 				.fabricclk_mhz = 875.0,
358 				.dispclk_mhz = 734.0,
359 				.dppclk_mhz = 734.0,
360 				.phyclk_mhz = 810.0,
361 				.socclk_mhz = 875.0,
362 				.dscclk_mhz = 245.0,
363 				.dram_speed_mts = 14000.0,
364 			},
365 			{
366 				.state = 3,
367 				.dcfclk_mhz = 1000.0,
368 				.fabricclk_mhz = 1000.0,
369 				.dispclk_mhz = 1100.0,
370 				.dppclk_mhz = 1100.0,
371 				.phyclk_mhz = 810.0,
372 				.socclk_mhz = 1000.0,
373 				.dscclk_mhz = 367.0,
374 				.dram_speed_mts = 16000.0,
375 			},
376 			{
377 				.state = 4,
378 				.dcfclk_mhz = 1200.0,
379 				.fabricclk_mhz = 1200.0,
380 				.dispclk_mhz = 1284.0,
381 				.dppclk_mhz = 1284.0,
382 				.phyclk_mhz = 810.0,
383 				.socclk_mhz = 1200.0,
384 				.dscclk_mhz = 428.0,
385 				.dram_speed_mts = 16000.0,
386 			},
387 			/*Extra state, no dispclk ramping*/
388 			{
389 				.state = 5,
390 				.dcfclk_mhz = 1200.0,
391 				.fabricclk_mhz = 1200.0,
392 				.dispclk_mhz = 1284.0,
393 				.dppclk_mhz = 1284.0,
394 				.phyclk_mhz = 810.0,
395 				.socclk_mhz = 1200.0,
396 				.dscclk_mhz = 428.0,
397 				.dram_speed_mts = 16000.0,
398 			},
399 		},
400 	.num_states = 5,
401 	.sr_exit_time_us = 11.6,
402 	.sr_enter_plus_exit_time_us = 13.9,
403 	.urgent_latency_us = 4.0,
404 	.urgent_latency_pixel_data_only_us = 4.0,
405 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
406 	.urgent_latency_vm_data_only_us = 4.0,
407 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
408 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
409 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
410 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
411 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
412 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
413 	.max_avg_sdp_bw_use_normal_percent = 40.0,
414 	.max_avg_dram_bw_use_normal_percent = 40.0,
415 	.writeback_latency_us = 12.0,
416 	.ideal_dram_bw_after_urgent_percent = 40.0,
417 	.max_request_size_bytes = 256,
418 	.dram_channel_width_bytes = 2,
419 	.fabric_datapath_to_dcn_data_return_bytes = 64,
420 	.dcn_downspread_percent = 0.5,
421 	.downspread_percent = 0.38,
422 	.dram_page_open_time_ns = 50.0,
423 	.dram_rw_turnaround_time_ns = 17.5,
424 	.dram_return_buffer_per_channel_bytes = 8192,
425 	.round_trip_ping_latency_dcfclk_cycles = 131,
426 	.urgent_out_of_order_return_per_channel_bytes = 256,
427 	.channel_interleave_bytes = 256,
428 	.num_banks = 8,
429 	.num_chans = 8,
430 	.vmm_page_size_bytes = 4096,
431 	.dram_clock_change_latency_us = 404.0,
432 	.dummy_pstate_latency_us = 5.0,
433 	.writeback_dram_clock_change_latency_us = 23.0,
434 	.return_bus_width_bytes = 64,
435 	.dispclk_dppclk_vco_speed_mhz = 3850,
436 	.xfc_bus_transport_time_us = 20,
437 	.xfc_xbuf_latency_tolerance_us = 4,
438 	.use_urgent_burst_bw = 0
439 };
440 
441 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = {
442 	.clock_limits = {
443 		{
444 			.state = 0,
445 			.dcfclk_mhz = 560.0,
446 			.fabricclk_mhz = 560.0,
447 			.dispclk_mhz = 513.0,
448 			.dppclk_mhz = 513.0,
449 			.phyclk_mhz = 540.0,
450 			.socclk_mhz = 560.0,
451 			.dscclk_mhz = 171.0,
452 			.dram_speed_mts = 1069.0,
453 		},
454 		{
455 			.state = 1,
456 			.dcfclk_mhz = 694.0,
457 			.fabricclk_mhz = 694.0,
458 			.dispclk_mhz = 642.0,
459 			.dppclk_mhz = 642.0,
460 			.phyclk_mhz = 600.0,
461 			.socclk_mhz = 694.0,
462 			.dscclk_mhz = 214.0,
463 			.dram_speed_mts = 1324.0,
464 		},
465 		{
466 			.state = 2,
467 			.dcfclk_mhz = 875.0,
468 			.fabricclk_mhz = 875.0,
469 			.dispclk_mhz = 734.0,
470 			.dppclk_mhz = 734.0,
471 			.phyclk_mhz = 810.0,
472 			.socclk_mhz = 875.0,
473 			.dscclk_mhz = 245.0,
474 			.dram_speed_mts = 1670.0,
475 		},
476 		{
477 			.state = 3,
478 			.dcfclk_mhz = 1000.0,
479 			.fabricclk_mhz = 1000.0,
480 			.dispclk_mhz = 1100.0,
481 			.dppclk_mhz = 1100.0,
482 			.phyclk_mhz = 810.0,
483 			.socclk_mhz = 1000.0,
484 			.dscclk_mhz = 367.0,
485 			.dram_speed_mts = 2000.0,
486 		},
487 		{
488 			.state = 4,
489 			.dcfclk_mhz = 1200.0,
490 			.fabricclk_mhz = 1200.0,
491 			.dispclk_mhz = 1284.0,
492 			.dppclk_mhz = 1284.0,
493 			.phyclk_mhz = 810.0,
494 			.socclk_mhz = 1200.0,
495 			.dscclk_mhz = 428.0,
496 			.dram_speed_mts = 2000.0,
497 		},
498 		{
499 			.state = 5,
500 			.dcfclk_mhz = 1200.0,
501 			.fabricclk_mhz = 1200.0,
502 			.dispclk_mhz = 1284.0,
503 			.dppclk_mhz = 1284.0,
504 			.phyclk_mhz = 810.0,
505 			.socclk_mhz = 1200.0,
506 			.dscclk_mhz = 428.0,
507 			.dram_speed_mts = 2000.0,
508 		},
509 	},
510 
511 	.num_states = 5,
512 	.sr_exit_time_us = 1.9,
513 	.sr_enter_plus_exit_time_us = 4.4,
514 	.urgent_latency_us = 3.0,
515 	.urgent_latency_pixel_data_only_us = 4.0,
516 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
517 	.urgent_latency_vm_data_only_us = 4.0,
518 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
519 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
520 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
521 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
522 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
523 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
524 	.max_avg_sdp_bw_use_normal_percent = 40.0,
525 	.max_avg_dram_bw_use_normal_percent = 40.0,
526 	.writeback_latency_us = 12.0,
527 	.ideal_dram_bw_after_urgent_percent = 40.0,
528 	.max_request_size_bytes = 256,
529 	.dram_channel_width_bytes = 16,
530 	.fabric_datapath_to_dcn_data_return_bytes = 64,
531 	.dcn_downspread_percent = 0.5,
532 	.downspread_percent = 0.5,
533 	.dram_page_open_time_ns = 50.0,
534 	.dram_rw_turnaround_time_ns = 17.5,
535 	.dram_return_buffer_per_channel_bytes = 8192,
536 	.round_trip_ping_latency_dcfclk_cycles = 131,
537 	.urgent_out_of_order_return_per_channel_bytes = 4096,
538 	.channel_interleave_bytes = 256,
539 	.num_banks = 8,
540 	.num_chans = 16,
541 	.vmm_page_size_bytes = 4096,
542 	.dram_clock_change_latency_us = 45.0,
543 	.writeback_dram_clock_change_latency_us = 23.0,
544 	.return_bus_width_bytes = 64,
545 	.dispclk_dppclk_vco_speed_mhz = 3850,
546 	.xfc_bus_transport_time_us = 20,
547 	.xfc_xbuf_latency_tolerance_us = 50,
548 	.use_urgent_burst_bw = 0,
549 };
550 
551 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
552 	.odm_capable = 1,
553 	.gpuvm_enable = 1,
554 	.hostvm_enable = 1,
555 	.gpuvm_max_page_table_levels = 1,
556 	.hostvm_max_page_table_levels = 4,
557 	.hostvm_cached_page_table_levels = 2,
558 	.num_dsc = 3,
559 	.rob_buffer_size_kbytes = 168,
560 	.det_buffer_size_kbytes = 164,
561 	.dpte_buffer_size_in_pte_reqs_luma = 44,
562 	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
563 	.dpp_output_buffer_pixels = 2560,
564 	.opp_output_buffer_lines = 1,
565 	.pixel_chunk_size_kbytes = 8,
566 	.pte_enable = 1,
567 	.max_page_table_levels = 4,
568 	.pte_chunk_size_kbytes = 2,
569 	.meta_chunk_size_kbytes = 2,
570 	.min_meta_chunk_size_bytes = 256,
571 	.writeback_chunk_size_kbytes = 2,
572 	.line_buffer_size_bits = 789504,
573 	.is_line_buffer_bpp_fixed = 0,
574 	.line_buffer_fixed_bpp = 0,
575 	.dcc_supported = true,
576 	.max_line_buffer_lines = 12,
577 	.writeback_luma_buffer_size_kbytes = 12,
578 	.writeback_chroma_buffer_size_kbytes = 8,
579 	.writeback_chroma_line_buffer_width_pixels = 4,
580 	.writeback_max_hscl_ratio = 1,
581 	.writeback_max_vscl_ratio = 1,
582 	.writeback_min_hscl_ratio = 1,
583 	.writeback_min_vscl_ratio = 1,
584 	.writeback_max_hscl_taps = 12,
585 	.writeback_max_vscl_taps = 12,
586 	.writeback_line_buffer_luma_buffer_size = 0,
587 	.writeback_line_buffer_chroma_buffer_size = 14643,
588 	.cursor_buffer_size = 8,
589 	.cursor_chunk_size = 2,
590 	.max_num_otg = 4,
591 	.max_num_dpp = 4,
592 	.max_num_wb = 1,
593 	.max_dchub_pscl_bw_pix_per_clk = 4,
594 	.max_pscl_lb_bw_pix_per_clk = 2,
595 	.max_lb_vscl_bw_pix_per_clk = 4,
596 	.max_vscl_hscl_bw_pix_per_clk = 4,
597 	.max_hscl_ratio = 4,
598 	.max_vscl_ratio = 4,
599 	.hscl_mults = 4,
600 	.vscl_mults = 4,
601 	.max_hscl_taps = 8,
602 	.max_vscl_taps = 8,
603 	.dispclk_ramp_margin_percent = 1,
604 	.underscan_factor = 1.10,
605 	.min_vblank_lines = 32, //
606 	.dppclk_delay_subtotal = 77, //
607 	.dppclk_delay_scl_lb_only = 16,
608 	.dppclk_delay_scl = 50,
609 	.dppclk_delay_cnvc_formatter = 8,
610 	.dppclk_delay_cnvc_cursor = 6,
611 	.dispclk_delay_subtotal = 87, //
612 	.dcfclk_cstate_latency = 10, // SRExitTime
613 	.max_inter_dcn_tile_repeaters = 8,
614 
615 	.xfc_supported = false,
616 	.xfc_fill_bw_overhead_percent = 10.0,
617 	.xfc_fill_constant_bytes = 0,
618 	.ptoi_supported = 0,
619 	.number_of_cursors = 1,
620 };
621 
622 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
623 	.clock_limits = {
624 			{
625 				.state = 0,
626 				.dcfclk_mhz = 400.0,
627 				.fabricclk_mhz = 400.0,
628 				.dispclk_mhz = 600.0,
629 				.dppclk_mhz = 400.00,
630 				.phyclk_mhz = 600.0,
631 				.socclk_mhz = 278.0,
632 				.dscclk_mhz = 205.67,
633 				.dram_speed_mts = 1600.0,
634 			},
635 			{
636 				.state = 1,
637 				.dcfclk_mhz = 464.52,
638 				.fabricclk_mhz = 800.0,
639 				.dispclk_mhz = 654.55,
640 				.dppclk_mhz = 626.09,
641 				.phyclk_mhz = 600.0,
642 				.socclk_mhz = 278.0,
643 				.dscclk_mhz = 205.67,
644 				.dram_speed_mts = 1600.0,
645 			},
646 			{
647 				.state = 2,
648 				.dcfclk_mhz = 514.29,
649 				.fabricclk_mhz = 933.0,
650 				.dispclk_mhz = 757.89,
651 				.dppclk_mhz = 685.71,
652 				.phyclk_mhz = 600.0,
653 				.socclk_mhz = 278.0,
654 				.dscclk_mhz = 287.67,
655 				.dram_speed_mts = 1866.0,
656 			},
657 			{
658 				.state = 3,
659 				.dcfclk_mhz = 576.00,
660 				.fabricclk_mhz = 1067.0,
661 				.dispclk_mhz = 847.06,
662 				.dppclk_mhz = 757.89,
663 				.phyclk_mhz = 600.0,
664 				.socclk_mhz = 715.0,
665 				.dscclk_mhz = 318.334,
666 				.dram_speed_mts = 2134.0,
667 			},
668 			{
669 				.state = 4,
670 				.dcfclk_mhz = 626.09,
671 				.fabricclk_mhz = 1200.0,
672 				.dispclk_mhz = 900.00,
673 				.dppclk_mhz = 847.06,
674 				.phyclk_mhz = 810.0,
675 				.socclk_mhz = 953.0,
676 				.dscclk_mhz = 300.0,
677 				.dram_speed_mts = 2400.0,
678 			},
679 			{
680 				.state = 5,
681 				.dcfclk_mhz = 685.71,
682 				.fabricclk_mhz = 1333.0,
683 				.dispclk_mhz = 1028.57,
684 				.dppclk_mhz = 960.00,
685 				.phyclk_mhz = 810.0,
686 				.socclk_mhz = 278.0,
687 				.dscclk_mhz = 342.86,
688 				.dram_speed_mts = 2666.0,
689 			},
690 			{
691 				.state = 6,
692 				.dcfclk_mhz = 757.89,
693 				.fabricclk_mhz = 1467.0,
694 				.dispclk_mhz = 1107.69,
695 				.dppclk_mhz = 1028.57,
696 				.phyclk_mhz = 810.0,
697 				.socclk_mhz = 715.0,
698 				.dscclk_mhz = 369.23,
699 				.dram_speed_mts = 3200.0,
700 			},
701 			{
702 				.state = 7,
703 				.dcfclk_mhz = 847.06,
704 				.fabricclk_mhz = 1600.0,
705 				.dispclk_mhz = 1395.0,
706 				.dppclk_mhz = 1285.00,
707 				.phyclk_mhz = 1325.0,
708 				.socclk_mhz = 953.0,
709 				.dscclk_mhz = 489.0,
710 				.dram_speed_mts = 4266.0,
711 			},
712 			/*Extra state, no dispclk ramping*/
713 			{
714 				.state = 8,
715 				.dcfclk_mhz = 847.06,
716 				.fabricclk_mhz = 1600.0,
717 				.dispclk_mhz = 1395.0,
718 				.dppclk_mhz = 1285.0,
719 				.phyclk_mhz = 1325.0,
720 				.socclk_mhz = 953.0,
721 				.dscclk_mhz = 489.0,
722 				.dram_speed_mts = 4266.0,
723 			},
724 
725 		},
726 
727 	.sr_exit_time_us = 12.5,
728 	.sr_enter_plus_exit_time_us = 17.0,
729 	.urgent_latency_us = 4.0,
730 	.urgent_latency_pixel_data_only_us = 4.0,
731 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
732 	.urgent_latency_vm_data_only_us = 4.0,
733 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
734 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
735 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
736 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
737 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
738 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
739 	.max_avg_sdp_bw_use_normal_percent = 60.0,
740 	.max_avg_dram_bw_use_normal_percent = 100.0,
741 	.writeback_latency_us = 12.0,
742 	.max_request_size_bytes = 256,
743 	.dram_channel_width_bytes = 4,
744 	.fabric_datapath_to_dcn_data_return_bytes = 32,
745 	.dcn_downspread_percent = 0.5,
746 	.downspread_percent = 0.38,
747 	.dram_page_open_time_ns = 50.0,
748 	.dram_rw_turnaround_time_ns = 17.5,
749 	.dram_return_buffer_per_channel_bytes = 8192,
750 	.round_trip_ping_latency_dcfclk_cycles = 128,
751 	.urgent_out_of_order_return_per_channel_bytes = 4096,
752 	.channel_interleave_bytes = 256,
753 	.num_banks = 8,
754 	.num_chans = 4,
755 	.vmm_page_size_bytes = 4096,
756 	.dram_clock_change_latency_us = 23.84,
757 	.return_bus_width_bytes = 64,
758 	.dispclk_dppclk_vco_speed_mhz = 3600,
759 	.xfc_bus_transport_time_us = 4,
760 	.xfc_xbuf_latency_tolerance_us = 4,
761 	.use_urgent_burst_bw = 1,
762 	.num_states = 8
763 };
764 
765 struct wm_table ddr4_wm_table_gs = {
766 	.entries = {
767 		{
768 			.wm_inst = WM_A,
769 			.wm_type = WM_TYPE_PSTATE_CHG,
770 			.pstate_latency_us = 11.72,
771 			.sr_exit_time_us = 7.09,
772 			.sr_enter_plus_exit_time_us = 8.14,
773 			.valid = true,
774 		},
775 		{
776 			.wm_inst = WM_B,
777 			.wm_type = WM_TYPE_PSTATE_CHG,
778 			.pstate_latency_us = 11.72,
779 			.sr_exit_time_us = 10.12,
780 			.sr_enter_plus_exit_time_us = 11.48,
781 			.valid = true,
782 		},
783 		{
784 			.wm_inst = WM_C,
785 			.wm_type = WM_TYPE_PSTATE_CHG,
786 			.pstate_latency_us = 11.72,
787 			.sr_exit_time_us = 10.12,
788 			.sr_enter_plus_exit_time_us = 11.48,
789 			.valid = true,
790 		},
791 		{
792 			.wm_inst = WM_D,
793 			.wm_type = WM_TYPE_PSTATE_CHG,
794 			.pstate_latency_us = 11.72,
795 			.sr_exit_time_us = 10.12,
796 			.sr_enter_plus_exit_time_us = 11.48,
797 			.valid = true,
798 		},
799 	}
800 };
801 
802 struct wm_table lpddr4_wm_table_gs = {
803 	.entries = {
804 		{
805 			.wm_inst = WM_A,
806 			.wm_type = WM_TYPE_PSTATE_CHG,
807 			.pstate_latency_us = 11.65333,
808 			.sr_exit_time_us = 5.32,
809 			.sr_enter_plus_exit_time_us = 6.38,
810 			.valid = true,
811 		},
812 		{
813 			.wm_inst = WM_B,
814 			.wm_type = WM_TYPE_PSTATE_CHG,
815 			.pstate_latency_us = 11.65333,
816 			.sr_exit_time_us = 9.82,
817 			.sr_enter_plus_exit_time_us = 11.196,
818 			.valid = true,
819 		},
820 		{
821 			.wm_inst = WM_C,
822 			.wm_type = WM_TYPE_PSTATE_CHG,
823 			.pstate_latency_us = 11.65333,
824 			.sr_exit_time_us = 9.89,
825 			.sr_enter_plus_exit_time_us = 11.24,
826 			.valid = true,
827 		},
828 		{
829 			.wm_inst = WM_D,
830 			.wm_type = WM_TYPE_PSTATE_CHG,
831 			.pstate_latency_us = 11.65333,
832 			.sr_exit_time_us = 9.748,
833 			.sr_enter_plus_exit_time_us = 11.102,
834 			.valid = true,
835 		},
836 	}
837 };
838 
839 struct wm_table lpddr4_wm_table_with_disabled_ppt = {
840 	.entries = {
841 		{
842 			.wm_inst = WM_A,
843 			.wm_type = WM_TYPE_PSTATE_CHG,
844 			.pstate_latency_us = 11.65333,
845 			.sr_exit_time_us = 8.32,
846 			.sr_enter_plus_exit_time_us = 9.38,
847 			.valid = true,
848 		},
849 		{
850 			.wm_inst = WM_B,
851 			.wm_type = WM_TYPE_PSTATE_CHG,
852 			.pstate_latency_us = 11.65333,
853 			.sr_exit_time_us = 9.82,
854 			.sr_enter_plus_exit_time_us = 11.196,
855 			.valid = true,
856 		},
857 		{
858 			.wm_inst = WM_C,
859 			.wm_type = WM_TYPE_PSTATE_CHG,
860 			.pstate_latency_us = 11.65333,
861 			.sr_exit_time_us = 9.89,
862 			.sr_enter_plus_exit_time_us = 11.24,
863 			.valid = true,
864 		},
865 		{
866 			.wm_inst = WM_D,
867 			.wm_type = WM_TYPE_PSTATE_CHG,
868 			.pstate_latency_us = 11.65333,
869 			.sr_exit_time_us = 9.748,
870 			.sr_enter_plus_exit_time_us = 11.102,
871 			.valid = true,
872 		},
873 	}
874 };
875 
876 struct wm_table ddr4_wm_table_rn = {
877 	.entries = {
878 		{
879 			.wm_inst = WM_A,
880 			.wm_type = WM_TYPE_PSTATE_CHG,
881 			.pstate_latency_us = 11.72,
882 			.sr_exit_time_us = 11.90,
883 			.sr_enter_plus_exit_time_us = 12.80,
884 			.valid = true,
885 		},
886 		{
887 			.wm_inst = WM_B,
888 			.wm_type = WM_TYPE_PSTATE_CHG,
889 			.pstate_latency_us = 11.72,
890 			.sr_exit_time_us = 13.18,
891 			.sr_enter_plus_exit_time_us = 14.30,
892 			.valid = true,
893 		},
894 		{
895 			.wm_inst = WM_C,
896 			.wm_type = WM_TYPE_PSTATE_CHG,
897 			.pstate_latency_us = 11.72,
898 			.sr_exit_time_us = 13.18,
899 			.sr_enter_plus_exit_time_us = 14.30,
900 			.valid = true,
901 		},
902 		{
903 			.wm_inst = WM_D,
904 			.wm_type = WM_TYPE_PSTATE_CHG,
905 			.pstate_latency_us = 11.72,
906 			.sr_exit_time_us = 13.18,
907 			.sr_enter_plus_exit_time_us = 14.30,
908 			.valid = true,
909 		},
910 	}
911 };
912 
913 struct wm_table ddr4_1R_wm_table_rn = {
914 	.entries = {
915 		{
916 			.wm_inst = WM_A,
917 			.wm_type = WM_TYPE_PSTATE_CHG,
918 			.pstate_latency_us = 11.72,
919 			.sr_exit_time_us = 13.90,
920 			.sr_enter_plus_exit_time_us = 14.80,
921 			.valid = true,
922 		},
923 		{
924 			.wm_inst = WM_B,
925 			.wm_type = WM_TYPE_PSTATE_CHG,
926 			.pstate_latency_us = 11.72,
927 			.sr_exit_time_us = 13.90,
928 			.sr_enter_plus_exit_time_us = 14.80,
929 			.valid = true,
930 		},
931 		{
932 			.wm_inst = WM_C,
933 			.wm_type = WM_TYPE_PSTATE_CHG,
934 			.pstate_latency_us = 11.72,
935 			.sr_exit_time_us = 13.90,
936 			.sr_enter_plus_exit_time_us = 14.80,
937 			.valid = true,
938 		},
939 		{
940 			.wm_inst = WM_D,
941 			.wm_type = WM_TYPE_PSTATE_CHG,
942 			.pstate_latency_us = 11.72,
943 			.sr_exit_time_us = 13.90,
944 			.sr_enter_plus_exit_time_us = 14.80,
945 			.valid = true,
946 		},
947 	}
948 };
949 
950 struct wm_table lpddr4_wm_table_rn = {
951 	.entries = {
952 		{
953 			.wm_inst = WM_A,
954 			.wm_type = WM_TYPE_PSTATE_CHG,
955 			.pstate_latency_us = 11.65333,
956 			.sr_exit_time_us = 7.32,
957 			.sr_enter_plus_exit_time_us = 8.38,
958 			.valid = true,
959 		},
960 		{
961 			.wm_inst = WM_B,
962 			.wm_type = WM_TYPE_PSTATE_CHG,
963 			.pstate_latency_us = 11.65333,
964 			.sr_exit_time_us = 9.82,
965 			.sr_enter_plus_exit_time_us = 11.196,
966 			.valid = true,
967 		},
968 		{
969 			.wm_inst = WM_C,
970 			.wm_type = WM_TYPE_PSTATE_CHG,
971 			.pstate_latency_us = 11.65333,
972 			.sr_exit_time_us = 9.89,
973 			.sr_enter_plus_exit_time_us = 11.24,
974 			.valid = true,
975 		},
976 		{
977 			.wm_inst = WM_D,
978 			.wm_type = WM_TYPE_PSTATE_CHG,
979 			.pstate_latency_us = 11.65333,
980 			.sr_exit_time_us = 9.748,
981 			.sr_enter_plus_exit_time_us = 11.102,
982 			.valid = true,
983 		},
984 	}
985 };
986 
dcn20_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)987 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
988 					       struct resource_context *res_ctx,
989 					       display_e2e_pipe_params_st *pipes)
990 {
991 	int pipe_cnt, i;
992 
993 	dc_assert_fp_enabled();
994 
995 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
996 		struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
997 
998 		if (!res_ctx->pipe_ctx[i].stream)
999 			continue;
1000 
1001 		/* Set writeback information */
1002 		pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1003 		pipes[pipe_cnt].dout.num_active_wb++;
1004 		pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1005 		pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1006 		pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1007 		pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1008 		pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1009 		pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1010 		pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1011 		pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1012 		pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1013 		pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1014 		if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1015 			if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1016 				pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1017 			else
1018 				pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1019 		} else {
1020 			pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1021 		}
1022 
1023 		pipe_cnt++;
1024 	}
1025 }
1026 
dcn20_fpu_set_wb_arb_params(struct mcif_arb_params * wb_arb_params,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int i)1027 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
1028 				 struct dc_state *context,
1029 				 display_e2e_pipe_params_st *pipes,
1030 				 int pipe_cnt, int i)
1031 {
1032 	int k;
1033 
1034 	dc_assert_fp_enabled();
1035 
1036 	for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1037 		wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1038 		wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1039 	}
1040 	wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
1041 }
1042 
is_dtbclk_required(struct dc * dc,struct dc_state * context)1043 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
1044 {
1045 	int i;
1046 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1047 		if (!context->res_ctx.pipe_ctx[i].stream)
1048 			continue;
1049 		if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
1050 			return true;
1051 	}
1052 	return false;
1053 }
1054 
decide_zstate_support(struct dc * dc,struct dc_state * context)1055 static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struct dc_state *context)
1056 {
1057 	int plane_count;
1058 	int i;
1059 
1060 	plane_count = 0;
1061 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1062 		if (context->res_ctx.pipe_ctx[i].plane_state)
1063 			plane_count++;
1064 	}
1065 
1066 	/*
1067 	 * Z9 and Z10 allowed cases:
1068 	 * 	1. 0 Planes enabled
1069 	 * 	2. single eDP, on link 0, 1 plane and stutter period > 5ms
1070 	 * Z10 only cases:
1071 	 * 	1. single eDP, on link 0, 1 plane and stutter period >= 5ms
1072 	 * Z8 cases:
1073 	 * 	1. stutter period sufficient
1074 	 * Zstate not allowed cases:
1075 	 * 	1. Everything else
1076 	 */
1077 	if (plane_count == 0)
1078 		return DCN_ZSTATE_SUPPORT_ALLOW;
1079 	else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
1080 		struct dc_link *link = context->streams[0]->sink->link;
1081 		struct dc_stream_status *stream_status = &context->stream_status[0];
1082 		int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
1083 		bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
1084 		bool is_pwrseq0 = link->link_index == 0;
1085 
1086 		/* Don't support multi-plane configurations */
1087 		if (stream_status->plane_count > 1)
1088 			return DCN_ZSTATE_SUPPORT_DISALLOW;
1089 
1090 		if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
1091 			return DCN_ZSTATE_SUPPORT_ALLOW;
1092 		else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)
1093 			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
1094 		else
1095 			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW;
1096 	} else {
1097 		return DCN_ZSTATE_SUPPORT_DISALLOW;
1098 	}
1099 }
1100 
dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing * dc_crtc_timing,int * vstartup_start)1101 static void dcn20_adjust_freesync_v_startup(
1102 		const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
1103 {
1104 	struct dc_crtc_timing patched_crtc_timing;
1105 	uint32_t asic_blank_end   = 0;
1106 	uint32_t asic_blank_start = 0;
1107 	uint32_t newVstartup	  = 0;
1108 
1109 	patched_crtc_timing = *dc_crtc_timing;
1110 
1111 	if (patched_crtc_timing.flags.INTERLACE == 1) {
1112 		if (patched_crtc_timing.v_front_porch < 2)
1113 			patched_crtc_timing.v_front_porch = 2;
1114 	} else {
1115 		if (patched_crtc_timing.v_front_porch < 1)
1116 			patched_crtc_timing.v_front_porch = 1;
1117 	}
1118 
1119 	/* blank_start = frame end - front porch */
1120 	asic_blank_start = patched_crtc_timing.v_total -
1121 					patched_crtc_timing.v_front_porch;
1122 
1123 	/* blank_end = blank_start - active */
1124 	asic_blank_end = asic_blank_start -
1125 					patched_crtc_timing.v_border_bottom -
1126 					patched_crtc_timing.v_addressable -
1127 					patched_crtc_timing.v_border_top;
1128 
1129 	newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start);
1130 
1131 	*vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
1132 }
1133 
dcn20_calculate_dlg_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1134 void dcn20_calculate_dlg_params(struct dc *dc,
1135 				struct dc_state *context,
1136 				display_e2e_pipe_params_st *pipes,
1137 				int pipe_cnt,
1138 				int vlevel)
1139 {
1140 	int i, pipe_idx, active_hubp_count = 0;
1141 
1142 	dc_assert_fp_enabled();
1143 
1144 	/* Writeback MCIF_WB arbitration parameters */
1145 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1146 
1147 	context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1148 	context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1149 	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1150 	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1151 
1152 	if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
1153 		context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
1154 
1155 	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1156 	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1157 	context->bw_ctx.bw.dcn.clk.p_state_change_support =
1158 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1159 							!= dm_dram_clock_change_unsupported;
1160 
1161 	/* Pstate change might not be supported by hardware, but it might be
1162 	 * possible with firmware driven vertical blank stretching.
1163 	 */
1164 	context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
1165 
1166 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1167 
1168 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1169 
1170 	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1171 		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1172 
1173 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1174 		if (!context->res_ctx.pipe_ctx[i].stream)
1175 			continue;
1176 		if (context->res_ctx.pipe_ctx[i].plane_state)
1177 			active_hubp_count++;
1178 		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1179 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1180 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1181 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1182 
1183 		if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1184 			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1185 			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1186 			context->res_ctx.pipe_ctx[i].unbounded_req = false;
1187 		} else {
1188 			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
1189 			context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
1190 		}
1191 
1192 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1193 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1194 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
1195 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1196 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1197 		if (dc->ctx->dce_version < DCN_VERSION_3_1 &&
1198 		    context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
1199 			dcn20_adjust_freesync_v_startup(
1200 				&context->res_ctx.pipe_ctx[i].stream->timing,
1201 				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
1202 
1203 		pipe_idx++;
1204 	}
1205 	/* If DCN isn't making memory requests we can allow pstate change */
1206 	if (!active_hubp_count) {
1207 		context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
1208 	}
1209 	/*save a original dppclock copy*/
1210 	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1211 	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1212 	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
1213 	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
1214 
1215 	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
1216 						- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
1217 
1218 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1219 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
1220 
1221 		if (!context->res_ctx.pipe_ctx[i].stream)
1222 			continue;
1223 
1224 		/* cstate disabled on 201 */
1225 		if (dc->ctx->dce_version == DCN_VERSION_2_01)
1226 			cstate_en = false;
1227 
1228 		context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
1229 				&context->res_ctx.pipe_ctx[i].dlg_regs,
1230 				&context->res_ctx.pipe_ctx[i].ttu_regs,
1231 				pipes,
1232 				pipe_cnt,
1233 				pipe_idx,
1234 				cstate_en,
1235 				context->bw_ctx.bw.dcn.clk.p_state_change_support,
1236 				false, false, true);
1237 
1238 		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
1239 				&context->res_ctx.pipe_ctx[i].rq_regs,
1240 				&pipes[pipe_idx].pipe);
1241 		pipe_idx++;
1242 	}
1243 	context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
1244 }
1245 
swizzle_to_dml_params(enum swizzle_mode_values swizzle,unsigned int * sw_mode)1246 static void swizzle_to_dml_params(
1247 		enum swizzle_mode_values swizzle,
1248 		unsigned int *sw_mode)
1249 {
1250 	switch (swizzle) {
1251 	case DC_SW_LINEAR:
1252 		*sw_mode = dm_sw_linear;
1253 		break;
1254 	case DC_SW_4KB_S:
1255 		*sw_mode = dm_sw_4kb_s;
1256 		break;
1257 	case DC_SW_4KB_S_X:
1258 		*sw_mode = dm_sw_4kb_s_x;
1259 		break;
1260 	case DC_SW_4KB_D:
1261 		*sw_mode = dm_sw_4kb_d;
1262 		break;
1263 	case DC_SW_4KB_D_X:
1264 		*sw_mode = dm_sw_4kb_d_x;
1265 		break;
1266 	case DC_SW_64KB_S:
1267 		*sw_mode = dm_sw_64kb_s;
1268 		break;
1269 	case DC_SW_64KB_S_X:
1270 		*sw_mode = dm_sw_64kb_s_x;
1271 		break;
1272 	case DC_SW_64KB_S_T:
1273 		*sw_mode = dm_sw_64kb_s_t;
1274 		break;
1275 	case DC_SW_64KB_D:
1276 		*sw_mode = dm_sw_64kb_d;
1277 		break;
1278 	case DC_SW_64KB_D_X:
1279 		*sw_mode = dm_sw_64kb_d_x;
1280 		break;
1281 	case DC_SW_64KB_D_T:
1282 		*sw_mode = dm_sw_64kb_d_t;
1283 		break;
1284 	case DC_SW_64KB_R_X:
1285 		*sw_mode = dm_sw_64kb_r_x;
1286 		break;
1287 	case DC_SW_VAR_S:
1288 		*sw_mode = dm_sw_var_s;
1289 		break;
1290 	case DC_SW_VAR_S_X:
1291 		*sw_mode = dm_sw_var_s_x;
1292 		break;
1293 	case DC_SW_VAR_D:
1294 		*sw_mode = dm_sw_var_d;
1295 		break;
1296 	case DC_SW_VAR_D_X:
1297 		*sw_mode = dm_sw_var_d_x;
1298 		break;
1299 	case DC_SW_VAR_R_X:
1300 		*sw_mode = dm_sw_var_r_x;
1301 		break;
1302 	default:
1303 		ASSERT(0); /* Not supported */
1304 		break;
1305 	}
1306 }
1307 
dcn20_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1308 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
1309 					  struct dc_state *context,
1310 					  display_e2e_pipe_params_st *pipes,
1311 					  bool fast_validate)
1312 {
1313 	int pipe_cnt, i;
1314 	bool synchronized_vblank = true;
1315 	struct resource_context *res_ctx = &context->res_ctx;
1316 
1317 	dc_assert_fp_enabled();
1318 
1319 	for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1320 		if (!res_ctx->pipe_ctx[i].stream)
1321 			continue;
1322 
1323 		if (pipe_cnt < 0) {
1324 			pipe_cnt = i;
1325 			continue;
1326 		}
1327 
1328 		if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
1329 			continue;
1330 
1331 		if (dc->debug.disable_timing_sync ||
1332 			(!resource_are_streams_timing_synchronizable(
1333 				res_ctx->pipe_ctx[pipe_cnt].stream,
1334 				res_ctx->pipe_ctx[i].stream) &&
1335 			!resource_are_vblanks_synchronizable(
1336 				res_ctx->pipe_ctx[pipe_cnt].stream,
1337 				res_ctx->pipe_ctx[i].stream))) {
1338 			synchronized_vblank = false;
1339 			break;
1340 		}
1341 	}
1342 
1343 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1344 		struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1345 		unsigned int v_total;
1346 		unsigned int front_porch;
1347 		int output_bpc;
1348 		struct audio_check aud_check = {0};
1349 
1350 		if (!res_ctx->pipe_ctx[i].stream)
1351 			continue;
1352 
1353 		v_total = timing->v_total;
1354 		front_porch = timing->v_front_porch;
1355 
1356 		/* todo:
1357 		pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1358 		pipes[pipe_cnt].pipe.src.dcc = 0;
1359 		pipes[pipe_cnt].pipe.src.vm = 0;*/
1360 
1361 		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1362 
1363 		pipes[pipe_cnt].pipe.dest.use_maximum_vstartup = dc->ctx->dce_version == DCN_VERSION_2_01;
1364 
1365 		pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1366 		/* todo: rotation?*/
1367 		pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1368 		if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1369 			pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1370 			/* 1/2 vblank */
1371 			pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1372 				(v_total - timing->v_addressable
1373 					- timing->v_border_top - timing->v_border_bottom) / 2;
1374 			/* 36 bytes dp, 32 hdmi */
1375 			pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1376 				dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1377 		}
1378 		pipes[pipe_cnt].pipe.src.dcc = false;
1379 		pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1380 		pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1381 		pipes[pipe_cnt].pipe.dest.synchronize_timings = synchronized_vblank;
1382 		pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1383 		pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1384 				- timing->h_addressable
1385 				- timing->h_border_left
1386 				- timing->h_border_right;
1387 		pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
1388 		pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1389 				- timing->v_addressable
1390 				- timing->v_border_top
1391 				- timing->v_border_bottom;
1392 		pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1393 		pipes[pipe_cnt].pipe.dest.vtotal = v_total;
1394 		pipes[pipe_cnt].pipe.dest.hactive =
1395 			timing->h_addressable + timing->h_border_left + timing->h_border_right;
1396 		pipes[pipe_cnt].pipe.dest.vactive =
1397 			timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1398 		pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1399 		pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1400 		if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1401 			pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1402 		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1403 		pipes[pipe_cnt].dout.dp_lanes = 4;
1404 		pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
1405 		pipes[pipe_cnt].dout.is_virtual = 0;
1406 		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1407 		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1408 		switch (resource_get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
1409 		case 1:
1410 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
1411 			break;
1412 		case 3:
1413 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
1414 			break;
1415 		default:
1416 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
1417 		}
1418 		pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1419 		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1420 				== res_ctx->pipe_ctx[i].plane_state) {
1421 			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
1422 			int split_idx = 0;
1423 
1424 			while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
1425 					== res_ctx->pipe_ctx[i].plane_state) {
1426 				first_pipe = first_pipe->top_pipe;
1427 				split_idx++;
1428 			}
1429 			/* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
1430 			if (split_idx == 0)
1431 				pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1432 			else if (split_idx == 1)
1433 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1434 			else if (split_idx == 2)
1435 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1436 		} else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1437 			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1438 
1439 			while (first_pipe->prev_odm_pipe)
1440 				first_pipe = first_pipe->prev_odm_pipe;
1441 			pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1442 		}
1443 
1444 		switch (res_ctx->pipe_ctx[i].stream->signal) {
1445 		case SIGNAL_TYPE_DISPLAY_PORT_MST:
1446 		case SIGNAL_TYPE_DISPLAY_PORT:
1447 			pipes[pipe_cnt].dout.output_type = dm_dp;
1448 			if (dc->link_srv->dp_is_128b_132b_signal(&res_ctx->pipe_ctx[i]))
1449 				pipes[pipe_cnt].dout.output_type = dm_dp2p0;
1450 			break;
1451 		case SIGNAL_TYPE_EDP:
1452 			pipes[pipe_cnt].dout.output_type = dm_edp;
1453 			break;
1454 		case SIGNAL_TYPE_HDMI_TYPE_A:
1455 		case SIGNAL_TYPE_DVI_SINGLE_LINK:
1456 		case SIGNAL_TYPE_DVI_DUAL_LINK:
1457 			pipes[pipe_cnt].dout.output_type = dm_hdmi;
1458 			break;
1459 		default:
1460 			/* In case there is no signal, set dp with 4 lanes to allow max config */
1461 			pipes[pipe_cnt].dout.is_virtual = 1;
1462 			pipes[pipe_cnt].dout.output_type = dm_dp;
1463 			pipes[pipe_cnt].dout.dp_lanes = 4;
1464 		}
1465 
1466 		switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1467 		case COLOR_DEPTH_666:
1468 			output_bpc = 6;
1469 			break;
1470 		case COLOR_DEPTH_888:
1471 			output_bpc = 8;
1472 			break;
1473 		case COLOR_DEPTH_101010:
1474 			output_bpc = 10;
1475 			break;
1476 		case COLOR_DEPTH_121212:
1477 			output_bpc = 12;
1478 			break;
1479 		case COLOR_DEPTH_141414:
1480 			output_bpc = 14;
1481 			break;
1482 		case COLOR_DEPTH_161616:
1483 			output_bpc = 16;
1484 			break;
1485 		case COLOR_DEPTH_999:
1486 			output_bpc = 9;
1487 			break;
1488 		case COLOR_DEPTH_111111:
1489 			output_bpc = 11;
1490 			break;
1491 		default:
1492 			output_bpc = 8;
1493 			break;
1494 		}
1495 
1496 		switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1497 		case PIXEL_ENCODING_RGB:
1498 		case PIXEL_ENCODING_YCBCR444:
1499 			pipes[pipe_cnt].dout.output_format = dm_444;
1500 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1501 			break;
1502 		case PIXEL_ENCODING_YCBCR420:
1503 			pipes[pipe_cnt].dout.output_format = dm_420;
1504 			pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
1505 			break;
1506 		case PIXEL_ENCODING_YCBCR422:
1507 			if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
1508 			    !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
1509 				pipes[pipe_cnt].dout.output_format = dm_n422;
1510 			else
1511 				pipes[pipe_cnt].dout.output_format = dm_s422;
1512 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1513 			break;
1514 		default:
1515 			pipes[pipe_cnt].dout.output_format = dm_444;
1516 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1517 		}
1518 
1519 		if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
1520 			pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
1521 
1522 		/* todo: default max for now, until there is logic reflecting this in dc*/
1523 		pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1524 		/*fill up the audio sample rate (unit in kHz)*/
1525 		get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
1526 		pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
1527 		/*
1528 		 * For graphic plane, cursor number is 1, nv12 is 0
1529 		 * bw calculations due to cursor on/off
1530 		 */
1531 		if (res_ctx->pipe_ctx[i].plane_state &&
1532 				(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||
1533 				 res_ctx->pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM))
1534 			pipes[pipe_cnt].pipe.src.num_cursors = 0;
1535 		else
1536 			pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
1537 
1538 		pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1539 		pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1540 
1541 		if (!res_ctx->pipe_ctx[i].plane_state) {
1542 			pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1543 			pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1544 			pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1545 			pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
1546 			pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1547 			pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1548 			if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1549 				pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1550 			pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1551 			if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1552 				pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1553 			pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
1554 			pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
1555 			pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
1556 			pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
1557 			pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
1558 			pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1559 			pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1560 			pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1561 			pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
1562 			pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1563 			pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1564 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1565 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1566 			pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1567 			pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1568 			pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1569 			pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
1570 			pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
1571 
1572 			if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
1573 				pipes[pipe_cnt].pipe.src.viewport_width /= 2;
1574 				pipes[pipe_cnt].pipe.dest.recout_width /= 2;
1575 			} else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
1576 				pipes[pipe_cnt].pipe.src.viewport_width /= 4;
1577 				pipes[pipe_cnt].pipe.dest.recout_width /= 4;
1578 			}
1579 		} else {
1580 			struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1581 			struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1582 
1583 			pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1584 			pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1585 					|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
1586 					|| pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1587 
1588 			/* stereo is not split */
1589 			if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
1590 			    pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
1591 				pipes[pipe_cnt].pipe.src.is_hsplit = false;
1592 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1593 			}
1594 
1595 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1596 					|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1597 			switch (pln->rotation) {
1598 			case ROTATION_ANGLE_0:
1599 				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1600 				break;
1601 			case ROTATION_ANGLE_90:
1602 				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90;
1603 				break;
1604 			case ROTATION_ANGLE_180:
1605 				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180;
1606 				break;
1607 			case ROTATION_ANGLE_270:
1608 				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270;
1609 				break;
1610 			default:
1611 				break;
1612 			}
1613 
1614 			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1615 			pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1616 			pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x;
1617 			pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x;
1618 			pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1619 			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1620 			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1621 			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1622 			pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
1623 			pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
1624 			pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
1625 			pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
1626 			pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
1627 			pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
1628 			if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
1629 					|| pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1630 				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1631 				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1632 				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1633 				pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
1634 			} else {
1635 				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1636 				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1637 			}
1638 			pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1639 			pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1640 			pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1641 			pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1642 			pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1643 			if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
1644 				pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
1645 			else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
1646 				pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
1647 			else {
1648 				struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
1649 
1650 				while (split_pipe && split_pipe->plane_state == pln) {
1651 					pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1652 					split_pipe = split_pipe->bottom_pipe;
1653 				}
1654 				split_pipe = res_ctx->pipe_ctx[i].top_pipe;
1655 				while (split_pipe && split_pipe->plane_state == pln) {
1656 					pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1657 					split_pipe = split_pipe->top_pipe;
1658 				}
1659 			}
1660 
1661 			pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1662 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1663 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1664 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1665 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1666 			pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1667 					scl->ratios.vert.value != dc_fixpt_one.value
1668 					|| scl->ratios.horz.value != dc_fixpt_one.value
1669 					|| scl->ratios.vert_c.value != dc_fixpt_one.value
1670 					|| scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1671 					|| dc->debug.always_scale; /*support always scale*/
1672 			pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1673 			pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1674 			pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1675 			pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1676 
1677 			pipes[pipe_cnt].pipe.src.macro_tile_size =
1678 					swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
1679 			swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1680 					&pipes[pipe_cnt].pipe.src.sw_mode);
1681 
1682 			switch (pln->format) {
1683 			case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1684 			case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1685 				pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1686 				break;
1687 			case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1688 			case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1689 				pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1690 				break;
1691 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1692 			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
1693 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1694 			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1695 				pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1696 				break;
1697 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1698 			case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1699 				pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1700 				break;
1701 			case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1702 				pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1703 				break;
1704 			case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
1705 				pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
1706 				break;
1707 			default:
1708 				pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1709 				break;
1710 			}
1711 		}
1712 
1713 		pipe_cnt++;
1714 	}
1715 
1716 	/* populate writeback information */
1717 	dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1718 
1719 	return pipe_cnt;
1720 }
1721 
dcn20_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel,bool fast_validate)1722 void dcn20_calculate_wm(struct dc *dc, struct dc_state *context,
1723 			display_e2e_pipe_params_st *pipes,
1724 			int *out_pipe_cnt,
1725 			int *pipe_split_from,
1726 			int vlevel,
1727 			bool fast_validate)
1728 {
1729 	int pipe_cnt, i, pipe_idx;
1730 
1731 	dc_assert_fp_enabled();
1732 
1733 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1734 		if (!context->res_ctx.pipe_ctx[i].stream)
1735 			continue;
1736 
1737 		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1738 		pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1739 
1740 		if (pipe_split_from[i] < 0) {
1741 			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1742 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1743 			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1744 				pipes[pipe_cnt].pipe.dest.odm_combine =
1745 						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
1746 			else
1747 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1748 			pipe_idx++;
1749 		} else {
1750 			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1751 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1752 			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1753 				pipes[pipe_cnt].pipe.dest.odm_combine =
1754 						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
1755 			else
1756 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1757 		}
1758 
1759 		if (dc->config.forced_clocks) {
1760 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1761 			pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1762 		}
1763 		if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
1764 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1765 		if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
1766 			pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1767 
1768 		pipe_cnt++;
1769 	}
1770 
1771 	if (pipe_cnt != pipe_idx) {
1772 		if (dc->res_pool->funcs->populate_dml_pipes)
1773 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1774 				context, pipes, fast_validate);
1775 		else
1776 			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
1777 				context, pipes, fast_validate);
1778 	}
1779 
1780 	*out_pipe_cnt = pipe_cnt;
1781 
1782 	pipes[0].clks_cfg.voltage = vlevel;
1783 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1784 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1785 
1786 	/* only pipe 0 is read for voltage and dcf/soc clocks */
1787 	if (vlevel < 1) {
1788 		pipes[0].clks_cfg.voltage = 1;
1789 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
1790 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
1791 	}
1792 	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1793 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1794 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1795 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1796 	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1797 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1798 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1799 	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1800 
1801 	if (vlevel < 2) {
1802 		pipes[0].clks_cfg.voltage = 2;
1803 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1804 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1805 	}
1806 	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1807 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1808 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1809 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1810 	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1811 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1812 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1813 
1814 	if (vlevel < 3) {
1815 		pipes[0].clks_cfg.voltage = 3;
1816 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1817 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1818 	}
1819 	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1820 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1821 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1822 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1823 	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1824 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1825 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1826 
1827 	pipes[0].clks_cfg.voltage = vlevel;
1828 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1829 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1830 	context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1831 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1832 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1833 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1834 	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1835 	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1836 	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1837 }
1838 
dcn20_update_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb,struct pp_smu_nv_clock_table * max_clocks,unsigned int * uclk_states,unsigned int num_states)1839 void dcn20_update_bounding_box(struct dc *dc,
1840 			       struct _vcs_dpi_soc_bounding_box_st *bb,
1841 			       struct pp_smu_nv_clock_table *max_clocks,
1842 			       unsigned int *uclk_states,
1843 			       unsigned int num_states)
1844 {
1845 	int num_calculated_states = 0;
1846 	int min_dcfclk = 0;
1847 	int i;
1848 
1849 	dc_assert_fp_enabled();
1850 
1851 	if (num_states == 0)
1852 		return;
1853 
1854 	memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
1855 
1856 	if (dc->bb_overrides.min_dcfclk_mhz > 0) {
1857 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
1858 	} else {
1859 		if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
1860 			min_dcfclk = 310;
1861 		else
1862 			// Accounting for SOC/DCF relationship, we can go as high as
1863 			// 506Mhz in Vmin.
1864 			min_dcfclk = 506;
1865 	}
1866 
1867 	for (i = 0; i < num_states; i++) {
1868 		int min_fclk_required_by_uclk;
1869 		bb->clock_limits[i].state = i;
1870 		bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
1871 
1872 		// FCLK:UCLK ratio is 1.08
1873 		min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
1874 			1000000);
1875 
1876 		bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
1877 				min_dcfclk : min_fclk_required_by_uclk;
1878 
1879 		bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
1880 				max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
1881 
1882 		bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
1883 				max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
1884 
1885 		bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
1886 		bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
1887 		bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
1888 
1889 		bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
1890 
1891 		num_calculated_states++;
1892 	}
1893 
1894 	bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
1895 	bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
1896 	bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
1897 
1898 	bb->num_states = num_calculated_states;
1899 
1900 	// Duplicate the last state, DML always an extra state identical to max state to work
1901 	memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
1902 	bb->clock_limits[num_calculated_states].state = bb->num_states;
1903 }
1904 
dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st * bb,struct pp_smu_nv_clock_table max_clocks)1905 void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,
1906 			  struct pp_smu_nv_clock_table max_clocks)
1907 {
1908 	int i;
1909 
1910 	dc_assert_fp_enabled();
1911 
1912 	// First pass - cap all clocks higher than the reported max
1913 	for (i = 0; i < bb->num_states; i++) {
1914 		if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
1915 				&& max_clocks.dcfClockInKhz != 0)
1916 			bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
1917 
1918 		if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
1919 						&& max_clocks.uClockInKhz != 0)
1920 			bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
1921 
1922 		if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
1923 						&& max_clocks.fabricClockInKhz != 0)
1924 			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
1925 
1926 		if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
1927 						&& max_clocks.displayClockInKhz != 0)
1928 			bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
1929 
1930 		if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
1931 						&& max_clocks.dppClockInKhz != 0)
1932 			bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
1933 
1934 		if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
1935 						&& max_clocks.phyClockInKhz != 0)
1936 			bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
1937 
1938 		if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
1939 						&& max_clocks.socClockInKhz != 0)
1940 			bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
1941 
1942 		if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
1943 						&& max_clocks.dscClockInKhz != 0)
1944 			bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
1945 	}
1946 
1947 	// Second pass - remove all duplicate clock states
1948 	for (i = bb->num_states - 1; i > 1; i--) {
1949 		bool duplicate = true;
1950 
1951 		if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
1952 			duplicate = false;
1953 		if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
1954 			duplicate = false;
1955 		if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
1956 			duplicate = false;
1957 		if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
1958 			duplicate = false;
1959 		if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
1960 			duplicate = false;
1961 		if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
1962 			duplicate = false;
1963 		if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
1964 			duplicate = false;
1965 		if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
1966 			duplicate = false;
1967 
1968 		if (duplicate)
1969 			bb->num_states--;
1970 	}
1971 }
1972 
dcn20_patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)1973 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1974 {
1975 	dc_assert_fp_enabled();
1976 
1977 	if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
1978 			&& dc->bb_overrides.sr_exit_time_ns) {
1979 		bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
1980 	}
1981 
1982 	if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
1983 				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
1984 			&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1985 		bb->sr_enter_plus_exit_time_us =
1986 				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1987 	}
1988 
1989 	if ((int)(bb->sr_exit_z8_time_us * 1000)
1990 				!= dc->bb_overrides.sr_exit_z8_time_ns
1991 			&& dc->bb_overrides.sr_exit_z8_time_ns) {
1992 		bb->sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;
1993 	}
1994 
1995 	if ((int)(bb->sr_enter_plus_exit_z8_time_us * 1000)
1996 				!= dc->bb_overrides.sr_enter_plus_exit_z8_time_ns
1997 			&& dc->bb_overrides.sr_enter_plus_exit_z8_time_ns) {
1998 		bb->sr_enter_plus_exit_z8_time_us = dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;
1999 	}
2000 	if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2001 			&& dc->bb_overrides.urgent_latency_ns) {
2002 		bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2003 	}
2004 
2005 	if ((int)(bb->dram_clock_change_latency_us * 1000)
2006 				!= dc->bb_overrides.dram_clock_change_latency_ns
2007 			&& dc->bb_overrides.dram_clock_change_latency_ns) {
2008 		bb->dram_clock_change_latency_us =
2009 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2010 	}
2011 
2012 	if ((int)(bb->dummy_pstate_latency_us * 1000)
2013 				!= dc->bb_overrides.dummy_clock_change_latency_ns
2014 			&& dc->bb_overrides.dummy_clock_change_latency_ns) {
2015 		bb->dummy_pstate_latency_us =
2016 				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
2017 	}
2018 }
2019 
dcn20_validate_bandwidth_internal(struct dc * dc,struct dc_state * context,bool fast_validate)2020 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
2021 		bool fast_validate)
2022 {
2023 	bool out = false;
2024 
2025 	BW_VAL_TRACE_SETUP();
2026 
2027 	int vlevel = 0;
2028 	int pipe_split_from[MAX_PIPES];
2029 	int pipe_cnt = 0;
2030 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
2031 	DC_LOGGER_INIT(dc->ctx->logger);
2032 
2033 	BW_VAL_TRACE_COUNT();
2034 
2035 	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2036 
2037 	if (pipe_cnt == 0)
2038 		goto validate_out;
2039 
2040 	if (!out)
2041 		goto validate_fail;
2042 
2043 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2044 
2045 	if (fast_validate) {
2046 		BW_VAL_TRACE_SKIP(fast);
2047 		goto validate_out;
2048 	}
2049 
2050 	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2051 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2052 
2053 	BW_VAL_TRACE_END_WATERMARKS();
2054 
2055 	goto validate_out;
2056 
2057 validate_fail:
2058 	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2059 		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2060 
2061 	BW_VAL_TRACE_SKIP(fail);
2062 	out = false;
2063 
2064 validate_out:
2065 	kfree(pipes);
2066 
2067 	BW_VAL_TRACE_FINISH();
2068 
2069 	return out;
2070 }
2071 
dcn20_validate_bandwidth_fp(struct dc * dc,struct dc_state * context,bool fast_validate)2072 bool dcn20_validate_bandwidth_fp(struct dc *dc,
2073 				 struct dc_state *context,
2074 				 bool fast_validate)
2075 {
2076 	bool voltage_supported = false;
2077 	bool full_pstate_supported = false;
2078 	bool dummy_pstate_supported = false;
2079 	double p_state_latency_us;
2080 
2081 	dc_assert_fp_enabled();
2082 
2083 	p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
2084 	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
2085 		dc->debug.disable_dram_clock_change_vactive_support;
2086 	context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
2087 		dc->debug.enable_dram_clock_change_one_display_vactive;
2088 
2089 	/*Unsafe due to current pipe merge and split logic*/
2090 	ASSERT(context != dc->current_state);
2091 
2092 	if (fast_validate) {
2093 		return dcn20_validate_bandwidth_internal(dc, context, true);
2094 	}
2095 
2096 	// Best case, we support full UCLK switch latency
2097 	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2098 	full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2099 
2100 	if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
2101 		(voltage_supported && full_pstate_supported)) {
2102 		context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
2103 		goto restore_dml_state;
2104 	}
2105 
2106 	// Fallback: Try to only support G6 temperature read latency
2107 	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2108 
2109 	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2110 	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2111 
2112 	if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
2113 		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2114 		goto restore_dml_state;
2115 	}
2116 
2117 	// ERROR: fallback is supposed to always work.
2118 	ASSERT(false);
2119 
2120 restore_dml_state:
2121 	context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2122 	return voltage_supported;
2123 }
2124 
dcn20_fpu_set_wm_ranges(int i,struct pp_smu_wm_range_sets * ranges,struct _vcs_dpi_soc_bounding_box_st * loaded_bb)2125 void dcn20_fpu_set_wm_ranges(int i,
2126 			     struct pp_smu_wm_range_sets *ranges,
2127 			     struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
2128 {
2129 	dc_assert_fp_enabled();
2130 
2131 	ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
2132 	ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
2133 }
2134 
dcn20_fpu_adjust_dppclk(struct vba_vars_st * v,int vlevel,int max_mpc_comb,int pipe_idx,bool is_validating_bw)2135 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
2136 			     int vlevel,
2137 			     int max_mpc_comb,
2138 			     int pipe_idx,
2139 			     bool is_validating_bw)
2140 {
2141 	dc_assert_fp_enabled();
2142 
2143 	if (is_validating_bw)
2144 		v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2;
2145 	else
2146 		v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
2147 }
2148 
dcn21_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)2149 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
2150 					  struct dc_state *context,
2151 					  display_e2e_pipe_params_st *pipes,
2152 					  bool fast_validate)
2153 {
2154 	uint32_t pipe_cnt;
2155 	int i;
2156 
2157 	dc_assert_fp_enabled();
2158 
2159 	pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
2160 
2161 	for (i = 0; i < pipe_cnt; i++) {
2162 
2163 		pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
2164 		pipes[i].pipe.src.gpuvm = 1;
2165 	}
2166 
2167 	return pipe_cnt;
2168 }
2169 
patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)2170 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2171 {
2172 	int i;
2173 
2174 	if (dc->bb_overrides.sr_exit_time_ns) {
2175 		for (i = 0; i < WM_SET_COUNT; i++) {
2176 			  dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
2177 					  dc->bb_overrides.sr_exit_time_ns / 1000.0;
2178 		}
2179 	}
2180 
2181 	if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2182 		for (i = 0; i < WM_SET_COUNT; i++) {
2183 			  dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
2184 					  dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2185 		}
2186 	}
2187 
2188 	if (dc->bb_overrides.urgent_latency_ns) {
2189 		bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2190 	}
2191 
2192 	if (dc->bb_overrides.dram_clock_change_latency_ns) {
2193 		for (i = 0; i < WM_SET_COUNT; i++) {
2194 			dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
2195 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2196 		}
2197 	}
2198 }
2199 
calculate_wm_set_for_vlevel(int vlevel,struct wm_range_table_entry * table_entry,struct dcn_watermarks * wm_set,struct display_mode_lib * dml,display_e2e_pipe_params_st * pipes,int pipe_cnt)2200 static void calculate_wm_set_for_vlevel(int vlevel,
2201 					struct wm_range_table_entry *table_entry,
2202 					struct dcn_watermarks *wm_set,
2203 					struct display_mode_lib *dml,
2204 					display_e2e_pipe_params_st *pipes,
2205 					int pipe_cnt)
2206 {
2207 	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
2208 
2209 	ASSERT(vlevel < dml->soc.num_states);
2210 	/* only pipe 0 is read for voltage and dcf/soc clocks */
2211 	pipes[0].clks_cfg.voltage = vlevel;
2212 	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
2213 	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
2214 
2215 	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
2216 	dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
2217 	dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
2218 
2219 	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
2220 	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
2221 	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
2222 	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
2223 	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
2224 	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
2225 	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
2226 	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
2227 	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
2228 }
2229 
dcn21_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel_req,bool fast_validate)2230 static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,
2231 			display_e2e_pipe_params_st *pipes,
2232 			int *out_pipe_cnt,
2233 			int *pipe_split_from,
2234 			int vlevel_req,
2235 			bool fast_validate)
2236 {
2237 	int pipe_cnt, i, pipe_idx;
2238 	int vlevel, vlevel_max;
2239 	struct wm_range_table_entry *table_entry;
2240 	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
2241 
2242 	ASSERT(bw_params);
2243 
2244 	patch_bounding_box(dc, &context->bw_ctx.dml.soc);
2245 
2246 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2247 			if (!context->res_ctx.pipe_ctx[i].stream)
2248 				continue;
2249 
2250 			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2251 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
2252 
2253 			if (pipe_split_from[i] < 0) {
2254 				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2255 						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2256 				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2257 					pipes[pipe_cnt].pipe.dest.odm_combine =
2258 							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
2259 				else
2260 					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2261 				pipe_idx++;
2262 			} else {
2263 				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2264 						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2265 				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2266 					pipes[pipe_cnt].pipe.dest.odm_combine =
2267 							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
2268 				else
2269 					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2270 			}
2271 			pipe_cnt++;
2272 	}
2273 
2274 	if (pipe_cnt != pipe_idx) {
2275 		if (dc->res_pool->funcs->populate_dml_pipes)
2276 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2277 				context, pipes, fast_validate);
2278 		else
2279 			pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2280 				context, pipes, fast_validate);
2281 	}
2282 
2283 	*out_pipe_cnt = pipe_cnt;
2284 
2285 	vlevel_max = bw_params->clk_table.num_entries - 1;
2286 
2287 
2288 	/* WM Set D */
2289 	table_entry = &bw_params->wm_table.entries[WM_D];
2290 	if (table_entry->wm_type == WM_TYPE_RETRAINING)
2291 		vlevel = 0;
2292 	else
2293 		vlevel = vlevel_max;
2294 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
2295 						&context->bw_ctx.dml, pipes, pipe_cnt);
2296 	/* WM Set C */
2297 	table_entry = &bw_params->wm_table.entries[WM_C];
2298 	vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
2299 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
2300 						&context->bw_ctx.dml, pipes, pipe_cnt);
2301 	/* WM Set B */
2302 	table_entry = &bw_params->wm_table.entries[WM_B];
2303 	vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
2304 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
2305 						&context->bw_ctx.dml, pipes, pipe_cnt);
2306 
2307 	/* WM Set A */
2308 	table_entry = &bw_params->wm_table.entries[WM_A];
2309 	vlevel = MIN(vlevel_req, vlevel_max);
2310 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
2311 						&context->bw_ctx.dml, pipes, pipe_cnt);
2312 }
2313 
dcn21_validate_bandwidth_fp(struct dc * dc,struct dc_state * context,bool fast_validate)2314 bool dcn21_validate_bandwidth_fp(struct dc *dc,
2315 				 struct dc_state *context,
2316 				 bool fast_validate)
2317 {
2318 	bool out = false;
2319 
2320 	BW_VAL_TRACE_SETUP();
2321 
2322 	int vlevel = 0;
2323 	int pipe_split_from[MAX_PIPES];
2324 	int pipe_cnt = 0;
2325 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
2326 	DC_LOGGER_INIT(dc->ctx->logger);
2327 
2328 	BW_VAL_TRACE_COUNT();
2329 
2330 	dc_assert_fp_enabled();
2331 
2332 	/*Unsafe due to current pipe merge and split logic*/
2333 	ASSERT(context != dc->current_state);
2334 
2335 	out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2336 
2337 	if (pipe_cnt == 0)
2338 		goto validate_out;
2339 
2340 	if (!out)
2341 		goto validate_fail;
2342 
2343 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2344 
2345 	if (fast_validate) {
2346 		BW_VAL_TRACE_SKIP(fast);
2347 		goto validate_out;
2348 	}
2349 
2350 	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2351 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2352 
2353 	BW_VAL_TRACE_END_WATERMARKS();
2354 
2355 	goto validate_out;
2356 
2357 validate_fail:
2358 	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2359 			dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2360 
2361 	BW_VAL_TRACE_SKIP(fail);
2362 	out = false;
2363 
2364 validate_out:
2365 	kfree(pipes);
2366 
2367 	BW_VAL_TRACE_FINISH();
2368 
2369 	return out;
2370 }
2371 
construct_low_pstate_lvl(struct clk_limit_table * clk_table,unsigned int high_voltage_lvl)2372 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
2373 {
2374 	struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
2375 	int i;
2376 
2377 	low_pstate_lvl.state = 1;
2378 	low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
2379 	low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
2380 	low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
2381 	low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
2382 
2383 	low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
2384 	low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
2385 	low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
2386 	low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
2387 	low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
2388 	low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
2389 	low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
2390 
2391 	for (i = clk_table->num_entries; i > 1; i--)
2392 		clk_table->entries[i] = clk_table->entries[i-1];
2393 	clk_table->entries[1] = clk_table->entries[0];
2394 	clk_table->num_entries++;
2395 
2396 	return low_pstate_lvl;
2397 }
2398 
dcn21_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)2399 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2400 {
2401 	struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
2402 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
2403 	struct clk_limit_table *clk_table = &bw_params->clk_table;
2404 	unsigned int i, closest_clk_lvl = 0, k = 0;
2405 	int j;
2406 
2407 	dc_assert_fp_enabled();
2408 
2409 	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2410 	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
2411 	dcn2_1_soc.num_chans = bw_params->num_channels;
2412 
2413 	ASSERT(clk_table->num_entries);
2414 	/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
2415 	memcpy(s, dcn2_1_soc.clock_limits, sizeof(dcn2_1_soc.clock_limits));
2416 
2417 	for (i = 0; i < clk_table->num_entries; i++) {
2418 		/* loop backwards*/
2419 		for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
2420 			if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2421 				closest_clk_lvl = j;
2422 				break;
2423 			}
2424 		}
2425 
2426 		/* clk_table[1] is reserved for min DF PState.  skip here to fill in later. */
2427 		if (i == 1)
2428 			k++;
2429 
2430 		s[k].state = k;
2431 		s[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2432 		s[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2433 		s[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
2434 		s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
2435 
2436 		s[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2437 		s[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2438 		s[k].dram_bw_per_chan_gbps =
2439 			dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2440 		s[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2441 		s[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2442 		s[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2443 		s[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2444 
2445 		k++;
2446 	}
2447 
2448 	memcpy(&dcn2_1_soc.clock_limits, s, sizeof(dcn2_1_soc.clock_limits));
2449 
2450 	if (clk_table->num_entries) {
2451 		dcn2_1_soc.num_states = clk_table->num_entries + 1;
2452 		/* fill in min DF PState */
2453 		dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
2454 		/* duplicate last level */
2455 		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
2456 		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
2457 	}
2458 
2459 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2460 }
2461 
dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params * bw_params)2462 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params)
2463 {
2464 	dc_assert_fp_enabled();
2465 
2466 	bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
2467 	bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
2468 	bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
2469 	bw_params->wm_table.entries[WM_D].valid = true;
2470 }
2471 
dcn201_populate_dml_writeback_from_context_fpu(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)2472 void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
2473 						    struct resource_context *res_ctx,
2474 						    display_e2e_pipe_params_st *pipes)
2475 {
2476 	int pipe_cnt, i, j;
2477 	double max_calc_writeback_dispclk;
2478 	double writeback_dispclk;
2479 	struct writeback_st dout_wb;
2480 
2481 	dc_assert_fp_enabled();
2482 
2483 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2484 		struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
2485 
2486 		if (!stream)
2487 			continue;
2488 		max_calc_writeback_dispclk = 0;
2489 
2490 		/* Set writeback information */
2491 		pipes[pipe_cnt].dout.wb_enable = 0;
2492 		pipes[pipe_cnt].dout.num_active_wb = 0;
2493 		for (j = 0; j < stream->num_wb_info; j++) {
2494 			struct dc_writeback_info *wb_info = &stream->writeback_info[j];
2495 
2496 			if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
2497 					(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
2498 				pipes[pipe_cnt].dout.wb_enable = 1;
2499 				pipes[pipe_cnt].dout.num_active_wb++;
2500 				dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
2501 					wb_info->dwb_params.cnv_params.crop_height :
2502 					wb_info->dwb_params.cnv_params.src_height;
2503 				dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
2504 					wb_info->dwb_params.cnv_params.crop_width :
2505 					wb_info->dwb_params.cnv_params.src_width;
2506 				dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
2507 				dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
2508 				dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
2509 				dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
2510 				dout_wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
2511 				dout_wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
2512 				dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
2513 					(double)wb_info->dwb_params.cnv_params.crop_width /
2514 						(double)wb_info->dwb_params.dest_width :
2515 					(double)wb_info->dwb_params.cnv_params.src_width /
2516 						(double)wb_info->dwb_params.dest_width;
2517 				dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
2518 					(double)wb_info->dwb_params.cnv_params.crop_height /
2519 						(double)wb_info->dwb_params.dest_height :
2520 					(double)wb_info->dwb_params.cnv_params.src_height /
2521 						(double)wb_info->dwb_params.dest_height;
2522 				if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
2523 					if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2524 						dout_wb.wb_pixel_format = dm_420_8;
2525 					else
2526 						dout_wb.wb_pixel_format = dm_420_10;
2527 				} else
2528 					dout_wb.wb_pixel_format = dm_444_32;
2529 
2530 				/* Workaround for cases where multiple writebacks are connected to same plane
2531 				 * In which case, need to compute worst case and set the associated writeback parameters
2532 				 * This workaround is necessary due to DML computation assuming only 1 set of writeback
2533 				 * parameters per pipe */
2534 				writeback_dispclk = CalculateWriteBackDISPCLK(
2535 						dout_wb.wb_pixel_format,
2536 						pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
2537 						dout_wb.wb_hratio,
2538 						dout_wb.wb_vratio,
2539 						dout_wb.wb_htaps_luma,
2540 						dout_wb.wb_vtaps_luma,
2541 						dout_wb.wb_htaps_chroma,
2542 						dout_wb.wb_vtaps_chroma,
2543 						dout_wb.wb_dst_width,
2544 						pipes[pipe_cnt].pipe.dest.htotal,
2545 						2);
2546 
2547 				if (writeback_dispclk > max_calc_writeback_dispclk) {
2548 					max_calc_writeback_dispclk = writeback_dispclk;
2549 					pipes[pipe_cnt].dout.wb = dout_wb;
2550 				}
2551 			}
2552 		}
2553 
2554 		pipe_cnt++;
2555 	}
2556 
2557 }
2558