1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #include <linux/delay.h>
26 
27 #include "dm_services.h"
28 #include "basics/dc_common.h"
29 #include "dm_helpers.h"
30 #include "core_types.h"
31 #include "resource.h"
32 #include "dcn20_resource.h"
33 #include "dcn20_hwseq.h"
34 #include "dce/dce_hwseq.h"
35 #include "dcn20_dsc.h"
36 #include "dcn20_optc.h"
37 #include "abm.h"
38 #include "clk_mgr.h"
39 #include "dmcu.h"
40 #include "hubp.h"
41 #include "timing_generator.h"
42 #include "opp.h"
43 #include "ipp.h"
44 #include "mpc.h"
45 #include "mcif_wb.h"
46 #include "dchubbub.h"
47 #include "reg_helper.h"
48 #include "dcn10/dcn10_cm_common.h"
49 #include "dc_link_dp.h"
50 #include "vm_helper.h"
51 #include "dccg.h"
52 #include "dc_dmub_srv.h"
53 #include "dce/dmub_hw_lock_mgr.h"
54 #include "hw_sequencer.h"
55 #include "inc/link_dpcd.h"
56 #include "dpcd_defs.h"
57 #include "inc/link_enc_cfg.h"
58 #include "link_hwss.h"
59 
60 #define DC_LOGGER_INIT(logger)
61 
62 #define CTX \
63 	hws->ctx
64 #define REG(reg)\
65 	hws->regs->reg
66 
67 #undef FN
68 #define FN(reg_name, field_name) \
69 	hws->shifts->field_name, hws->masks->field_name
70 
find_free_gsl_group(const struct dc * dc)71 static int find_free_gsl_group(const struct dc *dc)
72 {
73 	if (dc->res_pool->gsl_groups.gsl_0 == 0)
74 		return 1;
75 	if (dc->res_pool->gsl_groups.gsl_1 == 0)
76 		return 2;
77 	if (dc->res_pool->gsl_groups.gsl_2 == 0)
78 		return 3;
79 
80 	return 0;
81 }
82 
83 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
84  * This is only used to lock pipes in pipe splitting case with immediate flip
85  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
86  * so we get tearing with freesync since we cannot flip multiple pipes
87  * atomically.
88  * We use GSL for this:
89  * - immediate flip: find first available GSL group if not already assigned
90  *                   program gsl with that group, set current OTG as master
91  *                   and always us 0x4 = AND of flip_ready from all pipes
92  * - vsync flip: disable GSL if used
93  *
94  * Groups in stream_res are stored as +1 from HW registers, i.e.
95  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
96  * Using a magic value like -1 would require tracking all inits/resets
97  */
dcn20_setup_gsl_group_as_lock(const struct dc * dc,struct pipe_ctx * pipe_ctx,bool enable)98 static void dcn20_setup_gsl_group_as_lock(
99 		const struct dc *dc,
100 		struct pipe_ctx *pipe_ctx,
101 		bool enable)
102 {
103 	struct gsl_params gsl;
104 	int group_idx;
105 
106 	memset(&gsl, 0, sizeof(struct gsl_params));
107 
108 	if (enable) {
109 		/* return if group already assigned since GSL was set up
110 		 * for vsync flip, we would unassign so it can't be "left over"
111 		 */
112 		if (pipe_ctx->stream_res.gsl_group > 0)
113 			return;
114 
115 		group_idx = find_free_gsl_group(dc);
116 		ASSERT(group_idx != 0);
117 		pipe_ctx->stream_res.gsl_group = group_idx;
118 
119 		/* set gsl group reg field and mark resource used */
120 		switch (group_idx) {
121 		case 1:
122 			gsl.gsl0_en = 1;
123 			dc->res_pool->gsl_groups.gsl_0 = 1;
124 			break;
125 		case 2:
126 			gsl.gsl1_en = 1;
127 			dc->res_pool->gsl_groups.gsl_1 = 1;
128 			break;
129 		case 3:
130 			gsl.gsl2_en = 1;
131 			dc->res_pool->gsl_groups.gsl_2 = 1;
132 			break;
133 		default:
134 			BREAK_TO_DEBUGGER();
135 			return; // invalid case
136 		}
137 		gsl.gsl_master_en = 1;
138 	} else {
139 		group_idx = pipe_ctx->stream_res.gsl_group;
140 		if (group_idx == 0)
141 			return; // if not in use, just return
142 
143 		pipe_ctx->stream_res.gsl_group = 0;
144 
145 		/* unset gsl group reg field and mark resource free */
146 		switch (group_idx) {
147 		case 1:
148 			gsl.gsl0_en = 0;
149 			dc->res_pool->gsl_groups.gsl_0 = 0;
150 			break;
151 		case 2:
152 			gsl.gsl1_en = 0;
153 			dc->res_pool->gsl_groups.gsl_1 = 0;
154 			break;
155 		case 3:
156 			gsl.gsl2_en = 0;
157 			dc->res_pool->gsl_groups.gsl_2 = 0;
158 			break;
159 		default:
160 			BREAK_TO_DEBUGGER();
161 			return;
162 		}
163 		gsl.gsl_master_en = 0;
164 	}
165 
166 	/* at this point we want to program whether it's to enable or disable */
167 	if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
168 		pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
169 		pipe_ctx->stream_res.tg->funcs->set_gsl(
170 			pipe_ctx->stream_res.tg,
171 			&gsl);
172 
173 		pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
174 			pipe_ctx->stream_res.tg, group_idx,	enable ? 4 : 0);
175 	} else
176 		BREAK_TO_DEBUGGER();
177 }
178 
dcn20_set_flip_control_gsl(struct pipe_ctx * pipe_ctx,bool flip_immediate)179 void dcn20_set_flip_control_gsl(
180 		struct pipe_ctx *pipe_ctx,
181 		bool flip_immediate)
182 {
183 	if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
184 		pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
185 				pipe_ctx->plane_res.hubp, flip_immediate);
186 
187 }
188 
dcn20_enable_power_gating_plane(struct dce_hwseq * hws,bool enable)189 void dcn20_enable_power_gating_plane(
190 	struct dce_hwseq *hws,
191 	bool enable)
192 {
193 	bool force_on = true; /* disable power gating */
194 
195 	if (enable)
196 		force_on = false;
197 
198 	/* DCHUBP0/1/2/3/4/5 */
199 	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
200 	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
201 	REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
202 	REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
203 	if (REG(DOMAIN8_PG_CONFIG))
204 		REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
205 	if (REG(DOMAIN10_PG_CONFIG))
206 		REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
207 
208 	/* DPP0/1/2/3/4/5 */
209 	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
210 	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
211 	REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
212 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
213 	if (REG(DOMAIN9_PG_CONFIG))
214 		REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
215 	if (REG(DOMAIN11_PG_CONFIG))
216 		REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
217 
218 	/* DCS0/1/2/3/4/5 */
219 	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
220 	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
221 	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
222 	if (REG(DOMAIN19_PG_CONFIG))
223 		REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
224 	if (REG(DOMAIN20_PG_CONFIG))
225 		REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
226 	if (REG(DOMAIN21_PG_CONFIG))
227 		REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
228 }
229 
dcn20_dccg_init(struct dce_hwseq * hws)230 void dcn20_dccg_init(struct dce_hwseq *hws)
231 {
232 	/*
233 	 * set MICROSECOND_TIME_BASE_DIV
234 	 * 100Mhz refclk -> 0x120264
235 	 * 27Mhz refclk -> 0x12021b
236 	 * 48Mhz refclk -> 0x120230
237 	 *
238 	 */
239 	REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
240 
241 	/*
242 	 * set MILLISECOND_TIME_BASE_DIV
243 	 * 100Mhz refclk -> 0x1186a0
244 	 * 27Mhz refclk -> 0x106978
245 	 * 48Mhz refclk -> 0x10bb80
246 	 *
247 	 */
248 	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
249 
250 	/* This value is dependent on the hardware pipeline delay so set once per SOC */
251 	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
252 }
253 
dcn20_disable_vga(struct dce_hwseq * hws)254 void dcn20_disable_vga(
255 	struct dce_hwseq *hws)
256 {
257 	REG_WRITE(D1VGA_CONTROL, 0);
258 	REG_WRITE(D2VGA_CONTROL, 0);
259 	REG_WRITE(D3VGA_CONTROL, 0);
260 	REG_WRITE(D4VGA_CONTROL, 0);
261 	REG_WRITE(D5VGA_CONTROL, 0);
262 	REG_WRITE(D6VGA_CONTROL, 0);
263 }
264 
dcn20_program_triple_buffer(const struct dc * dc,struct pipe_ctx * pipe_ctx,bool enable_triple_buffer)265 void dcn20_program_triple_buffer(
266 	const struct dc *dc,
267 	struct pipe_ctx *pipe_ctx,
268 	bool enable_triple_buffer)
269 {
270 	if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
271 		pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
272 			pipe_ctx->plane_res.hubp,
273 			enable_triple_buffer);
274 	}
275 }
276 
277 /* Blank pixel data during initialization */
dcn20_init_blank(struct dc * dc,struct timing_generator * tg)278 void dcn20_init_blank(
279 		struct dc *dc,
280 		struct timing_generator *tg)
281 {
282 	struct dce_hwseq *hws = dc->hwseq;
283 	enum dc_color_space color_space;
284 	struct tg_color black_color = {0};
285 	struct output_pixel_processor *opp = NULL;
286 	struct output_pixel_processor *bottom_opp = NULL;
287 	uint32_t num_opps, opp_id_src0, opp_id_src1;
288 	uint32_t otg_active_width, otg_active_height;
289 
290 	/* program opp dpg blank color */
291 	color_space = COLOR_SPACE_SRGB;
292 	color_space_to_black_color(dc, color_space, &black_color);
293 
294 	/* get the OTG active size */
295 	tg->funcs->get_otg_active_size(tg,
296 			&otg_active_width,
297 			&otg_active_height);
298 
299 	/* get the OPTC source */
300 	tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
301 
302 	if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
303 		ASSERT(false);
304 		return;
305 	}
306 	opp = dc->res_pool->opps[opp_id_src0];
307 
308 	if (num_opps == 2) {
309 		otg_active_width = otg_active_width / 2;
310 
311 		if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
312 			ASSERT(false);
313 			return;
314 		}
315 		bottom_opp = dc->res_pool->opps[opp_id_src1];
316 	}
317 
318 	opp->funcs->opp_set_disp_pattern_generator(
319 			opp,
320 			CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
321 			CONTROLLER_DP_COLOR_SPACE_UDEFINED,
322 			COLOR_DEPTH_UNDEFINED,
323 			&black_color,
324 			otg_active_width,
325 			otg_active_height,
326 			0);
327 
328 	if (num_opps == 2) {
329 		bottom_opp->funcs->opp_set_disp_pattern_generator(
330 				bottom_opp,
331 				CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
332 				CONTROLLER_DP_COLOR_SPACE_UDEFINED,
333 				COLOR_DEPTH_UNDEFINED,
334 				&black_color,
335 				otg_active_width,
336 				otg_active_height,
337 				0);
338 	}
339 
340 	hws->funcs.wait_for_blank_complete(opp);
341 }
342 
dcn20_dsc_pg_control(struct dce_hwseq * hws,unsigned int dsc_inst,bool power_on)343 void dcn20_dsc_pg_control(
344 		struct dce_hwseq *hws,
345 		unsigned int dsc_inst,
346 		bool power_on)
347 {
348 	uint32_t power_gate = power_on ? 0 : 1;
349 	uint32_t pwr_status = power_on ? 0 : 2;
350 	uint32_t org_ip_request_cntl = 0;
351 
352 	if (hws->ctx->dc->debug.disable_dsc_power_gate)
353 		return;
354 
355 	if (REG(DOMAIN16_PG_CONFIG) == 0)
356 		return;
357 
358 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
359 	if (org_ip_request_cntl == 0)
360 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
361 
362 	switch (dsc_inst) {
363 	case 0: /* DSC0 */
364 		REG_UPDATE(DOMAIN16_PG_CONFIG,
365 				DOMAIN16_POWER_GATE, power_gate);
366 
367 		REG_WAIT(DOMAIN16_PG_STATUS,
368 				DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
369 				1, 1000);
370 		break;
371 	case 1: /* DSC1 */
372 		REG_UPDATE(DOMAIN17_PG_CONFIG,
373 				DOMAIN17_POWER_GATE, power_gate);
374 
375 		REG_WAIT(DOMAIN17_PG_STATUS,
376 				DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
377 				1, 1000);
378 		break;
379 	case 2: /* DSC2 */
380 		REG_UPDATE(DOMAIN18_PG_CONFIG,
381 				DOMAIN18_POWER_GATE, power_gate);
382 
383 		REG_WAIT(DOMAIN18_PG_STATUS,
384 				DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
385 				1, 1000);
386 		break;
387 	case 3: /* DSC3 */
388 		REG_UPDATE(DOMAIN19_PG_CONFIG,
389 				DOMAIN19_POWER_GATE, power_gate);
390 
391 		REG_WAIT(DOMAIN19_PG_STATUS,
392 				DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
393 				1, 1000);
394 		break;
395 	case 4: /* DSC4 */
396 		REG_UPDATE(DOMAIN20_PG_CONFIG,
397 				DOMAIN20_POWER_GATE, power_gate);
398 
399 		REG_WAIT(DOMAIN20_PG_STATUS,
400 				DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
401 				1, 1000);
402 		break;
403 	case 5: /* DSC5 */
404 		REG_UPDATE(DOMAIN21_PG_CONFIG,
405 				DOMAIN21_POWER_GATE, power_gate);
406 
407 		REG_WAIT(DOMAIN21_PG_STATUS,
408 				DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
409 				1, 1000);
410 		break;
411 	default:
412 		BREAK_TO_DEBUGGER();
413 		break;
414 	}
415 
416 	if (org_ip_request_cntl == 0)
417 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
418 }
419 
dcn20_dpp_pg_control(struct dce_hwseq * hws,unsigned int dpp_inst,bool power_on)420 void dcn20_dpp_pg_control(
421 		struct dce_hwseq *hws,
422 		unsigned int dpp_inst,
423 		bool power_on)
424 {
425 	uint32_t power_gate = power_on ? 0 : 1;
426 	uint32_t pwr_status = power_on ? 0 : 2;
427 
428 	if (hws->ctx->dc->debug.disable_dpp_power_gate)
429 		return;
430 	if (REG(DOMAIN1_PG_CONFIG) == 0)
431 		return;
432 
433 	switch (dpp_inst) {
434 	case 0: /* DPP0 */
435 		REG_UPDATE(DOMAIN1_PG_CONFIG,
436 				DOMAIN1_POWER_GATE, power_gate);
437 
438 		REG_WAIT(DOMAIN1_PG_STATUS,
439 				DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
440 				1, 1000);
441 		break;
442 	case 1: /* DPP1 */
443 		REG_UPDATE(DOMAIN3_PG_CONFIG,
444 				DOMAIN3_POWER_GATE, power_gate);
445 
446 		REG_WAIT(DOMAIN3_PG_STATUS,
447 				DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
448 				1, 1000);
449 		break;
450 	case 2: /* DPP2 */
451 		REG_UPDATE(DOMAIN5_PG_CONFIG,
452 				DOMAIN5_POWER_GATE, power_gate);
453 
454 		REG_WAIT(DOMAIN5_PG_STATUS,
455 				DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
456 				1, 1000);
457 		break;
458 	case 3: /* DPP3 */
459 		REG_UPDATE(DOMAIN7_PG_CONFIG,
460 				DOMAIN7_POWER_GATE, power_gate);
461 
462 		REG_WAIT(DOMAIN7_PG_STATUS,
463 				DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
464 				1, 1000);
465 		break;
466 	case 4: /* DPP4 */
467 		REG_UPDATE(DOMAIN9_PG_CONFIG,
468 				DOMAIN9_POWER_GATE, power_gate);
469 
470 		REG_WAIT(DOMAIN9_PG_STATUS,
471 				DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
472 				1, 1000);
473 		break;
474 	case 5: /* DPP5 */
475 		/*
476 		 * Do not power gate DPP5, should be left at HW default, power on permanently.
477 		 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
478 		 * reset.
479 		 * REG_UPDATE(DOMAIN11_PG_CONFIG,
480 		 *		DOMAIN11_POWER_GATE, power_gate);
481 		 *
482 		 * REG_WAIT(DOMAIN11_PG_STATUS,
483 		 *		DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
484 		 * 		1, 1000);
485 		 */
486 		break;
487 	default:
488 		BREAK_TO_DEBUGGER();
489 		break;
490 	}
491 }
492 
493 
dcn20_hubp_pg_control(struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)494 void dcn20_hubp_pg_control(
495 		struct dce_hwseq *hws,
496 		unsigned int hubp_inst,
497 		bool power_on)
498 {
499 	uint32_t power_gate = power_on ? 0 : 1;
500 	uint32_t pwr_status = power_on ? 0 : 2;
501 
502 	if (hws->ctx->dc->debug.disable_hubp_power_gate)
503 		return;
504 	if (REG(DOMAIN0_PG_CONFIG) == 0)
505 		return;
506 
507 	switch (hubp_inst) {
508 	case 0: /* DCHUBP0 */
509 		REG_UPDATE(DOMAIN0_PG_CONFIG,
510 				DOMAIN0_POWER_GATE, power_gate);
511 
512 		REG_WAIT(DOMAIN0_PG_STATUS,
513 				DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
514 				1, 1000);
515 		break;
516 	case 1: /* DCHUBP1 */
517 		REG_UPDATE(DOMAIN2_PG_CONFIG,
518 				DOMAIN2_POWER_GATE, power_gate);
519 
520 		REG_WAIT(DOMAIN2_PG_STATUS,
521 				DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
522 				1, 1000);
523 		break;
524 	case 2: /* DCHUBP2 */
525 		REG_UPDATE(DOMAIN4_PG_CONFIG,
526 				DOMAIN4_POWER_GATE, power_gate);
527 
528 		REG_WAIT(DOMAIN4_PG_STATUS,
529 				DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
530 				1, 1000);
531 		break;
532 	case 3: /* DCHUBP3 */
533 		REG_UPDATE(DOMAIN6_PG_CONFIG,
534 				DOMAIN6_POWER_GATE, power_gate);
535 
536 		REG_WAIT(DOMAIN6_PG_STATUS,
537 				DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
538 				1, 1000);
539 		break;
540 	case 4: /* DCHUBP4 */
541 		REG_UPDATE(DOMAIN8_PG_CONFIG,
542 				DOMAIN8_POWER_GATE, power_gate);
543 
544 		REG_WAIT(DOMAIN8_PG_STATUS,
545 				DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
546 				1, 1000);
547 		break;
548 	case 5: /* DCHUBP5 */
549 		/*
550 		 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
551 		 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
552 		 * reset.
553 		 * REG_UPDATE(DOMAIN10_PG_CONFIG,
554 		 *		DOMAIN10_POWER_GATE, power_gate);
555 		 *
556 		 * REG_WAIT(DOMAIN10_PG_STATUS,
557 		 *		DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
558 		 *		1, 1000);
559 		 */
560 		break;
561 	default:
562 		BREAK_TO_DEBUGGER();
563 		break;
564 	}
565 }
566 
567 
568 /* disable HW used by plane.
569  * note:  cannot disable until disconnect is complete
570  */
dcn20_plane_atomic_disable(struct dc * dc,struct pipe_ctx * pipe_ctx)571 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
572 {
573 	struct dce_hwseq *hws = dc->hwseq;
574 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
575 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
576 
577 	dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
578 
579 	/* In flip immediate with pipe splitting case GSL is used for
580 	 * synchronization so we must disable it when the plane is disabled.
581 	 */
582 	if (pipe_ctx->stream_res.gsl_group != 0)
583 		dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
584 
585 	dc->hwss.set_flip_control_gsl(pipe_ctx, false);
586 
587 	hubp->funcs->hubp_clk_cntl(hubp, false);
588 
589 	dpp->funcs->dpp_dppclk_control(dpp, false, false);
590 
591 	hubp->power_gated = true;
592 
593 	hws->funcs.plane_atomic_power_down(dc,
594 			pipe_ctx->plane_res.dpp,
595 			pipe_ctx->plane_res.hubp);
596 
597 	pipe_ctx->stream = NULL;
598 	memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
599 	memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
600 	pipe_ctx->top_pipe = NULL;
601 	pipe_ctx->bottom_pipe = NULL;
602 	pipe_ctx->plane_state = NULL;
603 }
604 
605 
dcn20_disable_plane(struct dc * dc,struct pipe_ctx * pipe_ctx)606 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
607 {
608 	DC_LOGGER_INIT(dc->ctx->logger);
609 
610 	if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
611 		return;
612 
613 	dcn20_plane_atomic_disable(dc, pipe_ctx);
614 
615 	DC_LOG_DC("Power down front end %d\n",
616 					pipe_ctx->pipe_idx);
617 }
618 
dcn20_disable_pixel_data(struct dc * dc,struct pipe_ctx * pipe_ctx,bool blank)619 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
620 {
621 	dcn20_blank_pixel_data(dc, pipe_ctx, blank);
622 }
623 
calc_mpc_flow_ctrl_cnt(const struct dc_stream_state * stream,int opp_cnt)624 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
625 		int opp_cnt)
626 {
627 	bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
628 	int flow_ctrl_cnt;
629 
630 	if (opp_cnt >= 2)
631 		hblank_halved = true;
632 
633 	flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
634 			stream->timing.h_border_left -
635 			stream->timing.h_border_right;
636 
637 	if (hblank_halved)
638 		flow_ctrl_cnt /= 2;
639 
640 	/* ODM combine 4:1 case */
641 	if (opp_cnt == 4)
642 		flow_ctrl_cnt /= 2;
643 
644 	return flow_ctrl_cnt;
645 }
646 
dcn20_enable_stream_timing(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc)647 enum dc_status dcn20_enable_stream_timing(
648 		struct pipe_ctx *pipe_ctx,
649 		struct dc_state *context,
650 		struct dc *dc)
651 {
652 	struct dce_hwseq *hws = dc->hwseq;
653 	struct dc_stream_state *stream = pipe_ctx->stream;
654 	struct drr_params params = {0};
655 	unsigned int event_triggers = 0;
656 	struct pipe_ctx *odm_pipe;
657 	int opp_cnt = 1;
658 	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
659 	bool interlace = stream->timing.flags.INTERLACE;
660 	int i;
661 	struct mpc_dwb_flow_control flow_control;
662 	struct mpc *mpc = dc->res_pool->mpc;
663 	bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
664 	unsigned int k1_div = PIXEL_RATE_DIV_NA;
665 	unsigned int k2_div = PIXEL_RATE_DIV_NA;
666 
667 	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
668 		hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
669 
670 		dc->res_pool->dccg->funcs->set_pixel_rate_div(
671 			dc->res_pool->dccg,
672 			pipe_ctx->stream_res.tg->inst,
673 			k1_div, k2_div);
674 	}
675 	/* by upper caller loop, pipe0 is parent pipe and be called first.
676 	 * back end is set up by for pipe0. Other children pipe share back end
677 	 * with pipe 0. No program is needed.
678 	 */
679 	if (pipe_ctx->top_pipe != NULL)
680 		return DC_OK;
681 
682 	/* TODO check if timing_changed, disable stream if timing changed */
683 
684 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
685 		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
686 		opp_cnt++;
687 	}
688 
689 	if (opp_cnt > 1)
690 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
691 				pipe_ctx->stream_res.tg,
692 				opp_inst, opp_cnt,
693 				&pipe_ctx->stream->timing);
694 
695 	/* HW program guide assume display already disable
696 	 * by unplug sequence. OTG assume stop.
697 	 */
698 	pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
699 
700 	if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
701 			pipe_ctx->clock_source,
702 			&pipe_ctx->stream_res.pix_clk_params,
703 			dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings),
704 			&pipe_ctx->pll_settings)) {
705 		BREAK_TO_DEBUGGER();
706 		return DC_ERROR_UNEXPECTED;
707 	}
708 
709 	if (dc_is_hdmi_tmds_signal(stream->signal)) {
710 		stream->link->phy_state.symclk_ref_cnts.otg = 1;
711 		if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
712 			stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
713 		else
714 			stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
715 	}
716 
717 	if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
718 		dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
719 
720 	pipe_ctx->stream_res.tg->funcs->program_timing(
721 			pipe_ctx->stream_res.tg,
722 			&stream->timing,
723 			pipe_ctx->pipe_dlg_param.vready_offset,
724 			pipe_ctx->pipe_dlg_param.vstartup_start,
725 			pipe_ctx->pipe_dlg_param.vupdate_offset,
726 			pipe_ctx->pipe_dlg_param.vupdate_width,
727 			pipe_ctx->stream->signal,
728 			true);
729 
730 	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
731 	flow_control.flow_ctrl_mode = 0;
732 	flow_control.flow_ctrl_cnt0 = 0x80;
733 	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
734 	if (mpc->funcs->set_out_rate_control) {
735 		for (i = 0; i < opp_cnt; ++i) {
736 			mpc->funcs->set_out_rate_control(
737 					mpc, opp_inst[i],
738 					true,
739 					rate_control_2x_pclk,
740 					&flow_control);
741 		}
742 	}
743 
744 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
745 		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
746 				odm_pipe->stream_res.opp,
747 				true);
748 
749 	pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
750 			pipe_ctx->stream_res.opp,
751 			true);
752 
753 	hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
754 
755 	/* VTG is  within DCHUB command block. DCFCLK is always on */
756 	if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
757 		BREAK_TO_DEBUGGER();
758 		return DC_ERROR_UNEXPECTED;
759 	}
760 
761 	hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
762 
763 	params.vertical_total_min = stream->adjust.v_total_min;
764 	params.vertical_total_max = stream->adjust.v_total_max;
765 	params.vertical_total_mid = stream->adjust.v_total_mid;
766 	params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
767 	if (pipe_ctx->stream_res.tg->funcs->set_drr)
768 		pipe_ctx->stream_res.tg->funcs->set_drr(
769 			pipe_ctx->stream_res.tg, &params);
770 
771 	// DRR should set trigger event to monitor surface update event
772 	if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
773 		event_triggers = 0x80;
774 	/* Event triggers and num frames initialized for DRR, but can be
775 	 * later updated for PSR use. Note DRR trigger events are generated
776 	 * regardless of whether num frames met.
777 	 */
778 	if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
779 		pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
780 				pipe_ctx->stream_res.tg, event_triggers, 2);
781 
782 	/* TODO program crtc source select for non-virtual signal*/
783 	/* TODO program FMT */
784 	/* TODO setup link_enc */
785 	/* TODO set stream attributes */
786 	/* TODO program audio */
787 	/* TODO enable stream if timing changed */
788 	/* TODO unblank stream if DP */
789 
790 	if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
791 		if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
792 			pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
793 	}
794 	return DC_OK;
795 }
796 
dcn20_program_output_csc(struct dc * dc,struct pipe_ctx * pipe_ctx,enum dc_color_space colorspace,uint16_t * matrix,int opp_id)797 void dcn20_program_output_csc(struct dc *dc,
798 		struct pipe_ctx *pipe_ctx,
799 		enum dc_color_space colorspace,
800 		uint16_t *matrix,
801 		int opp_id)
802 {
803 	struct mpc *mpc = dc->res_pool->mpc;
804 	enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
805 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
806 
807 	if (mpc->funcs->power_on_mpc_mem_pwr)
808 		mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
809 
810 	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
811 		if (mpc->funcs->set_output_csc != NULL)
812 			mpc->funcs->set_output_csc(mpc,
813 					opp_id,
814 					matrix,
815 					ocsc_mode);
816 	} else {
817 		if (mpc->funcs->set_ocsc_default != NULL)
818 			mpc->funcs->set_ocsc_default(mpc,
819 					opp_id,
820 					colorspace,
821 					ocsc_mode);
822 	}
823 }
824 
dcn20_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)825 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
826 				const struct dc_stream_state *stream)
827 {
828 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
829 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
830 	struct pwl_params *params = NULL;
831 	/*
832 	 * program OGAM only for the top pipe
833 	 * if there is a pipe split then fix diagnostic is required:
834 	 * how to pass OGAM parameter for stream.
835 	 * if programming for all pipes is required then remove condition
836 	 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
837 	 */
838 	if (mpc->funcs->power_on_mpc_mem_pwr)
839 		mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
840 	if (pipe_ctx->top_pipe == NULL
841 			&& mpc->funcs->set_output_gamma && stream->out_transfer_func) {
842 		if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
843 			params = &stream->out_transfer_func->pwl;
844 		else if (pipe_ctx->stream->out_transfer_func->type ==
845 			TF_TYPE_DISTRIBUTED_POINTS &&
846 			cm_helper_translate_curve_to_hw_format(
847 			stream->out_transfer_func,
848 			&mpc->blender_params, false))
849 			params = &mpc->blender_params;
850 		/*
851 		 * there is no ROM
852 		 */
853 		if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
854 			BREAK_TO_DEBUGGER();
855 	}
856 	/*
857 	 * if above if is not executed then 'params' equal to 0 and set in bypass
858 	 */
859 	mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
860 
861 	return true;
862 }
863 
dcn20_set_blend_lut(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)864 bool dcn20_set_blend_lut(
865 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
866 {
867 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
868 	bool result = true;
869 	struct pwl_params *blend_lut = NULL;
870 
871 	if (plane_state->blend_tf) {
872 		if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
873 			blend_lut = &plane_state->blend_tf->pwl;
874 		else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
875 			cm_helper_translate_curve_to_hw_format(
876 					plane_state->blend_tf,
877 					&dpp_base->regamma_params, false);
878 			blend_lut = &dpp_base->regamma_params;
879 		}
880 	}
881 	result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
882 
883 	return result;
884 }
885 
dcn20_set_shaper_3dlut(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)886 bool dcn20_set_shaper_3dlut(
887 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
888 {
889 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
890 	bool result = true;
891 	struct pwl_params *shaper_lut = NULL;
892 
893 	if (plane_state->in_shaper_func) {
894 		if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
895 			shaper_lut = &plane_state->in_shaper_func->pwl;
896 		else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
897 			cm_helper_translate_curve_to_hw_format(
898 					plane_state->in_shaper_func,
899 					&dpp_base->shaper_params, true);
900 			shaper_lut = &dpp_base->shaper_params;
901 		}
902 	}
903 
904 	result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
905 	if (plane_state->lut3d_func &&
906 		plane_state->lut3d_func->state.bits.initialized == 1)
907 		result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
908 								&plane_state->lut3d_func->lut_3d);
909 	else
910 		result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
911 
912 	return result;
913 }
914 
dcn20_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)915 bool dcn20_set_input_transfer_func(struct dc *dc,
916 				struct pipe_ctx *pipe_ctx,
917 				const struct dc_plane_state *plane_state)
918 {
919 	struct dce_hwseq *hws = dc->hwseq;
920 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
921 	const struct dc_transfer_func *tf = NULL;
922 	bool result = true;
923 	bool use_degamma_ram = false;
924 
925 	if (dpp_base == NULL || plane_state == NULL)
926 		return false;
927 
928 	hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
929 	hws->funcs.set_blend_lut(pipe_ctx, plane_state);
930 
931 	if (plane_state->in_transfer_func)
932 		tf = plane_state->in_transfer_func;
933 
934 
935 	if (tf == NULL) {
936 		dpp_base->funcs->dpp_set_degamma(dpp_base,
937 				IPP_DEGAMMA_MODE_BYPASS);
938 		return true;
939 	}
940 
941 	if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
942 		use_degamma_ram = true;
943 
944 	if (use_degamma_ram == true) {
945 		if (tf->type == TF_TYPE_HWPWL)
946 			dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
947 					&tf->pwl);
948 		else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
949 			cm_helper_translate_curve_to_degamma_hw_format(tf,
950 					&dpp_base->degamma_params);
951 			dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
952 				&dpp_base->degamma_params);
953 		}
954 		return true;
955 	}
956 	/* handle here the optimized cases when de-gamma ROM could be used.
957 	 *
958 	 */
959 	if (tf->type == TF_TYPE_PREDEFINED) {
960 		switch (tf->tf) {
961 		case TRANSFER_FUNCTION_SRGB:
962 			dpp_base->funcs->dpp_set_degamma(dpp_base,
963 					IPP_DEGAMMA_MODE_HW_sRGB);
964 			break;
965 		case TRANSFER_FUNCTION_BT709:
966 			dpp_base->funcs->dpp_set_degamma(dpp_base,
967 					IPP_DEGAMMA_MODE_HW_xvYCC);
968 			break;
969 		case TRANSFER_FUNCTION_LINEAR:
970 			dpp_base->funcs->dpp_set_degamma(dpp_base,
971 					IPP_DEGAMMA_MODE_BYPASS);
972 			break;
973 		case TRANSFER_FUNCTION_PQ:
974 			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
975 			cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
976 			dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
977 			result = true;
978 			break;
979 		default:
980 			result = false;
981 			break;
982 		}
983 	} else if (tf->type == TF_TYPE_BYPASS)
984 		dpp_base->funcs->dpp_set_degamma(dpp_base,
985 				IPP_DEGAMMA_MODE_BYPASS);
986 	else {
987 		/*
988 		 * if we are here, we did not handle correctly.
989 		 * fix is required for this use case
990 		 */
991 		BREAK_TO_DEBUGGER();
992 		dpp_base->funcs->dpp_set_degamma(dpp_base,
993 				IPP_DEGAMMA_MODE_BYPASS);
994 	}
995 
996 	return result;
997 }
998 
dcn20_update_odm(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)999 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1000 {
1001 	struct pipe_ctx *odm_pipe;
1002 	int opp_cnt = 1;
1003 	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
1004 
1005 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1006 		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
1007 		opp_cnt++;
1008 	}
1009 
1010 	if (opp_cnt > 1)
1011 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1012 				pipe_ctx->stream_res.tg,
1013 				opp_inst, opp_cnt,
1014 				&pipe_ctx->stream->timing);
1015 	else
1016 		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1017 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1018 }
1019 
dcn20_blank_pixel_data(struct dc * dc,struct pipe_ctx * pipe_ctx,bool blank)1020 void dcn20_blank_pixel_data(
1021 		struct dc *dc,
1022 		struct pipe_ctx *pipe_ctx,
1023 		bool blank)
1024 {
1025 	struct tg_color black_color = {0};
1026 	struct stream_resource *stream_res = &pipe_ctx->stream_res;
1027 	struct dc_stream_state *stream = pipe_ctx->stream;
1028 	enum dc_color_space color_space = stream->output_color_space;
1029 	enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
1030 	enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1031 	struct pipe_ctx *odm_pipe;
1032 	int odm_cnt = 1;
1033 
1034 	int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1035 	int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1036 
1037 	if (stream->link->test_pattern_enabled)
1038 		return;
1039 
1040 	/* get opp dpg blank color */
1041 	color_space_to_black_color(dc, color_space, &black_color);
1042 
1043 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1044 		odm_cnt++;
1045 
1046 	width = width / odm_cnt;
1047 
1048 	if (blank) {
1049 		dc->hwss.set_abm_immediate_disable(pipe_ctx);
1050 
1051 		if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
1052 			test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1053 			test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1054 		}
1055 	} else {
1056 		test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1057 	}
1058 
1059 	dc->hwss.set_disp_pattern_generator(dc,
1060 			pipe_ctx,
1061 			test_pattern,
1062 			test_pattern_color_space,
1063 			stream->timing.display_color_depth,
1064 			&black_color,
1065 			width,
1066 			height,
1067 			0);
1068 
1069 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1070 		dc->hwss.set_disp_pattern_generator(dc,
1071 				odm_pipe,
1072 				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
1073 						CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
1074 				test_pattern_color_space,
1075 				stream->timing.display_color_depth,
1076 				&black_color,
1077 				width,
1078 				height,
1079 				0);
1080 	}
1081 
1082 	if (!blank)
1083 		if (stream_res->abm) {
1084 			dc->hwss.set_pipe(pipe_ctx);
1085 			stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1086 		}
1087 }
1088 
1089 
dcn20_power_on_plane(struct dce_hwseq * hws,struct pipe_ctx * pipe_ctx)1090 static void dcn20_power_on_plane(
1091 	struct dce_hwseq *hws,
1092 	struct pipe_ctx *pipe_ctx)
1093 {
1094 	DC_LOGGER_INIT(hws->ctx->logger);
1095 	if (REG(DC_IP_REQUEST_CNTL)) {
1096 		REG_SET(DC_IP_REQUEST_CNTL, 0,
1097 				IP_REQUEST_EN, 1);
1098 
1099 		if (hws->funcs.dpp_pg_control)
1100 			hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1101 
1102 		if (hws->funcs.hubp_pg_control)
1103 			hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1104 
1105 		REG_SET(DC_IP_REQUEST_CNTL, 0,
1106 				IP_REQUEST_EN, 0);
1107 		DC_LOG_DEBUG(
1108 				"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1109 	}
1110 }
1111 
dcn20_enable_plane(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)1112 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1113 			       struct dc_state *context)
1114 {
1115 	//if (dc->debug.sanity_checks) {
1116 	//	dcn10_verify_allow_pstate_change_high(dc);
1117 	//}
1118 	dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1119 
1120 	/* enable DCFCLK current DCHUB */
1121 	pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1122 
1123 	/* initialize HUBP on power up */
1124 	pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1125 
1126 	/* make sure OPP_PIPE_CLOCK_EN = 1 */
1127 	pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1128 			pipe_ctx->stream_res.opp,
1129 			true);
1130 
1131 /* TODO: enable/disable in dm as per update type.
1132 	if (plane_state) {
1133 		DC_LOG_DC(dc->ctx->logger,
1134 				"Pipe:%d 0x%x: addr hi:0x%x, "
1135 				"addr low:0x%x, "
1136 				"src: %d, %d, %d,"
1137 				" %d; dst: %d, %d, %d, %d;\n",
1138 				pipe_ctx->pipe_idx,
1139 				plane_state,
1140 				plane_state->address.grph.addr.high_part,
1141 				plane_state->address.grph.addr.low_part,
1142 				plane_state->src_rect.x,
1143 				plane_state->src_rect.y,
1144 				plane_state->src_rect.width,
1145 				plane_state->src_rect.height,
1146 				plane_state->dst_rect.x,
1147 				plane_state->dst_rect.y,
1148 				plane_state->dst_rect.width,
1149 				plane_state->dst_rect.height);
1150 
1151 		DC_LOG_DC(dc->ctx->logger,
1152 				"Pipe %d: width, height, x, y         format:%d\n"
1153 				"viewport:%d, %d, %d, %d\n"
1154 				"recout:  %d, %d, %d, %d\n",
1155 				pipe_ctx->pipe_idx,
1156 				plane_state->format,
1157 				pipe_ctx->plane_res.scl_data.viewport.width,
1158 				pipe_ctx->plane_res.scl_data.viewport.height,
1159 				pipe_ctx->plane_res.scl_data.viewport.x,
1160 				pipe_ctx->plane_res.scl_data.viewport.y,
1161 				pipe_ctx->plane_res.scl_data.recout.width,
1162 				pipe_ctx->plane_res.scl_data.recout.height,
1163 				pipe_ctx->plane_res.scl_data.recout.x,
1164 				pipe_ctx->plane_res.scl_data.recout.y);
1165 		print_rq_dlg_ttu(dc, pipe_ctx);
1166 	}
1167 */
1168 	if (dc->vm_pa_config.valid) {
1169 		struct vm_system_aperture_param apt;
1170 
1171 		apt.sys_default.quad_part = 0;
1172 
1173 		apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1174 		apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1175 
1176 		// Program system aperture settings
1177 		pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1178 	}
1179 
1180 	if (!pipe_ctx->top_pipe
1181 		&& pipe_ctx->plane_state
1182 		&& pipe_ctx->plane_state->flip_int_enabled
1183 		&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1184 			pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1185 
1186 //	if (dc->debug.sanity_checks) {
1187 //		dcn10_verify_allow_pstate_change_high(dc);
1188 //	}
1189 }
1190 
dcn20_pipe_control_lock(struct dc * dc,struct pipe_ctx * pipe,bool lock)1191 void dcn20_pipe_control_lock(
1192 	struct dc *dc,
1193 	struct pipe_ctx *pipe,
1194 	bool lock)
1195 {
1196 	struct pipe_ctx *temp_pipe;
1197 	bool flip_immediate = false;
1198 
1199 	/* use TG master update lock to lock everything on the TG
1200 	 * therefore only top pipe need to lock
1201 	 */
1202 	if (!pipe || pipe->top_pipe)
1203 		return;
1204 
1205 	if (pipe->plane_state != NULL)
1206 		flip_immediate = pipe->plane_state->flip_immediate;
1207 
1208 	if  (pipe->stream_res.gsl_group > 0) {
1209 	    temp_pipe = pipe->bottom_pipe;
1210 	    while (!flip_immediate && temp_pipe) {
1211 		    if (temp_pipe->plane_state != NULL)
1212 			    flip_immediate = temp_pipe->plane_state->flip_immediate;
1213 		    temp_pipe = temp_pipe->bottom_pipe;
1214 	    }
1215 	}
1216 
1217 	if (flip_immediate && lock) {
1218 		const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1219 		int i;
1220 
1221 		temp_pipe = pipe;
1222 		while (temp_pipe) {
1223 			if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1224 				for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1225 					if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1226 						break;
1227 					udelay(1);
1228 				}
1229 
1230 				/* no reason it should take this long for immediate flips */
1231 				ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
1232 			}
1233 			temp_pipe = temp_pipe->bottom_pipe;
1234 		}
1235 	}
1236 
1237 	/* In flip immediate and pipe splitting case, we need to use GSL
1238 	 * for synchronization. Only do setup on locking and on flip type change.
1239 	 */
1240 	if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
1241 		if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1242 		    (!flip_immediate && pipe->stream_res.gsl_group > 0))
1243 			dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1244 
1245 	if (pipe->plane_state != NULL)
1246 		flip_immediate = pipe->plane_state->flip_immediate;
1247 
1248 	temp_pipe = pipe->bottom_pipe;
1249 	while (flip_immediate && temp_pipe) {
1250 	    if (temp_pipe->plane_state != NULL)
1251 		flip_immediate = temp_pipe->plane_state->flip_immediate;
1252 	    temp_pipe = temp_pipe->bottom_pipe;
1253 	}
1254 
1255 	if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1256 		!flip_immediate)
1257 	    dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1258 
1259 	if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1260 		union dmub_hw_lock_flags hw_locks = { 0 };
1261 		struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1262 
1263 		hw_locks.bits.lock_pipe = 1;
1264 		inst_flags.otg_inst =  pipe->stream_res.tg->inst;
1265 
1266 		if (pipe->plane_state != NULL)
1267 			hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1268 
1269 		dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1270 					lock,
1271 					&hw_locks,
1272 					&inst_flags);
1273 	} else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1274 		if (lock)
1275 			pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1276 		else
1277 			pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1278 	} else {
1279 		if (lock)
1280 			pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1281 		else
1282 			pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1283 	}
1284 }
1285 
dcn20_detect_pipe_changes(struct pipe_ctx * old_pipe,struct pipe_ctx * new_pipe)1286 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1287 {
1288 	new_pipe->update_flags.raw = 0;
1289 
1290 	/* Exit on unchanged, unused pipe */
1291 	if (!old_pipe->plane_state && !new_pipe->plane_state)
1292 		return;
1293 	/* Detect pipe enable/disable */
1294 	if (!old_pipe->plane_state && new_pipe->plane_state) {
1295 		new_pipe->update_flags.bits.enable = 1;
1296 		new_pipe->update_flags.bits.mpcc = 1;
1297 		new_pipe->update_flags.bits.dppclk = 1;
1298 		new_pipe->update_flags.bits.hubp_interdependent = 1;
1299 		new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1300 		new_pipe->update_flags.bits.gamut_remap = 1;
1301 		new_pipe->update_flags.bits.scaler = 1;
1302 		new_pipe->update_flags.bits.viewport = 1;
1303 		new_pipe->update_flags.bits.det_size = 1;
1304 		if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1305 			new_pipe->update_flags.bits.odm = 1;
1306 			new_pipe->update_flags.bits.global_sync = 1;
1307 		}
1308 		return;
1309 	}
1310 
1311 	/* For SubVP we need to unconditionally enable because any phantom pipes are
1312 	 * always removed then newly added for every full updates whenever SubVP is in use.
1313 	 * The remove-add sequence of the phantom pipe always results in the pipe
1314 	 * being blanked in enable_stream_timing (DPG).
1315 	 */
1316 	if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1317 		new_pipe->update_flags.bits.enable = 1;
1318 
1319 	/* Phantom pipes are effectively disabled, if the pipe was previously phantom
1320 	 * we have to enable
1321 	 */
1322 	if (old_pipe->plane_state && old_pipe->plane_state->is_phantom &&
1323 			new_pipe->plane_state && !new_pipe->plane_state->is_phantom)
1324 		new_pipe->update_flags.bits.enable = 1;
1325 
1326 	if (old_pipe->plane_state && !new_pipe->plane_state) {
1327 		new_pipe->update_flags.bits.disable = 1;
1328 		return;
1329 	}
1330 
1331 	/* Detect plane change */
1332 	if (old_pipe->plane_state != new_pipe->plane_state) {
1333 		new_pipe->update_flags.bits.plane_changed = true;
1334 	}
1335 
1336 	/* Detect top pipe only changes */
1337 	if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1338 		/* Detect odm changes */
1339 		if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1340 			&& old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1341 				|| (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1342 				|| (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1343 				|| old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1344 			new_pipe->update_flags.bits.odm = 1;
1345 
1346 		/* Detect global sync changes */
1347 		if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1348 				|| old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1349 				|| old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1350 				|| old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1351 			new_pipe->update_flags.bits.global_sync = 1;
1352 	}
1353 
1354 	if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
1355 		new_pipe->update_flags.bits.det_size = 1;
1356 
1357 	/*
1358 	 * Detect opp / tg change, only set on change, not on enable
1359 	 * Assume mpcc inst = pipe index, if not this code needs to be updated
1360 	 * since mpcc is what is affected by these. In fact all of our sequence
1361 	 * makes this assumption at the moment with how hubp reset is matched to
1362 	 * same index mpcc reset.
1363 	 */
1364 	if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1365 		new_pipe->update_flags.bits.opp_changed = 1;
1366 	if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1367 		new_pipe->update_flags.bits.tg_changed = 1;
1368 
1369 	/*
1370 	 * Detect mpcc blending changes, only dpp inst and opp matter here,
1371 	 * mpccs getting removed/inserted update connected ones during their own
1372 	 * programming
1373 	 */
1374 	if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1375 			|| old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1376 		new_pipe->update_flags.bits.mpcc = 1;
1377 
1378 	/* Detect dppclk change */
1379 	if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1380 		new_pipe->update_flags.bits.dppclk = 1;
1381 
1382 	/* Check for scl update */
1383 	if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1384 			new_pipe->update_flags.bits.scaler = 1;
1385 	/* Check for vp update */
1386 	if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1387 			|| memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1388 				&new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1389 		new_pipe->update_flags.bits.viewport = 1;
1390 
1391 	/* Detect dlg/ttu/rq updates */
1392 	{
1393 		struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1394 		struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1395 		struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1396 		struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1397 
1398 		/* Detect pipe interdependent updates */
1399 		if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1400 				old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1401 				old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1402 				old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1403 				old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1404 				old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1405 				old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1406 				old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1407 				old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1408 				old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1409 				old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1410 				old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1411 				old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1412 				old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1413 				old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1414 				old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1415 				old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1416 				old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1417 			old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1418 			old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1419 			old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1420 			old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1421 			old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1422 			old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1423 			old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1424 			old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1425 			old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1426 			old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1427 			old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1428 			old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1429 			old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1430 			old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1431 			old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1432 			old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1433 			old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1434 			old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1435 			new_pipe->update_flags.bits.hubp_interdependent = 1;
1436 		}
1437 		/* Detect any other updates to ttu/rq/dlg */
1438 		if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1439 				memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1440 				memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1441 			new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1442 	}
1443 }
1444 
dcn20_update_dchubp_dpp(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)1445 static void dcn20_update_dchubp_dpp(
1446 	struct dc *dc,
1447 	struct pipe_ctx *pipe_ctx,
1448 	struct dc_state *context)
1449 {
1450 	struct dce_hwseq *hws = dc->hwseq;
1451 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
1452 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
1453 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1454 	struct dccg *dccg = dc->res_pool->dccg;
1455 	bool viewport_changed = false;
1456 
1457 	if (pipe_ctx->update_flags.bits.dppclk)
1458 		dpp->funcs->dpp_dppclk_control(dpp, false, true);
1459 
1460 	if (pipe_ctx->update_flags.bits.enable)
1461 		dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
1462 
1463 	/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1464 	 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1465 	 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1466 	 */
1467 	if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1468 		hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1469 
1470 		hubp->funcs->hubp_setup(
1471 			hubp,
1472 			&pipe_ctx->dlg_regs,
1473 			&pipe_ctx->ttu_regs,
1474 			&pipe_ctx->rq_regs,
1475 			&pipe_ctx->pipe_dlg_param);
1476 
1477 		if (hubp->funcs->set_unbounded_requesting)
1478 			hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
1479 	}
1480 	if (pipe_ctx->update_flags.bits.hubp_interdependent)
1481 		hubp->funcs->hubp_setup_interdependent(
1482 			hubp,
1483 			&pipe_ctx->dlg_regs,
1484 			&pipe_ctx->ttu_regs);
1485 
1486 	if (pipe_ctx->update_flags.bits.enable ||
1487 			pipe_ctx->update_flags.bits.plane_changed ||
1488 			plane_state->update_flags.bits.bpp_change ||
1489 			plane_state->update_flags.bits.input_csc_change ||
1490 			plane_state->update_flags.bits.color_space_change ||
1491 			plane_state->update_flags.bits.coeff_reduction_change) {
1492 		struct dc_bias_and_scale bns_params = {0};
1493 
1494 		// program the input csc
1495 		dpp->funcs->dpp_setup(dpp,
1496 				plane_state->format,
1497 				EXPANSION_MODE_ZERO,
1498 				plane_state->input_csc_color_matrix,
1499 				plane_state->color_space,
1500 				NULL);
1501 
1502 		if (dpp->funcs->dpp_program_bias_and_scale) {
1503 			//TODO :for CNVC set scale and bias registers if necessary
1504 			build_prescale_params(&bns_params, plane_state);
1505 			dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1506 		}
1507 	}
1508 
1509 	if (pipe_ctx->update_flags.bits.mpcc
1510 			|| pipe_ctx->update_flags.bits.plane_changed
1511 			|| plane_state->update_flags.bits.global_alpha_change
1512 			|| plane_state->update_flags.bits.per_pixel_alpha_change) {
1513 		// MPCC inst is equal to pipe index in practice
1514 		int mpcc_inst = hubp->inst;
1515 		int opp_inst;
1516 		int opp_count = dc->res_pool->pipe_count;
1517 
1518 		for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1519 			if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1520 				dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1521 				dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1522 				break;
1523 			}
1524 		}
1525 		hws->funcs.update_mpcc(dc, pipe_ctx);
1526 	}
1527 
1528 	if (pipe_ctx->update_flags.bits.scaler ||
1529 			plane_state->update_flags.bits.scaling_change ||
1530 			plane_state->update_flags.bits.position_change ||
1531 			plane_state->update_flags.bits.per_pixel_alpha_change ||
1532 			pipe_ctx->stream->update_flags.bits.scaling) {
1533 		pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1534 		ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
1535 		/* scaler configuration */
1536 		pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1537 				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1538 	}
1539 
1540 	if (pipe_ctx->update_flags.bits.viewport ||
1541 			(context == dc->current_state && plane_state->update_flags.bits.position_change) ||
1542 			(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1543 			(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1544 
1545 		hubp->funcs->mem_program_viewport(
1546 			hubp,
1547 			&pipe_ctx->plane_res.scl_data.viewport,
1548 			&pipe_ctx->plane_res.scl_data.viewport_c);
1549 		viewport_changed = true;
1550 	}
1551 
1552 	/* Any updates are handled in dc interface, just need to apply existing for plane enable */
1553 	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1554 			pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1555 			pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1556 		dc->hwss.set_cursor_position(pipe_ctx);
1557 		dc->hwss.set_cursor_attribute(pipe_ctx);
1558 
1559 		if (dc->hwss.set_cursor_sdr_white_level)
1560 			dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1561 	}
1562 
1563 	/* Any updates are handled in dc interface, just need
1564 	 * to apply existing for plane enable / opp change */
1565 	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1566 			|| pipe_ctx->update_flags.bits.plane_changed
1567 			|| pipe_ctx->stream->update_flags.bits.gamut_remap
1568 			|| pipe_ctx->stream->update_flags.bits.out_csc) {
1569 		/* dpp/cm gamut remap*/
1570 		dc->hwss.program_gamut_remap(pipe_ctx);
1571 
1572 		/*call the dcn2 method which uses mpc csc*/
1573 		dc->hwss.program_output_csc(dc,
1574 				pipe_ctx,
1575 				pipe_ctx->stream->output_color_space,
1576 				pipe_ctx->stream->csc_color_matrix.matrix,
1577 				hubp->opp_id);
1578 	}
1579 
1580 	if (pipe_ctx->update_flags.bits.enable ||
1581 			pipe_ctx->update_flags.bits.plane_changed ||
1582 			pipe_ctx->update_flags.bits.opp_changed ||
1583 			plane_state->update_flags.bits.pixel_format_change ||
1584 			plane_state->update_flags.bits.horizontal_mirror_change ||
1585 			plane_state->update_flags.bits.rotation_change ||
1586 			plane_state->update_flags.bits.swizzle_change ||
1587 			plane_state->update_flags.bits.dcc_change ||
1588 			plane_state->update_flags.bits.bpp_change ||
1589 			plane_state->update_flags.bits.scaling_change ||
1590 			plane_state->update_flags.bits.plane_size_change) {
1591 		struct plane_size size = plane_state->plane_size;
1592 
1593 		size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1594 		hubp->funcs->hubp_program_surface_config(
1595 			hubp,
1596 			plane_state->format,
1597 			&plane_state->tiling_info,
1598 			&size,
1599 			plane_state->rotation,
1600 			&plane_state->dcc,
1601 			plane_state->horizontal_mirror,
1602 			0);
1603 		hubp->power_gated = false;
1604 	}
1605 
1606 	if (pipe_ctx->update_flags.bits.enable ||
1607 		pipe_ctx->update_flags.bits.plane_changed ||
1608 		plane_state->update_flags.bits.addr_update)
1609 		hws->funcs.update_plane_addr(dc, pipe_ctx);
1610 
1611 	if (pipe_ctx->update_flags.bits.enable)
1612 		hubp->funcs->set_blank(hubp, false);
1613 	/* If the stream paired with this plane is phantom, the plane is also phantom */
1614 	if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
1615 			&& hubp->funcs->phantom_hubp_post_enable)
1616 		hubp->funcs->phantom_hubp_post_enable(hubp);
1617 }
1618 
calculate_vready_offset_for_group(struct pipe_ctx * pipe)1619 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)
1620 {
1621 	struct pipe_ctx *other_pipe;
1622 	int vready_offset = pipe->pipe_dlg_param.vready_offset;
1623 
1624 	/* Always use the largest vready_offset of all connected pipes */
1625 	for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) {
1626 		if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1627 			vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1628 	}
1629 	for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) {
1630 		if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1631 			vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1632 	}
1633 	for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) {
1634 		if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1635 			vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1636 	}
1637 	for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) {
1638 		if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1639 			vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1640 	}
1641 
1642 	return vready_offset;
1643 }
1644 
dcn20_program_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)1645 static void dcn20_program_pipe(
1646 		struct dc *dc,
1647 		struct pipe_ctx *pipe_ctx,
1648 		struct dc_state *context)
1649 {
1650 	struct dce_hwseq *hws = dc->hwseq;
1651 	/* Only need to unblank on top pipe */
1652 
1653 	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1654 			&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1655 		hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1656 
1657 	/* Only update TG on top pipe */
1658 	if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1659 			&& !pipe_ctx->prev_odm_pipe) {
1660 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
1661 				pipe_ctx->stream_res.tg,
1662 				calculate_vready_offset_for_group(pipe_ctx),
1663 				pipe_ctx->pipe_dlg_param.vstartup_start,
1664 				pipe_ctx->pipe_dlg_param.vupdate_offset,
1665 				pipe_ctx->pipe_dlg_param.vupdate_width);
1666 
1667 		if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1668 			pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
1669 			pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
1670 		}
1671 
1672 		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1673 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1674 
1675 		if (hws->funcs.setup_vupdate_interrupt)
1676 			hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1677 	}
1678 
1679 	if (pipe_ctx->update_flags.bits.odm)
1680 		hws->funcs.update_odm(dc, context, pipe_ctx);
1681 
1682 	if (pipe_ctx->update_flags.bits.enable) {
1683 		dcn20_enable_plane(dc, pipe_ctx, context);
1684 		if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1685 			dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1686 	}
1687 
1688 	if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
1689 		dc->res_pool->hubbub->funcs->program_det_size(
1690 			dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
1691 
1692 	if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1693 		dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1694 
1695 	if (pipe_ctx->update_flags.bits.enable
1696 			|| pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1697 		hws->funcs.set_hdr_multiplier(pipe_ctx);
1698 
1699 	if (pipe_ctx->update_flags.bits.enable ||
1700 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1701 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
1702 		hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1703 
1704 	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
1705 	 * only do gamma programming for powering on, internal memcmp to avoid
1706 	 * updating on slave planes
1707 	 */
1708 	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1709 		hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1710 
1711 	/* If the pipe has been enabled or has a different opp, we
1712 	 * should reprogram the fmt. This deals with cases where
1713 	 * interation between mpc and odm combine on different streams
1714 	 * causes a different pipe to be chosen to odm combine with.
1715 	 */
1716 	if (pipe_ctx->update_flags.bits.enable
1717 	    || pipe_ctx->update_flags.bits.opp_changed) {
1718 
1719 		pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1720 			pipe_ctx->stream_res.opp,
1721 			COLOR_SPACE_YCBCR601,
1722 			pipe_ctx->stream->timing.display_color_depth,
1723 			pipe_ctx->stream->signal);
1724 
1725 		pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1726 			pipe_ctx->stream_res.opp,
1727 			&pipe_ctx->stream->bit_depth_params,
1728 			&pipe_ctx->stream->clamping);
1729 	}
1730 }
1731 
dcn20_program_front_end_for_ctx(struct dc * dc,struct dc_state * context)1732 void dcn20_program_front_end_for_ctx(
1733 		struct dc *dc,
1734 		struct dc_state *context)
1735 {
1736 	int i;
1737 	struct dce_hwseq *hws = dc->hwseq;
1738 	DC_LOGGER_INIT(dc->ctx->logger);
1739 
1740 	/* Carry over GSL groups in case the context is changing. */
1741 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1742 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1743 		struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1744 
1745 		if (pipe_ctx->stream == old_pipe_ctx->stream)
1746 			pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
1747 	}
1748 
1749 	if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1750 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
1751 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1752 
1753 			if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1754 				ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
1755 				/*turn off triple buffer for full update*/
1756 				dc->hwss.program_triplebuffer(
1757 						dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
1758 			}
1759 		}
1760 	}
1761 
1762 	/* Set pipe update flags and lock pipes */
1763 	for (i = 0; i < dc->res_pool->pipe_count; i++)
1764 		dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1765 				&context->res_ctx.pipe_ctx[i]);
1766 
1767 	/* OTG blank before disabling all front ends */
1768 	for (i = 0; i < dc->res_pool->pipe_count; i++)
1769 		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1770 				&& !context->res_ctx.pipe_ctx[i].top_pipe
1771 				&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1772 				&& context->res_ctx.pipe_ctx[i].stream)
1773 			hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1774 
1775 
1776 	/* Disconnect mpcc */
1777 	for (i = 0; i < dc->res_pool->pipe_count; i++)
1778 		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1779 				|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1780 			struct hubbub *hubbub = dc->res_pool->hubbub;
1781 
1782 			/* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom
1783 			 * then we want to do the programming here (effectively it's being disabled). If we do
1784 			 * the programming later the DET won't be updated until the OTG for the phantom pipe is
1785 			 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with
1786 			 * DET allocation.
1787 			 */
1788 			if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||
1789 					(context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom)))
1790 				hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
1791 			hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1792 			DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1793 		}
1794 
1795 	/*
1796 	 * Program all updated pipes, order matters for mpcc setup. Start with
1797 	 * top pipe and program all pipes that follow in order
1798 	 */
1799 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1800 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1801 
1802 		if (pipe->plane_state && !pipe->top_pipe) {
1803 			while (pipe) {
1804 				if (hws->funcs.program_pipe)
1805 					hws->funcs.program_pipe(dc, pipe, context);
1806 				else {
1807 					/* Don't program phantom pipes in the regular front end programming sequence.
1808 					 * There is an MPO transition case where a pipe being used by a video plane is
1809 					 * transitioned directly to be a phantom pipe when closing the MPO video. However
1810 					 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away),
1811 					 * but the MPO still exists until the double buffered update of the main pipe so we
1812 					 * will get a frame of underflow if the phantom pipe is programmed here.
1813 					 */
1814 					if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM)
1815 						dcn20_program_pipe(dc, pipe, context);
1816 				}
1817 
1818 				pipe = pipe->bottom_pipe;
1819 			}
1820 		}
1821 		/* Program secondary blending tree and writeback pipes */
1822 		pipe = &context->res_ctx.pipe_ctx[i];
1823 		if (!pipe->top_pipe && !pipe->prev_odm_pipe
1824 				&& pipe->stream && pipe->stream->num_wb_info > 0
1825 				&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
1826 					|| pipe->stream->update_flags.raw)
1827 				&& hws->funcs.program_all_writeback_pipes_in_tree)
1828 			hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1829 
1830 		/* Avoid underflow by check of pipe line read when adding 2nd plane. */
1831 		if (hws->wa.wait_hubpret_read_start_during_mpo_transition &&
1832 			!pipe->top_pipe &&
1833 			pipe->stream &&
1834 			pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&
1835 			dc->current_state->stream_status[0].plane_count == 1 &&
1836 			context->stream_status[0].plane_count > 1) {
1837 			pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
1838 		}
1839 	}
1840 }
1841 
dcn20_post_unlock_program_front_end(struct dc * dc,struct dc_state * context)1842 void dcn20_post_unlock_program_front_end(
1843 		struct dc *dc,
1844 		struct dc_state *context)
1845 {
1846 	int i;
1847 	const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1848 	struct dce_hwseq *hwseq = dc->hwseq;
1849 
1850 	DC_LOGGER_INIT(dc->ctx->logger);
1851 
1852 	for (i = 0; i < dc->res_pool->pipe_count; i++)
1853 		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1854 			dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1855 
1856 	/*
1857 	 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1858 	 * part of the enable operation otherwise, DM may request an immediate flip which
1859 	 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1860 	 * is unsupported on DCN.
1861 	 */
1862 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1863 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1864 		// Don't check flip pending on phantom pipes
1865 		if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&
1866 				pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1867 			struct hubp *hubp = pipe->plane_res.hubp;
1868 			int j = 0;
1869 
1870 			for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1871 					&& hubp->funcs->hubp_is_flip_pending(hubp); j++)
1872 				udelay(1);
1873 		}
1874 	}
1875 
1876 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1877 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1878 		struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1879 
1880 		/* If an active, non-phantom pipe is being transitioned into a phantom
1881 		 * pipe, wait for the double buffer update to complete first before we do
1882 		 * phantom pipe programming (HUBP_VTG_SEL updates right away so that can
1883 		 * cause issues).
1884 		 */
1885 		if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM &&
1886 				old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1887 			old_pipe->stream_res.tg->funcs->wait_for_state(
1888 					old_pipe->stream_res.tg,
1889 					CRTC_STATE_VBLANK);
1890 			old_pipe->stream_res.tg->funcs->wait_for_state(
1891 					old_pipe->stream_res.tg,
1892 					CRTC_STATE_VACTIVE);
1893 		}
1894 	}
1895 
1896 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1897 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1898 
1899 		if (pipe->plane_state && !pipe->top_pipe) {
1900 			/* Program phantom pipe here to prevent a frame of underflow in the MPO transition
1901 			 * case (if a pipe being used for a video plane transitions to a phantom pipe, it
1902 			 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end
1903 			 * programming sequence).
1904 			 */
1905 			while (pipe) {
1906 				if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1907 					if (dc->hwss.update_phantom_vp_position)
1908 						dc->hwss.update_phantom_vp_position(dc, context, pipe);
1909 					dcn20_program_pipe(dc, pipe, context);
1910 				}
1911 				pipe = pipe->bottom_pipe;
1912 			}
1913 		}
1914 	}
1915 
1916 	/* Only program the MALL registers after all the main and phantom pipes
1917 	 * are done programming.
1918 	 */
1919 	if (hwseq->funcs.program_mall_pipe_config)
1920 		hwseq->funcs.program_mall_pipe_config(dc, context);
1921 
1922 	/* WA to apply WM setting*/
1923 	if (hwseq->wa.DEGVIDCN21)
1924 		dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1925 
1926 
1927 	/* WA for stutter underflow during MPO transitions when adding 2nd plane */
1928 	if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
1929 
1930 		if (dc->current_state->stream_status[0].plane_count == 1 &&
1931 				context->stream_status[0].plane_count > 1) {
1932 
1933 			struct timing_generator *tg = dc->res_pool->timing_generators[0];
1934 
1935 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
1936 
1937 			hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
1938 			hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
1939 		}
1940 	}
1941 }
1942 
dcn20_prepare_bandwidth(struct dc * dc,struct dc_state * context)1943 void dcn20_prepare_bandwidth(
1944 		struct dc *dc,
1945 		struct dc_state *context)
1946 {
1947 	struct hubbub *hubbub = dc->res_pool->hubbub;
1948 	unsigned int compbuf_size_kb = 0;
1949 	unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns;
1950 	unsigned int i;
1951 
1952 	dc->clk_mgr->funcs->update_clocks(
1953 			dc->clk_mgr,
1954 			context,
1955 			false);
1956 
1957 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1958 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1959 
1960 		// At optimize don't restore the original watermark value
1961 		if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
1962 			context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
1963 			break;
1964 		}
1965 	}
1966 
1967 	/* program dchubbub watermarks */
1968 	dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
1969 					&context->bw_ctx.bw.dcn.watermarks,
1970 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1971 					false);
1972 
1973 	// Restore the real watermark so we can commit the value to DMCUB
1974 	// DMCUB uses the "original" watermark value in SubVP MCLK switch
1975 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a;
1976 
1977 	/* decrease compbuf size */
1978 	if (hubbub->funcs->program_compbuf_size) {
1979 		if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
1980 			compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
1981 		else
1982 			compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
1983 
1984 		hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
1985 	}
1986 }
1987 
dcn20_optimize_bandwidth(struct dc * dc,struct dc_state * context)1988 void dcn20_optimize_bandwidth(
1989 		struct dc *dc,
1990 		struct dc_state *context)
1991 {
1992 	struct hubbub *hubbub = dc->res_pool->hubbub;
1993 	int i;
1994 
1995 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1996 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1997 
1998 		// At optimize don't need  to restore the original watermark value
1999 		if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2000 			context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2001 			break;
2002 		}
2003 	}
2004 
2005 	/* program dchubbub watermarks */
2006 	hubbub->funcs->program_watermarks(hubbub,
2007 					&context->bw_ctx.bw.dcn.watermarks,
2008 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2009 					true);
2010 
2011 	if (dc->clk_mgr->dc_mode_softmax_enabled)
2012 		if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
2013 				context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
2014 			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
2015 
2016 	/* increase compbuf size */
2017 	if (hubbub->funcs->program_compbuf_size)
2018 		hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
2019 
2020 	dc->clk_mgr->funcs->update_clocks(
2021 			dc->clk_mgr,
2022 			context,
2023 			true);
2024 	if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
2025 		for (i = 0; i < dc->res_pool->pipe_count; ++i) {
2026 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2027 
2028 			if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank
2029 				&& pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max
2030 				&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
2031 					pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,
2032 						pipe_ctx->dlg_regs.optimized_min_dst_y_next_start);
2033 		}
2034 	}
2035 }
2036 
dcn20_update_bandwidth(struct dc * dc,struct dc_state * context)2037 bool dcn20_update_bandwidth(
2038 		struct dc *dc,
2039 		struct dc_state *context)
2040 {
2041 	int i;
2042 	struct dce_hwseq *hws = dc->hwseq;
2043 
2044 	/* recalculate DML parameters */
2045 	if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
2046 		return false;
2047 
2048 	/* apply updated bandwidth parameters */
2049 	dc->hwss.prepare_bandwidth(dc, context);
2050 
2051 	/* update hubp configs for all pipes */
2052 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2053 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2054 
2055 		if (pipe_ctx->plane_state == NULL)
2056 			continue;
2057 
2058 		if (pipe_ctx->top_pipe == NULL) {
2059 			bool blank = !is_pipe_tree_visible(pipe_ctx);
2060 
2061 			pipe_ctx->stream_res.tg->funcs->program_global_sync(
2062 					pipe_ctx->stream_res.tg,
2063 					calculate_vready_offset_for_group(pipe_ctx),
2064 					pipe_ctx->pipe_dlg_param.vstartup_start,
2065 					pipe_ctx->pipe_dlg_param.vupdate_offset,
2066 					pipe_ctx->pipe_dlg_param.vupdate_width);
2067 
2068 			pipe_ctx->stream_res.tg->funcs->set_vtg_params(
2069 					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
2070 
2071 			if (pipe_ctx->prev_odm_pipe == NULL)
2072 				hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
2073 
2074 			if (hws->funcs.setup_vupdate_interrupt)
2075 				hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
2076 		}
2077 
2078 		pipe_ctx->plane_res.hubp->funcs->hubp_setup(
2079 				pipe_ctx->plane_res.hubp,
2080 					&pipe_ctx->dlg_regs,
2081 					&pipe_ctx->ttu_regs,
2082 					&pipe_ctx->rq_regs,
2083 					&pipe_ctx->pipe_dlg_param);
2084 	}
2085 
2086 	return true;
2087 }
2088 
dcn20_enable_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)2089 void dcn20_enable_writeback(
2090 		struct dc *dc,
2091 		struct dc_writeback_info *wb_info,
2092 		struct dc_state *context)
2093 {
2094 	struct dwbc *dwb;
2095 	struct mcif_wb *mcif_wb;
2096 	struct timing_generator *optc;
2097 
2098 	ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
2099 	ASSERT(wb_info->wb_enabled);
2100 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
2101 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
2102 
2103 	/* set the OPTC source mux */
2104 	optc = dc->res_pool->timing_generators[dwb->otg_inst];
2105 	optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
2106 	/* set MCIF_WB buffer and arbitration configuration */
2107 	mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
2108 	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
2109 	/* Enable MCIF_WB */
2110 	mcif_wb->funcs->enable_mcif(mcif_wb);
2111 	/* Enable DWB */
2112 	dwb->funcs->enable(dwb, &wb_info->dwb_params);
2113 	/* TODO: add sequence to enable/disable warmup */
2114 }
2115 
dcn20_disable_writeback(struct dc * dc,unsigned int dwb_pipe_inst)2116 void dcn20_disable_writeback(
2117 		struct dc *dc,
2118 		unsigned int dwb_pipe_inst)
2119 {
2120 	struct dwbc *dwb;
2121 	struct mcif_wb *mcif_wb;
2122 
2123 	ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
2124 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
2125 	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
2126 
2127 	dwb->funcs->disable(dwb);
2128 	mcif_wb->funcs->disable_mcif(mcif_wb);
2129 }
2130 
dcn20_wait_for_blank_complete(struct output_pixel_processor * opp)2131 bool dcn20_wait_for_blank_complete(
2132 		struct output_pixel_processor *opp)
2133 {
2134 	int counter;
2135 
2136 	for (counter = 0; counter < 1000; counter++) {
2137 		if (opp->funcs->dpg_is_blanked(opp))
2138 			break;
2139 
2140 		udelay(100);
2141 	}
2142 
2143 	if (counter == 1000) {
2144 		dm_error("DC: failed to blank crtc!\n");
2145 		return false;
2146 	}
2147 
2148 	return true;
2149 }
2150 
dcn20_dmdata_status_done(struct pipe_ctx * pipe_ctx)2151 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
2152 {
2153 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
2154 
2155 	if (!hubp)
2156 		return false;
2157 	return hubp->funcs->dmdata_status_done(hubp);
2158 }
2159 
dcn20_disable_stream_gating(struct dc * dc,struct pipe_ctx * pipe_ctx)2160 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2161 {
2162 	struct dce_hwseq *hws = dc->hwseq;
2163 
2164 	if (pipe_ctx->stream_res.dsc) {
2165 		struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2166 
2167 		hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
2168 		while (odm_pipe) {
2169 			hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
2170 			odm_pipe = odm_pipe->next_odm_pipe;
2171 		}
2172 	}
2173 }
2174 
dcn20_enable_stream_gating(struct dc * dc,struct pipe_ctx * pipe_ctx)2175 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
2176 {
2177 	struct dce_hwseq *hws = dc->hwseq;
2178 
2179 	if (pipe_ctx->stream_res.dsc) {
2180 		struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2181 
2182 		hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
2183 		while (odm_pipe) {
2184 			hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
2185 			odm_pipe = odm_pipe->next_odm_pipe;
2186 		}
2187 	}
2188 }
2189 
dcn20_set_dmdata_attributes(struct pipe_ctx * pipe_ctx)2190 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
2191 {
2192 	struct dc_dmdata_attributes attr = { 0 };
2193 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
2194 
2195 	attr.dmdata_mode = DMDATA_HW_MODE;
2196 	attr.dmdata_size =
2197 		dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2198 	attr.address.quad_part =
2199 			pipe_ctx->stream->dmdata_address.quad_part;
2200 	attr.dmdata_dl_delta = 0;
2201 	attr.dmdata_qos_mode = 0;
2202 	attr.dmdata_qos_level = 0;
2203 	attr.dmdata_repeat = 1; /* always repeat */
2204 	attr.dmdata_updated = 1;
2205 	attr.dmdata_sw_data = NULL;
2206 
2207 	hubp->funcs->dmdata_set_attributes(hubp, &attr);
2208 }
2209 
dcn20_init_vm_ctx(struct dce_hwseq * hws,struct dc * dc,struct dc_virtual_addr_space_config * va_config,int vmid)2210 void dcn20_init_vm_ctx(
2211 		struct dce_hwseq *hws,
2212 		struct dc *dc,
2213 		struct dc_virtual_addr_space_config *va_config,
2214 		int vmid)
2215 {
2216 	struct dcn_hubbub_virt_addr_config config;
2217 
2218 	if (vmid == 0) {
2219 		ASSERT(0); /* VMID cannot be 0 for vm context */
2220 		return;
2221 	}
2222 
2223 	config.page_table_start_addr = va_config->page_table_start_addr;
2224 	config.page_table_end_addr = va_config->page_table_end_addr;
2225 	config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2226 	config.page_table_depth = va_config->page_table_depth;
2227 	config.page_table_base_addr = va_config->page_table_base_addr;
2228 
2229 	dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2230 }
2231 
dcn20_init_sys_ctx(struct dce_hwseq * hws,struct dc * dc,struct dc_phy_addr_space_config * pa_config)2232 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
2233 {
2234 	struct dcn_hubbub_phys_addr_config config;
2235 
2236 	config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2237 	config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2238 	config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2239 	config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2240 	config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2241 	config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2242 	config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2243 	config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2244 	config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
2245 	config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
2246 
2247 	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
2248 }
2249 
patch_address_for_sbs_tb_stereo(struct pipe_ctx * pipe_ctx,PHYSICAL_ADDRESS_LOC * addr)2250 static bool patch_address_for_sbs_tb_stereo(
2251 		struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2252 {
2253 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2254 	bool sec_split = pipe_ctx->top_pipe &&
2255 			pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2256 	if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2257 			(pipe_ctx->stream->timing.timing_3d_format ==
2258 			TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2259 			pipe_ctx->stream->timing.timing_3d_format ==
2260 			TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2261 		*addr = plane_state->address.grph_stereo.left_addr;
2262 		plane_state->address.grph_stereo.left_addr =
2263 				plane_state->address.grph_stereo.right_addr;
2264 		return true;
2265 	}
2266 
2267 	if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2268 			plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2269 		plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2270 		plane_state->address.grph_stereo.right_addr =
2271 				plane_state->address.grph_stereo.left_addr;
2272 		plane_state->address.grph_stereo.right_meta_addr =
2273 				plane_state->address.grph_stereo.left_meta_addr;
2274 	}
2275 	return false;
2276 }
2277 
dcn20_update_plane_addr(const struct dc * dc,struct pipe_ctx * pipe_ctx)2278 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
2279 {
2280 	bool addr_patched = false;
2281 	PHYSICAL_ADDRESS_LOC addr;
2282 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2283 
2284 	if (plane_state == NULL)
2285 		return;
2286 
2287 	addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2288 
2289 	// Call Helper to track VMID use
2290 	vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
2291 
2292 	pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2293 			pipe_ctx->plane_res.hubp,
2294 			&plane_state->address,
2295 			plane_state->flip_immediate);
2296 
2297 	plane_state->status.requested_address = plane_state->address;
2298 
2299 	if (plane_state->flip_immediate)
2300 		plane_state->status.current_address = plane_state->address;
2301 
2302 	if (addr_patched)
2303 		pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2304 }
2305 
dcn20_unblank_stream(struct pipe_ctx * pipe_ctx,struct dc_link_settings * link_settings)2306 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2307 		struct dc_link_settings *link_settings)
2308 {
2309 	struct encoder_unblank_param params = {0};
2310 	struct dc_stream_state *stream = pipe_ctx->stream;
2311 	struct dc_link *link = stream->link;
2312 	struct dce_hwseq *hws = link->dc->hwseq;
2313 	struct pipe_ctx *odm_pipe;
2314 
2315 	params.opp_cnt = 1;
2316 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2317 		params.opp_cnt++;
2318 	}
2319 	/* only 3 items below are used by unblank */
2320 	params.timing = pipe_ctx->stream->timing;
2321 
2322 	params.link_settings.link_rate = link_settings->link_rate;
2323 
2324 	if (is_dp_128b_132b_signal(pipe_ctx)) {
2325 		/* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
2326 		pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
2327 				pipe_ctx->stream_res.hpo_dp_stream_enc,
2328 				pipe_ctx->stream_res.tg->inst);
2329 	} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2330 		if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
2331 			params.timing.pix_clk_100hz /= 2;
2332 		pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
2333 				pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
2334 		pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
2335 	}
2336 
2337 	if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2338 		hws->funcs.edp_backlight_control(link, true);
2339 	}
2340 }
2341 
dcn20_setup_vupdate_interrupt(struct dc * dc,struct pipe_ctx * pipe_ctx)2342 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2343 {
2344 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
2345 	int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2346 
2347 	if (start_line < 0)
2348 		start_line = 0;
2349 
2350 	if (tg->funcs->setup_vertical_interrupt2)
2351 		tg->funcs->setup_vertical_interrupt2(tg, start_line);
2352 }
2353 
dcn20_reset_back_end_for_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)2354 static void dcn20_reset_back_end_for_pipe(
2355 		struct dc *dc,
2356 		struct pipe_ctx *pipe_ctx,
2357 		struct dc_state *context)
2358 {
2359 	int i;
2360 	struct dc_link *link = pipe_ctx->stream->link;
2361 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2362 
2363 	DC_LOGGER_INIT(dc->ctx->logger);
2364 	if (pipe_ctx->stream_res.stream_enc == NULL) {
2365 		pipe_ctx->stream = NULL;
2366 		return;
2367 	}
2368 
2369 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2370 		/* DPMS may already disable or */
2371 		/* dpms_off status is incorrect due to fastboot
2372 		 * feature. When system resume from S4 with second
2373 		 * screen only, the dpms_off would be true but
2374 		 * VBIOS lit up eDP, so check link status too.
2375 		 */
2376 		if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2377 			core_link_disable_stream(pipe_ctx);
2378 		else if (pipe_ctx->stream_res.audio)
2379 			dc->hwss.disable_audio_stream(pipe_ctx);
2380 
2381 		/* free acquired resources */
2382 		if (pipe_ctx->stream_res.audio) {
2383 			/*disable az_endpoint*/
2384 			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2385 
2386 			/*free audio*/
2387 			if (dc->caps.dynamic_audio == true) {
2388 				/*we have to dynamic arbitrate the audio endpoints*/
2389 				/*we free the resource, need reset is_audio_acquired*/
2390 				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2391 						pipe_ctx->stream_res.audio, false);
2392 				pipe_ctx->stream_res.audio = NULL;
2393 			}
2394 		}
2395 	}
2396 	else if (pipe_ctx->stream_res.dsc) {
2397 		dp_set_dsc_enable(pipe_ctx, false);
2398 	}
2399 
2400 	/* by upper caller loop, parent pipe: pipe0, will be reset last.
2401 	 * back end share by all pipes and will be disable only when disable
2402 	 * parent pipe.
2403 	 */
2404 	if (pipe_ctx->top_pipe == NULL) {
2405 
2406 		dc->hwss.set_abm_immediate_disable(pipe_ctx);
2407 
2408 		pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2409 
2410 		pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2411 		if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2412 			pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2413 					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2414 
2415 		if (pipe_ctx->stream_res.tg->funcs->set_drr)
2416 			pipe_ctx->stream_res.tg->funcs->set_drr(
2417 					pipe_ctx->stream_res.tg, NULL);
2418 		/* TODO - convert symclk_ref_cnts for otg to a bit map to solve
2419 		 * the case where the same symclk is shared across multiple otg
2420 		 * instances
2421 		 */
2422 		link->phy_state.symclk_ref_cnts.otg = 0;
2423 		if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
2424 			link_hwss->disable_link_output(link,
2425 					&pipe_ctx->link_res, pipe_ctx->stream->signal);
2426 			link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
2427 		}
2428 	}
2429 
2430 	for (i = 0; i < dc->res_pool->pipe_count; i++)
2431 		if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2432 			break;
2433 
2434 	if (i == dc->res_pool->pipe_count)
2435 		return;
2436 
2437 	pipe_ctx->stream = NULL;
2438 	DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2439 					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2440 }
2441 
dcn20_reset_hw_ctx_wrap(struct dc * dc,struct dc_state * context)2442 void dcn20_reset_hw_ctx_wrap(
2443 		struct dc *dc,
2444 		struct dc_state *context)
2445 {
2446 	int i;
2447 	struct dce_hwseq *hws = dc->hwseq;
2448 
2449 	/* Reset Back End*/
2450 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2451 		struct pipe_ctx *pipe_ctx_old =
2452 			&dc->current_state->res_ctx.pipe_ctx[i];
2453 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2454 
2455 		if (!pipe_ctx_old->stream)
2456 			continue;
2457 
2458 		if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2459 			continue;
2460 
2461 		if (!pipe_ctx->stream ||
2462 				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2463 			struct clock_source *old_clk = pipe_ctx_old->clock_source;
2464 
2465 			dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2466 			if (hws->funcs.enable_stream_gating)
2467 				hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
2468 			if (old_clk)
2469 				old_clk->funcs->cs_power_down(old_clk);
2470 		}
2471 	}
2472 }
2473 
dcn20_update_visual_confirm_color(struct dc * dc,struct pipe_ctx * pipe_ctx,struct tg_color * color,int mpcc_id)2474 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
2475 {
2476 	struct mpc *mpc = dc->res_pool->mpc;
2477 
2478 	// input to MPCC is always RGB, by default leave black_color at 0
2479 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
2480 		get_hdr_visual_confirm_color(pipe_ctx, color);
2481 	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
2482 		get_surface_visual_confirm_color(pipe_ctx, color);
2483 	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
2484 		get_mpctree_visual_confirm_color(pipe_ctx, color);
2485 	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
2486 		get_surface_tile_visual_confirm_color(pipe_ctx, color);
2487 	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
2488 		get_subvp_visual_confirm_color(dc, pipe_ctx, color);
2489 
2490 	if (mpc->funcs->set_bg_color) {
2491 		memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
2492 		mpc->funcs->set_bg_color(mpc, color, mpcc_id);
2493 	}
2494 }
2495 
dcn20_update_mpcc(struct dc * dc,struct pipe_ctx * pipe_ctx)2496 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2497 {
2498 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
2499 	struct mpcc_blnd_cfg blnd_cfg = {0};
2500 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2501 	int mpcc_id;
2502 	struct mpcc *new_mpcc;
2503 	struct mpc *mpc = dc->res_pool->mpc;
2504 	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2505 
2506 	blnd_cfg.overlap_only = false;
2507 	blnd_cfg.global_gain = 0xff;
2508 
2509 	if (per_pixel_alpha) {
2510 		blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;
2511 		if (pipe_ctx->plane_state->global_alpha) {
2512 			blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2513 			blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2514 		} else {
2515 			blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2516 		}
2517 	} else {
2518 		blnd_cfg.pre_multiplied_alpha = false;
2519 		blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2520 	}
2521 
2522 	if (pipe_ctx->plane_state->global_alpha)
2523 		blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2524 	else
2525 		blnd_cfg.global_alpha = 0xff;
2526 
2527 	blnd_cfg.background_color_bpc = 4;
2528 	blnd_cfg.bottom_gain_mode = 0;
2529 	blnd_cfg.top_gain = 0x1f000;
2530 	blnd_cfg.bottom_inside_gain = 0x1f000;
2531 	blnd_cfg.bottom_outside_gain = 0x1f000;
2532 
2533 	if (pipe_ctx->plane_state->format
2534 			== SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2535 		blnd_cfg.pre_multiplied_alpha = false;
2536 
2537 	/*
2538 	 * TODO: remove hack
2539 	 * Note: currently there is a bug in init_hw such that
2540 	 * on resume from hibernate, BIOS sets up MPCC0, and
2541 	 * we do mpcc_remove but the mpcc cannot go to idle
2542 	 * after remove. This cause us to pick mpcc1 here,
2543 	 * which causes a pstate hang for yet unknown reason.
2544 	 */
2545 	mpcc_id = hubp->inst;
2546 
2547 	/* If there is no full update, don't need to touch MPC tree*/
2548 	if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2549 		!pipe_ctx->update_flags.bits.mpcc) {
2550 		mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2551 		dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2552 		return;
2553 	}
2554 
2555 	/* check if this MPCC is already being used */
2556 	new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2557 	/* remove MPCC if being used */
2558 	if (new_mpcc != NULL)
2559 		mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2560 	else
2561 		if (dc->debug.sanity_checks)
2562 			mpc->funcs->assert_mpcc_idle_before_connect(
2563 					dc->res_pool->mpc, mpcc_id);
2564 
2565 	/* Call MPC to insert new plane */
2566 	new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2567 			mpc_tree_params,
2568 			&blnd_cfg,
2569 			NULL,
2570 			NULL,
2571 			hubp->inst,
2572 			mpcc_id);
2573 	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
2574 
2575 	ASSERT(new_mpcc != NULL);
2576 	hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2577 	hubp->mpcc_id = mpcc_id;
2578 }
2579 
dcn20_enable_stream(struct pipe_ctx * pipe_ctx)2580 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2581 {
2582 	enum dc_lane_count lane_count =
2583 		pipe_ctx->stream->link->cur_link_settings.lane_count;
2584 
2585 	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2586 	struct dc_link *link = pipe_ctx->stream->link;
2587 
2588 	uint32_t active_total_with_borders;
2589 	uint32_t early_control = 0;
2590 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
2591 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2592 	struct dc *dc = pipe_ctx->stream->ctx->dc;
2593 
2594 	if (is_dp_128b_132b_signal(pipe_ctx)) {
2595 		if (dc->hwseq->funcs.setup_hpo_hw_control)
2596 			dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
2597 	}
2598 
2599 	link_hwss->setup_stream_encoder(pipe_ctx);
2600 
2601 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2602 		if (dc->hwss.program_dmdata_engine)
2603 			dc->hwss.program_dmdata_engine(pipe_ctx);
2604 	}
2605 
2606 	dc->hwss.update_info_frame(pipe_ctx);
2607 
2608 	if (dc_is_dp_signal(pipe_ctx->stream->signal))
2609 		dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
2610 
2611 	/* enable early control to avoid corruption on DP monitor*/
2612 	active_total_with_borders =
2613 			timing->h_addressable
2614 				+ timing->h_border_left
2615 				+ timing->h_border_right;
2616 
2617 	if (lane_count != 0)
2618 		early_control = active_total_with_borders % lane_count;
2619 
2620 	if (early_control == 0)
2621 		early_control = lane_count;
2622 
2623 	tg->funcs->set_early_control(tg, early_control);
2624 
2625 	if (dc->hwseq->funcs.set_pixels_per_cycle)
2626 		dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
2627 
2628 	/* enable audio only within mode set */
2629 	if (pipe_ctx->stream_res.audio != NULL) {
2630 		if (is_dp_128b_132b_signal(pipe_ctx))
2631 			pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc);
2632 		else if (dc_is_dp_signal(pipe_ctx->stream->signal))
2633 			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2634 	}
2635 }
2636 
dcn20_program_dmdata_engine(struct pipe_ctx * pipe_ctx)2637 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2638 {
2639 	struct dc_stream_state    *stream     = pipe_ctx->stream;
2640 	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2641 	bool                       enable     = false;
2642 	struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2643 	enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2644 							? dmdata_dp
2645 							: dmdata_hdmi;
2646 
2647 	/* if using dynamic meta, don't set up generic infopackets */
2648 	if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2649 		pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2650 		enable = true;
2651 	}
2652 
2653 	if (!hubp)
2654 		return;
2655 
2656 	if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2657 		return;
2658 
2659 	stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2660 						hubp->inst, mode);
2661 }
2662 
dcn20_fpga_init_hw(struct dc * dc)2663 void dcn20_fpga_init_hw(struct dc *dc)
2664 {
2665 	int i, j;
2666 	struct dce_hwseq *hws = dc->hwseq;
2667 	struct resource_pool *res_pool = dc->res_pool;
2668 	struct dc_state  *context = dc->current_state;
2669 
2670 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2671 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2672 
2673 	// Initialize the dccg
2674 	if (res_pool->dccg->funcs->dccg_init)
2675 		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2676 
2677 	//Enable ability to power gate / don't force power on permanently
2678 	hws->funcs.enable_power_gating_plane(hws, true);
2679 
2680 	// Specific to FPGA dccg and registers
2681 	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2682 	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2683 
2684 	hws->funcs.dccg_init(hws);
2685 
2686 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2687 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2688 	if (REG(REFCLK_CNTL))
2689 		REG_WRITE(REFCLK_CNTL, 0);
2690 	//
2691 
2692 
2693 	/* Blank pixel data with OPP DPG */
2694 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2695 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
2696 
2697 		if (tg->funcs->is_tg_enabled(tg))
2698 			dcn20_init_blank(dc, tg);
2699 	}
2700 
2701 	for (i = 0; i < res_pool->timing_generator_count; i++) {
2702 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
2703 
2704 		if (tg->funcs->is_tg_enabled(tg))
2705 			tg->funcs->lock(tg);
2706 	}
2707 
2708 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2709 		struct dpp *dpp = res_pool->dpps[i];
2710 
2711 		dpp->funcs->dpp_reset(dpp);
2712 	}
2713 
2714 	/* Reset all MPCC muxes */
2715 	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2716 
2717 	/* initialize OPP mpc_tree parameter */
2718 	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2719 		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2720 		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2721 		for (j = 0; j < MAX_PIPES; j++)
2722 			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2723 	}
2724 
2725 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2726 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
2727 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2728 		struct hubp *hubp = dc->res_pool->hubps[i];
2729 		struct dpp *dpp = dc->res_pool->dpps[i];
2730 
2731 		pipe_ctx->stream_res.tg = tg;
2732 		pipe_ctx->pipe_idx = i;
2733 
2734 		pipe_ctx->plane_res.hubp = hubp;
2735 		pipe_ctx->plane_res.dpp = dpp;
2736 		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2737 		hubp->mpcc_id = dpp->inst;
2738 		hubp->opp_id = OPP_ID_INVALID;
2739 		hubp->power_gated = false;
2740 		pipe_ctx->stream_res.opp = NULL;
2741 
2742 		hubp->funcs->hubp_init(hubp);
2743 
2744 		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2745 		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2746 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2747 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2748 		/*to do*/
2749 		hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2750 	}
2751 
2752 	/* initialize DWB pointer to MCIF_WB */
2753 	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2754 		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2755 
2756 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2757 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
2758 
2759 		if (tg->funcs->is_tg_enabled(tg))
2760 			tg->funcs->unlock(tg);
2761 	}
2762 
2763 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2764 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2765 
2766 		dc->hwss.disable_plane(dc, pipe_ctx);
2767 
2768 		pipe_ctx->stream_res.tg = NULL;
2769 		pipe_ctx->plane_res.hubp = NULL;
2770 	}
2771 
2772 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2773 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
2774 
2775 		tg->funcs->tg_init(tg);
2776 	}
2777 
2778 	if (dc->res_pool->hubbub->funcs->init_crb)
2779 		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
2780 }
2781 #ifndef TRIM_FSFT
dcn20_optimize_timing_for_fsft(struct dc * dc,struct dc_crtc_timing * timing,unsigned int max_input_rate_in_khz)2782 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2783 		struct dc_crtc_timing *timing,
2784 		unsigned int max_input_rate_in_khz)
2785 {
2786 	unsigned int old_v_front_porch;
2787 	unsigned int old_v_total;
2788 	unsigned int max_input_rate_in_100hz;
2789 	unsigned long long new_v_total;
2790 
2791 	max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2792 	if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2793 		return false;
2794 
2795 	old_v_total = timing->v_total;
2796 	old_v_front_porch = timing->v_front_porch;
2797 
2798 	timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2799 	timing->pix_clk_100hz = max_input_rate_in_100hz;
2800 
2801 	new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2802 
2803 	timing->v_total = new_v_total;
2804 	timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2805 	return true;
2806 }
2807 #endif
2808 
dcn20_set_disp_pattern_generator(const struct dc * dc,struct pipe_ctx * pipe_ctx,enum controller_dp_test_pattern test_pattern,enum controller_dp_color_space color_space,enum dc_color_depth color_depth,const struct tg_color * solid_color,int width,int height,int offset)2809 void dcn20_set_disp_pattern_generator(const struct dc *dc,
2810 		struct pipe_ctx *pipe_ctx,
2811 		enum controller_dp_test_pattern test_pattern,
2812 		enum controller_dp_color_space color_space,
2813 		enum dc_color_depth color_depth,
2814 		const struct tg_color *solid_color,
2815 		int width, int height, int offset)
2816 {
2817 	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2818 			color_space, color_depth, solid_color, width, height, offset);
2819 }
2820