1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3  * Copyright 2019 Raptor Engineering, LLC
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include <linux/slab.h>
28 
29 #include "dm_services.h"
30 #include "dc.h"
31 
32 #include "dcn20_init.h"
33 
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 
38 #include "dml/dcn20/dcn20_fpu.h"
39 
40 #include "dcn10/dcn10_hubp.h"
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn20_hubbub.h"
43 #include "dcn20_mpc.h"
44 #include "dcn20_hubp.h"
45 #include "irq/dcn20/irq_service_dcn20.h"
46 #include "dcn20_dpp.h"
47 #include "dcn20_optc.h"
48 #include "dcn20_hwseq.h"
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dcn10/dcn10_resource.h"
51 #include "dcn20_opp.h"
52 
53 #include "dcn20_dsc.h"
54 
55 #include "dcn20_link_encoder.h"
56 #include "dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "virtual/virtual_stream_encoder.h"
61 #include "dce110/dce110_resource.h"
62 #include "dml/display_mode_vba.h"
63 #include "dcn20_dccg.h"
64 #include "dcn20_vmid.h"
65 #include "dc_link_ddc.h"
66 #include "dce/dce_panel_cntl.h"
67 
68 #include "navi10_ip_offset.h"
69 
70 #include "dcn/dcn_2_0_0_offset.h"
71 #include "dcn/dcn_2_0_0_sh_mask.h"
72 #include "dpcs/dpcs_2_0_0_offset.h"
73 #include "dpcs/dpcs_2_0_0_sh_mask.h"
74 
75 #include "nbio/nbio_2_3_offset.h"
76 
77 #include "dcn20/dcn20_dwb.h"
78 #include "dcn20/dcn20_mmhubbub.h"
79 
80 #include "mmhub/mmhub_2_0_0_offset.h"
81 #include "mmhub/mmhub_2_0_0_sh_mask.h"
82 
83 #include "reg_helper.h"
84 #include "dce/dce_abm.h"
85 #include "dce/dce_dmcu.h"
86 #include "dce/dce_aux.h"
87 #include "dce/dce_i2c.h"
88 #include "vm_helper.h"
89 #include "link_enc_cfg.h"
90 
91 #include "amdgpu_socbb.h"
92 
93 #define DC_LOGGER_INIT(logger)
94 
95 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
96 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
97 	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
98 	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
99 	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
100 	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
101 	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
102 	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
103 	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
104 	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
105 	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
106 	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
107 	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
108 	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
109 	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
110 #endif
111 
112 
113 enum dcn20_clk_src_array_id {
114 	DCN20_CLK_SRC_PLL0,
115 	DCN20_CLK_SRC_PLL1,
116 	DCN20_CLK_SRC_PLL2,
117 	DCN20_CLK_SRC_PLL3,
118 	DCN20_CLK_SRC_PLL4,
119 	DCN20_CLK_SRC_PLL5,
120 	DCN20_CLK_SRC_TOTAL
121 };
122 
123 /* begin *********************
124  * macros to expend register list macro defined in HW object header file */
125 
126 /* DCN */
127 /* TODO awful hack. fixup dcn20_dwb.h */
128 #undef BASE_INNER
129 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
130 
131 #define BASE(seg) BASE_INNER(seg)
132 
133 #define SR(reg_name)\
134 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
135 					mm ## reg_name
136 
137 #define SRI(reg_name, block, id)\
138 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 					mm ## block ## id ## _ ## reg_name
140 
141 #define SRIR(var_name, reg_name, block, id)\
142 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 					mm ## block ## id ## _ ## reg_name
144 
145 #define SRII(reg_name, block, id)\
146 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 					mm ## block ## id ## _ ## reg_name
148 
149 #define DCCG_SRII(reg_name, block, id)\
150 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 					mm ## block ## id ## _ ## reg_name
152 
153 #define VUPDATE_SRII(reg_name, block, id)\
154 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
155 					mm ## reg_name ## _ ## block ## id
156 
157 /* NBIO */
158 #define NBIO_BASE_INNER(seg) \
159 	NBIO_BASE__INST0_SEG ## seg
160 
161 #define NBIO_BASE(seg) \
162 	NBIO_BASE_INNER(seg)
163 
164 #define NBIO_SR(reg_name)\
165 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
166 					mm ## reg_name
167 
168 /* MMHUB */
169 #define MMHUB_BASE_INNER(seg) \
170 	MMHUB_BASE__INST0_SEG ## seg
171 
172 #define MMHUB_BASE(seg) \
173 	MMHUB_BASE_INNER(seg)
174 
175 #define MMHUB_SR(reg_name)\
176 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
177 					mmMM ## reg_name
178 
179 static const struct bios_registers bios_regs = {
180 		NBIO_SR(BIOS_SCRATCH_3),
181 		NBIO_SR(BIOS_SCRATCH_6)
182 };
183 
184 #define clk_src_regs(index, pllid)\
185 [index] = {\
186 	CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
187 }
188 
189 static const struct dce110_clk_src_regs clk_src_regs[] = {
190 	clk_src_regs(0, A),
191 	clk_src_regs(1, B),
192 	clk_src_regs(2, C),
193 	clk_src_regs(3, D),
194 	clk_src_regs(4, E),
195 	clk_src_regs(5, F)
196 };
197 
198 static const struct dce110_clk_src_shift cs_shift = {
199 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
200 };
201 
202 static const struct dce110_clk_src_mask cs_mask = {
203 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
204 };
205 
206 static const struct dce_dmcu_registers dmcu_regs = {
207 		DMCU_DCN10_REG_LIST()
208 };
209 
210 static const struct dce_dmcu_shift dmcu_shift = {
211 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
212 };
213 
214 static const struct dce_dmcu_mask dmcu_mask = {
215 		DMCU_MASK_SH_LIST_DCN10(_MASK)
216 };
217 
218 static const struct dce_abm_registers abm_regs = {
219 		ABM_DCN20_REG_LIST()
220 };
221 
222 static const struct dce_abm_shift abm_shift = {
223 		ABM_MASK_SH_LIST_DCN20(__SHIFT)
224 };
225 
226 static const struct dce_abm_mask abm_mask = {
227 		ABM_MASK_SH_LIST_DCN20(_MASK)
228 };
229 
230 #define audio_regs(id)\
231 [id] = {\
232 		AUD_COMMON_REG_LIST(id)\
233 }
234 
235 static const struct dce_audio_registers audio_regs[] = {
236 	audio_regs(0),
237 	audio_regs(1),
238 	audio_regs(2),
239 	audio_regs(3),
240 	audio_regs(4),
241 	audio_regs(5),
242 	audio_regs(6),
243 };
244 
245 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
246 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
247 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
248 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
249 
250 static const struct dce_audio_shift audio_shift = {
251 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
252 };
253 
254 static const struct dce_audio_mask audio_mask = {
255 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
256 };
257 
258 #define stream_enc_regs(id)\
259 [id] = {\
260 	SE_DCN2_REG_LIST(id)\
261 }
262 
263 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
264 	stream_enc_regs(0),
265 	stream_enc_regs(1),
266 	stream_enc_regs(2),
267 	stream_enc_regs(3),
268 	stream_enc_regs(4),
269 	stream_enc_regs(5),
270 };
271 
272 static const struct dcn10_stream_encoder_shift se_shift = {
273 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
274 };
275 
276 static const struct dcn10_stream_encoder_mask se_mask = {
277 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
278 };
279 
280 
281 #define aux_regs(id)\
282 [id] = {\
283 	DCN2_AUX_REG_LIST(id)\
284 }
285 
286 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
287 		aux_regs(0),
288 		aux_regs(1),
289 		aux_regs(2),
290 		aux_regs(3),
291 		aux_regs(4),
292 		aux_regs(5)
293 };
294 
295 #define hpd_regs(id)\
296 [id] = {\
297 	HPD_REG_LIST(id)\
298 }
299 
300 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
301 		hpd_regs(0),
302 		hpd_regs(1),
303 		hpd_regs(2),
304 		hpd_regs(3),
305 		hpd_regs(4),
306 		hpd_regs(5)
307 };
308 
309 #define link_regs(id, phyid)\
310 [id] = {\
311 	LE_DCN10_REG_LIST(id), \
312 	UNIPHY_DCN2_REG_LIST(phyid), \
313 	DPCS_DCN2_REG_LIST(id), \
314 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
315 }
316 
317 static const struct dcn10_link_enc_registers link_enc_regs[] = {
318 	link_regs(0, A),
319 	link_regs(1, B),
320 	link_regs(2, C),
321 	link_regs(3, D),
322 	link_regs(4, E),
323 	link_regs(5, F)
324 };
325 
326 static const struct dcn10_link_enc_shift le_shift = {
327 	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
328 	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
329 };
330 
331 static const struct dcn10_link_enc_mask le_mask = {
332 	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
333 	DPCS_DCN2_MASK_SH_LIST(_MASK)
334 };
335 
336 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
337 	{ DCN_PANEL_CNTL_REG_LIST() }
338 };
339 
340 static const struct dce_panel_cntl_shift panel_cntl_shift = {
341 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
342 };
343 
344 static const struct dce_panel_cntl_mask panel_cntl_mask = {
345 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
346 };
347 
348 #define ipp_regs(id)\
349 [id] = {\
350 	IPP_REG_LIST_DCN20(id),\
351 }
352 
353 static const struct dcn10_ipp_registers ipp_regs[] = {
354 	ipp_regs(0),
355 	ipp_regs(1),
356 	ipp_regs(2),
357 	ipp_regs(3),
358 	ipp_regs(4),
359 	ipp_regs(5),
360 };
361 
362 static const struct dcn10_ipp_shift ipp_shift = {
363 		IPP_MASK_SH_LIST_DCN20(__SHIFT)
364 };
365 
366 static const struct dcn10_ipp_mask ipp_mask = {
367 		IPP_MASK_SH_LIST_DCN20(_MASK),
368 };
369 
370 #define opp_regs(id)\
371 [id] = {\
372 	OPP_REG_LIST_DCN20(id),\
373 }
374 
375 static const struct dcn20_opp_registers opp_regs[] = {
376 	opp_regs(0),
377 	opp_regs(1),
378 	opp_regs(2),
379 	opp_regs(3),
380 	opp_regs(4),
381 	opp_regs(5),
382 };
383 
384 static const struct dcn20_opp_shift opp_shift = {
385 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
386 };
387 
388 static const struct dcn20_opp_mask opp_mask = {
389 		OPP_MASK_SH_LIST_DCN20(_MASK)
390 };
391 
392 #define aux_engine_regs(id)\
393 [id] = {\
394 	AUX_COMMON_REG_LIST0(id), \
395 	.AUXN_IMPCAL = 0, \
396 	.AUXP_IMPCAL = 0, \
397 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
398 }
399 
400 static const struct dce110_aux_registers aux_engine_regs[] = {
401 		aux_engine_regs(0),
402 		aux_engine_regs(1),
403 		aux_engine_regs(2),
404 		aux_engine_regs(3),
405 		aux_engine_regs(4),
406 		aux_engine_regs(5)
407 };
408 
409 #define tf_regs(id)\
410 [id] = {\
411 	TF_REG_LIST_DCN20(id),\
412 	TF_REG_LIST_DCN20_COMMON_APPEND(id),\
413 }
414 
415 static const struct dcn2_dpp_registers tf_regs[] = {
416 	tf_regs(0),
417 	tf_regs(1),
418 	tf_regs(2),
419 	tf_regs(3),
420 	tf_regs(4),
421 	tf_regs(5),
422 };
423 
424 static const struct dcn2_dpp_shift tf_shift = {
425 		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
426 		TF_DEBUG_REG_LIST_SH_DCN20
427 };
428 
429 static const struct dcn2_dpp_mask tf_mask = {
430 		TF_REG_LIST_SH_MASK_DCN20(_MASK),
431 		TF_DEBUG_REG_LIST_MASK_DCN20
432 };
433 
434 #define dwbc_regs_dcn2(id)\
435 [id] = {\
436 	DWBC_COMMON_REG_LIST_DCN2_0(id),\
437 		}
438 
439 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
440 	dwbc_regs_dcn2(0),
441 };
442 
443 static const struct dcn20_dwbc_shift dwbc20_shift = {
444 	DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
445 };
446 
447 static const struct dcn20_dwbc_mask dwbc20_mask = {
448 	DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
449 };
450 
451 #define mcif_wb_regs_dcn2(id)\
452 [id] = {\
453 	MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
454 		}
455 
456 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
457 	mcif_wb_regs_dcn2(0),
458 };
459 
460 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
461 	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
462 };
463 
464 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
465 	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
466 };
467 
468 static const struct dcn20_mpc_registers mpc_regs = {
469 		MPC_REG_LIST_DCN2_0(0),
470 		MPC_REG_LIST_DCN2_0(1),
471 		MPC_REG_LIST_DCN2_0(2),
472 		MPC_REG_LIST_DCN2_0(3),
473 		MPC_REG_LIST_DCN2_0(4),
474 		MPC_REG_LIST_DCN2_0(5),
475 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
476 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
477 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
478 		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
479 		MPC_OUT_MUX_REG_LIST_DCN2_0(4),
480 		MPC_OUT_MUX_REG_LIST_DCN2_0(5),
481 		MPC_DBG_REG_LIST_DCN2_0()
482 };
483 
484 static const struct dcn20_mpc_shift mpc_shift = {
485 	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
486 	MPC_DEBUG_REG_LIST_SH_DCN20
487 };
488 
489 static const struct dcn20_mpc_mask mpc_mask = {
490 	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
491 	MPC_DEBUG_REG_LIST_MASK_DCN20
492 };
493 
494 #define tg_regs(id)\
495 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
496 
497 
498 static const struct dcn_optc_registers tg_regs[] = {
499 	tg_regs(0),
500 	tg_regs(1),
501 	tg_regs(2),
502 	tg_regs(3),
503 	tg_regs(4),
504 	tg_regs(5)
505 };
506 
507 static const struct dcn_optc_shift tg_shift = {
508 	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
509 };
510 
511 static const struct dcn_optc_mask tg_mask = {
512 	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
513 };
514 
515 #define hubp_regs(id)\
516 [id] = {\
517 	HUBP_REG_LIST_DCN20(id)\
518 }
519 
520 static const struct dcn_hubp2_registers hubp_regs[] = {
521 		hubp_regs(0),
522 		hubp_regs(1),
523 		hubp_regs(2),
524 		hubp_regs(3),
525 		hubp_regs(4),
526 		hubp_regs(5)
527 };
528 
529 static const struct dcn_hubp2_shift hubp_shift = {
530 		HUBP_MASK_SH_LIST_DCN20(__SHIFT)
531 };
532 
533 static const struct dcn_hubp2_mask hubp_mask = {
534 		HUBP_MASK_SH_LIST_DCN20(_MASK)
535 };
536 
537 static const struct dcn_hubbub_registers hubbub_reg = {
538 		HUBBUB_REG_LIST_DCN20(0)
539 };
540 
541 static const struct dcn_hubbub_shift hubbub_shift = {
542 		HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
543 };
544 
545 static const struct dcn_hubbub_mask hubbub_mask = {
546 		HUBBUB_MASK_SH_LIST_DCN20(_MASK)
547 };
548 
549 #define vmid_regs(id)\
550 [id] = {\
551 		DCN20_VMID_REG_LIST(id)\
552 }
553 
554 static const struct dcn_vmid_registers vmid_regs[] = {
555 	vmid_regs(0),
556 	vmid_regs(1),
557 	vmid_regs(2),
558 	vmid_regs(3),
559 	vmid_regs(4),
560 	vmid_regs(5),
561 	vmid_regs(6),
562 	vmid_regs(7),
563 	vmid_regs(8),
564 	vmid_regs(9),
565 	vmid_regs(10),
566 	vmid_regs(11),
567 	vmid_regs(12),
568 	vmid_regs(13),
569 	vmid_regs(14),
570 	vmid_regs(15)
571 };
572 
573 static const struct dcn20_vmid_shift vmid_shifts = {
574 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
575 };
576 
577 static const struct dcn20_vmid_mask vmid_masks = {
578 		DCN20_VMID_MASK_SH_LIST(_MASK)
579 };
580 
581 static const struct dce110_aux_registers_shift aux_shift = {
582 		DCN_AUX_MASK_SH_LIST(__SHIFT)
583 };
584 
585 static const struct dce110_aux_registers_mask aux_mask = {
586 		DCN_AUX_MASK_SH_LIST(_MASK)
587 };
588 
map_transmitter_id_to_phy_instance(enum transmitter transmitter)589 static int map_transmitter_id_to_phy_instance(
590 	enum transmitter transmitter)
591 {
592 	switch (transmitter) {
593 	case TRANSMITTER_UNIPHY_A:
594 		return 0;
595 	break;
596 	case TRANSMITTER_UNIPHY_B:
597 		return 1;
598 	break;
599 	case TRANSMITTER_UNIPHY_C:
600 		return 2;
601 	break;
602 	case TRANSMITTER_UNIPHY_D:
603 		return 3;
604 	break;
605 	case TRANSMITTER_UNIPHY_E:
606 		return 4;
607 	break;
608 	case TRANSMITTER_UNIPHY_F:
609 		return 5;
610 	break;
611 	default:
612 		ASSERT(0);
613 		return 0;
614 	}
615 }
616 
617 #define dsc_regsDCN20(id)\
618 [id] = {\
619 	DSC_REG_LIST_DCN20(id)\
620 }
621 
622 static const struct dcn20_dsc_registers dsc_regs[] = {
623 	dsc_regsDCN20(0),
624 	dsc_regsDCN20(1),
625 	dsc_regsDCN20(2),
626 	dsc_regsDCN20(3),
627 	dsc_regsDCN20(4),
628 	dsc_regsDCN20(5)
629 };
630 
631 static const struct dcn20_dsc_shift dsc_shift = {
632 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
633 };
634 
635 static const struct dcn20_dsc_mask dsc_mask = {
636 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
637 };
638 
639 static const struct dccg_registers dccg_regs = {
640 		DCCG_REG_LIST_DCN2()
641 };
642 
643 static const struct dccg_shift dccg_shift = {
644 		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
645 };
646 
647 static const struct dccg_mask dccg_mask = {
648 		DCCG_MASK_SH_LIST_DCN2(_MASK)
649 };
650 
651 static const struct resource_caps res_cap_nv10 = {
652 		.num_timing_generator = 6,
653 		.num_opp = 6,
654 		.num_video_plane = 6,
655 		.num_audio = 7,
656 		.num_stream_encoder = 6,
657 		.num_pll = 6,
658 		.num_dwb = 1,
659 		.num_ddc = 6,
660 		.num_vmid = 16,
661 		.num_dsc = 6,
662 };
663 
664 static const struct dc_plane_cap plane_cap = {
665 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
666 	.blends_with_above = true,
667 	.blends_with_below = true,
668 	.per_pixel_alpha = true,
669 
670 	.pixel_format_support = {
671 			.argb8888 = true,
672 			.nv12 = true,
673 			.fp16 = true,
674 			.p010 = true
675 	},
676 
677 	.max_upscale_factor = {
678 			.argb8888 = 16000,
679 			.nv12 = 16000,
680 			.fp16 = 1
681 	},
682 
683 	.max_downscale_factor = {
684 			.argb8888 = 250,
685 			.nv12 = 250,
686 			.fp16 = 1
687 	},
688 	16,
689 	16
690 };
691 static const struct resource_caps res_cap_nv14 = {
692 		.num_timing_generator = 5,
693 		.num_opp = 5,
694 		.num_video_plane = 5,
695 		.num_audio = 6,
696 		.num_stream_encoder = 5,
697 		.num_pll = 5,
698 		.num_dwb = 1,
699 		.num_ddc = 5,
700 		.num_vmid = 16,
701 		.num_dsc = 5,
702 };
703 
704 static const struct dc_debug_options debug_defaults_drv = {
705 		.disable_dmcu = false,
706 		.force_abm_enable = false,
707 		.timing_trace = false,
708 		.clock_trace = true,
709 		.disable_pplib_clock_request = true,
710 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
711 		.force_single_disp_pipe_split = false,
712 		.disable_dcc = DCC_ENABLE,
713 		.vsr_support = true,
714 		.performance_trace = false,
715 		.max_downscale_src_width = 5120,/*upto 5K*/
716 		.disable_pplib_wm_range = false,
717 		.scl_reset_length10 = true,
718 		.sanity_checks = false,
719 		.underflow_assert_delay_us = 0xFFFFFFFF,
720 };
721 
722 static const struct dc_debug_options debug_defaults_diags = {
723 		.disable_dmcu = false,
724 		.force_abm_enable = false,
725 		.timing_trace = true,
726 		.clock_trace = true,
727 		.disable_dpp_power_gate = true,
728 		.disable_hubp_power_gate = true,
729 		.disable_clock_gate = true,
730 		.disable_pplib_clock_request = true,
731 		.disable_pplib_wm_range = true,
732 		.disable_stutter = true,
733 		.scl_reset_length10 = true,
734 		.underflow_assert_delay_us = 0xFFFFFFFF,
735 		.enable_tri_buf = true,
736 };
737 
dcn20_dpp_destroy(struct dpp ** dpp)738 void dcn20_dpp_destroy(struct dpp **dpp)
739 {
740 	kfree(TO_DCN20_DPP(*dpp));
741 	*dpp = NULL;
742 }
743 
dcn20_dpp_create(struct dc_context * ctx,uint32_t inst)744 struct dpp *dcn20_dpp_create(
745 	struct dc_context *ctx,
746 	uint32_t inst)
747 {
748 	struct dcn20_dpp *dpp =
749 		kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
750 
751 	if (!dpp)
752 		return NULL;
753 
754 	if (dpp2_construct(dpp, ctx, inst,
755 			&tf_regs[inst], &tf_shift, &tf_mask))
756 		return &dpp->base;
757 
758 	BREAK_TO_DEBUGGER();
759 	kfree(dpp);
760 	return NULL;
761 }
762 
dcn20_ipp_create(struct dc_context * ctx,uint32_t inst)763 struct input_pixel_processor *dcn20_ipp_create(
764 	struct dc_context *ctx, uint32_t inst)
765 {
766 	struct dcn10_ipp *ipp =
767 		kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
768 
769 	if (!ipp) {
770 		BREAK_TO_DEBUGGER();
771 		return NULL;
772 	}
773 
774 	dcn20_ipp_construct(ipp, ctx, inst,
775 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
776 	return &ipp->base;
777 }
778 
779 
dcn20_opp_create(struct dc_context * ctx,uint32_t inst)780 struct output_pixel_processor *dcn20_opp_create(
781 	struct dc_context *ctx, uint32_t inst)
782 {
783 	struct dcn20_opp *opp =
784 		kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
785 
786 	if (!opp) {
787 		BREAK_TO_DEBUGGER();
788 		return NULL;
789 	}
790 
791 	dcn20_opp_construct(opp, ctx, inst,
792 			&opp_regs[inst], &opp_shift, &opp_mask);
793 	return &opp->base;
794 }
795 
dcn20_aux_engine_create(struct dc_context * ctx,uint32_t inst)796 struct dce_aux *dcn20_aux_engine_create(
797 	struct dc_context *ctx,
798 	uint32_t inst)
799 {
800 	struct aux_engine_dce110 *aux_engine =
801 		kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
802 
803 	if (!aux_engine)
804 		return NULL;
805 
806 	dce110_aux_engine_construct(aux_engine, ctx, inst,
807 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
808 				    &aux_engine_regs[inst],
809 					&aux_mask,
810 					&aux_shift,
811 					ctx->dc->caps.extended_aux_timeout_support);
812 
813 	return &aux_engine->base;
814 }
815 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
816 
817 static const struct dce_i2c_registers i2c_hw_regs[] = {
818 		i2c_inst_regs(1),
819 		i2c_inst_regs(2),
820 		i2c_inst_regs(3),
821 		i2c_inst_regs(4),
822 		i2c_inst_regs(5),
823 		i2c_inst_regs(6),
824 };
825 
826 static const struct dce_i2c_shift i2c_shifts = {
827 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
828 };
829 
830 static const struct dce_i2c_mask i2c_masks = {
831 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
832 };
833 
dcn20_i2c_hw_create(struct dc_context * ctx,uint32_t inst)834 struct dce_i2c_hw *dcn20_i2c_hw_create(
835 	struct dc_context *ctx,
836 	uint32_t inst)
837 {
838 	struct dce_i2c_hw *dce_i2c_hw =
839 		kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
840 
841 	if (!dce_i2c_hw)
842 		return NULL;
843 
844 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
845 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
846 
847 	return dce_i2c_hw;
848 }
dcn20_mpc_create(struct dc_context * ctx)849 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
850 {
851 	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
852 					  GFP_ATOMIC);
853 
854 	if (!mpc20)
855 		return NULL;
856 
857 	dcn20_mpc_construct(mpc20, ctx,
858 			&mpc_regs,
859 			&mpc_shift,
860 			&mpc_mask,
861 			6);
862 
863 	return &mpc20->base;
864 }
865 
dcn20_hubbub_create(struct dc_context * ctx)866 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
867 {
868 	int i;
869 	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
870 					  GFP_ATOMIC);
871 
872 	if (!hubbub)
873 		return NULL;
874 
875 	hubbub2_construct(hubbub, ctx,
876 			&hubbub_reg,
877 			&hubbub_shift,
878 			&hubbub_mask);
879 
880 	for (i = 0; i < res_cap_nv10.num_vmid; i++) {
881 		struct dcn20_vmid *vmid = &hubbub->vmid[i];
882 
883 		vmid->ctx = ctx;
884 
885 		vmid->regs = &vmid_regs[i];
886 		vmid->shifts = &vmid_shifts;
887 		vmid->masks = &vmid_masks;
888 	}
889 
890 	return &hubbub->base;
891 }
892 
dcn20_timing_generator_create(struct dc_context * ctx,uint32_t instance)893 struct timing_generator *dcn20_timing_generator_create(
894 		struct dc_context *ctx,
895 		uint32_t instance)
896 {
897 	struct optc *tgn10 =
898 		kzalloc(sizeof(struct optc), GFP_ATOMIC);
899 
900 	if (!tgn10)
901 		return NULL;
902 
903 	tgn10->base.inst = instance;
904 	tgn10->base.ctx = ctx;
905 
906 	tgn10->tg_regs = &tg_regs[instance];
907 	tgn10->tg_shift = &tg_shift;
908 	tgn10->tg_mask = &tg_mask;
909 
910 	dcn20_timing_generator_init(tgn10);
911 
912 	return &tgn10->base;
913 }
914 
915 static const struct encoder_feature_support link_enc_feature = {
916 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
917 		.max_hdmi_pixel_clock = 600000,
918 		.hdmi_ycbcr420_supported = true,
919 		.dp_ycbcr420_supported = true,
920 		.fec_supported = true,
921 		.flags.bits.IS_HBR2_CAPABLE = true,
922 		.flags.bits.IS_HBR3_CAPABLE = true,
923 		.flags.bits.IS_TPS3_CAPABLE = true,
924 		.flags.bits.IS_TPS4_CAPABLE = true
925 };
926 
dcn20_link_encoder_create(const struct encoder_init_data * enc_init_data)927 struct link_encoder *dcn20_link_encoder_create(
928 	const struct encoder_init_data *enc_init_data)
929 {
930 	struct dcn20_link_encoder *enc20 =
931 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
932 	int link_regs_id;
933 
934 	if (!enc20)
935 		return NULL;
936 
937 	link_regs_id =
938 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
939 
940 	dcn20_link_encoder_construct(enc20,
941 				      enc_init_data,
942 				      &link_enc_feature,
943 				      &link_enc_regs[link_regs_id],
944 				      &link_enc_aux_regs[enc_init_data->channel - 1],
945 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
946 				      &le_shift,
947 				      &le_mask);
948 
949 	return &enc20->enc10.base;
950 }
951 
dcn20_panel_cntl_create(const struct panel_cntl_init_data * init_data)952 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
953 {
954 	struct dce_panel_cntl *panel_cntl =
955 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
956 
957 	if (!panel_cntl)
958 		return NULL;
959 
960 	dce_panel_cntl_construct(panel_cntl,
961 			init_data,
962 			&panel_cntl_regs[init_data->inst],
963 			&panel_cntl_shift,
964 			&panel_cntl_mask);
965 
966 	return &panel_cntl->base;
967 }
968 
dcn20_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)969 static struct clock_source *dcn20_clock_source_create(
970 	struct dc_context *ctx,
971 	struct dc_bios *bios,
972 	enum clock_source_id id,
973 	const struct dce110_clk_src_regs *regs,
974 	bool dp_clk_src)
975 {
976 	struct dce110_clk_src *clk_src =
977 		kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
978 
979 	if (!clk_src)
980 		return NULL;
981 
982 	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
983 			regs, &cs_shift, &cs_mask)) {
984 		clk_src->base.dp_clk_src = dp_clk_src;
985 		return &clk_src->base;
986 	}
987 
988 	kfree(clk_src);
989 	BREAK_TO_DEBUGGER();
990 	return NULL;
991 }
992 
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)993 static void read_dce_straps(
994 	struct dc_context *ctx,
995 	struct resource_straps *straps)
996 {
997 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
998 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
999 }
1000 
dcn20_create_audio(struct dc_context * ctx,unsigned int inst)1001 static struct audio *dcn20_create_audio(
1002 		struct dc_context *ctx, unsigned int inst)
1003 {
1004 	return dce_audio_create(ctx, inst,
1005 			&audio_regs[inst], &audio_shift, &audio_mask);
1006 }
1007 
dcn20_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1008 struct stream_encoder *dcn20_stream_encoder_create(
1009 	enum engine_id eng_id,
1010 	struct dc_context *ctx)
1011 {
1012 	struct dcn10_stream_encoder *enc1 =
1013 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1014 
1015 	if (!enc1)
1016 		return NULL;
1017 
1018 	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1019 		if (eng_id >= ENGINE_ID_DIGD)
1020 			eng_id++;
1021 	}
1022 
1023 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1024 					&stream_enc_regs[eng_id],
1025 					&se_shift, &se_mask);
1026 
1027 	return &enc1->base;
1028 }
1029 
1030 static const struct dce_hwseq_registers hwseq_reg = {
1031 		HWSEQ_DCN2_REG_LIST()
1032 };
1033 
1034 static const struct dce_hwseq_shift hwseq_shift = {
1035 		HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1036 };
1037 
1038 static const struct dce_hwseq_mask hwseq_mask = {
1039 		HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1040 };
1041 
dcn20_hwseq_create(struct dc_context * ctx)1042 struct dce_hwseq *dcn20_hwseq_create(
1043 	struct dc_context *ctx)
1044 {
1045 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1046 
1047 	if (hws) {
1048 		hws->ctx = ctx;
1049 		hws->regs = &hwseq_reg;
1050 		hws->shifts = &hwseq_shift;
1051 		hws->masks = &hwseq_mask;
1052 	}
1053 	return hws;
1054 }
1055 
1056 static const struct resource_create_funcs res_create_funcs = {
1057 	.read_dce_straps = read_dce_straps,
1058 	.create_audio = dcn20_create_audio,
1059 	.create_stream_encoder = dcn20_stream_encoder_create,
1060 	.create_hwseq = dcn20_hwseq_create,
1061 };
1062 
1063 static const struct resource_create_funcs res_create_maximus_funcs = {
1064 	.read_dce_straps = NULL,
1065 	.create_audio = NULL,
1066 	.create_stream_encoder = NULL,
1067 	.create_hwseq = dcn20_hwseq_create,
1068 };
1069 
1070 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1071 
dcn20_clock_source_destroy(struct clock_source ** clk_src)1072 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1073 {
1074 	kfree(TO_DCE110_CLK_SRC(*clk_src));
1075 	*clk_src = NULL;
1076 }
1077 
1078 
dcn20_dsc_create(struct dc_context * ctx,uint32_t inst)1079 struct display_stream_compressor *dcn20_dsc_create(
1080 	struct dc_context *ctx, uint32_t inst)
1081 {
1082 	struct dcn20_dsc *dsc =
1083 		kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);
1084 
1085 	if (!dsc) {
1086 		BREAK_TO_DEBUGGER();
1087 		return NULL;
1088 	}
1089 
1090 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1091 	return &dsc->base;
1092 }
1093 
dcn20_dsc_destroy(struct display_stream_compressor ** dsc)1094 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1095 {
1096 	kfree(container_of(*dsc, struct dcn20_dsc, base));
1097 	*dsc = NULL;
1098 }
1099 
1100 
dcn20_resource_destruct(struct dcn20_resource_pool * pool)1101 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1102 {
1103 	unsigned int i;
1104 
1105 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1106 		if (pool->base.stream_enc[i] != NULL) {
1107 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1108 			pool->base.stream_enc[i] = NULL;
1109 		}
1110 	}
1111 
1112 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1113 		if (pool->base.dscs[i] != NULL)
1114 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1115 	}
1116 
1117 	if (pool->base.mpc != NULL) {
1118 		kfree(TO_DCN20_MPC(pool->base.mpc));
1119 		pool->base.mpc = NULL;
1120 	}
1121 	if (pool->base.hubbub != NULL) {
1122 		kfree(pool->base.hubbub);
1123 		pool->base.hubbub = NULL;
1124 	}
1125 	for (i = 0; i < pool->base.pipe_count; i++) {
1126 		if (pool->base.dpps[i] != NULL)
1127 			dcn20_dpp_destroy(&pool->base.dpps[i]);
1128 
1129 		if (pool->base.ipps[i] != NULL)
1130 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1131 
1132 		if (pool->base.hubps[i] != NULL) {
1133 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1134 			pool->base.hubps[i] = NULL;
1135 		}
1136 
1137 		if (pool->base.irqs != NULL) {
1138 			dal_irq_service_destroy(&pool->base.irqs);
1139 		}
1140 	}
1141 
1142 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1143 		if (pool->base.engines[i] != NULL)
1144 			dce110_engine_destroy(&pool->base.engines[i]);
1145 		if (pool->base.hw_i2cs[i] != NULL) {
1146 			kfree(pool->base.hw_i2cs[i]);
1147 			pool->base.hw_i2cs[i] = NULL;
1148 		}
1149 		if (pool->base.sw_i2cs[i] != NULL) {
1150 			kfree(pool->base.sw_i2cs[i]);
1151 			pool->base.sw_i2cs[i] = NULL;
1152 		}
1153 	}
1154 
1155 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1156 		if (pool->base.opps[i] != NULL)
1157 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1158 	}
1159 
1160 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1161 		if (pool->base.timing_generators[i] != NULL)	{
1162 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1163 			pool->base.timing_generators[i] = NULL;
1164 		}
1165 	}
1166 
1167 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1168 		if (pool->base.dwbc[i] != NULL) {
1169 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1170 			pool->base.dwbc[i] = NULL;
1171 		}
1172 		if (pool->base.mcif_wb[i] != NULL) {
1173 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1174 			pool->base.mcif_wb[i] = NULL;
1175 		}
1176 	}
1177 
1178 	for (i = 0; i < pool->base.audio_count; i++) {
1179 		if (pool->base.audios[i])
1180 			dce_aud_destroy(&pool->base.audios[i]);
1181 	}
1182 
1183 	for (i = 0; i < pool->base.clk_src_count; i++) {
1184 		if (pool->base.clock_sources[i] != NULL) {
1185 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1186 			pool->base.clock_sources[i] = NULL;
1187 		}
1188 	}
1189 
1190 	if (pool->base.dp_clock_source != NULL) {
1191 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1192 		pool->base.dp_clock_source = NULL;
1193 	}
1194 
1195 
1196 	if (pool->base.abm != NULL)
1197 		dce_abm_destroy(&pool->base.abm);
1198 
1199 	if (pool->base.dmcu != NULL)
1200 		dce_dmcu_destroy(&pool->base.dmcu);
1201 
1202 	if (pool->base.dccg != NULL)
1203 		dcn_dccg_destroy(&pool->base.dccg);
1204 
1205 	if (pool->base.pp_smu != NULL)
1206 		dcn20_pp_smu_destroy(&pool->base.pp_smu);
1207 
1208 	if (pool->base.oem_device != NULL)
1209 		dal_ddc_service_destroy(&pool->base.oem_device);
1210 }
1211 
dcn20_hubp_create(struct dc_context * ctx,uint32_t inst)1212 struct hubp *dcn20_hubp_create(
1213 	struct dc_context *ctx,
1214 	uint32_t inst)
1215 {
1216 	struct dcn20_hubp *hubp2 =
1217 		kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);
1218 
1219 	if (!hubp2)
1220 		return NULL;
1221 
1222 	if (hubp2_construct(hubp2, ctx, inst,
1223 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1224 		return &hubp2->base;
1225 
1226 	BREAK_TO_DEBUGGER();
1227 	kfree(hubp2);
1228 	return NULL;
1229 }
1230 
get_pixel_clock_parameters(struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)1231 static void get_pixel_clock_parameters(
1232 	struct pipe_ctx *pipe_ctx,
1233 	struct pixel_clk_params *pixel_clk_params)
1234 {
1235 	const struct dc_stream_state *stream = pipe_ctx->stream;
1236 	struct pipe_ctx *odm_pipe;
1237 	int opp_cnt = 1;
1238 	struct dc_link *link = stream->link;
1239 	struct link_encoder *link_enc = NULL;
1240 
1241 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1242 		opp_cnt++;
1243 
1244 	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1245 
1246 	link_enc = link_enc_cfg_get_link_enc(link);
1247 	ASSERT(link_enc);
1248 
1249 	if (link_enc)
1250 		pixel_clk_params->encoder_object_id = link_enc->id;
1251 	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1252 	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1253 	/* TODO: un-hardcode*/
1254 	/* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1255 	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1256 		LINK_RATE_REF_FREQ_IN_KHZ;
1257 	pixel_clk_params->flags.ENABLE_SS = 0;
1258 	pixel_clk_params->color_depth =
1259 		stream->timing.display_color_depth;
1260 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1261 	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1262 
1263 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1264 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
1265 
1266 	if (opp_cnt == 4)
1267 		pixel_clk_params->requested_pix_clk_100hz /= 4;
1268 	else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1269 		pixel_clk_params->requested_pix_clk_100hz /= 2;
1270 
1271 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1272 		pixel_clk_params->requested_pix_clk_100hz *= 2;
1273 
1274 }
1275 
build_clamping_params(struct dc_stream_state * stream)1276 static void build_clamping_params(struct dc_stream_state *stream)
1277 {
1278 	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1279 	stream->clamping.c_depth = stream->timing.display_color_depth;
1280 	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1281 }
1282 
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1283 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1284 {
1285 
1286 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1287 
1288 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1289 		pipe_ctx->clock_source,
1290 		&pipe_ctx->stream_res.pix_clk_params,
1291 		&pipe_ctx->pll_settings);
1292 
1293 	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1294 
1295 	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1296 					&pipe_ctx->stream->bit_depth_params);
1297 	build_clamping_params(pipe_ctx->stream);
1298 
1299 	return DC_OK;
1300 }
1301 
dcn20_build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1302 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1303 {
1304 	enum dc_status status = DC_OK;
1305 	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1306 
1307 	if (!pipe_ctx)
1308 		return DC_ERROR_UNEXPECTED;
1309 
1310 
1311 	status = build_pipe_hw_param(pipe_ctx);
1312 
1313 	return status;
1314 }
1315 
1316 
dcn20_acquire_dsc(const struct dc * dc,struct resource_context * res_ctx,struct display_stream_compressor ** dsc,int pipe_idx)1317 void dcn20_acquire_dsc(const struct dc *dc,
1318 			struct resource_context *res_ctx,
1319 			struct display_stream_compressor **dsc,
1320 			int pipe_idx)
1321 {
1322 	int i;
1323 	const struct resource_pool *pool = dc->res_pool;
1324 	struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
1325 
1326 	ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
1327 	*dsc = NULL;
1328 
1329 	/* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
1330 	if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1331 		*dsc = pool->dscs[pipe_idx];
1332 		res_ctx->is_dsc_acquired[pipe_idx] = true;
1333 		return;
1334 	}
1335 
1336 	/* Return old DSC to avoid the need for re-programming */
1337 	if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1338 		*dsc = dsc_old;
1339 		res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1340 		return ;
1341 	}
1342 
1343 	/* Find first free DSC */
1344 	for (i = 0; i < pool->res_cap->num_dsc; i++)
1345 		if (!res_ctx->is_dsc_acquired[i]) {
1346 			*dsc = pool->dscs[i];
1347 			res_ctx->is_dsc_acquired[i] = true;
1348 			break;
1349 		}
1350 }
1351 
dcn20_release_dsc(struct resource_context * res_ctx,const struct resource_pool * pool,struct display_stream_compressor ** dsc)1352 void dcn20_release_dsc(struct resource_context *res_ctx,
1353 			const struct resource_pool *pool,
1354 			struct display_stream_compressor **dsc)
1355 {
1356 	int i;
1357 
1358 	for (i = 0; i < pool->res_cap->num_dsc; i++)
1359 		if (pool->dscs[i] == *dsc) {
1360 			res_ctx->is_dsc_acquired[i] = false;
1361 			*dsc = NULL;
1362 			break;
1363 		}
1364 }
1365 
1366 
1367 
dcn20_add_dsc_to_stream_resource(struct dc * dc,struct dc_state * dc_ctx,struct dc_stream_state * dc_stream)1368 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1369 		struct dc_state *dc_ctx,
1370 		struct dc_stream_state *dc_stream)
1371 {
1372 	enum dc_status result = DC_OK;
1373 	int i;
1374 
1375 	/* Get a DSC if required and available */
1376 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1377 		struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1378 
1379 		if (pipe_ctx->stream != dc_stream)
1380 			continue;
1381 
1382 		if (pipe_ctx->stream_res.dsc)
1383 			continue;
1384 
1385 		dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
1386 
1387 		/* The number of DSCs can be less than the number of pipes */
1388 		if (!pipe_ctx->stream_res.dsc) {
1389 			result = DC_NO_DSC_RESOURCE;
1390 		}
1391 
1392 		break;
1393 	}
1394 
1395 	return result;
1396 }
1397 
1398 
remove_dsc_from_stream_resource(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1399 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1400 		struct dc_state *new_ctx,
1401 		struct dc_stream_state *dc_stream)
1402 {
1403 	struct pipe_ctx *pipe_ctx = NULL;
1404 	int i;
1405 
1406 	for (i = 0; i < MAX_PIPES; i++) {
1407 		if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1408 			pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1409 
1410 			if (pipe_ctx->stream_res.dsc)
1411 				dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1412 		}
1413 	}
1414 
1415 	if (!pipe_ctx)
1416 		return DC_ERROR_UNEXPECTED;
1417 	else
1418 		return DC_OK;
1419 }
1420 
1421 
dcn20_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1422 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1423 {
1424 	enum dc_status result = DC_ERROR_UNEXPECTED;
1425 
1426 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1427 
1428 	if (result == DC_OK)
1429 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1430 
1431 	/* Get a DSC if required and available */
1432 	if (result == DC_OK && dc_stream->timing.flags.DSC)
1433 		result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1434 
1435 	if (result == DC_OK)
1436 		result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1437 
1438 	return result;
1439 }
1440 
1441 
dcn20_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1442 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1443 {
1444 	enum dc_status result = DC_OK;
1445 
1446 	result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1447 
1448 	return result;
1449 }
1450 
dcn20_split_stream_for_odm(const struct dc * dc,struct resource_context * res_ctx,struct pipe_ctx * prev_odm_pipe,struct pipe_ctx * next_odm_pipe)1451 bool dcn20_split_stream_for_odm(
1452 		const struct dc *dc,
1453 		struct resource_context *res_ctx,
1454 		struct pipe_ctx *prev_odm_pipe,
1455 		struct pipe_ctx *next_odm_pipe)
1456 {
1457 	int pipe_idx = next_odm_pipe->pipe_idx;
1458 	const struct resource_pool *pool = dc->res_pool;
1459 
1460 	*next_odm_pipe = *prev_odm_pipe;
1461 
1462 	next_odm_pipe->pipe_idx = pipe_idx;
1463 	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1464 	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1465 	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1466 	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1467 	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1468 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1469 	next_odm_pipe->stream_res.dsc = NULL;
1470 	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1471 		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1472 		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1473 	}
1474 	if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1475 		prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1476 		next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1477 	}
1478 	if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1479 		prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1480 		next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1481 	}
1482 	prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1483 	next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1484 
1485 	if (prev_odm_pipe->plane_state) {
1486 		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1487 		int new_width;
1488 
1489 		/* HACTIVE halved for odm combine */
1490 		sd->h_active /= 2;
1491 		/* Calculate new vp and recout for left pipe */
1492 		/* Need at least 16 pixels width per side */
1493 		if (sd->recout.x + 16 >= sd->h_active)
1494 			return false;
1495 		new_width = sd->h_active - sd->recout.x;
1496 		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1497 				sd->ratios.horz, sd->recout.width - new_width));
1498 		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1499 				sd->ratios.horz_c, sd->recout.width - new_width));
1500 		sd->recout.width = new_width;
1501 
1502 		/* Calculate new vp and recout for right pipe */
1503 		sd = &next_odm_pipe->plane_res.scl_data;
1504 		/* HACTIVE halved for odm combine */
1505 		sd->h_active /= 2;
1506 		/* Need at least 16 pixels width per side */
1507 		if (new_width <= 16)
1508 			return false;
1509 		new_width = sd->recout.width + sd->recout.x - sd->h_active;
1510 		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1511 				sd->ratios.horz, sd->recout.width - new_width));
1512 		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1513 				sd->ratios.horz_c, sd->recout.width - new_width));
1514 		sd->recout.width = new_width;
1515 		sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1516 				sd->ratios.horz, sd->h_active - sd->recout.x));
1517 		sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1518 				sd->ratios.horz_c, sd->h_active - sd->recout.x));
1519 		sd->recout.x = 0;
1520 	}
1521 	if (!next_odm_pipe->top_pipe)
1522 		next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1523 	else
1524 		next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
1525 	if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
1526 		dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1527 		ASSERT(next_odm_pipe->stream_res.dsc);
1528 		if (next_odm_pipe->stream_res.dsc == NULL)
1529 			return false;
1530 	}
1531 
1532 	return true;
1533 }
1534 
dcn20_split_stream_for_mpc(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * primary_pipe,struct pipe_ctx * secondary_pipe)1535 void dcn20_split_stream_for_mpc(
1536 		struct resource_context *res_ctx,
1537 		const struct resource_pool *pool,
1538 		struct pipe_ctx *primary_pipe,
1539 		struct pipe_ctx *secondary_pipe)
1540 {
1541 	int pipe_idx = secondary_pipe->pipe_idx;
1542 	struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1543 
1544 	*secondary_pipe = *primary_pipe;
1545 	secondary_pipe->bottom_pipe = sec_bot_pipe;
1546 
1547 	secondary_pipe->pipe_idx = pipe_idx;
1548 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1549 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1550 	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1551 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1552 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1553 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1554 	secondary_pipe->stream_res.dsc = NULL;
1555 	if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1556 		ASSERT(!secondary_pipe->bottom_pipe);
1557 		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1558 		secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1559 	}
1560 	primary_pipe->bottom_pipe = secondary_pipe;
1561 	secondary_pipe->top_pipe = primary_pipe;
1562 
1563 	ASSERT(primary_pipe->plane_state);
1564 }
1565 
dcn20_calc_max_scaled_time(unsigned int time_per_pixel,enum mmhubbub_wbif_mode mode,unsigned int urgent_watermark)1566 unsigned int dcn20_calc_max_scaled_time(
1567 		unsigned int time_per_pixel,
1568 		enum mmhubbub_wbif_mode mode,
1569 		unsigned int urgent_watermark)
1570 {
1571 	unsigned int time_per_byte = 0;
1572 	unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
1573 	unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
1574 	unsigned int small_free_entry, max_free_entry;
1575 	unsigned int buf_lh_capability;
1576 	unsigned int max_scaled_time;
1577 
1578 	if (mode == PACKED_444) /* packed mode */
1579 		time_per_byte = time_per_pixel/4;
1580 	else if (mode == PLANAR_420_8BPC)
1581 		time_per_byte  = time_per_pixel;
1582 	else if (mode == PLANAR_420_10BPC) /* p010 */
1583 		time_per_byte  = time_per_pixel * 819/1024;
1584 
1585 	if (time_per_byte == 0)
1586 		time_per_byte = 1;
1587 
1588 	small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
1589 	max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
1590 	buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
1591 	max_scaled_time   = buf_lh_capability - urgent_watermark;
1592 	return max_scaled_time;
1593 }
1594 
dcn20_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1595 void dcn20_set_mcif_arb_params(
1596 		struct dc *dc,
1597 		struct dc_state *context,
1598 		display_e2e_pipe_params_st *pipes,
1599 		int pipe_cnt)
1600 {
1601 	enum mmhubbub_wbif_mode wbif_mode;
1602 	struct mcif_arb_params *wb_arb_params;
1603 	int i, j, dwb_pipe;
1604 
1605 	/* Writeback MCIF_WB arbitration parameters */
1606 	dwb_pipe = 0;
1607 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1608 
1609 		if (!context->res_ctx.pipe_ctx[i].stream)
1610 			continue;
1611 
1612 		for (j = 0; j < MAX_DWB_PIPES; j++) {
1613 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
1614 				continue;
1615 
1616 			//wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1617 			wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1618 
1619 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
1620 				if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1621 					wbif_mode = PLANAR_420_8BPC;
1622 				else
1623 					wbif_mode = PLANAR_420_10BPC;
1624 			} else
1625 				wbif_mode = PACKED_444;
1626 
1627 			DC_FP_START();
1628 			dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i);
1629 			DC_FP_END();
1630 
1631 			wb_arb_params->slice_lines = 32;
1632 			wb_arb_params->arbitration_slice = 2;
1633 			wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1634 				wbif_mode,
1635 				wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1636 
1637 			dwb_pipe++;
1638 
1639 			if (dwb_pipe >= MAX_DWB_PIPES)
1640 				return;
1641 		}
1642 		if (dwb_pipe >= MAX_DWB_PIPES)
1643 			return;
1644 	}
1645 }
1646 
dcn20_validate_dsc(struct dc * dc,struct dc_state * new_ctx)1647 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
1648 {
1649 	int i;
1650 
1651 	/* Validate DSC config, dsc count validation is already done */
1652 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1653 		struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1654 		struct dc_stream_state *stream = pipe_ctx->stream;
1655 		struct dsc_config dsc_cfg;
1656 		struct pipe_ctx *odm_pipe;
1657 		int opp_cnt = 1;
1658 
1659 		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1660 			opp_cnt++;
1661 
1662 		/* Only need to validate top pipe */
1663 		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
1664 			continue;
1665 
1666 		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
1667 				+ stream->timing.h_border_right) / opp_cnt;
1668 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
1669 				+ stream->timing.v_border_bottom;
1670 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1671 		dsc_cfg.color_depth = stream->timing.display_color_depth;
1672 		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1673 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1674 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1675 
1676 		if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
1677 			return false;
1678 	}
1679 	return true;
1680 }
1681 
dcn20_find_secondary_pipe(struct dc * dc,struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1682 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
1683 		struct resource_context *res_ctx,
1684 		const struct resource_pool *pool,
1685 		const struct pipe_ctx *primary_pipe)
1686 {
1687 	struct pipe_ctx *secondary_pipe = NULL;
1688 
1689 	if (dc && primary_pipe) {
1690 		int j;
1691 		int preferred_pipe_idx = 0;
1692 
1693 		/* first check the prev dc state:
1694 		 * if this primary pipe has a bottom pipe in prev. state
1695 		 * and if the bottom pipe is still available (which it should be),
1696 		 * pick that pipe as secondary
1697 		 * Same logic applies for ODM pipes
1698 		 */
1699 		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
1700 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
1701 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1702 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1703 				secondary_pipe->pipe_idx = preferred_pipe_idx;
1704 			}
1705 		}
1706 		if (secondary_pipe == NULL &&
1707 				dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
1708 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
1709 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1710 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1711 				secondary_pipe->pipe_idx = preferred_pipe_idx;
1712 			}
1713 		}
1714 
1715 		/*
1716 		 * if this primary pipe does not have a bottom pipe in prev. state
1717 		 * start backward and find a pipe that did not used to be a bottom pipe in
1718 		 * prev. dc state. This way we make sure we keep the same assignment as
1719 		 * last state and will not have to reprogram every pipe
1720 		 */
1721 		if (secondary_pipe == NULL) {
1722 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1723 				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
1724 						&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
1725 					preferred_pipe_idx = j;
1726 
1727 					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1728 						secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1729 						secondary_pipe->pipe_idx = preferred_pipe_idx;
1730 						break;
1731 					}
1732 				}
1733 			}
1734 		}
1735 		/*
1736 		 * We should never hit this assert unless assignments are shuffled around
1737 		 * if this happens we will prob. hit a vsync tdr
1738 		 */
1739 		ASSERT(secondary_pipe);
1740 		/*
1741 		 * search backwards for the second pipe to keep pipe
1742 		 * assignment more consistent
1743 		 */
1744 		if (secondary_pipe == NULL) {
1745 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1746 				preferred_pipe_idx = j;
1747 
1748 				if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1749 					secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1750 					secondary_pipe->pipe_idx = preferred_pipe_idx;
1751 					break;
1752 				}
1753 			}
1754 		}
1755 	}
1756 
1757 	return secondary_pipe;
1758 }
1759 
dcn20_merge_pipes_for_validate(struct dc * dc,struct dc_state * context)1760 void dcn20_merge_pipes_for_validate(
1761 		struct dc *dc,
1762 		struct dc_state *context)
1763 {
1764 	int i;
1765 
1766 	/* merge previously split odm pipes since mode support needs to make the decision */
1767 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1768 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1769 		struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
1770 
1771 		if (pipe->prev_odm_pipe)
1772 			continue;
1773 
1774 		pipe->next_odm_pipe = NULL;
1775 		while (odm_pipe) {
1776 			struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1777 
1778 			odm_pipe->plane_state = NULL;
1779 			odm_pipe->stream = NULL;
1780 			odm_pipe->top_pipe = NULL;
1781 			odm_pipe->bottom_pipe = NULL;
1782 			odm_pipe->prev_odm_pipe = NULL;
1783 			odm_pipe->next_odm_pipe = NULL;
1784 			if (odm_pipe->stream_res.dsc)
1785 				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
1786 			/* Clear plane_res and stream_res */
1787 			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
1788 			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
1789 			odm_pipe = next_odm_pipe;
1790 		}
1791 		if (pipe->plane_state)
1792 			resource_build_scaling_params(pipe);
1793 	}
1794 
1795 	/* merge previously mpc split pipes since mode support needs to make the decision */
1796 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1797 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1798 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1799 
1800 		if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
1801 			continue;
1802 
1803 		pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1804 		if (hsplit_pipe->bottom_pipe)
1805 			hsplit_pipe->bottom_pipe->top_pipe = pipe;
1806 		hsplit_pipe->plane_state = NULL;
1807 		hsplit_pipe->stream = NULL;
1808 		hsplit_pipe->top_pipe = NULL;
1809 		hsplit_pipe->bottom_pipe = NULL;
1810 
1811 		/* Clear plane_res and stream_res */
1812 		memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1813 		memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1814 		if (pipe->plane_state)
1815 			resource_build_scaling_params(pipe);
1816 	}
1817 }
1818 
dcn20_validate_apply_pipe_split_flags(struct dc * dc,struct dc_state * context,int vlevel,int * split,bool * merge)1819 int dcn20_validate_apply_pipe_split_flags(
1820 		struct dc *dc,
1821 		struct dc_state *context,
1822 		int vlevel,
1823 		int *split,
1824 		bool *merge)
1825 {
1826 	int i, pipe_idx, vlevel_split;
1827 	int plane_count = 0;
1828 	bool force_split = false;
1829 	bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
1830 	struct vba_vars_st *v = &context->bw_ctx.dml.vba;
1831 	int max_mpc_comb = v->maxMpcComb;
1832 
1833 	if (context->stream_count > 1) {
1834 		if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
1835 			avoid_split = true;
1836 	} else if (dc->debug.force_single_disp_pipe_split)
1837 			force_split = true;
1838 
1839 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1840 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1841 
1842 		/**
1843 		 * Workaround for avoiding pipe-split in cases where we'd split
1844 		 * planes that are too small, resulting in splits that aren't
1845 		 * valid for the scaler.
1846 		 */
1847 		if (pipe->plane_state &&
1848 		    (pipe->plane_state->dst_rect.width <= 16 ||
1849 		     pipe->plane_state->dst_rect.height <= 16 ||
1850 		     pipe->plane_state->src_rect.width <= 16 ||
1851 		     pipe->plane_state->src_rect.height <= 16))
1852 			avoid_split = true;
1853 
1854 		/* TODO: fix dc bugs and remove this split threshold thing */
1855 		if (pipe->stream && !pipe->prev_odm_pipe &&
1856 				(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
1857 			++plane_count;
1858 	}
1859 	if (plane_count > dc->res_pool->pipe_count / 2)
1860 		avoid_split = true;
1861 
1862 	/* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
1863 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1864 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1865 		struct dc_crtc_timing timing;
1866 
1867 		if (!pipe->stream)
1868 			continue;
1869 		else {
1870 			timing = pipe->stream->timing;
1871 			if (timing.h_border_left + timing.h_border_right
1872 					+ timing.v_border_top + timing.v_border_bottom > 0) {
1873 				avoid_split = true;
1874 				break;
1875 			}
1876 		}
1877 	}
1878 
1879 	/* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
1880 	if (avoid_split) {
1881 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1882 			if (!context->res_ctx.pipe_ctx[i].stream)
1883 				continue;
1884 
1885 			for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
1886 				if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
1887 						v->ModeSupport[vlevel][0])
1888 					break;
1889 			/* Impossible to not split this pipe */
1890 			if (vlevel > context->bw_ctx.dml.soc.num_states)
1891 				vlevel = vlevel_split;
1892 			else
1893 				max_mpc_comb = 0;
1894 			pipe_idx++;
1895 		}
1896 		v->maxMpcComb = max_mpc_comb;
1897 	}
1898 
1899 	/* Split loop sets which pipe should be split based on dml outputs and dc flags */
1900 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1901 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1902 		int pipe_plane = v->pipe_plane[pipe_idx];
1903 		bool split4mpc = context->stream_count == 1 && plane_count == 1
1904 				&& dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
1905 
1906 		if (!context->res_ctx.pipe_ctx[i].stream)
1907 			continue;
1908 
1909 		if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
1910 			split[i] = 4;
1911 		else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
1912 				split[i] = 2;
1913 
1914 		if ((pipe->stream->view_format ==
1915 				VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1916 				pipe->stream->view_format ==
1917 				VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1918 				(pipe->stream->timing.timing_3d_format ==
1919 				TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1920 				 pipe->stream->timing.timing_3d_format ==
1921 				TIMING_3D_FORMAT_SIDE_BY_SIDE))
1922 			split[i] = 2;
1923 		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
1924 			split[i] = 2;
1925 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
1926 		}
1927 		if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
1928 			split[i] = 4;
1929 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
1930 		}
1931 		/*420 format workaround*/
1932 		if (pipe->stream->timing.h_addressable > 7680 &&
1933 				pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1934 			split[i] = 4;
1935 		}
1936 		v->ODMCombineEnabled[pipe_plane] =
1937 			v->ODMCombineEnablePerState[vlevel][pipe_plane];
1938 
1939 		if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
1940 			if (get_num_mpc_splits(pipe) == 1) {
1941 				/*If need split for mpc but 2 way split already*/
1942 				if (split[i] == 4)
1943 					split[i] = 2; /* 2 -> 4 MPC */
1944 				else if (split[i] == 2)
1945 					split[i] = 0; /* 2 -> 2 MPC */
1946 				else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1947 					merge[i] = true; /* 2 -> 1 MPC */
1948 			} else if (get_num_mpc_splits(pipe) == 3) {
1949 				/*If need split for mpc but 4 way split already*/
1950 				if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
1951 						|| !pipe->bottom_pipe)) {
1952 					merge[i] = true; /* 4 -> 2 MPC */
1953 				} else if (split[i] == 0 && pipe->top_pipe &&
1954 						pipe->top_pipe->plane_state == pipe->plane_state)
1955 					merge[i] = true; /* 4 -> 1 MPC */
1956 				split[i] = 0;
1957 			} else if (get_num_odm_splits(pipe)) {
1958 				/* ODM -> MPC transition */
1959 				if (pipe->prev_odm_pipe) {
1960 					split[i] = 0;
1961 					merge[i] = true;
1962 				}
1963 			}
1964 		} else {
1965 			if (get_num_odm_splits(pipe) == 1) {
1966 				/*If need split for odm but 2 way split already*/
1967 				if (split[i] == 4)
1968 					split[i] = 2; /* 2 -> 4 ODM */
1969 				else if (split[i] == 2)
1970 					split[i] = 0; /* 2 -> 2 ODM */
1971 				else if (pipe->prev_odm_pipe) {
1972 					ASSERT(0); /* NOT expected yet */
1973 					merge[i] = true; /* exit ODM */
1974 				}
1975 			} else if (get_num_odm_splits(pipe) == 3) {
1976 				/*If need split for odm but 4 way split already*/
1977 				if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
1978 						|| !pipe->next_odm_pipe)) {
1979 					merge[i] = true; /* 4 -> 2 ODM */
1980 				} else if (split[i] == 0 && pipe->prev_odm_pipe) {
1981 					ASSERT(0); /* NOT expected yet */
1982 					merge[i] = true; /* exit ODM */
1983 				}
1984 				split[i] = 0;
1985 			} else if (get_num_mpc_splits(pipe)) {
1986 				/* MPC -> ODM transition */
1987 				ASSERT(0); /* NOT expected yet */
1988 				if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1989 					split[i] = 0;
1990 					merge[i] = true;
1991 				}
1992 			}
1993 		}
1994 
1995 		/* Adjust dppclk when split is forced, do not bother with dispclk */
1996 		if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) {
1997 			DC_FP_START();
1998 			dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false);
1999 			DC_FP_END();
2000 		}
2001 		pipe_idx++;
2002 	}
2003 
2004 	return vlevel;
2005 }
2006 
dcn20_fast_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * pipe_split_from,int * vlevel_out,bool fast_validate)2007 bool dcn20_fast_validate_bw(
2008 		struct dc *dc,
2009 		struct dc_state *context,
2010 		display_e2e_pipe_params_st *pipes,
2011 		int *pipe_cnt_out,
2012 		int *pipe_split_from,
2013 		int *vlevel_out,
2014 		bool fast_validate)
2015 {
2016 	bool out = false;
2017 	int split[MAX_PIPES] = { 0 };
2018 	int pipe_cnt, i, pipe_idx, vlevel;
2019 
2020 	ASSERT(pipes);
2021 	if (!pipes)
2022 		return false;
2023 
2024 	dcn20_merge_pipes_for_validate(dc, context);
2025 
2026 	DC_FP_START();
2027 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2028 	DC_FP_END();
2029 
2030 	*pipe_cnt_out = pipe_cnt;
2031 
2032 	if (!pipe_cnt) {
2033 		out = true;
2034 		goto validate_out;
2035 	}
2036 
2037 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2038 
2039 	if (vlevel > context->bw_ctx.dml.soc.num_states)
2040 		goto validate_fail;
2041 
2042 	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
2043 
2044 	/*initialize pipe_just_split_from to invalid idx*/
2045 	for (i = 0; i < MAX_PIPES; i++)
2046 		pipe_split_from[i] = -1;
2047 
2048 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2049 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2050 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2051 
2052 		if (!pipe->stream || pipe_split_from[i] >= 0)
2053 			continue;
2054 
2055 		pipe_idx++;
2056 
2057 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2058 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2059 			ASSERT(hsplit_pipe);
2060 			if (!dcn20_split_stream_for_odm(
2061 					dc, &context->res_ctx,
2062 					pipe, hsplit_pipe))
2063 				goto validate_fail;
2064 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2065 			dcn20_build_mapped_resource(dc, context, pipe->stream);
2066 		}
2067 
2068 		if (!pipe->plane_state)
2069 			continue;
2070 		/* Skip 2nd half of already split pipe */
2071 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2072 			continue;
2073 
2074 		/* We do not support mpo + odm at the moment */
2075 		if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2076 				&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2077 			goto validate_fail;
2078 
2079 		if (split[i] == 2) {
2080 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2081 				/* pipe not split previously needs split */
2082 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2083 				ASSERT(hsplit_pipe);
2084 				if (!hsplit_pipe) {
2085 					DC_FP_START();
2086 					dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
2087 					DC_FP_END();
2088 					continue;
2089 				}
2090 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2091 					if (!dcn20_split_stream_for_odm(
2092 							dc, &context->res_ctx,
2093 							pipe, hsplit_pipe))
2094 						goto validate_fail;
2095 					dcn20_build_mapped_resource(dc, context, pipe->stream);
2096 				} else {
2097 					dcn20_split_stream_for_mpc(
2098 							&context->res_ctx, dc->res_pool,
2099 							pipe, hsplit_pipe);
2100 					resource_build_scaling_params(pipe);
2101 					resource_build_scaling_params(hsplit_pipe);
2102 				}
2103 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2104 			}
2105 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2106 			/* merge should already have been done */
2107 			ASSERT(0);
2108 		}
2109 	}
2110 	/* Actual dsc count per stream dsc validation*/
2111 	if (!dcn20_validate_dsc(dc, context)) {
2112 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2113 				DML_FAIL_DSC_VALIDATION_FAILURE;
2114 		goto validate_fail;
2115 	}
2116 
2117 	*vlevel_out = vlevel;
2118 
2119 	out = true;
2120 	goto validate_out;
2121 
2122 validate_fail:
2123 	out = false;
2124 
2125 validate_out:
2126 	return out;
2127 }
2128 
dcn20_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)2129 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2130 		bool fast_validate)
2131 {
2132 	bool voltage_supported;
2133 	DC_FP_START();
2134 	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
2135 	DC_FP_END();
2136 	return voltage_supported;
2137 }
2138 
dcn20_acquire_idle_pipe_for_layer(struct dc_state * state,const struct resource_pool * pool,struct dc_stream_state * stream)2139 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2140 		struct dc_state *state,
2141 		const struct resource_pool *pool,
2142 		struct dc_stream_state *stream)
2143 {
2144 	struct resource_context *res_ctx = &state->res_ctx;
2145 	struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2146 	struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2147 
2148 	if (!head_pipe)
2149 		ASSERT(0);
2150 
2151 	if (!idle_pipe)
2152 		return NULL;
2153 
2154 	idle_pipe->stream = head_pipe->stream;
2155 	idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2156 	idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2157 
2158 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2159 	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2160 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2161 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2162 
2163 	return idle_pipe;
2164 }
2165 
dcn20_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)2166 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2167 		const struct dc_dcc_surface_param *input,
2168 		struct dc_surface_dcc_cap *output)
2169 {
2170 	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2171 			dc->res_pool->hubbub,
2172 			input,
2173 			output);
2174 }
2175 
dcn20_destroy_resource_pool(struct resource_pool ** pool)2176 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2177 {
2178 	struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2179 
2180 	dcn20_resource_destruct(dcn20_pool);
2181 	kfree(dcn20_pool);
2182 	*pool = NULL;
2183 }
2184 
2185 
2186 static struct dc_cap_funcs cap_funcs = {
2187 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2188 };
2189 
2190 
dcn20_patch_unknown_plane_state(struct dc_plane_state * plane_state)2191 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
2192 {
2193 	enum surface_pixel_format surf_pix_format = plane_state->format;
2194 	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2195 
2196 	enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2197 
2198 	if (bpp == 64)
2199 		swizzle = DC_SW_64KB_D;
2200 	else
2201 		swizzle = DC_SW_64KB_S;
2202 
2203 	plane_state->tiling_info.gfx9.swizzle = swizzle;
2204 	return DC_OK;
2205 }
2206 
2207 static const struct resource_funcs dcn20_res_pool_funcs = {
2208 	.destroy = dcn20_destroy_resource_pool,
2209 	.link_enc_create = dcn20_link_encoder_create,
2210 	.panel_cntl_create = dcn20_panel_cntl_create,
2211 	.validate_bandwidth = dcn20_validate_bandwidth,
2212 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2213 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
2214 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2215 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2216 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2217 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2218 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
2219 	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
2220 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
2221 };
2222 
dcn20_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)2223 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2224 {
2225 	int i;
2226 	uint32_t pipe_count = pool->res_cap->num_dwb;
2227 
2228 	for (i = 0; i < pipe_count; i++) {
2229 		struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2230 						    GFP_KERNEL);
2231 
2232 		if (!dwbc20) {
2233 			dm_error("DC: failed to create dwbc20!\n");
2234 			return false;
2235 		}
2236 		dcn20_dwbc_construct(dwbc20, ctx,
2237 				&dwbc20_regs[i],
2238 				&dwbc20_shift,
2239 				&dwbc20_mask,
2240 				i);
2241 		pool->dwbc[i] = &dwbc20->base;
2242 	}
2243 	return true;
2244 }
2245 
dcn20_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)2246 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2247 {
2248 	int i;
2249 	uint32_t pipe_count = pool->res_cap->num_dwb;
2250 
2251 	ASSERT(pipe_count > 0);
2252 
2253 	for (i = 0; i < pipe_count; i++) {
2254 		struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2255 						    GFP_KERNEL);
2256 
2257 		if (!mcif_wb20) {
2258 			dm_error("DC: failed to create mcif_wb20!\n");
2259 			return false;
2260 		}
2261 
2262 		dcn20_mmhubbub_construct(mcif_wb20, ctx,
2263 				&mcif_wb20_regs[i],
2264 				&mcif_wb20_shift,
2265 				&mcif_wb20_mask,
2266 				i);
2267 
2268 		pool->mcif_wb[i] = &mcif_wb20->base;
2269 	}
2270 	return true;
2271 }
2272 
dcn20_pp_smu_create(struct dc_context * ctx)2273 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2274 {
2275 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);
2276 
2277 	if (!pp_smu)
2278 		return pp_smu;
2279 
2280 	dm_pp_get_funcs(ctx, pp_smu);
2281 
2282 	if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2283 		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2284 
2285 	return pp_smu;
2286 }
2287 
dcn20_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)2288 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2289 {
2290 	if (pp_smu && *pp_smu) {
2291 		kfree(*pp_smu);
2292 		*pp_smu = NULL;
2293 	}
2294 }
2295 
get_asic_rev_soc_bb(uint32_t hw_internal_rev)2296 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
2297 	uint32_t hw_internal_rev)
2298 {
2299 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
2300 		return &dcn2_0_nv14_soc;
2301 
2302 	if (ASICREV_IS_NAVI12_P(hw_internal_rev))
2303 		return &dcn2_0_nv12_soc;
2304 
2305 	return &dcn2_0_soc;
2306 }
2307 
get_asic_rev_ip_params(uint32_t hw_internal_rev)2308 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
2309 	uint32_t hw_internal_rev)
2310 {
2311 	/* NV14 */
2312 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
2313 		return &dcn2_0_nv14_ip;
2314 
2315 	/* NV12 and NV10 */
2316 	return &dcn2_0_ip;
2317 }
2318 
get_dml_project_version(uint32_t hw_internal_rev)2319 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
2320 {
2321 	return DML_PROJECT_NAVI10v2;
2322 }
2323 
init_soc_bounding_box(struct dc * dc,struct dcn20_resource_pool * pool)2324 static bool init_soc_bounding_box(struct dc *dc,
2325 				  struct dcn20_resource_pool *pool)
2326 {
2327 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
2328 			get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
2329 	struct _vcs_dpi_ip_params_st *loaded_ip =
2330 			get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
2331 
2332 	DC_LOGGER_INIT(dc->ctx->logger);
2333 
2334 	if (pool->base.pp_smu) {
2335 		struct pp_smu_nv_clock_table max_clocks = {0};
2336 		unsigned int uclk_states[8] = {0};
2337 		unsigned int num_states = 0;
2338 		enum pp_smu_status status;
2339 		bool clock_limits_available = false;
2340 		bool uclk_states_available = false;
2341 
2342 		if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2343 			status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2344 				(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2345 
2346 			uclk_states_available = (status == PP_SMU_RESULT_OK);
2347 		}
2348 
2349 		if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2350 			status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2351 					(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
2352 			/* SMU cannot set DCF clock to anything equal to or higher than SOC clock
2353 			 */
2354 			if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
2355 				max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
2356 			clock_limits_available = (status == PP_SMU_RESULT_OK);
2357 		}
2358 
2359 		if (clock_limits_available && uclk_states_available && num_states) {
2360 			DC_FP_START();
2361 			dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
2362 			DC_FP_END();
2363 		} else if (clock_limits_available) {
2364 			DC_FP_START();
2365 			dcn20_cap_soc_clocks(loaded_bb, max_clocks);
2366 			DC_FP_END();
2367 		}
2368 	}
2369 
2370 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
2371 	loaded_ip->max_num_dpp = pool->base.pipe_count;
2372 	DC_FP_START();
2373 	dcn20_patch_bounding_box(dc, loaded_bb);
2374 	DC_FP_END();
2375 	return true;
2376 }
2377 
dcn20_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn20_resource_pool * pool)2378 static bool dcn20_resource_construct(
2379 	uint8_t num_virtual_links,
2380 	struct dc *dc,
2381 	struct dcn20_resource_pool *pool)
2382 {
2383 	int i;
2384 	struct dc_context *ctx = dc->ctx;
2385 	struct irq_service_init_data init_data;
2386 	struct ddc_service_init_data ddc_init_data = {0};
2387 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
2388 			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
2389 	struct _vcs_dpi_ip_params_st *loaded_ip =
2390 			get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
2391 	enum dml_project dml_project_version =
2392 			get_dml_project_version(ctx->asic_id.hw_internal_rev);
2393 
2394 	ctx->dc_bios->regs = &bios_regs;
2395 	pool->base.funcs = &dcn20_res_pool_funcs;
2396 
2397 	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
2398 		pool->base.res_cap = &res_cap_nv14;
2399 		pool->base.pipe_count = 5;
2400 		pool->base.mpcc_count = 5;
2401 	} else {
2402 		pool->base.res_cap = &res_cap_nv10;
2403 		pool->base.pipe_count = 6;
2404 		pool->base.mpcc_count = 6;
2405 	}
2406 	/*************************************************
2407 	 *  Resource + asic cap harcoding                *
2408 	 *************************************************/
2409 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2410 
2411 	dc->caps.max_downscale_ratio = 200;
2412 	dc->caps.i2c_speed_in_khz = 100;
2413 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2414 	dc->caps.max_cursor_size = 256;
2415 	dc->caps.min_horizontal_blanking_period = 80;
2416 	dc->caps.dmdata_alloc_size = 2048;
2417 
2418 	dc->caps.max_slave_planes = 1;
2419 	dc->caps.max_slave_yuv_planes = 1;
2420 	dc->caps.max_slave_rgb_planes = 1;
2421 	dc->caps.post_blend_color_processing = true;
2422 	dc->caps.force_dp_tps4_for_cp2520 = true;
2423 	dc->caps.extended_aux_timeout_support = true;
2424 
2425 	/* Color pipeline capabilities */
2426 	dc->caps.color.dpp.dcn_arch = 1;
2427 	dc->caps.color.dpp.input_lut_shared = 0;
2428 	dc->caps.color.dpp.icsc = 1;
2429 	dc->caps.color.dpp.dgam_ram = 1;
2430 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2431 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2432 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
2433 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
2434 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
2435 	dc->caps.color.dpp.post_csc = 0;
2436 	dc->caps.color.dpp.gamma_corr = 0;
2437 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
2438 
2439 	dc->caps.color.dpp.hw_3d_lut = 1;
2440 	dc->caps.color.dpp.ogam_ram = 1;
2441 	// no OGAM ROM on DCN2, only MPC ROM
2442 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2443 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2444 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2445 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2446 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2447 	dc->caps.color.dpp.ocsc = 0;
2448 
2449 	dc->caps.color.mpc.gamut_remap = 0;
2450 	dc->caps.color.mpc.num_3dluts = 0;
2451 	dc->caps.color.mpc.shared_3d_lut = 0;
2452 	dc->caps.color.mpc.ogam_ram = 1;
2453 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2454 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2455 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2456 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2457 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2458 	dc->caps.color.mpc.ocsc = 1;
2459 
2460 	dc->caps.hdmi_frl_pcon_support = true;
2461 
2462 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
2463 		dc->debug = debug_defaults_drv;
2464 	} else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2465 		pool->base.pipe_count = 4;
2466 		pool->base.mpcc_count = pool->base.pipe_count;
2467 		dc->debug = debug_defaults_diags;
2468 	} else {
2469 		dc->debug = debug_defaults_diags;
2470 	}
2471 	//dcn2.0x
2472 	dc->work_arounds.dedcn20_305_wa = true;
2473 
2474 	// Init the vm_helper
2475 	if (dc->vm_helper)
2476 		vm_helper_init(dc->vm_helper, 16);
2477 
2478 	/*************************************************
2479 	 *  Create resources                             *
2480 	 *************************************************/
2481 
2482 	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2483 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2484 				CLOCK_SOURCE_COMBO_PHY_PLL0,
2485 				&clk_src_regs[0], false);
2486 	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2487 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2488 				CLOCK_SOURCE_COMBO_PHY_PLL1,
2489 				&clk_src_regs[1], false);
2490 	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2491 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2492 				CLOCK_SOURCE_COMBO_PHY_PLL2,
2493 				&clk_src_regs[2], false);
2494 	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2495 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2496 				CLOCK_SOURCE_COMBO_PHY_PLL3,
2497 				&clk_src_regs[3], false);
2498 	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2499 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2500 				CLOCK_SOURCE_COMBO_PHY_PLL4,
2501 				&clk_src_regs[4], false);
2502 	pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
2503 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2504 				CLOCK_SOURCE_COMBO_PHY_PLL5,
2505 				&clk_src_regs[5], false);
2506 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
2507 	/* todo: not reuse phy_pll registers */
2508 	pool->base.dp_clock_source =
2509 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2510 				CLOCK_SOURCE_ID_DP_DTO,
2511 				&clk_src_regs[0], true);
2512 
2513 	for (i = 0; i < pool->base.clk_src_count; i++) {
2514 		if (pool->base.clock_sources[i] == NULL) {
2515 			dm_error("DC: failed to create clock sources!\n");
2516 			BREAK_TO_DEBUGGER();
2517 			goto create_fail;
2518 		}
2519 	}
2520 
2521 	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2522 	if (pool->base.dccg == NULL) {
2523 		dm_error("DC: failed to create dccg!\n");
2524 		BREAK_TO_DEBUGGER();
2525 		goto create_fail;
2526 	}
2527 
2528 	pool->base.dmcu = dcn20_dmcu_create(ctx,
2529 			&dmcu_regs,
2530 			&dmcu_shift,
2531 			&dmcu_mask);
2532 	if (pool->base.dmcu == NULL) {
2533 		dm_error("DC: failed to create dmcu!\n");
2534 		BREAK_TO_DEBUGGER();
2535 		goto create_fail;
2536 	}
2537 
2538 	pool->base.abm = dce_abm_create(ctx,
2539 			&abm_regs,
2540 			&abm_shift,
2541 			&abm_mask);
2542 	if (pool->base.abm == NULL) {
2543 		dm_error("DC: failed to create abm!\n");
2544 		BREAK_TO_DEBUGGER();
2545 		goto create_fail;
2546 	}
2547 
2548 	pool->base.pp_smu = dcn20_pp_smu_create(ctx);
2549 
2550 
2551 	if (!init_soc_bounding_box(dc, pool)) {
2552 		dm_error("DC: failed to initialize soc bounding box!\n");
2553 		BREAK_TO_DEBUGGER();
2554 		goto create_fail;
2555 	}
2556 
2557 	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
2558 
2559 	if (!dc->debug.disable_pplib_wm_range) {
2560 		struct pp_smu_wm_range_sets ranges = {0};
2561 		int i = 0;
2562 
2563 		ranges.num_reader_wm_sets = 0;
2564 
2565 		if (loaded_bb->num_states == 1) {
2566 			ranges.reader_wm_sets[0].wm_inst = i;
2567 			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2568 			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2569 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2570 			ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2571 
2572 			ranges.num_reader_wm_sets = 1;
2573 		} else if (loaded_bb->num_states > 1) {
2574 			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
2575 				ranges.reader_wm_sets[i].wm_inst = i;
2576 				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2577 				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2578 				DC_FP_START();
2579 				dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb);
2580 				DC_FP_END();
2581 
2582 				ranges.num_reader_wm_sets = i + 1;
2583 			}
2584 
2585 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2586 			ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2587 		}
2588 
2589 		ranges.num_writer_wm_sets = 1;
2590 
2591 		ranges.writer_wm_sets[0].wm_inst = 0;
2592 		ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2593 		ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2594 		ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2595 		ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2596 
2597 		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
2598 		if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
2599 			pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
2600 	}
2601 
2602 	init_data.ctx = dc->ctx;
2603 	pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
2604 	if (!pool->base.irqs)
2605 		goto create_fail;
2606 
2607 	/* mem input -> ipp -> dpp -> opp -> TG */
2608 	for (i = 0; i < pool->base.pipe_count; i++) {
2609 		pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
2610 		if (pool->base.hubps[i] == NULL) {
2611 			BREAK_TO_DEBUGGER();
2612 			dm_error(
2613 				"DC: failed to create memory input!\n");
2614 			goto create_fail;
2615 		}
2616 
2617 		pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
2618 		if (pool->base.ipps[i] == NULL) {
2619 			BREAK_TO_DEBUGGER();
2620 			dm_error(
2621 				"DC: failed to create input pixel processor!\n");
2622 			goto create_fail;
2623 		}
2624 
2625 		pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
2626 		if (pool->base.dpps[i] == NULL) {
2627 			BREAK_TO_DEBUGGER();
2628 			dm_error(
2629 				"DC: failed to create dpps!\n");
2630 			goto create_fail;
2631 		}
2632 	}
2633 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2634 		pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
2635 		if (pool->base.engines[i] == NULL) {
2636 			BREAK_TO_DEBUGGER();
2637 			dm_error(
2638 				"DC:failed to create aux engine!!\n");
2639 			goto create_fail;
2640 		}
2641 		pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
2642 		if (pool->base.hw_i2cs[i] == NULL) {
2643 			BREAK_TO_DEBUGGER();
2644 			dm_error(
2645 				"DC:failed to create hw i2c!!\n");
2646 			goto create_fail;
2647 		}
2648 		pool->base.sw_i2cs[i] = NULL;
2649 	}
2650 
2651 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2652 		pool->base.opps[i] = dcn20_opp_create(ctx, i);
2653 		if (pool->base.opps[i] == NULL) {
2654 			BREAK_TO_DEBUGGER();
2655 			dm_error(
2656 				"DC: failed to create output pixel processor!\n");
2657 			goto create_fail;
2658 		}
2659 	}
2660 
2661 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2662 		pool->base.timing_generators[i] = dcn20_timing_generator_create(
2663 				ctx, i);
2664 		if (pool->base.timing_generators[i] == NULL) {
2665 			BREAK_TO_DEBUGGER();
2666 			dm_error("DC: failed to create tg!\n");
2667 			goto create_fail;
2668 		}
2669 	}
2670 
2671 	pool->base.timing_generator_count = i;
2672 
2673 	pool->base.mpc = dcn20_mpc_create(ctx);
2674 	if (pool->base.mpc == NULL) {
2675 		BREAK_TO_DEBUGGER();
2676 		dm_error("DC: failed to create mpc!\n");
2677 		goto create_fail;
2678 	}
2679 
2680 	pool->base.hubbub = dcn20_hubbub_create(ctx);
2681 	if (pool->base.hubbub == NULL) {
2682 		BREAK_TO_DEBUGGER();
2683 		dm_error("DC: failed to create hubbub!\n");
2684 		goto create_fail;
2685 	}
2686 
2687 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2688 		pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
2689 		if (pool->base.dscs[i] == NULL) {
2690 			BREAK_TO_DEBUGGER();
2691 			dm_error("DC: failed to create display stream compressor %d!\n", i);
2692 			goto create_fail;
2693 		}
2694 	}
2695 
2696 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
2697 		BREAK_TO_DEBUGGER();
2698 		dm_error("DC: failed to create dwbc!\n");
2699 		goto create_fail;
2700 	}
2701 	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2702 		BREAK_TO_DEBUGGER();
2703 		dm_error("DC: failed to create mcif_wb!\n");
2704 		goto create_fail;
2705 	}
2706 
2707 	if (!resource_construct(num_virtual_links, dc, &pool->base,
2708 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2709 			&res_create_funcs : &res_create_maximus_funcs)))
2710 			goto create_fail;
2711 
2712 	dcn20_hw_sequencer_construct(dc);
2713 
2714 	// IF NV12, set PG function pointer to NULL. It's not that
2715 	// PG isn't supported for NV12, it's that we don't want to
2716 	// program the registers because that will cause more power
2717 	// to be consumed. We could have created dcn20_init_hw to get
2718 	// the same effect by checking ASIC rev, but there was a
2719 	// request at some point to not check ASIC rev on hw sequencer.
2720 	if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
2721 		dc->hwseq->funcs.enable_power_gating_plane = NULL;
2722 		dc->debug.disable_dpp_power_gate = true;
2723 		dc->debug.disable_hubp_power_gate = true;
2724 	}
2725 
2726 
2727 	dc->caps.max_planes =  pool->base.pipe_count;
2728 
2729 	for (i = 0; i < dc->caps.max_planes; ++i)
2730 		dc->caps.planes[i] = plane_cap;
2731 
2732 	dc->cap_funcs = cap_funcs;
2733 
2734 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2735 		ddc_init_data.ctx = dc->ctx;
2736 		ddc_init_data.link = NULL;
2737 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2738 		ddc_init_data.id.enum_id = 0;
2739 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2740 		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2741 	} else {
2742 		pool->base.oem_device = NULL;
2743 	}
2744 
2745 	return true;
2746 
2747 create_fail:
2748 
2749 	dcn20_resource_destruct(pool);
2750 
2751 	return false;
2752 }
2753 
dcn20_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2754 struct resource_pool *dcn20_create_resource_pool(
2755 		const struct dc_init_data *init_data,
2756 		struct dc *dc)
2757 {
2758 	struct dcn20_resource_pool *pool =
2759 		kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);
2760 
2761 	if (!pool)
2762 		return NULL;
2763 
2764 	if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
2765 		return &pool->base;
2766 
2767 	BREAK_TO_DEBUGGER();
2768 	kfree(pool);
2769 	return NULL;
2770 }
2771