1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2021 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include "resource.h"
28 #include "clk_mgr.h"
29 #include "dc_link_dp.h"
30 #include "dchubbub.h"
31 #include "dcn20/dcn20_resource.h"
32 #include "dcn21/dcn21_resource.h"
33 #include "clk_mgr/dcn21/rn_clk_mgr.h"
34 
35 #include "dcn20_fpu.h"
36 
37 #define DC_LOGGER_INIT(logger)
38 
39 #ifndef MAX
40 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
41 #endif
42 #ifndef MIN
43 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
44 #endif
45 
46 /* Constant */
47 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
48 
49 /**
50  * DOC: DCN2x FPU manipulation Overview
51  *
52  * The DCN architecture relies on FPU operations, which require special
53  * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
54  * want to avoid spreading FPU access across multiple files. With this idea in
55  * mind, this file aims to centralize all DCN20 and DCN2.1 (DCN2x) functions
56  * that require FPU access in a single place. Code in this file follows the
57  * following code pattern:
58  *
59  * 1. Functions that use FPU operations should be isolated in static functions.
60  * 2. The FPU functions should have the noinline attribute to ensure anything
61  *    that deals with FP register is contained within this call.
62  * 3. All function that needs to be accessed outside this file requires a
63  *    public interface that not uses any FPU reference.
64  * 4. Developers **must not** use DC_FP_START/END in this file, but they need
65  *    to ensure that the caller invokes it before access any function available
66  *    in this file. For this reason, public functions in this file must invoke
67  *    dc_assert_fp_enabled();
68  *
69  * Let's expand a little bit more the idea in the code pattern. To fully
70  * isolate FPU operations in a single place, we must avoid situations where
71  * compilers spill FP values to registers due to FP enable in a specific C
72  * file. Note that even if we isolate all FPU functions in a single file and
73  * call its interface from other files, the compiler might enable the use of
74  * FPU before we call DC_FP_START. Nevertheless, it is the programmer's
75  * responsibility to invoke DC_FP_START/END in the correct place. To highlight
76  * situations where developers forgot to use the FP protection before calling
77  * the DC FPU interface functions, we introduce a helper that checks if the
78  * function is invoked under FP protection. If not, it will trigger a kernel
79  * warning.
80  */
81 
82 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
83 	.odm_capable = 1,
84 	.gpuvm_enable = 0,
85 	.hostvm_enable = 0,
86 	.gpuvm_max_page_table_levels = 4,
87 	.hostvm_max_page_table_levels = 4,
88 	.hostvm_cached_page_table_levels = 0,
89 	.pte_group_size_bytes = 2048,
90 	.num_dsc = 6,
91 	.rob_buffer_size_kbytes = 168,
92 	.det_buffer_size_kbytes = 164,
93 	.dpte_buffer_size_in_pte_reqs_luma = 84,
94 	.pde_proc_buffer_size_64k_reqs = 48,
95 	.dpp_output_buffer_pixels = 2560,
96 	.opp_output_buffer_lines = 1,
97 	.pixel_chunk_size_kbytes = 8,
98 	.pte_chunk_size_kbytes = 2,
99 	.meta_chunk_size_kbytes = 2,
100 	.writeback_chunk_size_kbytes = 2,
101 	.line_buffer_size_bits = 789504,
102 	.is_line_buffer_bpp_fixed = 0,
103 	.line_buffer_fixed_bpp = 0,
104 	.dcc_supported = true,
105 	.max_line_buffer_lines = 12,
106 	.writeback_luma_buffer_size_kbytes = 12,
107 	.writeback_chroma_buffer_size_kbytes = 8,
108 	.writeback_chroma_line_buffer_width_pixels = 4,
109 	.writeback_max_hscl_ratio = 1,
110 	.writeback_max_vscl_ratio = 1,
111 	.writeback_min_hscl_ratio = 1,
112 	.writeback_min_vscl_ratio = 1,
113 	.writeback_max_hscl_taps = 12,
114 	.writeback_max_vscl_taps = 12,
115 	.writeback_line_buffer_luma_buffer_size = 0,
116 	.writeback_line_buffer_chroma_buffer_size = 14643,
117 	.cursor_buffer_size = 8,
118 	.cursor_chunk_size = 2,
119 	.max_num_otg = 6,
120 	.max_num_dpp = 6,
121 	.max_num_wb = 1,
122 	.max_dchub_pscl_bw_pix_per_clk = 4,
123 	.max_pscl_lb_bw_pix_per_clk = 2,
124 	.max_lb_vscl_bw_pix_per_clk = 4,
125 	.max_vscl_hscl_bw_pix_per_clk = 4,
126 	.max_hscl_ratio = 8,
127 	.max_vscl_ratio = 8,
128 	.hscl_mults = 4,
129 	.vscl_mults = 4,
130 	.max_hscl_taps = 8,
131 	.max_vscl_taps = 8,
132 	.dispclk_ramp_margin_percent = 1,
133 	.underscan_factor = 1.10,
134 	.min_vblank_lines = 32, //
135 	.dppclk_delay_subtotal = 77, //
136 	.dppclk_delay_scl_lb_only = 16,
137 	.dppclk_delay_scl = 50,
138 	.dppclk_delay_cnvc_formatter = 8,
139 	.dppclk_delay_cnvc_cursor = 6,
140 	.dispclk_delay_subtotal = 87, //
141 	.dcfclk_cstate_latency = 10, // SRExitTime
142 	.max_inter_dcn_tile_repeaters = 8,
143 	.xfc_supported = true,
144 	.xfc_fill_bw_overhead_percent = 10.0,
145 	.xfc_fill_constant_bytes = 0,
146 	.number_of_cursors = 1,
147 };
148 
149 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
150 	.odm_capable = 1,
151 	.gpuvm_enable = 0,
152 	.hostvm_enable = 0,
153 	.gpuvm_max_page_table_levels = 4,
154 	.hostvm_max_page_table_levels = 4,
155 	.hostvm_cached_page_table_levels = 0,
156 	.num_dsc = 5,
157 	.rob_buffer_size_kbytes = 168,
158 	.det_buffer_size_kbytes = 164,
159 	.dpte_buffer_size_in_pte_reqs_luma = 84,
160 	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
161 	.dpp_output_buffer_pixels = 2560,
162 	.opp_output_buffer_lines = 1,
163 	.pixel_chunk_size_kbytes = 8,
164 	.pte_enable = 1,
165 	.max_page_table_levels = 4,
166 	.pte_chunk_size_kbytes = 2,
167 	.meta_chunk_size_kbytes = 2,
168 	.writeback_chunk_size_kbytes = 2,
169 	.line_buffer_size_bits = 789504,
170 	.is_line_buffer_bpp_fixed = 0,
171 	.line_buffer_fixed_bpp = 0,
172 	.dcc_supported = true,
173 	.max_line_buffer_lines = 12,
174 	.writeback_luma_buffer_size_kbytes = 12,
175 	.writeback_chroma_buffer_size_kbytes = 8,
176 	.writeback_chroma_line_buffer_width_pixels = 4,
177 	.writeback_max_hscl_ratio = 1,
178 	.writeback_max_vscl_ratio = 1,
179 	.writeback_min_hscl_ratio = 1,
180 	.writeback_min_vscl_ratio = 1,
181 	.writeback_max_hscl_taps = 12,
182 	.writeback_max_vscl_taps = 12,
183 	.writeback_line_buffer_luma_buffer_size = 0,
184 	.writeback_line_buffer_chroma_buffer_size = 14643,
185 	.cursor_buffer_size = 8,
186 	.cursor_chunk_size = 2,
187 	.max_num_otg = 5,
188 	.max_num_dpp = 5,
189 	.max_num_wb = 1,
190 	.max_dchub_pscl_bw_pix_per_clk = 4,
191 	.max_pscl_lb_bw_pix_per_clk = 2,
192 	.max_lb_vscl_bw_pix_per_clk = 4,
193 	.max_vscl_hscl_bw_pix_per_clk = 4,
194 	.max_hscl_ratio = 8,
195 	.max_vscl_ratio = 8,
196 	.hscl_mults = 4,
197 	.vscl_mults = 4,
198 	.max_hscl_taps = 8,
199 	.max_vscl_taps = 8,
200 	.dispclk_ramp_margin_percent = 1,
201 	.underscan_factor = 1.10,
202 	.min_vblank_lines = 32, //
203 	.dppclk_delay_subtotal = 77, //
204 	.dppclk_delay_scl_lb_only = 16,
205 	.dppclk_delay_scl = 50,
206 	.dppclk_delay_cnvc_formatter = 8,
207 	.dppclk_delay_cnvc_cursor = 6,
208 	.dispclk_delay_subtotal = 87, //
209 	.dcfclk_cstate_latency = 10, // SRExitTime
210 	.max_inter_dcn_tile_repeaters = 8,
211 	.xfc_supported = true,
212 	.xfc_fill_bw_overhead_percent = 10.0,
213 	.xfc_fill_constant_bytes = 0,
214 	.ptoi_supported = 0,
215 	.number_of_cursors = 1,
216 };
217 
218 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
219 	/* Defaults that get patched on driver load from firmware. */
220 	.clock_limits = {
221 			{
222 				.state = 0,
223 				.dcfclk_mhz = 560.0,
224 				.fabricclk_mhz = 560.0,
225 				.dispclk_mhz = 513.0,
226 				.dppclk_mhz = 513.0,
227 				.phyclk_mhz = 540.0,
228 				.socclk_mhz = 560.0,
229 				.dscclk_mhz = 171.0,
230 				.dram_speed_mts = 8960.0,
231 			},
232 			{
233 				.state = 1,
234 				.dcfclk_mhz = 694.0,
235 				.fabricclk_mhz = 694.0,
236 				.dispclk_mhz = 642.0,
237 				.dppclk_mhz = 642.0,
238 				.phyclk_mhz = 600.0,
239 				.socclk_mhz = 694.0,
240 				.dscclk_mhz = 214.0,
241 				.dram_speed_mts = 11104.0,
242 			},
243 			{
244 				.state = 2,
245 				.dcfclk_mhz = 875.0,
246 				.fabricclk_mhz = 875.0,
247 				.dispclk_mhz = 734.0,
248 				.dppclk_mhz = 734.0,
249 				.phyclk_mhz = 810.0,
250 				.socclk_mhz = 875.0,
251 				.dscclk_mhz = 245.0,
252 				.dram_speed_mts = 14000.0,
253 			},
254 			{
255 				.state = 3,
256 				.dcfclk_mhz = 1000.0,
257 				.fabricclk_mhz = 1000.0,
258 				.dispclk_mhz = 1100.0,
259 				.dppclk_mhz = 1100.0,
260 				.phyclk_mhz = 810.0,
261 				.socclk_mhz = 1000.0,
262 				.dscclk_mhz = 367.0,
263 				.dram_speed_mts = 16000.0,
264 			},
265 			{
266 				.state = 4,
267 				.dcfclk_mhz = 1200.0,
268 				.fabricclk_mhz = 1200.0,
269 				.dispclk_mhz = 1284.0,
270 				.dppclk_mhz = 1284.0,
271 				.phyclk_mhz = 810.0,
272 				.socclk_mhz = 1200.0,
273 				.dscclk_mhz = 428.0,
274 				.dram_speed_mts = 16000.0,
275 			},
276 			/*Extra state, no dispclk ramping*/
277 			{
278 				.state = 5,
279 				.dcfclk_mhz = 1200.0,
280 				.fabricclk_mhz = 1200.0,
281 				.dispclk_mhz = 1284.0,
282 				.dppclk_mhz = 1284.0,
283 				.phyclk_mhz = 810.0,
284 				.socclk_mhz = 1200.0,
285 				.dscclk_mhz = 428.0,
286 				.dram_speed_mts = 16000.0,
287 			},
288 		},
289 	.num_states = 5,
290 	.sr_exit_time_us = 8.6,
291 	.sr_enter_plus_exit_time_us = 10.9,
292 	.urgent_latency_us = 4.0,
293 	.urgent_latency_pixel_data_only_us = 4.0,
294 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
295 	.urgent_latency_vm_data_only_us = 4.0,
296 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
297 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
298 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
299 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
300 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
301 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
302 	.max_avg_sdp_bw_use_normal_percent = 40.0,
303 	.max_avg_dram_bw_use_normal_percent = 40.0,
304 	.writeback_latency_us = 12.0,
305 	.ideal_dram_bw_after_urgent_percent = 40.0,
306 	.max_request_size_bytes = 256,
307 	.dram_channel_width_bytes = 2,
308 	.fabric_datapath_to_dcn_data_return_bytes = 64,
309 	.dcn_downspread_percent = 0.5,
310 	.downspread_percent = 0.38,
311 	.dram_page_open_time_ns = 50.0,
312 	.dram_rw_turnaround_time_ns = 17.5,
313 	.dram_return_buffer_per_channel_bytes = 8192,
314 	.round_trip_ping_latency_dcfclk_cycles = 131,
315 	.urgent_out_of_order_return_per_channel_bytes = 256,
316 	.channel_interleave_bytes = 256,
317 	.num_banks = 8,
318 	.num_chans = 16,
319 	.vmm_page_size_bytes = 4096,
320 	.dram_clock_change_latency_us = 404.0,
321 	.dummy_pstate_latency_us = 5.0,
322 	.writeback_dram_clock_change_latency_us = 23.0,
323 	.return_bus_width_bytes = 64,
324 	.dispclk_dppclk_vco_speed_mhz = 3850,
325 	.xfc_bus_transport_time_us = 20,
326 	.xfc_xbuf_latency_tolerance_us = 4,
327 	.use_urgent_burst_bw = 0
328 };
329 
330 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
331 	.clock_limits = {
332 			{
333 				.state = 0,
334 				.dcfclk_mhz = 560.0,
335 				.fabricclk_mhz = 560.0,
336 				.dispclk_mhz = 513.0,
337 				.dppclk_mhz = 513.0,
338 				.phyclk_mhz = 540.0,
339 				.socclk_mhz = 560.0,
340 				.dscclk_mhz = 171.0,
341 				.dram_speed_mts = 8960.0,
342 			},
343 			{
344 				.state = 1,
345 				.dcfclk_mhz = 694.0,
346 				.fabricclk_mhz = 694.0,
347 				.dispclk_mhz = 642.0,
348 				.dppclk_mhz = 642.0,
349 				.phyclk_mhz = 600.0,
350 				.socclk_mhz = 694.0,
351 				.dscclk_mhz = 214.0,
352 				.dram_speed_mts = 11104.0,
353 			},
354 			{
355 				.state = 2,
356 				.dcfclk_mhz = 875.0,
357 				.fabricclk_mhz = 875.0,
358 				.dispclk_mhz = 734.0,
359 				.dppclk_mhz = 734.0,
360 				.phyclk_mhz = 810.0,
361 				.socclk_mhz = 875.0,
362 				.dscclk_mhz = 245.0,
363 				.dram_speed_mts = 14000.0,
364 			},
365 			{
366 				.state = 3,
367 				.dcfclk_mhz = 1000.0,
368 				.fabricclk_mhz = 1000.0,
369 				.dispclk_mhz = 1100.0,
370 				.dppclk_mhz = 1100.0,
371 				.phyclk_mhz = 810.0,
372 				.socclk_mhz = 1000.0,
373 				.dscclk_mhz = 367.0,
374 				.dram_speed_mts = 16000.0,
375 			},
376 			{
377 				.state = 4,
378 				.dcfclk_mhz = 1200.0,
379 				.fabricclk_mhz = 1200.0,
380 				.dispclk_mhz = 1284.0,
381 				.dppclk_mhz = 1284.0,
382 				.phyclk_mhz = 810.0,
383 				.socclk_mhz = 1200.0,
384 				.dscclk_mhz = 428.0,
385 				.dram_speed_mts = 16000.0,
386 			},
387 			/*Extra state, no dispclk ramping*/
388 			{
389 				.state = 5,
390 				.dcfclk_mhz = 1200.0,
391 				.fabricclk_mhz = 1200.0,
392 				.dispclk_mhz = 1284.0,
393 				.dppclk_mhz = 1284.0,
394 				.phyclk_mhz = 810.0,
395 				.socclk_mhz = 1200.0,
396 				.dscclk_mhz = 428.0,
397 				.dram_speed_mts = 16000.0,
398 			},
399 		},
400 	.num_states = 5,
401 	.sr_exit_time_us = 11.6,
402 	.sr_enter_plus_exit_time_us = 13.9,
403 	.urgent_latency_us = 4.0,
404 	.urgent_latency_pixel_data_only_us = 4.0,
405 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
406 	.urgent_latency_vm_data_only_us = 4.0,
407 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
408 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
409 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
410 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
411 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
412 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
413 	.max_avg_sdp_bw_use_normal_percent = 40.0,
414 	.max_avg_dram_bw_use_normal_percent = 40.0,
415 	.writeback_latency_us = 12.0,
416 	.ideal_dram_bw_after_urgent_percent = 40.0,
417 	.max_request_size_bytes = 256,
418 	.dram_channel_width_bytes = 2,
419 	.fabric_datapath_to_dcn_data_return_bytes = 64,
420 	.dcn_downspread_percent = 0.5,
421 	.downspread_percent = 0.38,
422 	.dram_page_open_time_ns = 50.0,
423 	.dram_rw_turnaround_time_ns = 17.5,
424 	.dram_return_buffer_per_channel_bytes = 8192,
425 	.round_trip_ping_latency_dcfclk_cycles = 131,
426 	.urgent_out_of_order_return_per_channel_bytes = 256,
427 	.channel_interleave_bytes = 256,
428 	.num_banks = 8,
429 	.num_chans = 8,
430 	.vmm_page_size_bytes = 4096,
431 	.dram_clock_change_latency_us = 404.0,
432 	.dummy_pstate_latency_us = 5.0,
433 	.writeback_dram_clock_change_latency_us = 23.0,
434 	.return_bus_width_bytes = 64,
435 	.dispclk_dppclk_vco_speed_mhz = 3850,
436 	.xfc_bus_transport_time_us = 20,
437 	.xfc_xbuf_latency_tolerance_us = 4,
438 	.use_urgent_burst_bw = 0
439 };
440 
441 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
442 
443 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
444 	.odm_capable = 1,
445 	.gpuvm_enable = 1,
446 	.hostvm_enable = 1,
447 	.gpuvm_max_page_table_levels = 1,
448 	.hostvm_max_page_table_levels = 4,
449 	.hostvm_cached_page_table_levels = 2,
450 	.num_dsc = 3,
451 	.rob_buffer_size_kbytes = 168,
452 	.det_buffer_size_kbytes = 164,
453 	.dpte_buffer_size_in_pte_reqs_luma = 44,
454 	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
455 	.dpp_output_buffer_pixels = 2560,
456 	.opp_output_buffer_lines = 1,
457 	.pixel_chunk_size_kbytes = 8,
458 	.pte_enable = 1,
459 	.max_page_table_levels = 4,
460 	.pte_chunk_size_kbytes = 2,
461 	.meta_chunk_size_kbytes = 2,
462 	.min_meta_chunk_size_bytes = 256,
463 	.writeback_chunk_size_kbytes = 2,
464 	.line_buffer_size_bits = 789504,
465 	.is_line_buffer_bpp_fixed = 0,
466 	.line_buffer_fixed_bpp = 0,
467 	.dcc_supported = true,
468 	.max_line_buffer_lines = 12,
469 	.writeback_luma_buffer_size_kbytes = 12,
470 	.writeback_chroma_buffer_size_kbytes = 8,
471 	.writeback_chroma_line_buffer_width_pixels = 4,
472 	.writeback_max_hscl_ratio = 1,
473 	.writeback_max_vscl_ratio = 1,
474 	.writeback_min_hscl_ratio = 1,
475 	.writeback_min_vscl_ratio = 1,
476 	.writeback_max_hscl_taps = 12,
477 	.writeback_max_vscl_taps = 12,
478 	.writeback_line_buffer_luma_buffer_size = 0,
479 	.writeback_line_buffer_chroma_buffer_size = 14643,
480 	.cursor_buffer_size = 8,
481 	.cursor_chunk_size = 2,
482 	.max_num_otg = 4,
483 	.max_num_dpp = 4,
484 	.max_num_wb = 1,
485 	.max_dchub_pscl_bw_pix_per_clk = 4,
486 	.max_pscl_lb_bw_pix_per_clk = 2,
487 	.max_lb_vscl_bw_pix_per_clk = 4,
488 	.max_vscl_hscl_bw_pix_per_clk = 4,
489 	.max_hscl_ratio = 4,
490 	.max_vscl_ratio = 4,
491 	.hscl_mults = 4,
492 	.vscl_mults = 4,
493 	.max_hscl_taps = 8,
494 	.max_vscl_taps = 8,
495 	.dispclk_ramp_margin_percent = 1,
496 	.underscan_factor = 1.10,
497 	.min_vblank_lines = 32, //
498 	.dppclk_delay_subtotal = 77, //
499 	.dppclk_delay_scl_lb_only = 16,
500 	.dppclk_delay_scl = 50,
501 	.dppclk_delay_cnvc_formatter = 8,
502 	.dppclk_delay_cnvc_cursor = 6,
503 	.dispclk_delay_subtotal = 87, //
504 	.dcfclk_cstate_latency = 10, // SRExitTime
505 	.max_inter_dcn_tile_repeaters = 8,
506 
507 	.xfc_supported = false,
508 	.xfc_fill_bw_overhead_percent = 10.0,
509 	.xfc_fill_constant_bytes = 0,
510 	.ptoi_supported = 0,
511 	.number_of_cursors = 1,
512 };
513 
514 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
515 	.clock_limits = {
516 			{
517 				.state = 0,
518 				.dcfclk_mhz = 400.0,
519 				.fabricclk_mhz = 400.0,
520 				.dispclk_mhz = 600.0,
521 				.dppclk_mhz = 400.00,
522 				.phyclk_mhz = 600.0,
523 				.socclk_mhz = 278.0,
524 				.dscclk_mhz = 205.67,
525 				.dram_speed_mts = 1600.0,
526 			},
527 			{
528 				.state = 1,
529 				.dcfclk_mhz = 464.52,
530 				.fabricclk_mhz = 800.0,
531 				.dispclk_mhz = 654.55,
532 				.dppclk_mhz = 626.09,
533 				.phyclk_mhz = 600.0,
534 				.socclk_mhz = 278.0,
535 				.dscclk_mhz = 205.67,
536 				.dram_speed_mts = 1600.0,
537 			},
538 			{
539 				.state = 2,
540 				.dcfclk_mhz = 514.29,
541 				.fabricclk_mhz = 933.0,
542 				.dispclk_mhz = 757.89,
543 				.dppclk_mhz = 685.71,
544 				.phyclk_mhz = 600.0,
545 				.socclk_mhz = 278.0,
546 				.dscclk_mhz = 287.67,
547 				.dram_speed_mts = 1866.0,
548 			},
549 			{
550 				.state = 3,
551 				.dcfclk_mhz = 576.00,
552 				.fabricclk_mhz = 1067.0,
553 				.dispclk_mhz = 847.06,
554 				.dppclk_mhz = 757.89,
555 				.phyclk_mhz = 600.0,
556 				.socclk_mhz = 715.0,
557 				.dscclk_mhz = 318.334,
558 				.dram_speed_mts = 2134.0,
559 			},
560 			{
561 				.state = 4,
562 				.dcfclk_mhz = 626.09,
563 				.fabricclk_mhz = 1200.0,
564 				.dispclk_mhz = 900.00,
565 				.dppclk_mhz = 847.06,
566 				.phyclk_mhz = 810.0,
567 				.socclk_mhz = 953.0,
568 				.dscclk_mhz = 489.0,
569 				.dram_speed_mts = 2400.0,
570 			},
571 			{
572 				.state = 5,
573 				.dcfclk_mhz = 685.71,
574 				.fabricclk_mhz = 1333.0,
575 				.dispclk_mhz = 1028.57,
576 				.dppclk_mhz = 960.00,
577 				.phyclk_mhz = 810.0,
578 				.socclk_mhz = 278.0,
579 				.dscclk_mhz = 287.67,
580 				.dram_speed_mts = 2666.0,
581 			},
582 			{
583 				.state = 6,
584 				.dcfclk_mhz = 757.89,
585 				.fabricclk_mhz = 1467.0,
586 				.dispclk_mhz = 1107.69,
587 				.dppclk_mhz = 1028.57,
588 				.phyclk_mhz = 810.0,
589 				.socclk_mhz = 715.0,
590 				.dscclk_mhz = 318.334,
591 				.dram_speed_mts = 3200.0,
592 			},
593 			{
594 				.state = 7,
595 				.dcfclk_mhz = 847.06,
596 				.fabricclk_mhz = 1600.0,
597 				.dispclk_mhz = 1395.0,
598 				.dppclk_mhz = 1285.00,
599 				.phyclk_mhz = 1325.0,
600 				.socclk_mhz = 953.0,
601 				.dscclk_mhz = 489.0,
602 				.dram_speed_mts = 4266.0,
603 			},
604 			/*Extra state, no dispclk ramping*/
605 			{
606 				.state = 8,
607 				.dcfclk_mhz = 847.06,
608 				.fabricclk_mhz = 1600.0,
609 				.dispclk_mhz = 1395.0,
610 				.dppclk_mhz = 1285.0,
611 				.phyclk_mhz = 1325.0,
612 				.socclk_mhz = 953.0,
613 				.dscclk_mhz = 489.0,
614 				.dram_speed_mts = 4266.0,
615 			},
616 
617 		},
618 
619 	.sr_exit_time_us = 12.5,
620 	.sr_enter_plus_exit_time_us = 17.0,
621 	.urgent_latency_us = 4.0,
622 	.urgent_latency_pixel_data_only_us = 4.0,
623 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
624 	.urgent_latency_vm_data_only_us = 4.0,
625 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
626 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
627 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
628 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
629 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
630 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
631 	.max_avg_sdp_bw_use_normal_percent = 60.0,
632 	.max_avg_dram_bw_use_normal_percent = 100.0,
633 	.writeback_latency_us = 12.0,
634 	.max_request_size_bytes = 256,
635 	.dram_channel_width_bytes = 4,
636 	.fabric_datapath_to_dcn_data_return_bytes = 32,
637 	.dcn_downspread_percent = 0.5,
638 	.downspread_percent = 0.38,
639 	.dram_page_open_time_ns = 50.0,
640 	.dram_rw_turnaround_time_ns = 17.5,
641 	.dram_return_buffer_per_channel_bytes = 8192,
642 	.round_trip_ping_latency_dcfclk_cycles = 128,
643 	.urgent_out_of_order_return_per_channel_bytes = 4096,
644 	.channel_interleave_bytes = 256,
645 	.num_banks = 8,
646 	.num_chans = 4,
647 	.vmm_page_size_bytes = 4096,
648 	.dram_clock_change_latency_us = 23.84,
649 	.return_bus_width_bytes = 64,
650 	.dispclk_dppclk_vco_speed_mhz = 3600,
651 	.xfc_bus_transport_time_us = 4,
652 	.xfc_xbuf_latency_tolerance_us = 4,
653 	.use_urgent_burst_bw = 1,
654 	.num_states = 8
655 };
656 
657 struct wm_table ddr4_wm_table_gs = {
658 	.entries = {
659 		{
660 			.wm_inst = WM_A,
661 			.wm_type = WM_TYPE_PSTATE_CHG,
662 			.pstate_latency_us = 11.72,
663 			.sr_exit_time_us = 7.09,
664 			.sr_enter_plus_exit_time_us = 8.14,
665 			.valid = true,
666 		},
667 		{
668 			.wm_inst = WM_B,
669 			.wm_type = WM_TYPE_PSTATE_CHG,
670 			.pstate_latency_us = 11.72,
671 			.sr_exit_time_us = 10.12,
672 			.sr_enter_plus_exit_time_us = 11.48,
673 			.valid = true,
674 		},
675 		{
676 			.wm_inst = WM_C,
677 			.wm_type = WM_TYPE_PSTATE_CHG,
678 			.pstate_latency_us = 11.72,
679 			.sr_exit_time_us = 10.12,
680 			.sr_enter_plus_exit_time_us = 11.48,
681 			.valid = true,
682 		},
683 		{
684 			.wm_inst = WM_D,
685 			.wm_type = WM_TYPE_PSTATE_CHG,
686 			.pstate_latency_us = 11.72,
687 			.sr_exit_time_us = 10.12,
688 			.sr_enter_plus_exit_time_us = 11.48,
689 			.valid = true,
690 		},
691 	}
692 };
693 
694 struct wm_table lpddr4_wm_table_gs = {
695 	.entries = {
696 		{
697 			.wm_inst = WM_A,
698 			.wm_type = WM_TYPE_PSTATE_CHG,
699 			.pstate_latency_us = 11.65333,
700 			.sr_exit_time_us = 5.32,
701 			.sr_enter_plus_exit_time_us = 6.38,
702 			.valid = true,
703 		},
704 		{
705 			.wm_inst = WM_B,
706 			.wm_type = WM_TYPE_PSTATE_CHG,
707 			.pstate_latency_us = 11.65333,
708 			.sr_exit_time_us = 9.82,
709 			.sr_enter_plus_exit_time_us = 11.196,
710 			.valid = true,
711 		},
712 		{
713 			.wm_inst = WM_C,
714 			.wm_type = WM_TYPE_PSTATE_CHG,
715 			.pstate_latency_us = 11.65333,
716 			.sr_exit_time_us = 9.89,
717 			.sr_enter_plus_exit_time_us = 11.24,
718 			.valid = true,
719 		},
720 		{
721 			.wm_inst = WM_D,
722 			.wm_type = WM_TYPE_PSTATE_CHG,
723 			.pstate_latency_us = 11.65333,
724 			.sr_exit_time_us = 9.748,
725 			.sr_enter_plus_exit_time_us = 11.102,
726 			.valid = true,
727 		},
728 	}
729 };
730 
731 struct wm_table lpddr4_wm_table_with_disabled_ppt = {
732 	.entries = {
733 		{
734 			.wm_inst = WM_A,
735 			.wm_type = WM_TYPE_PSTATE_CHG,
736 			.pstate_latency_us = 11.65333,
737 			.sr_exit_time_us = 8.32,
738 			.sr_enter_plus_exit_time_us = 9.38,
739 			.valid = true,
740 		},
741 		{
742 			.wm_inst = WM_B,
743 			.wm_type = WM_TYPE_PSTATE_CHG,
744 			.pstate_latency_us = 11.65333,
745 			.sr_exit_time_us = 9.82,
746 			.sr_enter_plus_exit_time_us = 11.196,
747 			.valid = true,
748 		},
749 		{
750 			.wm_inst = WM_C,
751 			.wm_type = WM_TYPE_PSTATE_CHG,
752 			.pstate_latency_us = 11.65333,
753 			.sr_exit_time_us = 9.89,
754 			.sr_enter_plus_exit_time_us = 11.24,
755 			.valid = true,
756 		},
757 		{
758 			.wm_inst = WM_D,
759 			.wm_type = WM_TYPE_PSTATE_CHG,
760 			.pstate_latency_us = 11.65333,
761 			.sr_exit_time_us = 9.748,
762 			.sr_enter_plus_exit_time_us = 11.102,
763 			.valid = true,
764 		},
765 	}
766 };
767 
768 struct wm_table ddr4_wm_table_rn = {
769 	.entries = {
770 		{
771 			.wm_inst = WM_A,
772 			.wm_type = WM_TYPE_PSTATE_CHG,
773 			.pstate_latency_us = 11.72,
774 			.sr_exit_time_us = 11.90,
775 			.sr_enter_plus_exit_time_us = 12.80,
776 			.valid = true,
777 		},
778 		{
779 			.wm_inst = WM_B,
780 			.wm_type = WM_TYPE_PSTATE_CHG,
781 			.pstate_latency_us = 11.72,
782 			.sr_exit_time_us = 13.18,
783 			.sr_enter_plus_exit_time_us = 14.30,
784 			.valid = true,
785 		},
786 		{
787 			.wm_inst = WM_C,
788 			.wm_type = WM_TYPE_PSTATE_CHG,
789 			.pstate_latency_us = 11.72,
790 			.sr_exit_time_us = 13.18,
791 			.sr_enter_plus_exit_time_us = 14.30,
792 			.valid = true,
793 		},
794 		{
795 			.wm_inst = WM_D,
796 			.wm_type = WM_TYPE_PSTATE_CHG,
797 			.pstate_latency_us = 11.72,
798 			.sr_exit_time_us = 13.18,
799 			.sr_enter_plus_exit_time_us = 14.30,
800 			.valid = true,
801 		},
802 	}
803 };
804 
805 struct wm_table ddr4_1R_wm_table_rn = {
806 	.entries = {
807 		{
808 			.wm_inst = WM_A,
809 			.wm_type = WM_TYPE_PSTATE_CHG,
810 			.pstate_latency_us = 11.72,
811 			.sr_exit_time_us = 13.90,
812 			.sr_enter_plus_exit_time_us = 14.80,
813 			.valid = true,
814 		},
815 		{
816 			.wm_inst = WM_B,
817 			.wm_type = WM_TYPE_PSTATE_CHG,
818 			.pstate_latency_us = 11.72,
819 			.sr_exit_time_us = 13.90,
820 			.sr_enter_plus_exit_time_us = 14.80,
821 			.valid = true,
822 		},
823 		{
824 			.wm_inst = WM_C,
825 			.wm_type = WM_TYPE_PSTATE_CHG,
826 			.pstate_latency_us = 11.72,
827 			.sr_exit_time_us = 13.90,
828 			.sr_enter_plus_exit_time_us = 14.80,
829 			.valid = true,
830 		},
831 		{
832 			.wm_inst = WM_D,
833 			.wm_type = WM_TYPE_PSTATE_CHG,
834 			.pstate_latency_us = 11.72,
835 			.sr_exit_time_us = 13.90,
836 			.sr_enter_plus_exit_time_us = 14.80,
837 			.valid = true,
838 		},
839 	}
840 };
841 
842 struct wm_table lpddr4_wm_table_rn = {
843 	.entries = {
844 		{
845 			.wm_inst = WM_A,
846 			.wm_type = WM_TYPE_PSTATE_CHG,
847 			.pstate_latency_us = 11.65333,
848 			.sr_exit_time_us = 7.32,
849 			.sr_enter_plus_exit_time_us = 8.38,
850 			.valid = true,
851 		},
852 		{
853 			.wm_inst = WM_B,
854 			.wm_type = WM_TYPE_PSTATE_CHG,
855 			.pstate_latency_us = 11.65333,
856 			.sr_exit_time_us = 9.82,
857 			.sr_enter_plus_exit_time_us = 11.196,
858 			.valid = true,
859 		},
860 		{
861 			.wm_inst = WM_C,
862 			.wm_type = WM_TYPE_PSTATE_CHG,
863 			.pstate_latency_us = 11.65333,
864 			.sr_exit_time_us = 9.89,
865 			.sr_enter_plus_exit_time_us = 11.24,
866 			.valid = true,
867 		},
868 		{
869 			.wm_inst = WM_D,
870 			.wm_type = WM_TYPE_PSTATE_CHG,
871 			.pstate_latency_us = 11.65333,
872 			.sr_exit_time_us = 9.748,
873 			.sr_enter_plus_exit_time_us = 11.102,
874 			.valid = true,
875 		},
876 	}
877 };
878 
dcn20_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)879 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
880 					       struct resource_context *res_ctx,
881 					       display_e2e_pipe_params_st *pipes)
882 {
883 	int pipe_cnt, i;
884 
885 	dc_assert_fp_enabled();
886 
887 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
888 		struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
889 
890 		if (!res_ctx->pipe_ctx[i].stream)
891 			continue;
892 
893 		/* Set writeback information */
894 		pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
895 		pipes[pipe_cnt].dout.num_active_wb++;
896 		pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
897 		pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
898 		pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
899 		pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
900 		pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
901 		pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
902 		pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
903 		pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
904 		pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
905 		pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
906 		if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
907 			if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
908 				pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
909 			else
910 				pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
911 		} else {
912 			pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
913 		}
914 
915 		pipe_cnt++;
916 	}
917 }
918 
dcn20_fpu_set_wb_arb_params(struct mcif_arb_params * wb_arb_params,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int i)919 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
920                                 struct dc_state *context,
921                                 display_e2e_pipe_params_st *pipes,
922                                 int pipe_cnt, int i)
923 {
924        int k;
925 
926        dc_assert_fp_enabled();
927 
928        for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
929                wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
930                wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
931        }
932        wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
933 }
934 
is_dtbclk_required(struct dc * dc,struct dc_state * context)935 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
936 {
937 	int i;
938 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
939 		if (!context->res_ctx.pipe_ctx[i].stream)
940 			continue;
941 		if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
942 			return true;
943 	}
944 	return false;
945 }
946 
decide_zstate_support(struct dc * dc,struct dc_state * context)947 static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struct dc_state *context)
948 {
949 	int plane_count;
950 	int i;
951 	unsigned int optimized_min_dst_y_next_start_us;
952 
953 	plane_count = 0;
954 	optimized_min_dst_y_next_start_us = 0;
955 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
956 		if (context->res_ctx.pipe_ctx[i].plane_state)
957 			plane_count++;
958 	}
959 
960 	/*
961 	 * Z9 and Z10 allowed cases:
962 	 * 	1. 0 Planes enabled
963 	 * 	2. single eDP, on link 0, 1 plane and stutter period > 5ms
964 	 * Z10 only cases:
965 	 * 	1. single eDP, on link 0, 1 plane and stutter period >= 5ms
966 	 * Zstate not allowed cases:
967 	 * 	1. Everything else
968 	 */
969 	if (plane_count == 0)
970 		return DCN_ZSTATE_SUPPORT_ALLOW;
971 	else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
972 		struct dc_link *link = context->streams[0]->sink->link;
973 		struct dc_stream_status *stream_status = &context->stream_status[0];
974 
975 		if (dc_extended_blank_supported(dc)) {
976 			for (i = 0; i < dc->res_pool->pipe_count; i++) {
977 				if (context->res_ctx.pipe_ctx[i].stream == context->streams[0]
978 					&& context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min == context->res_ctx.pipe_ctx[i].stream->adjust.v_total_max
979 					&& context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min > context->res_ctx.pipe_ctx[i].stream->timing.v_total) {
980 						optimized_min_dst_y_next_start_us =
981 							context->res_ctx.pipe_ctx[i].dlg_regs.optimized_min_dst_y_next_start_us;
982 						break;
983 				}
984 			}
985 		}
986 		/* zstate only supported on PWRSEQ0  and when there's <2 planes*/
987 		if (link->link_index != 0 || stream_status->plane_count > 1)
988 			return DCN_ZSTATE_SUPPORT_DISALLOW;
989 
990 		if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000)
991 			return DCN_ZSTATE_SUPPORT_ALLOW;
992 		else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !dc->debug.disable_psr)
993 			return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
994 		else
995 			return DCN_ZSTATE_SUPPORT_DISALLOW;
996 	} else
997 		return DCN_ZSTATE_SUPPORT_DISALLOW;
998 }
999 
dcn20_calculate_dlg_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1000 void dcn20_calculate_dlg_params(
1001 		struct dc *dc, struct dc_state *context,
1002 		display_e2e_pipe_params_st *pipes,
1003 		int pipe_cnt,
1004 		int vlevel)
1005 {
1006 	int i, pipe_idx;
1007 
1008 	dc_assert_fp_enabled();
1009 
1010 	/* Writeback MCIF_WB arbitration parameters */
1011 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1012 
1013 	context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1014 	context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1015 	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1016 	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1017 
1018 	if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
1019 		context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
1020 
1021 	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1022 	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1023 	context->bw_ctx.bw.dcn.clk.p_state_change_support =
1024 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1025 							!= dm_dram_clock_change_unsupported;
1026 
1027 	/* Pstate change might not be supported by hardware, but it might be
1028 	 * possible with firmware driven vertical blank stretching.
1029 	 */
1030 	context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
1031 
1032 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1033 
1034 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1035 
1036 	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1037 		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1038 
1039 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1040 		if (!context->res_ctx.pipe_ctx[i].stream)
1041 			continue;
1042 		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1043 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1044 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1045 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1046 		if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1047 			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1048 			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1049 			context->res_ctx.pipe_ctx[i].unbounded_req = false;
1050 		} else {
1051 			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
1052 			context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
1053 		}
1054 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1055 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1056 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
1057 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1058 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1059 		pipe_idx++;
1060 	}
1061 	/*save a original dppclock copy*/
1062 	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1063 	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1064 	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
1065 	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
1066 
1067 	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
1068 						- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
1069 
1070 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1071 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
1072 
1073 		if (!context->res_ctx.pipe_ctx[i].stream)
1074 			continue;
1075 
1076 		if (dc->ctx->dce_version == DCN_VERSION_2_01)
1077 			cstate_en = false;
1078 
1079 		context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
1080 				&context->res_ctx.pipe_ctx[i].dlg_regs,
1081 				&context->res_ctx.pipe_ctx[i].ttu_regs,
1082 				pipes,
1083 				pipe_cnt,
1084 				pipe_idx,
1085 				cstate_en,
1086 				context->bw_ctx.bw.dcn.clk.p_state_change_support,
1087 				false, false, true);
1088 
1089 		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
1090 				&context->res_ctx.pipe_ctx[i].rq_regs,
1091 				&pipes[pipe_idx].pipe);
1092 		pipe_idx++;
1093 	}
1094 	context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
1095 }
1096 
swizzle_to_dml_params(enum swizzle_mode_values swizzle,unsigned int * sw_mode)1097 static void swizzle_to_dml_params(
1098 		enum swizzle_mode_values swizzle,
1099 		unsigned int *sw_mode)
1100 {
1101 	switch (swizzle) {
1102 	case DC_SW_LINEAR:
1103 		*sw_mode = dm_sw_linear;
1104 		break;
1105 	case DC_SW_4KB_S:
1106 		*sw_mode = dm_sw_4kb_s;
1107 		break;
1108 	case DC_SW_4KB_S_X:
1109 		*sw_mode = dm_sw_4kb_s_x;
1110 		break;
1111 	case DC_SW_4KB_D:
1112 		*sw_mode = dm_sw_4kb_d;
1113 		break;
1114 	case DC_SW_4KB_D_X:
1115 		*sw_mode = dm_sw_4kb_d_x;
1116 		break;
1117 	case DC_SW_64KB_S:
1118 		*sw_mode = dm_sw_64kb_s;
1119 		break;
1120 	case DC_SW_64KB_S_X:
1121 		*sw_mode = dm_sw_64kb_s_x;
1122 		break;
1123 	case DC_SW_64KB_S_T:
1124 		*sw_mode = dm_sw_64kb_s_t;
1125 		break;
1126 	case DC_SW_64KB_D:
1127 		*sw_mode = dm_sw_64kb_d;
1128 		break;
1129 	case DC_SW_64KB_D_X:
1130 		*sw_mode = dm_sw_64kb_d_x;
1131 		break;
1132 	case DC_SW_64KB_D_T:
1133 		*sw_mode = dm_sw_64kb_d_t;
1134 		break;
1135 	case DC_SW_64KB_R_X:
1136 		*sw_mode = dm_sw_64kb_r_x;
1137 		break;
1138 	case DC_SW_VAR_S:
1139 		*sw_mode = dm_sw_var_s;
1140 		break;
1141 	case DC_SW_VAR_S_X:
1142 		*sw_mode = dm_sw_var_s_x;
1143 		break;
1144 	case DC_SW_VAR_D:
1145 		*sw_mode = dm_sw_var_d;
1146 		break;
1147 	case DC_SW_VAR_D_X:
1148 		*sw_mode = dm_sw_var_d_x;
1149 		break;
1150 	case DC_SW_VAR_R_X:
1151 		*sw_mode = dm_sw_var_r_x;
1152 		break;
1153 	default:
1154 		ASSERT(0); /* Not supported */
1155 		break;
1156 	}
1157 }
1158 
dcn20_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1159 int dcn20_populate_dml_pipes_from_context(
1160 		struct dc *dc,
1161 		struct dc_state *context,
1162 		display_e2e_pipe_params_st *pipes,
1163 		bool fast_validate)
1164 {
1165 	int pipe_cnt, i;
1166 	bool synchronized_vblank = true;
1167 	struct resource_context *res_ctx = &context->res_ctx;
1168 
1169 	dc_assert_fp_enabled();
1170 
1171 	for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1172 		if (!res_ctx->pipe_ctx[i].stream)
1173 			continue;
1174 
1175 		if (pipe_cnt < 0) {
1176 			pipe_cnt = i;
1177 			continue;
1178 		}
1179 
1180 		if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
1181 			continue;
1182 
1183 		if (dc->debug.disable_timing_sync ||
1184 			(!resource_are_streams_timing_synchronizable(
1185 				res_ctx->pipe_ctx[pipe_cnt].stream,
1186 				res_ctx->pipe_ctx[i].stream) &&
1187 			!resource_are_vblanks_synchronizable(
1188 				res_ctx->pipe_ctx[pipe_cnt].stream,
1189 				res_ctx->pipe_ctx[i].stream))) {
1190 			synchronized_vblank = false;
1191 			break;
1192 		}
1193 	}
1194 
1195 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1196 		struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1197 		unsigned int v_total;
1198 		unsigned int front_porch;
1199 		int output_bpc;
1200 		struct audio_check aud_check = {0};
1201 
1202 		if (!res_ctx->pipe_ctx[i].stream)
1203 			continue;
1204 
1205 		v_total = timing->v_total;
1206 		front_porch = timing->v_front_porch;
1207 
1208 		/* todo:
1209 		pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1210 		pipes[pipe_cnt].pipe.src.dcc = 0;
1211 		pipes[pipe_cnt].pipe.src.vm = 0;*/
1212 
1213 		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1214 
1215 		pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1216 		/* todo: rotation?*/
1217 		pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1218 		if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1219 			pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1220 			/* 1/2 vblank */
1221 			pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1222 				(v_total - timing->v_addressable
1223 					- timing->v_border_top - timing->v_border_bottom) / 2;
1224 			/* 36 bytes dp, 32 hdmi */
1225 			pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1226 				dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1227 		}
1228 		pipes[pipe_cnt].pipe.src.dcc = false;
1229 		pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1230 		pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1231 		pipes[pipe_cnt].pipe.dest.synchronize_timings = synchronized_vblank;
1232 		pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1233 		pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1234 				- timing->h_addressable
1235 				- timing->h_border_left
1236 				- timing->h_border_right;
1237 		pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
1238 		pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1239 				- timing->v_addressable
1240 				- timing->v_border_top
1241 				- timing->v_border_bottom;
1242 		pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1243 		pipes[pipe_cnt].pipe.dest.vtotal = v_total;
1244 		pipes[pipe_cnt].pipe.dest.hactive =
1245 			timing->h_addressable + timing->h_border_left + timing->h_border_right;
1246 		pipes[pipe_cnt].pipe.dest.vactive =
1247 			timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1248 		pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1249 		pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1250 		if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1251 			pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1252 		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1253 		pipes[pipe_cnt].dout.dp_lanes = 4;
1254 		if (res_ctx->pipe_ctx[i].stream->link)
1255 			pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
1256 		pipes[pipe_cnt].dout.is_virtual = 0;
1257 		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1258 		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1259 		switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
1260 		case 1:
1261 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
1262 			break;
1263 		case 3:
1264 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
1265 			break;
1266 		default:
1267 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
1268 		}
1269 		pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1270 		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1271 				== res_ctx->pipe_ctx[i].plane_state) {
1272 			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
1273 			int split_idx = 0;
1274 
1275 			while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
1276 					== res_ctx->pipe_ctx[i].plane_state) {
1277 				first_pipe = first_pipe->top_pipe;
1278 				split_idx++;
1279 			}
1280 			/* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
1281 			if (split_idx == 0)
1282 				pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1283 			else if (split_idx == 1)
1284 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1285 			else if (split_idx == 2)
1286 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1287 		} else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1288 			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1289 
1290 			while (first_pipe->prev_odm_pipe)
1291 				first_pipe = first_pipe->prev_odm_pipe;
1292 			pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1293 		}
1294 
1295 		switch (res_ctx->pipe_ctx[i].stream->signal) {
1296 		case SIGNAL_TYPE_DISPLAY_PORT_MST:
1297 		case SIGNAL_TYPE_DISPLAY_PORT:
1298 			pipes[pipe_cnt].dout.output_type = dm_dp;
1299 			break;
1300 		case SIGNAL_TYPE_EDP:
1301 			pipes[pipe_cnt].dout.output_type = dm_edp;
1302 			break;
1303 		case SIGNAL_TYPE_HDMI_TYPE_A:
1304 		case SIGNAL_TYPE_DVI_SINGLE_LINK:
1305 		case SIGNAL_TYPE_DVI_DUAL_LINK:
1306 			pipes[pipe_cnt].dout.output_type = dm_hdmi;
1307 			break;
1308 		default:
1309 			/* In case there is no signal, set dp with 4 lanes to allow max config */
1310 			pipes[pipe_cnt].dout.is_virtual = 1;
1311 			pipes[pipe_cnt].dout.output_type = dm_dp;
1312 			pipes[pipe_cnt].dout.dp_lanes = 4;
1313 			pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
1314 		}
1315 
1316 		switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1317 		case COLOR_DEPTH_666:
1318 			output_bpc = 6;
1319 			break;
1320 		case COLOR_DEPTH_888:
1321 			output_bpc = 8;
1322 			break;
1323 		case COLOR_DEPTH_101010:
1324 			output_bpc = 10;
1325 			break;
1326 		case COLOR_DEPTH_121212:
1327 			output_bpc = 12;
1328 			break;
1329 		case COLOR_DEPTH_141414:
1330 			output_bpc = 14;
1331 			break;
1332 		case COLOR_DEPTH_161616:
1333 			output_bpc = 16;
1334 			break;
1335 		case COLOR_DEPTH_999:
1336 			output_bpc = 9;
1337 			break;
1338 		case COLOR_DEPTH_111111:
1339 			output_bpc = 11;
1340 			break;
1341 		default:
1342 			output_bpc = 8;
1343 			break;
1344 		}
1345 
1346 		switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1347 		case PIXEL_ENCODING_RGB:
1348 		case PIXEL_ENCODING_YCBCR444:
1349 			pipes[pipe_cnt].dout.output_format = dm_444;
1350 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1351 			break;
1352 		case PIXEL_ENCODING_YCBCR420:
1353 			pipes[pipe_cnt].dout.output_format = dm_420;
1354 			pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
1355 			break;
1356 		case PIXEL_ENCODING_YCBCR422:
1357 			if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
1358 			    !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
1359 				pipes[pipe_cnt].dout.output_format = dm_n422;
1360 			else
1361 				pipes[pipe_cnt].dout.output_format = dm_s422;
1362 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1363 			break;
1364 		default:
1365 			pipes[pipe_cnt].dout.output_format = dm_444;
1366 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1367 		}
1368 
1369 		if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
1370 			pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
1371 
1372 		/* todo: default max for now, until there is logic reflecting this in dc*/
1373 		pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1374 		/*fill up the audio sample rate (unit in kHz)*/
1375 		get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
1376 		pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
1377 		/*
1378 		 * For graphic plane, cursor number is 1, nv12 is 0
1379 		 * bw calculations due to cursor on/off
1380 		 */
1381 		if (res_ctx->pipe_ctx[i].plane_state &&
1382 				(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||
1383 				 res_ctx->pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM))
1384 			pipes[pipe_cnt].pipe.src.num_cursors = 0;
1385 		else
1386 			pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
1387 
1388 		pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1389 		pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1390 
1391 		if (!res_ctx->pipe_ctx[i].plane_state) {
1392 			pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1393 			pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1394 			pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1395 			pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
1396 			pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1397 			pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1398 			if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1399 				pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1400 			pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1401 			if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1402 				pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1403 			pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
1404 			pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
1405 			pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
1406 			pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
1407 			pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
1408 			pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1409 			pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1410 			pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1411 			pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
1412 			pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1413 			pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1414 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1415 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1416 			pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1417 			pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1418 			pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1419 			pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
1420 			pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
1421 
1422 			if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
1423 				pipes[pipe_cnt].pipe.src.viewport_width /= 2;
1424 				pipes[pipe_cnt].pipe.dest.recout_width /= 2;
1425 			} else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
1426 				pipes[pipe_cnt].pipe.src.viewport_width /= 4;
1427 				pipes[pipe_cnt].pipe.dest.recout_width /= 4;
1428 			}
1429 		} else {
1430 			struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1431 			struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1432 
1433 			pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1434 			pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1435 					|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
1436 					|| pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1437 
1438 			/* stereo is not split */
1439 			if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
1440 			    pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
1441 				pipes[pipe_cnt].pipe.src.is_hsplit = false;
1442 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1443 			}
1444 
1445 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1446 					|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1447 			switch (pln->rotation) {
1448 			case ROTATION_ANGLE_0:
1449 				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1450 				break;
1451 			case ROTATION_ANGLE_90:
1452 				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90;
1453 				break;
1454 			case ROTATION_ANGLE_180:
1455 				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180;
1456 				break;
1457 			case ROTATION_ANGLE_270:
1458 				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270;
1459 				break;
1460 			default:
1461 				break;
1462 			}
1463 			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1464 			pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1465 			pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x;
1466 			pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x;
1467 			pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1468 			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1469 			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1470 			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1471 			pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
1472 			pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
1473 			pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
1474 			pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
1475 			pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
1476 			pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
1477 			if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
1478 					|| pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1479 				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1480 				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1481 				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1482 				pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
1483 			} else {
1484 				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1485 				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1486 			}
1487 			pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1488 			pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1489 			pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1490 			pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1491 			pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1492 			if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
1493 				pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
1494 			else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
1495 				pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
1496 			else {
1497 				struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
1498 
1499 				while (split_pipe && split_pipe->plane_state == pln) {
1500 					pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1501 					split_pipe = split_pipe->bottom_pipe;
1502 				}
1503 				split_pipe = res_ctx->pipe_ctx[i].top_pipe;
1504 				while (split_pipe && split_pipe->plane_state == pln) {
1505 					pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1506 					split_pipe = split_pipe->top_pipe;
1507 				}
1508 			}
1509 
1510 			pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1511 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1512 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1513 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1514 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1515 			pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1516 					scl->ratios.vert.value != dc_fixpt_one.value
1517 					|| scl->ratios.horz.value != dc_fixpt_one.value
1518 					|| scl->ratios.vert_c.value != dc_fixpt_one.value
1519 					|| scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1520 					|| dc->debug.always_scale; /*support always scale*/
1521 			pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1522 			pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1523 			pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1524 			pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1525 
1526 			pipes[pipe_cnt].pipe.src.macro_tile_size =
1527 					swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
1528 			swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1529 					&pipes[pipe_cnt].pipe.src.sw_mode);
1530 
1531 			switch (pln->format) {
1532 			case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1533 			case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1534 				pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1535 				break;
1536 			case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1537 			case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1538 				pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1539 				break;
1540 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1541 			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
1542 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1543 			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1544 				pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1545 				break;
1546 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1547 			case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1548 				pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1549 				break;
1550 			case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1551 				pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1552 				break;
1553 			case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
1554 				pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
1555 				break;
1556 			default:
1557 				pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1558 				break;
1559 			}
1560 		}
1561 
1562 		pipe_cnt++;
1563 	}
1564 
1565 	/* populate writeback information */
1566 	dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1567 
1568 	return pipe_cnt;
1569 }
1570 
dcn20_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel,bool fast_validate)1571 void dcn20_calculate_wm(
1572 		struct dc *dc, struct dc_state *context,
1573 		display_e2e_pipe_params_st *pipes,
1574 		int *out_pipe_cnt,
1575 		int *pipe_split_from,
1576 		int vlevel,
1577 		bool fast_validate)
1578 {
1579 	int pipe_cnt, i, pipe_idx;
1580 
1581 	dc_assert_fp_enabled();
1582 
1583 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1584 		if (!context->res_ctx.pipe_ctx[i].stream)
1585 			continue;
1586 
1587 		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1588 		pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1589 
1590 		if (pipe_split_from[i] < 0) {
1591 			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1592 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1593 			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1594 				pipes[pipe_cnt].pipe.dest.odm_combine =
1595 						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
1596 			else
1597 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1598 			pipe_idx++;
1599 		} else {
1600 			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1601 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1602 			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1603 				pipes[pipe_cnt].pipe.dest.odm_combine =
1604 						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
1605 			else
1606 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1607 		}
1608 
1609 		if (dc->config.forced_clocks) {
1610 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1611 			pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1612 		}
1613 		if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
1614 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1615 		if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
1616 			pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1617 
1618 		pipe_cnt++;
1619 	}
1620 
1621 	if (pipe_cnt != pipe_idx) {
1622 		if (dc->res_pool->funcs->populate_dml_pipes)
1623 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1624 				context, pipes, fast_validate);
1625 		else
1626 			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
1627 				context, pipes, fast_validate);
1628 	}
1629 
1630 	*out_pipe_cnt = pipe_cnt;
1631 
1632 	pipes[0].clks_cfg.voltage = vlevel;
1633 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1634 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1635 
1636 	/* only pipe 0 is read for voltage and dcf/soc clocks */
1637 	if (vlevel < 1) {
1638 		pipes[0].clks_cfg.voltage = 1;
1639 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
1640 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
1641 	}
1642 	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1643 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1644 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1645 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1646 	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1647 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1648 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1649 	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1650 
1651 	if (vlevel < 2) {
1652 		pipes[0].clks_cfg.voltage = 2;
1653 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1654 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1655 	}
1656 	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1657 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1658 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1659 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1660 	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1661 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1662 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1663 
1664 	if (vlevel < 3) {
1665 		pipes[0].clks_cfg.voltage = 3;
1666 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1667 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1668 	}
1669 	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1670 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1671 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1672 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1673 	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1674 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1675 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1676 
1677 	pipes[0].clks_cfg.voltage = vlevel;
1678 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1679 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1680 	context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1681 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1682 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1683 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1684 	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1685 	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1686 	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1687 }
1688 
dcn20_update_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb,struct pp_smu_nv_clock_table * max_clocks,unsigned int * uclk_states,unsigned int num_states)1689 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
1690 		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
1691 {
1692 	int num_calculated_states = 0;
1693 	int min_dcfclk = 0;
1694 	int i;
1695 
1696 	dc_assert_fp_enabled();
1697 
1698 	if (num_states == 0)
1699 		return;
1700 
1701 	memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
1702 
1703 	if (dc->bb_overrides.min_dcfclk_mhz > 0) {
1704 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
1705 	} else {
1706 		if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
1707 			min_dcfclk = 310;
1708 		else
1709 			// Accounting for SOC/DCF relationship, we can go as high as
1710 			// 506Mhz in Vmin.
1711 			min_dcfclk = 506;
1712 	}
1713 
1714 	for (i = 0; i < num_states; i++) {
1715 		int min_fclk_required_by_uclk;
1716 		bb->clock_limits[i].state = i;
1717 		bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
1718 
1719 		// FCLK:UCLK ratio is 1.08
1720 		min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
1721 			1000000);
1722 
1723 		bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
1724 				min_dcfclk : min_fclk_required_by_uclk;
1725 
1726 		bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
1727 				max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
1728 
1729 		bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
1730 				max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
1731 
1732 		bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
1733 		bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
1734 		bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
1735 
1736 		bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
1737 
1738 		num_calculated_states++;
1739 	}
1740 
1741 	bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
1742 	bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
1743 	bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
1744 
1745 	bb->num_states = num_calculated_states;
1746 
1747 	// Duplicate the last state, DML always an extra state identical to max state to work
1748 	memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
1749 	bb->clock_limits[num_calculated_states].state = bb->num_states;
1750 }
1751 
dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st * bb,struct pp_smu_nv_clock_table max_clocks)1752 void dcn20_cap_soc_clocks(
1753 		struct _vcs_dpi_soc_bounding_box_st *bb,
1754 		struct pp_smu_nv_clock_table max_clocks)
1755 {
1756 	int i;
1757 
1758 	dc_assert_fp_enabled();
1759 
1760 	// First pass - cap all clocks higher than the reported max
1761 	for (i = 0; i < bb->num_states; i++) {
1762 		if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
1763 				&& max_clocks.dcfClockInKhz != 0)
1764 			bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
1765 
1766 		if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
1767 						&& max_clocks.uClockInKhz != 0)
1768 			bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
1769 
1770 		if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
1771 						&& max_clocks.fabricClockInKhz != 0)
1772 			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
1773 
1774 		if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
1775 						&& max_clocks.displayClockInKhz != 0)
1776 			bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
1777 
1778 		if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
1779 						&& max_clocks.dppClockInKhz != 0)
1780 			bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
1781 
1782 		if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
1783 						&& max_clocks.phyClockInKhz != 0)
1784 			bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
1785 
1786 		if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
1787 						&& max_clocks.socClockInKhz != 0)
1788 			bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
1789 
1790 		if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
1791 						&& max_clocks.dscClockInKhz != 0)
1792 			bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
1793 	}
1794 
1795 	// Second pass - remove all duplicate clock states
1796 	for (i = bb->num_states - 1; i > 1; i--) {
1797 		bool duplicate = true;
1798 
1799 		if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
1800 			duplicate = false;
1801 		if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
1802 			duplicate = false;
1803 		if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
1804 			duplicate = false;
1805 		if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
1806 			duplicate = false;
1807 		if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
1808 			duplicate = false;
1809 		if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
1810 			duplicate = false;
1811 		if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
1812 			duplicate = false;
1813 		if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
1814 			duplicate = false;
1815 
1816 		if (duplicate)
1817 			bb->num_states--;
1818 	}
1819 }
1820 
dcn20_patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)1821 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1822 {
1823 	dc_assert_fp_enabled();
1824 
1825 	if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
1826 			&& dc->bb_overrides.sr_exit_time_ns) {
1827 		bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
1828 	}
1829 
1830 	if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
1831 				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
1832 			&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1833 		bb->sr_enter_plus_exit_time_us =
1834 				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1835 	}
1836 
1837 	if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
1838 			&& dc->bb_overrides.urgent_latency_ns) {
1839 		bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1840 	}
1841 
1842 	if ((int)(bb->dram_clock_change_latency_us * 1000)
1843 				!= dc->bb_overrides.dram_clock_change_latency_ns
1844 			&& dc->bb_overrides.dram_clock_change_latency_ns) {
1845 		bb->dram_clock_change_latency_us =
1846 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1847 	}
1848 
1849 	if ((int)(bb->dummy_pstate_latency_us * 1000)
1850 				!= dc->bb_overrides.dummy_clock_change_latency_ns
1851 			&& dc->bb_overrides.dummy_clock_change_latency_ns) {
1852 		bb->dummy_pstate_latency_us =
1853 				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
1854 	}
1855 }
1856 
dcn20_validate_bandwidth_internal(struct dc * dc,struct dc_state * context,bool fast_validate)1857 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
1858 		bool fast_validate)
1859 {
1860 	bool out = false;
1861 
1862 	BW_VAL_TRACE_SETUP();
1863 
1864 	int vlevel = 0;
1865 	int pipe_split_from[MAX_PIPES];
1866 	int pipe_cnt = 0;
1867 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1868 	DC_LOGGER_INIT(dc->ctx->logger);
1869 
1870 	BW_VAL_TRACE_COUNT();
1871 
1872 	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1873 
1874 	if (pipe_cnt == 0)
1875 		goto validate_out;
1876 
1877 	if (!out)
1878 		goto validate_fail;
1879 
1880 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1881 
1882 	if (fast_validate) {
1883 		BW_VAL_TRACE_SKIP(fast);
1884 		goto validate_out;
1885 	}
1886 
1887 	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1888 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1889 
1890 	BW_VAL_TRACE_END_WATERMARKS();
1891 
1892 	goto validate_out;
1893 
1894 validate_fail:
1895 	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1896 		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1897 
1898 	BW_VAL_TRACE_SKIP(fail);
1899 	out = false;
1900 
1901 validate_out:
1902 	kfree(pipes);
1903 
1904 	BW_VAL_TRACE_FINISH();
1905 
1906 	return out;
1907 }
1908 
dcn20_validate_bandwidth_fp(struct dc * dc,struct dc_state * context,bool fast_validate)1909 bool dcn20_validate_bandwidth_fp(struct dc *dc,
1910                                 struct dc_state *context,
1911                                 bool fast_validate)
1912 {
1913        bool voltage_supported = false;
1914        bool full_pstate_supported = false;
1915        bool dummy_pstate_supported = false;
1916        double p_state_latency_us;
1917 
1918        dc_assert_fp_enabled();
1919 
1920        p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
1921        context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
1922                dc->debug.disable_dram_clock_change_vactive_support;
1923        context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
1924                dc->debug.enable_dram_clock_change_one_display_vactive;
1925 
1926        /*Unsafe due to current pipe merge and split logic*/
1927        ASSERT(context != dc->current_state);
1928 
1929        if (fast_validate) {
1930                return dcn20_validate_bandwidth_internal(dc, context, true);
1931        }
1932 
1933        // Best case, we support full UCLK switch latency
1934        voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
1935        full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1936 
1937        if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
1938                (voltage_supported && full_pstate_supported)) {
1939                context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
1940                goto restore_dml_state;
1941        }
1942 
1943        // Fallback: Try to only support G6 temperature read latency
1944        context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
1945 
1946        voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
1947        dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1948 
1949        if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
1950                context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1951                goto restore_dml_state;
1952        }
1953 
1954        // ERROR: fallback is supposed to always work.
1955        ASSERT(false);
1956 
1957 restore_dml_state:
1958        context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
1959        return voltage_supported;
1960 }
1961 
dcn20_fpu_set_wm_ranges(int i,struct pp_smu_wm_range_sets * ranges,struct _vcs_dpi_soc_bounding_box_st * loaded_bb)1962 void dcn20_fpu_set_wm_ranges(int i,
1963                             struct pp_smu_wm_range_sets *ranges,
1964                             struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1965 {
1966        dc_assert_fp_enabled();
1967 
1968        ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
1969        ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
1970 }
1971 
dcn20_fpu_adjust_dppclk(struct vba_vars_st * v,int vlevel,int max_mpc_comb,int pipe_idx,bool is_validating_bw)1972 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
1973                             int vlevel,
1974                             int max_mpc_comb,
1975                             int pipe_idx,
1976                             bool is_validating_bw)
1977 {
1978        dc_assert_fp_enabled();
1979 
1980        if (is_validating_bw)
1981                v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2;
1982        else
1983                v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
1984 }
1985 
dcn21_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1986 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
1987 					  struct dc_state *context,
1988 					  display_e2e_pipe_params_st *pipes,
1989 					  bool fast_validate)
1990 {
1991 	uint32_t pipe_cnt;
1992 	int i;
1993 
1994 	dc_assert_fp_enabled();
1995 
1996 	pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1997 
1998 	for (i = 0; i < pipe_cnt; i++) {
1999 
2000 		pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
2001 		pipes[i].pipe.src.gpuvm = 1;
2002 	}
2003 
2004 	return pipe_cnt;
2005 }
2006 
patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)2007 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2008 {
2009 	int i;
2010 
2011 	if (dc->bb_overrides.sr_exit_time_ns) {
2012 		for (i = 0; i < WM_SET_COUNT; i++) {
2013 			  dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
2014 					  dc->bb_overrides.sr_exit_time_ns / 1000.0;
2015 		}
2016 	}
2017 
2018 	if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2019 		for (i = 0; i < WM_SET_COUNT; i++) {
2020 			  dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
2021 					  dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2022 		}
2023 	}
2024 
2025 	if (dc->bb_overrides.urgent_latency_ns) {
2026 		bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2027 	}
2028 
2029 	if (dc->bb_overrides.dram_clock_change_latency_ns) {
2030 		for (i = 0; i < WM_SET_COUNT; i++) {
2031 			dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
2032 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2033 		}
2034 	}
2035 }
2036 
calculate_wm_set_for_vlevel(int vlevel,struct wm_range_table_entry * table_entry,struct dcn_watermarks * wm_set,struct display_mode_lib * dml,display_e2e_pipe_params_st * pipes,int pipe_cnt)2037 static void calculate_wm_set_for_vlevel(int vlevel,
2038 					struct wm_range_table_entry *table_entry,
2039 					struct dcn_watermarks *wm_set,
2040 					struct display_mode_lib *dml,
2041 					display_e2e_pipe_params_st *pipes,
2042 					int pipe_cnt)
2043 {
2044 	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
2045 
2046 	ASSERT(vlevel < dml->soc.num_states);
2047 	/* only pipe 0 is read for voltage and dcf/soc clocks */
2048 	pipes[0].clks_cfg.voltage = vlevel;
2049 	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
2050 	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
2051 
2052 	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
2053 	dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
2054 	dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
2055 
2056 	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
2057 	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
2058 	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
2059 	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
2060 	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
2061 	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
2062 	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
2063 	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
2064 	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
2065 }
2066 
dcn21_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel_req,bool fast_validate)2067 static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,
2068 			display_e2e_pipe_params_st *pipes,
2069 			int *out_pipe_cnt,
2070 			int *pipe_split_from,
2071 			int vlevel_req,
2072 			bool fast_validate)
2073 {
2074 	int pipe_cnt, i, pipe_idx;
2075 	int vlevel, vlevel_max;
2076 	struct wm_range_table_entry *table_entry;
2077 	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
2078 
2079 	ASSERT(bw_params);
2080 
2081 	patch_bounding_box(dc, &context->bw_ctx.dml.soc);
2082 
2083 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2084 			if (!context->res_ctx.pipe_ctx[i].stream)
2085 				continue;
2086 
2087 			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2088 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
2089 
2090 			if (pipe_split_from[i] < 0) {
2091 				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2092 						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2093 				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2094 					pipes[pipe_cnt].pipe.dest.odm_combine =
2095 							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
2096 				else
2097 					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2098 				pipe_idx++;
2099 			} else {
2100 				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2101 						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2102 				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2103 					pipes[pipe_cnt].pipe.dest.odm_combine =
2104 							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
2105 				else
2106 					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2107 			}
2108 			pipe_cnt++;
2109 	}
2110 
2111 	if (pipe_cnt != pipe_idx) {
2112 		if (dc->res_pool->funcs->populate_dml_pipes)
2113 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2114 				context, pipes, fast_validate);
2115 		else
2116 			pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2117 				context, pipes, fast_validate);
2118 	}
2119 
2120 	*out_pipe_cnt = pipe_cnt;
2121 
2122 	vlevel_max = bw_params->clk_table.num_entries - 1;
2123 
2124 
2125 	/* WM Set D */
2126 	table_entry = &bw_params->wm_table.entries[WM_D];
2127 	if (table_entry->wm_type == WM_TYPE_RETRAINING)
2128 		vlevel = 0;
2129 	else
2130 		vlevel = vlevel_max;
2131 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
2132 						&context->bw_ctx.dml, pipes, pipe_cnt);
2133 	/* WM Set C */
2134 	table_entry = &bw_params->wm_table.entries[WM_C];
2135 	vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
2136 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
2137 						&context->bw_ctx.dml, pipes, pipe_cnt);
2138 	/* WM Set B */
2139 	table_entry = &bw_params->wm_table.entries[WM_B];
2140 	vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
2141 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
2142 						&context->bw_ctx.dml, pipes, pipe_cnt);
2143 
2144 	/* WM Set A */
2145 	table_entry = &bw_params->wm_table.entries[WM_A];
2146 	vlevel = MIN(vlevel_req, vlevel_max);
2147 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
2148 						&context->bw_ctx.dml, pipes, pipe_cnt);
2149 }
2150 
dcn21_validate_bandwidth_fp(struct dc * dc,struct dc_state * context,bool fast_validate)2151 bool dcn21_validate_bandwidth_fp(struct dc *dc,
2152 				 struct dc_state *context,
2153 				 bool fast_validate)
2154 {
2155 	bool out = false;
2156 
2157 	BW_VAL_TRACE_SETUP();
2158 
2159 	int vlevel = 0;
2160 	int pipe_split_from[MAX_PIPES];
2161 	int pipe_cnt = 0;
2162 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
2163 	DC_LOGGER_INIT(dc->ctx->logger);
2164 
2165 	BW_VAL_TRACE_COUNT();
2166 
2167 	dc_assert_fp_enabled();
2168 
2169 	/*Unsafe due to current pipe merge and split logic*/
2170 	ASSERT(context != dc->current_state);
2171 
2172 	out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2173 
2174 	if (pipe_cnt == 0)
2175 		goto validate_out;
2176 
2177 	if (!out)
2178 		goto validate_fail;
2179 
2180 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2181 
2182 	if (fast_validate) {
2183 		BW_VAL_TRACE_SKIP(fast);
2184 		goto validate_out;
2185 	}
2186 
2187 	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2188 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2189 
2190 	BW_VAL_TRACE_END_WATERMARKS();
2191 
2192 	goto validate_out;
2193 
2194 validate_fail:
2195 	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2196 			dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2197 
2198 	BW_VAL_TRACE_SKIP(fail);
2199 	out = false;
2200 
2201 validate_out:
2202 	kfree(pipes);
2203 
2204 	BW_VAL_TRACE_FINISH();
2205 
2206 	return out;
2207 }
2208 
construct_low_pstate_lvl(struct clk_limit_table * clk_table,unsigned int high_voltage_lvl)2209 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
2210 {
2211 	struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
2212 	int i;
2213 
2214 	low_pstate_lvl.state = 1;
2215 	low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
2216 	low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
2217 	low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
2218 	low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
2219 
2220 	low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
2221 	low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
2222 	low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
2223 	low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
2224 	low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
2225 	low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
2226 	low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
2227 
2228 	for (i = clk_table->num_entries; i > 1; i--)
2229 		clk_table->entries[i] = clk_table->entries[i-1];
2230 	clk_table->entries[1] = clk_table->entries[0];
2231 	clk_table->num_entries++;
2232 
2233 	return low_pstate_lvl;
2234 }
2235 
dcn21_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)2236 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2237 {
2238 	struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
2239 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
2240 	struct clk_limit_table *clk_table = &bw_params->clk_table;
2241 	unsigned int i, closest_clk_lvl = 0, k = 0;
2242 	int j;
2243 
2244 	dc_assert_fp_enabled();
2245 
2246 	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2247 	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
2248 	dcn2_1_soc.num_chans = bw_params->num_channels;
2249 
2250 	ASSERT(clk_table->num_entries);
2251 	/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
2252 	memcpy(s, dcn2_1_soc.clock_limits, sizeof(dcn2_1_soc.clock_limits));
2253 
2254 	for (i = 0; i < clk_table->num_entries; i++) {
2255 		/* loop backwards*/
2256 		for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
2257 			if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2258 				closest_clk_lvl = j;
2259 				break;
2260 			}
2261 		}
2262 
2263 		/* clk_table[1] is reserved for min DF PState.  skip here to fill in later. */
2264 		if (i == 1)
2265 			k++;
2266 
2267 		s[k].state = k;
2268 		s[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2269 		s[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2270 		s[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
2271 		s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
2272 
2273 		s[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2274 		s[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2275 		s[k].dram_bw_per_chan_gbps =
2276 			dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2277 		s[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2278 		s[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2279 		s[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2280 		s[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2281 
2282 		k++;
2283 	}
2284 
2285 	memcpy(dcn2_1_soc.clock_limits, s, sizeof(dcn2_1_soc.clock_limits));
2286 
2287 	if (clk_table->num_entries) {
2288 		dcn2_1_soc.num_states = clk_table->num_entries + 1;
2289 		/* fill in min DF PState */
2290 		dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
2291 		/* duplicate last level */
2292 		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
2293 		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
2294 	}
2295 
2296 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2297 }
2298 
dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params * bw_params)2299 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params)
2300 {
2301 	dc_assert_fp_enabled();
2302 
2303 	bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
2304 	bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
2305 	bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
2306 	bw_params->wm_table.entries[WM_D].valid = true;
2307 }
2308 
dcn201_populate_dml_writeback_from_context_fpu(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)2309 void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
2310 						    struct resource_context *res_ctx,
2311 						    display_e2e_pipe_params_st *pipes)
2312 {
2313 	int pipe_cnt, i, j;
2314 	double max_calc_writeback_dispclk;
2315 	double writeback_dispclk;
2316 	struct writeback_st dout_wb;
2317 
2318 	dc_assert_fp_enabled();
2319 
2320 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2321 		struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
2322 
2323 		if (!stream)
2324 			continue;
2325 		max_calc_writeback_dispclk = 0;
2326 
2327 		/* Set writeback information */
2328 		pipes[pipe_cnt].dout.wb_enable = 0;
2329 		pipes[pipe_cnt].dout.num_active_wb = 0;
2330 		for (j = 0; j < stream->num_wb_info; j++) {
2331 			struct dc_writeback_info *wb_info = &stream->writeback_info[j];
2332 
2333 			if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
2334 					(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
2335 				pipes[pipe_cnt].dout.wb_enable = 1;
2336 				pipes[pipe_cnt].dout.num_active_wb++;
2337 				dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
2338 					wb_info->dwb_params.cnv_params.crop_height :
2339 					wb_info->dwb_params.cnv_params.src_height;
2340 				dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
2341 					wb_info->dwb_params.cnv_params.crop_width :
2342 					wb_info->dwb_params.cnv_params.src_width;
2343 				dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
2344 				dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
2345 				dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
2346 				dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
2347 				dout_wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
2348 				dout_wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
2349 				dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
2350 					(double)wb_info->dwb_params.cnv_params.crop_width /
2351 						(double)wb_info->dwb_params.dest_width :
2352 					(double)wb_info->dwb_params.cnv_params.src_width /
2353 						(double)wb_info->dwb_params.dest_width;
2354 				dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
2355 					(double)wb_info->dwb_params.cnv_params.crop_height /
2356 						(double)wb_info->dwb_params.dest_height :
2357 					(double)wb_info->dwb_params.cnv_params.src_height /
2358 						(double)wb_info->dwb_params.dest_height;
2359 				if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
2360 					if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2361 						dout_wb.wb_pixel_format = dm_420_8;
2362 					else
2363 						dout_wb.wb_pixel_format = dm_420_10;
2364 				} else
2365 					dout_wb.wb_pixel_format = dm_444_32;
2366 
2367 				/* Workaround for cases where multiple writebacks are connected to same plane
2368 				 * In which case, need to compute worst case and set the associated writeback parameters
2369 				 * This workaround is necessary due to DML computation assuming only 1 set of writeback
2370 				 * parameters per pipe */
2371 				writeback_dispclk = CalculateWriteBackDISPCLK(
2372 						dout_wb.wb_pixel_format,
2373 						pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
2374 						dout_wb.wb_hratio,
2375 						dout_wb.wb_vratio,
2376 						dout_wb.wb_htaps_luma,
2377 						dout_wb.wb_vtaps_luma,
2378 						dout_wb.wb_htaps_chroma,
2379 						dout_wb.wb_vtaps_chroma,
2380 						dout_wb.wb_dst_width,
2381 						pipes[pipe_cnt].pipe.dest.htotal,
2382 						2);
2383 
2384 				if (writeback_dispclk > max_calc_writeback_dispclk) {
2385 					max_calc_writeback_dispclk = writeback_dispclk;
2386 					pipes[pipe_cnt].dout.wb = dout_wb;
2387 				}
2388 			}
2389 		}
2390 
2391 		pipe_cnt++;
2392 	}
2393 
2394 }
2395