1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "core_types.h"
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30 #include "dcn201_clk_mgr.h"
31 #include "dcn20/dcn20_clk_mgr.h"
32 #include "dce100/dce_clk_mgr.h"
33 #include "dm_helpers.h"
34 #include "dm_services.h"
35
36 #include "cyan_skillfish_ip_offset.h"
37 #include "dcn/dcn_2_0_3_offset.h"
38 #include "dcn/dcn_2_0_3_sh_mask.h"
39 #include "clk/clk_11_0_1_offset.h"
40 #include "clk/clk_11_0_1_sh_mask.h"
41
42 #define REG(reg) \
43 (clk_mgr->regs->reg)
44
45 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
46
47 #define BASE(seg) BASE_INNER(seg)
48
49 #define SR(reg_name)\
50 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
51 mm ## reg_name
52
53 #define CLK_BASE_INNER(seg) \
54 CLK_BASE__INST0_SEG ## seg
55
56 #undef FN
57 #define FN(reg_name, field_name) \
58 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
59
60 #define CTX \
61 clk_mgr->base.ctx
62 #define DC_LOGGER \
63 clk_mgr->base.ctx->logger
64
65 static const struct clk_mgr_registers clk_mgr_regs = {
66 CLK_COMMON_REG_LIST_DCN_201()
67 };
68
69 static const struct clk_mgr_shift clk_mgr_shift = {
70 CLK_COMMON_MASK_SH_LIST_DCN201_BASE(__SHIFT)
71 };
72
73 static const struct clk_mgr_mask clk_mgr_mask = {
74 CLK_COMMON_MASK_SH_LIST_DCN201_BASE(_MASK)
75 };
76
dcn201_init_clocks(struct clk_mgr * clk_mgr)77 static void dcn201_init_clocks(struct clk_mgr *clk_mgr)
78 {
79 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
80 clk_mgr->clks.p_state_change_support = true;
81 clk_mgr->clks.prev_p_state_change_support = true;
82 clk_mgr->clks.max_supported_dppclk_khz = 1200000;
83 clk_mgr->clks.max_supported_dispclk_khz = 1200000;
84 }
85
dcn201_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)86 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base,
87 struct dc_state *context,
88 bool safe_to_lower)
89 {
90 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
91 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
92 struct dc *dc = clk_mgr_base->ctx->dc;
93 bool update_dppclk = false;
94 bool update_dispclk = false;
95 bool dpp_clock_lowered = false;
96 bool force_reset = false;
97 bool p_state_change_support;
98 int total_plane_count;
99
100 if (dc->work_arounds.skip_clock_update)
101 return;
102
103 if (clk_mgr_base->clks.dispclk_khz == 0 ||
104 dc->debug.force_clock_mode & 0x1) {
105 force_reset = true;
106
107 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
108 }
109
110 clk_mgr_helper_get_active_display_cnt(dc, context);
111
112 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz))
113 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
114
115 if (dc->debug.force_min_dcfclk_mhz > 0)
116 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
117 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
118
119 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz))
120 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
121
122 if (should_set_clock(safe_to_lower,
123 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz))
124 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
125
126 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
127 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
128
129 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
130 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
131 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
132 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
133 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
134 }
135
136 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz))
137 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
138
139 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
140 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
141 dpp_clock_lowered = true;
142 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
143
144 update_dppclk = true;
145 }
146
147 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
148 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
149
150 update_dispclk = true;
151 }
152
153 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
154 if (dpp_clock_lowered) {
155 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
156 dcn20_update_clocks_update_dentist(clk_mgr, context);
157 } else {
158 if (update_dppclk || update_dispclk)
159 dcn20_update_clocks_update_dentist(clk_mgr, context);
160 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
161 }
162 }
163 }
164
165 struct clk_mgr_funcs dcn201_funcs = {
166 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
167 .update_clocks = dcn201_update_clocks,
168 .init_clocks = dcn201_init_clocks,
169 .get_clock = dcn2_get_clock,
170 };
171
dcn201_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)172 void dcn201_clk_mgr_construct(struct dc_context *ctx,
173 struct clk_mgr_internal *clk_mgr,
174 struct pp_smu_funcs *pp_smu,
175 struct dccg *dccg)
176 {
177 struct dc_debug_options *debug = &ctx->dc->debug;
178 struct dc_bios *bp = ctx->dc_bios;
179 clk_mgr->base.ctx = ctx;
180 clk_mgr->base.funcs = &dcn201_funcs;
181 clk_mgr->regs = &clk_mgr_regs;
182 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
183 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
184
185 clk_mgr->dccg = dccg;
186
187 clk_mgr->dfs_bypass_disp_clk = 0;
188
189 clk_mgr->dprefclk_ss_percentage = 0;
190 clk_mgr->dprefclk_ss_divider = 1000;
191 clk_mgr->ss_on_dprefclk = false;
192
193 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
194 dcn201_funcs.update_clocks = dcn2_update_clocks_fpga;
195 clk_mgr->base.dprefclk_khz = 600000;
196 clk_mgr->base.dentist_vco_freq_khz = 3000000;
197 } else {
198 clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT);
199 clk_mgr->base.dprefclk_khz *= 100;
200
201 if (clk_mgr->base.dprefclk_khz == 0)
202 clk_mgr->base.dprefclk_khz = 600000;
203
204 REG_GET(CLK4_CLK_PLL_REQ, FbMult_int, &clk_mgr->base.dentist_vco_freq_khz);
205 clk_mgr->base.dentist_vco_freq_khz *= 100000;
206
207 if (clk_mgr->base.dentist_vco_freq_khz == 0)
208 clk_mgr->base.dentist_vco_freq_khz = 3000000;
209 }
210
211 if (!debug->disable_dfs_bypass && bp->integrated_info)
212 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
213 clk_mgr->dfs_bypass_enabled = true;
214
215 dce_clock_read_ss_info(clk_mgr);
216 }
217