1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "include/logger_interface.h"
31
32 #include "../dce110/irq_service_dce110.h"
33
34 #include "dcn/dcn_2_1_0_offset.h"
35 #include "dcn/dcn_2_1_0_sh_mask.h"
36 #include "renoir_ip_offset.h"
37
38
39 #include "irq_service_dcn21.h"
40
41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
42
to_dal_irq_source_dcn21(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)43 static enum dc_irq_source to_dal_irq_source_dcn21(struct irq_service *irq_service,
44 uint32_t src_id,
45 uint32_t ext_id)
46 {
47 switch (src_id) {
48 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
49 return DC_IRQ_SOURCE_VBLANK1;
50 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
51 return DC_IRQ_SOURCE_VBLANK2;
52 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
53 return DC_IRQ_SOURCE_VBLANK3;
54 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
55 return DC_IRQ_SOURCE_VBLANK4;
56 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
57 return DC_IRQ_SOURCE_VBLANK5;
58 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
59 return DC_IRQ_SOURCE_VBLANK6;
60 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
61 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
62 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
63 return DC_IRQ_SOURCE_DC1_VLINE0;
64 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
65 return DC_IRQ_SOURCE_DC2_VLINE0;
66 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
67 return DC_IRQ_SOURCE_DC3_VLINE0;
68 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
69 return DC_IRQ_SOURCE_DC4_VLINE0;
70 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
71 return DC_IRQ_SOURCE_DC5_VLINE0;
72 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
73 return DC_IRQ_SOURCE_DC6_VLINE0;
74 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
75 return DC_IRQ_SOURCE_PFLIP1;
76 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
77 return DC_IRQ_SOURCE_PFLIP2;
78 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
79 return DC_IRQ_SOURCE_PFLIP3;
80 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
81 return DC_IRQ_SOURCE_PFLIP4;
82 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
83 return DC_IRQ_SOURCE_PFLIP5;
84 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
85 return DC_IRQ_SOURCE_PFLIP6;
86 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
87 return DC_IRQ_SOURCE_VUPDATE1;
88 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
89 return DC_IRQ_SOURCE_VUPDATE2;
90 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
91 return DC_IRQ_SOURCE_VUPDATE3;
92 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
93 return DC_IRQ_SOURCE_VUPDATE4;
94 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
95 return DC_IRQ_SOURCE_VUPDATE5;
96 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
97 return DC_IRQ_SOURCE_VUPDATE6;
98
99 case DCN_1_0__SRCID__DC_HPD1_INT:
100 /* generic src_id for all HPD and HPDRX interrupts */
101 switch (ext_id) {
102 case DCN_1_0__CTXID__DC_HPD1_INT:
103 return DC_IRQ_SOURCE_HPD1;
104 case DCN_1_0__CTXID__DC_HPD2_INT:
105 return DC_IRQ_SOURCE_HPD2;
106 case DCN_1_0__CTXID__DC_HPD3_INT:
107 return DC_IRQ_SOURCE_HPD3;
108 case DCN_1_0__CTXID__DC_HPD4_INT:
109 return DC_IRQ_SOURCE_HPD4;
110 case DCN_1_0__CTXID__DC_HPD5_INT:
111 return DC_IRQ_SOURCE_HPD5;
112 case DCN_1_0__CTXID__DC_HPD6_INT:
113 return DC_IRQ_SOURCE_HPD6;
114 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
115 return DC_IRQ_SOURCE_HPD1RX;
116 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
117 return DC_IRQ_SOURCE_HPD2RX;
118 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
119 return DC_IRQ_SOURCE_HPD3RX;
120 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
121 return DC_IRQ_SOURCE_HPD4RX;
122 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
123 return DC_IRQ_SOURCE_HPD5RX;
124 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
125 return DC_IRQ_SOURCE_HPD6RX;
126 default:
127 return DC_IRQ_SOURCE_INVALID;
128 }
129 break;
130
131 default:
132 break;
133 }
134 return DC_IRQ_SOURCE_INVALID;
135 }
136
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)137 static bool hpd_ack(
138 struct irq_service *irq_service,
139 const struct irq_source_info *info)
140 {
141 uint32_t addr = info->status_reg;
142 uint32_t value = dm_read_reg(irq_service->ctx, addr);
143 uint32_t current_status =
144 get_reg_field_value(
145 value,
146 HPD0_DC_HPD_INT_STATUS,
147 DC_HPD_SENSE_DELAYED);
148
149 dal_irq_service_ack_generic(irq_service, info);
150
151 value = dm_read_reg(irq_service->ctx, info->enable_reg);
152
153 set_reg_field_value(
154 value,
155 current_status ? 0 : 1,
156 HPD0_DC_HPD_INT_CONTROL,
157 DC_HPD_INT_POLARITY);
158
159 dm_write_reg(irq_service->ctx, info->enable_reg, value);
160
161 return true;
162 }
163
164 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
165 .set = NULL,
166 .ack = hpd_ack
167 };
168
169 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
170 .set = NULL,
171 .ack = NULL
172 };
173
174 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
175 .set = NULL,
176 .ack = NULL
177 };
178
179 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
180 .set = NULL,
181 .ack = NULL
182 };
183
184 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
185 .set = NULL,
186 .ack = NULL
187 };
188
189 static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
190 .set = NULL,
191 .ack = NULL
192 };
193
194 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
195 .set = NULL,
196 .ack = NULL
197 };
198
199 #undef BASE_INNER
200 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
201
202 /* compile time expand base address. */
203 #define BASE(seg) \
204 BASE_INNER(seg)
205
206
207 #define SRI(reg_name, block, id)\
208 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
209 mm ## block ## id ## _ ## reg_name
210
211 #define SRI_DMUB(reg_name)\
212 BASE(mm ## reg_name ## _BASE_IDX) + \
213 mm ## reg_name
214
215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
216 .enable_reg = SRI(reg1, block, reg_num),\
217 .enable_mask = \
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
219 .enable_value = {\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
222 },\
223 .ack_reg = SRI(reg2, block, reg_num),\
224 .ack_mask = \
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
226 .ack_value = \
227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
228
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
230 .enable_reg = SRI_DMUB(reg1),\
231 .enable_mask = \
232 reg1 ## __ ## mask1 ## _MASK,\
233 .enable_value = {\
234 reg1 ## __ ## mask1 ## _MASK,\
235 ~reg1 ## __ ## mask1 ## _MASK \
236 },\
237 .ack_reg = SRI_DMUB(reg2),\
238 .ack_mask = \
239 reg2 ## __ ## mask2 ## _MASK,\
240 .ack_value = \
241 reg2 ## __ ## mask2 ## _MASK \
242
243 #define hpd_int_entry(reg_num)\
244 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
245 IRQ_REG_ENTRY(HPD, reg_num,\
246 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
247 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
248 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
249 .funcs = &hpd_irq_info_funcs\
250 }
251
252 #define hpd_rx_int_entry(reg_num)\
253 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
254 IRQ_REG_ENTRY(HPD, reg_num,\
255 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
256 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
257 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
258 .funcs = &hpd_rx_irq_info_funcs\
259 }
260 #define pflip_int_entry(reg_num)\
261 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
262 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
263 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
264 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
265 .funcs = &pflip_irq_info_funcs\
266 }
267
268 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
269 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
270 */
271 #define vupdate_no_lock_int_entry(reg_num)\
272 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
273 IRQ_REG_ENTRY(OTG, reg_num,\
274 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
275 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
276 .funcs = &vupdate_no_lock_irq_info_funcs\
277 }
278
279 #define vblank_int_entry(reg_num)\
280 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
281 IRQ_REG_ENTRY(OTG, reg_num,\
282 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
283 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
284 .funcs = &vblank_irq_info_funcs\
285 }
286
287 #define vline0_int_entry(reg_num)\
288 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
289 IRQ_REG_ENTRY(OTG, reg_num,\
290 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
291 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
292 .funcs = &vline0_irq_info_funcs\
293 }
294
295 #define dmub_outbox_int_entry()\
296 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
297 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
298 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
299 .funcs = &dmub_outbox_irq_info_funcs\
300 }
301
302 #define dummy_irq_entry() \
303 {\
304 .funcs = &dummy_irq_info_funcs\
305 }
306
307 #define i2c_int_entry(reg_num) \
308 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
309
310 #define dp_sink_int_entry(reg_num) \
311 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
312
313 #define gpio_pad_int_entry(reg_num) \
314 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
315
316 #define dc_underflow_int_entry(reg_num) \
317 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
318
319 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
320 .set = dal_irq_service_dummy_set,
321 .ack = dal_irq_service_dummy_ack
322 };
323
324 static const struct irq_source_info
325 irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
326 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
327 hpd_int_entry(0),
328 hpd_int_entry(1),
329 hpd_int_entry(2),
330 hpd_int_entry(3),
331 hpd_int_entry(4),
332 hpd_rx_int_entry(0),
333 hpd_rx_int_entry(1),
334 hpd_rx_int_entry(2),
335 hpd_rx_int_entry(3),
336 hpd_rx_int_entry(4),
337 i2c_int_entry(1),
338 i2c_int_entry(2),
339 i2c_int_entry(3),
340 i2c_int_entry(4),
341 i2c_int_entry(5),
342 i2c_int_entry(6),
343 dp_sink_int_entry(1),
344 dp_sink_int_entry(2),
345 dp_sink_int_entry(3),
346 dp_sink_int_entry(4),
347 dp_sink_int_entry(5),
348 dp_sink_int_entry(6),
349 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
350 pflip_int_entry(0),
351 pflip_int_entry(1),
352 pflip_int_entry(2),
353 pflip_int_entry(3),
354 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
355 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
356 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
357 gpio_pad_int_entry(0),
358 gpio_pad_int_entry(1),
359 gpio_pad_int_entry(2),
360 gpio_pad_int_entry(3),
361 gpio_pad_int_entry(4),
362 gpio_pad_int_entry(5),
363 gpio_pad_int_entry(6),
364 gpio_pad_int_entry(7),
365 gpio_pad_int_entry(8),
366 gpio_pad_int_entry(9),
367 gpio_pad_int_entry(10),
368 gpio_pad_int_entry(11),
369 gpio_pad_int_entry(12),
370 gpio_pad_int_entry(13),
371 gpio_pad_int_entry(14),
372 gpio_pad_int_entry(15),
373 gpio_pad_int_entry(16),
374 gpio_pad_int_entry(17),
375 gpio_pad_int_entry(18),
376 gpio_pad_int_entry(19),
377 gpio_pad_int_entry(20),
378 gpio_pad_int_entry(21),
379 gpio_pad_int_entry(22),
380 gpio_pad_int_entry(23),
381 gpio_pad_int_entry(24),
382 gpio_pad_int_entry(25),
383 gpio_pad_int_entry(26),
384 gpio_pad_int_entry(27),
385 gpio_pad_int_entry(28),
386 gpio_pad_int_entry(29),
387 gpio_pad_int_entry(30),
388 dc_underflow_int_entry(1),
389 dc_underflow_int_entry(2),
390 dc_underflow_int_entry(3),
391 dc_underflow_int_entry(4),
392 dc_underflow_int_entry(5),
393 dc_underflow_int_entry(6),
394 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
395 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
396 vupdate_no_lock_int_entry(0),
397 vupdate_no_lock_int_entry(1),
398 vupdate_no_lock_int_entry(2),
399 vupdate_no_lock_int_entry(3),
400 vupdate_no_lock_int_entry(4),
401 vupdate_no_lock_int_entry(5),
402 vblank_int_entry(0),
403 vblank_int_entry(1),
404 vblank_int_entry(2),
405 vblank_int_entry(3),
406 vblank_int_entry(4),
407 vblank_int_entry(5),
408 vline0_int_entry(0),
409 vline0_int_entry(1),
410 vline0_int_entry(2),
411 vline0_int_entry(3),
412 vline0_int_entry(4),
413 vline0_int_entry(5),
414 dmub_outbox_int_entry(),
415 };
416
417 static const struct irq_service_funcs irq_service_funcs_dcn21 = {
418 .to_dal_irq_source = to_dal_irq_source_dcn21
419 };
420
dcn21_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)421 static void dcn21_irq_construct(
422 struct irq_service *irq_service,
423 struct irq_service_init_data *init_data)
424 {
425 dal_irq_service_construct(irq_service, init_data);
426
427 irq_service->info = irq_source_info_dcn21;
428 irq_service->funcs = &irq_service_funcs_dcn21;
429 }
430
dal_irq_service_dcn21_create(struct irq_service_init_data * init_data)431 struct irq_service *dal_irq_service_dcn21_create(
432 struct irq_service_init_data *init_data)
433 {
434 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
435 GFP_KERNEL);
436
437 if (!irq_service)
438 return NULL;
439
440 dcn21_irq_construct(irq_service, init_data);
441 return irq_service;
442 }
443