1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 #include "dm_helpers.h"
28 #include "gpio_service_interface.h"
29 #include "include/ddc_service_types.h"
30 #include "include/grph_object_id.h"
31 #include "include/dpcd_defs.h"
32 #include "include/logger_interface.h"
33 #include "include/vector.h"
34 #include "core_types.h"
35 #include "dc_link_ddc.h"
36 #include "dce/dce_aux.h"
37 #include "dmub/inc/dmub_cmd.h"
38 #include "link_dpcd.h"
39 #include "include/dal_asic_id.h"
40 
41 #define DC_LOGGER_INIT(logger)
42 
43 static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";
44 /* DP to Dual link DVI converter */
45 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
46 static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
47 
48 #define AUX_POWER_UP_WA_DELAY 500
49 #define I2C_OVER_AUX_DEFER_WA_DELAY 70
50 #define DPVGA_DONGLE_AUX_DEFER_WA_DELAY 40
51 #define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1
52 
53 /* CV smart dongle slave address for retrieving supported HDTV modes*/
54 #define CV_SMART_DONGLE_ADDRESS 0x20
55 /* DVI-HDMI dongle slave address for retrieving dongle signature*/
56 #define DVI_HDMI_DONGLE_ADDRESS 0x68
57 struct dvi_hdmi_dongle_signature_data {
58 	int8_t vendor[3];/* "AMD" */
59 	uint8_t version[2];
60 	uint8_t size;
61 	int8_t id[11];/* "6140063500G"*/
62 };
63 /* DP-HDMI dongle slave address for retrieving dongle signature*/
64 #define DP_HDMI_DONGLE_ADDRESS 0x40
65 static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
66 #define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
67 
68 struct dp_hdmi_dongle_signature_data {
69 	int8_t id[15];/* "DP-HDMI ADAPTOR"*/
70 	uint8_t eot;/* end of transmition '\x4' */
71 };
72 
73 /* SCDC Address defines (HDMI 2.0)*/
74 #define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
75 #define HDMI_SCDC_ADDRESS  0x54
76 #define HDMI_SCDC_SINK_VERSION 0x01
77 #define HDMI_SCDC_SOURCE_VERSION 0x02
78 #define HDMI_SCDC_UPDATE_0 0x10
79 #define HDMI_SCDC_TMDS_CONFIG 0x20
80 #define HDMI_SCDC_SCRAMBLER_STATUS 0x21
81 #define HDMI_SCDC_CONFIG_0 0x30
82 #define HDMI_SCDC_STATUS_FLAGS 0x40
83 #define HDMI_SCDC_ERR_DETECT 0x50
84 #define HDMI_SCDC_TEST_CONFIG 0xC0
85 
86 union hdmi_scdc_update_read_data {
87 	uint8_t byte[2];
88 	struct {
89 		uint8_t STATUS_UPDATE:1;
90 		uint8_t CED_UPDATE:1;
91 		uint8_t RR_TEST:1;
92 		uint8_t RESERVED:5;
93 		uint8_t RESERVED2:8;
94 	} fields;
95 };
96 
97 union hdmi_scdc_status_flags_data {
98 	uint8_t byte;
99 	struct {
100 		uint8_t CLOCK_DETECTED:1;
101 		uint8_t CH0_LOCKED:1;
102 		uint8_t CH1_LOCKED:1;
103 		uint8_t CH2_LOCKED:1;
104 		uint8_t RESERVED:4;
105 	} fields;
106 };
107 
108 union hdmi_scdc_ced_data {
109 	uint8_t byte[7];
110 	struct {
111 		uint8_t CH0_8LOW:8;
112 		uint8_t CH0_7HIGH:7;
113 		uint8_t CH0_VALID:1;
114 		uint8_t CH1_8LOW:8;
115 		uint8_t CH1_7HIGH:7;
116 		uint8_t CH1_VALID:1;
117 		uint8_t CH2_8LOW:8;
118 		uint8_t CH2_7HIGH:7;
119 		uint8_t CH2_VALID:1;
120 		uint8_t CHECKSUM:8;
121 		uint8_t RESERVED:8;
122 		uint8_t RESERVED2:8;
123 		uint8_t RESERVED3:8;
124 		uint8_t RESERVED4:4;
125 	} fields;
126 };
127 
128 struct i2c_payloads {
129 	struct vector payloads;
130 };
131 
132 struct aux_payloads {
133 	struct vector payloads;
134 };
135 
dal_ddc_i2c_payloads_create(struct dc_context * ctx,struct i2c_payloads * payloads,uint32_t count)136 static bool dal_ddc_i2c_payloads_create(
137 		struct dc_context *ctx,
138 		struct i2c_payloads *payloads,
139 		uint32_t count)
140 {
141 	if (dal_vector_construct(
142 		&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
143 		return true;
144 
145 	return false;
146 }
147 
dal_ddc_i2c_payloads_get(struct i2c_payloads * p)148 static struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
149 {
150 	return (struct i2c_payload *)p->payloads.container;
151 }
152 
dal_ddc_i2c_payloads_get_count(struct i2c_payloads * p)153 static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
154 {
155 	return p->payloads.count;
156 }
157 
158 #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
159 
dal_ddc_i2c_payloads_add(struct i2c_payloads * payloads,uint32_t address,uint32_t len,uint8_t * data,bool write)160 void dal_ddc_i2c_payloads_add(
161 	struct i2c_payloads *payloads,
162 	uint32_t address,
163 	uint32_t len,
164 	uint8_t *data,
165 	bool write)
166 {
167 	uint32_t payload_size = EDID_SEGMENT_SIZE;
168 	uint32_t pos;
169 
170 	for (pos = 0; pos < len; pos += payload_size) {
171 		struct i2c_payload payload = {
172 			.write = write,
173 			.address = address,
174 			.length = DDC_MIN(payload_size, len - pos),
175 			.data = data + pos };
176 		dal_vector_append(&payloads->payloads, &payload);
177 	}
178 
179 }
180 
ddc_service_construct(struct ddc_service * ddc_service,struct ddc_service_init_data * init_data)181 static void ddc_service_construct(
182 	struct ddc_service *ddc_service,
183 	struct ddc_service_init_data *init_data)
184 {
185 	enum connector_id connector_id =
186 		dal_graphics_object_id_get_connector_id(init_data->id);
187 
188 	struct gpio_service *gpio_service = init_data->ctx->gpio_service;
189 	struct graphics_object_i2c_info i2c_info;
190 	struct gpio_ddc_hw_info hw_info;
191 	struct dc_bios *dcb = init_data->ctx->dc_bios;
192 
193 	ddc_service->link = init_data->link;
194 	ddc_service->ctx = init_data->ctx;
195 
196 	if (init_data->is_dpia_link ||
197 	    dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info) != BP_RESULT_OK) {
198 		ddc_service->ddc_pin = NULL;
199 	} else {
200 		DC_LOGGER_INIT(ddc_service->ctx->logger);
201 		DC_LOG_DC("BIOS object table - i2c_line: %d", i2c_info.i2c_line);
202 		DC_LOG_DC("BIOS object table - i2c_engine_id: %d", i2c_info.i2c_engine_id);
203 
204 		hw_info.ddc_channel = i2c_info.i2c_line;
205 		if (ddc_service->link != NULL)
206 			hw_info.hw_supported = i2c_info.i2c_hw_assist;
207 		else
208 			hw_info.hw_supported = false;
209 
210 		ddc_service->ddc_pin = dal_gpio_create_ddc(
211 			gpio_service,
212 			i2c_info.gpio_info.clk_a_register_index,
213 			1 << i2c_info.gpio_info.clk_a_shift,
214 			&hw_info);
215 	}
216 
217 	ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
218 	ddc_service->flags.FORCE_READ_REPEATED_START = false;
219 	ddc_service->flags.EDID_STRESS_READ = false;
220 
221 	ddc_service->flags.IS_INTERNAL_DISPLAY =
222 		connector_id == CONNECTOR_ID_EDP ||
223 		connector_id == CONNECTOR_ID_LVDS;
224 
225 	ddc_service->wa.raw = 0;
226 }
227 
dal_ddc_service_create(struct ddc_service_init_data * init_data)228 struct ddc_service *dal_ddc_service_create(
229 	struct ddc_service_init_data *init_data)
230 {
231 	struct ddc_service *ddc_service;
232 
233 	ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
234 
235 	if (!ddc_service)
236 		return NULL;
237 
238 	ddc_service_construct(ddc_service, init_data);
239 	return ddc_service;
240 }
241 
ddc_service_destruct(struct ddc_service * ddc)242 static void ddc_service_destruct(struct ddc_service *ddc)
243 {
244 	if (ddc->ddc_pin)
245 		dal_gpio_destroy_ddc(&ddc->ddc_pin);
246 }
247 
dal_ddc_service_destroy(struct ddc_service ** ddc)248 void dal_ddc_service_destroy(struct ddc_service **ddc)
249 {
250 	if (!ddc || !*ddc) {
251 		BREAK_TO_DEBUGGER();
252 		return;
253 	}
254 	ddc_service_destruct(*ddc);
255 	kfree(*ddc);
256 	*ddc = NULL;
257 }
258 
dal_ddc_service_get_type(struct ddc_service * ddc)259 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
260 {
261 	return DDC_SERVICE_TYPE_CONNECTOR;
262 }
263 
dal_ddc_service_set_transaction_type(struct ddc_service * ddc,enum ddc_transaction_type type)264 void dal_ddc_service_set_transaction_type(
265 	struct ddc_service *ddc,
266 	enum ddc_transaction_type type)
267 {
268 	ddc->transaction_type = type;
269 }
270 
dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service * ddc)271 bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
272 {
273 	switch (ddc->transaction_type) {
274 	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
275 	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
276 	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
277 		return true;
278 	default:
279 		break;
280 	}
281 	return false;
282 }
283 
ddc_service_set_dongle_type(struct ddc_service * ddc,enum display_dongle_type dongle_type)284 void ddc_service_set_dongle_type(struct ddc_service *ddc,
285 		enum display_dongle_type dongle_type)
286 {
287 	ddc->dongle_type = dongle_type;
288 }
289 
defer_delay_converter_wa(struct ddc_service * ddc,uint32_t defer_delay)290 static uint32_t defer_delay_converter_wa(
291 	struct ddc_service *ddc,
292 	uint32_t defer_delay)
293 {
294 	struct dc_link *link = ddc->link;
295 
296 	if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
297 		link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
298 		(link->dpcd_caps.branch_fw_revision[0] < 0x01 ||
299 				(link->dpcd_caps.branch_fw_revision[0] == 0x01 &&
300 				link->dpcd_caps.branch_fw_revision[1] < 0x40)) &&
301 		!memcmp(link->dpcd_caps.branch_dev_name,
302 		    DP_VGA_DONGLE_BRANCH_DEV_NAME,
303 			sizeof(link->dpcd_caps.branch_dev_name)))
304 
305 		return defer_delay > DPVGA_DONGLE_AUX_DEFER_WA_DELAY ?
306 			defer_delay : DPVGA_DONGLE_AUX_DEFER_WA_DELAY;
307 
308 	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
309 	    !memcmp(link->dpcd_caps.branch_dev_name,
310 		    DP_DVI_CONVERTER_ID_4,
311 		    sizeof(link->dpcd_caps.branch_dev_name)))
312 		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
313 			defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
314 	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 &&
315 	    !memcmp(link->dpcd_caps.branch_dev_name,
316 		    DP_DVI_CONVERTER_ID_5,
317 		    sizeof(link->dpcd_caps.branch_dev_name)))
318 		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ?
319 			I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay;
320 
321 	return defer_delay;
322 }
323 
324 #define DP_TRANSLATOR_DELAY 5
325 
get_defer_delay(struct ddc_service * ddc)326 uint32_t get_defer_delay(struct ddc_service *ddc)
327 {
328 	uint32_t defer_delay = 0;
329 
330 	switch (ddc->transaction_type) {
331 	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
332 		if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
333 			(DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
334 			(DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
335 				ddc->dongle_type)) {
336 
337 			defer_delay = DP_TRANSLATOR_DELAY;
338 
339 			defer_delay =
340 				defer_delay_converter_wa(ddc, defer_delay);
341 
342 		} else /*sink has a delay different from an Active Converter*/
343 			defer_delay = 0;
344 		break;
345 	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
346 		defer_delay = DP_TRANSLATOR_DELAY;
347 		break;
348 	default:
349 		break;
350 	}
351 	return defer_delay;
352 }
353 
i2c_read(struct ddc_service * ddc,uint32_t address,uint8_t * buffer,uint32_t len)354 static bool i2c_read(
355 	struct ddc_service *ddc,
356 	uint32_t address,
357 	uint8_t *buffer,
358 	uint32_t len)
359 {
360 	uint8_t offs_data = 0;
361 	struct i2c_payload payloads[2] = {
362 		{
363 		.write = true,
364 		.address = address,
365 		.length = 1,
366 		.data = &offs_data },
367 		{
368 		.write = false,
369 		.address = address,
370 		.length = len,
371 		.data = buffer } };
372 
373 	struct i2c_command command = {
374 		.payloads = payloads,
375 		.number_of_payloads = 2,
376 		.engine = DDC_I2C_COMMAND_ENGINE,
377 		.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
378 
379 	return dm_helpers_submit_i2c(
380 			ddc->ctx,
381 			ddc->link,
382 			&command);
383 }
384 
dal_ddc_service_i2c_query_dp_dual_mode_adaptor(struct ddc_service * ddc,struct display_sink_capability * sink_cap)385 void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
386 	struct ddc_service *ddc,
387 	struct display_sink_capability *sink_cap)
388 {
389 	uint8_t i;
390 	bool is_valid_hdmi_signature;
391 	enum display_dongle_type *dongle = &sink_cap->dongle_type;
392 	uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
393 	bool is_type2_dongle = false;
394 	int retry_count = 2;
395 	struct dp_hdmi_dongle_signature_data *dongle_signature;
396 
397 	/* Assume we have no valid DP passive dongle connected */
398 	*dongle = DISPLAY_DONGLE_NONE;
399 	sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
400 
401 	/* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
402 	if (!i2c_read(
403 		ddc,
404 		DP_HDMI_DONGLE_ADDRESS,
405 		type2_dongle_buf,
406 		sizeof(type2_dongle_buf))) {
407 		/* Passive HDMI dongles can sometimes fail here without retrying*/
408 		while (retry_count > 0) {
409 			if (i2c_read(ddc,
410 				DP_HDMI_DONGLE_ADDRESS,
411 				type2_dongle_buf,
412 				sizeof(type2_dongle_buf)))
413 				break;
414 			retry_count--;
415 		}
416 		if (retry_count == 0) {
417 			*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
418 			sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
419 
420 			CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
421 					"DP-DVI passive dongle %dMhz: ",
422 					DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
423 			return;
424 		}
425 	}
426 
427 	/* Check if Type 2 dongle.*/
428 	if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
429 		is_type2_dongle = true;
430 
431 	dongle_signature =
432 		(struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
433 
434 	is_valid_hdmi_signature = true;
435 
436 	/* Check EOT */
437 	if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
438 		is_valid_hdmi_signature = false;
439 	}
440 
441 	/* Check signature */
442 	for (i = 0; i < sizeof(dongle_signature->id); ++i) {
443 		/* If its not the right signature,
444 		 * skip mismatch in subversion byte.*/
445 		if (dongle_signature->id[i] !=
446 			dp_hdmi_dongle_signature_str[i] && i != 3) {
447 
448 			if (is_type2_dongle) {
449 				is_valid_hdmi_signature = false;
450 				break;
451 			}
452 
453 		}
454 	}
455 
456 	if (is_type2_dongle) {
457 		uint32_t max_tmds_clk =
458 			type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
459 
460 		max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
461 
462 		if (0 == max_tmds_clk ||
463 				max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
464 				max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
465 			*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
466 
467 			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
468 					sizeof(type2_dongle_buf),
469 					"DP-DVI passive dongle %dMhz: ",
470 					DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
471 		} else {
472 			if (is_valid_hdmi_signature == true) {
473 				*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
474 
475 				CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
476 						sizeof(type2_dongle_buf),
477 						"Type 2 DP-HDMI passive dongle %dMhz: ",
478 						max_tmds_clk);
479 			} else {
480 				*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
481 
482 				CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
483 						sizeof(type2_dongle_buf),
484 						"Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
485 						max_tmds_clk);
486 
487 			}
488 
489 			/* Multiply by 1000 to convert to kHz. */
490 			sink_cap->max_hdmi_pixel_clock =
491 				max_tmds_clk * 1000;
492 		}
493 		sink_cap->is_dongle_type_one = false;
494 
495 	} else {
496 		if (is_valid_hdmi_signature == true) {
497 			*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
498 
499 			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
500 					sizeof(type2_dongle_buf),
501 					"Type 1 DP-HDMI passive dongle %dMhz: ",
502 					sink_cap->max_hdmi_pixel_clock / 1000);
503 		} else {
504 			*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
505 
506 			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
507 					sizeof(type2_dongle_buf),
508 					"Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
509 					sink_cap->max_hdmi_pixel_clock / 1000);
510 		}
511 		sink_cap->is_dongle_type_one = true;
512 	}
513 
514 	return;
515 }
516 
517 enum {
518 	DP_SINK_CAP_SIZE =
519 		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
520 };
521 
dal_ddc_service_query_ddc_data(struct ddc_service * ddc,uint32_t address,uint8_t * write_buf,uint32_t write_size,uint8_t * read_buf,uint32_t read_size)522 bool dal_ddc_service_query_ddc_data(
523 	struct ddc_service *ddc,
524 	uint32_t address,
525 	uint8_t *write_buf,
526 	uint32_t write_size,
527 	uint8_t *read_buf,
528 	uint32_t read_size)
529 {
530 	bool success = true;
531 	uint32_t payload_size =
532 		dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
533 			DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
534 
535 	uint32_t write_payloads =
536 		(write_size + payload_size - 1) / payload_size;
537 
538 	uint32_t read_payloads =
539 		(read_size + payload_size - 1) / payload_size;
540 
541 	uint32_t payloads_num = write_payloads + read_payloads;
542 
543 	if (!payloads_num)
544 		return false;
545 
546 	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
547 		struct aux_payload payload;
548 
549 		payload.i2c_over_aux = true;
550 		payload.address = address;
551 		payload.reply = NULL;
552 		payload.defer_delay = get_defer_delay(ddc);
553 		payload.write_status_update = false;
554 
555 		if (write_size != 0) {
556 			payload.write = true;
557 			/* should not set mot (middle of transaction) to 0
558 			 * if there are pending read payloads
559 			 */
560 			payload.mot = !(read_size == 0);
561 			payload.length = write_size;
562 			payload.data = write_buf;
563 
564 			success = dal_ddc_submit_aux_command(ddc, &payload);
565 		}
566 
567 		if (read_size != 0 && success) {
568 			payload.write = false;
569 			/* should set mot (middle of transaction) to 0
570 			 * since it is the last payload to send
571 			 */
572 			payload.mot = false;
573 			payload.length = read_size;
574 			payload.data = read_buf;
575 
576 			success = dal_ddc_submit_aux_command(ddc, &payload);
577 		}
578 	} else {
579 		struct i2c_command command = {0};
580 		struct i2c_payloads payloads;
581 
582 		if (!dal_ddc_i2c_payloads_create(ddc->ctx, &payloads, payloads_num))
583 			return false;
584 
585 		command.payloads = dal_ddc_i2c_payloads_get(&payloads);
586 		command.number_of_payloads = 0;
587 		command.engine = DDC_I2C_COMMAND_ENGINE;
588 		command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;
589 
590 		dal_ddc_i2c_payloads_add(
591 			&payloads, address, write_size, write_buf, true);
592 
593 		dal_ddc_i2c_payloads_add(
594 			&payloads, address, read_size, read_buf, false);
595 
596 		command.number_of_payloads =
597 			dal_ddc_i2c_payloads_get_count(&payloads);
598 
599 		success = dm_helpers_submit_i2c(
600 				ddc->ctx,
601 				ddc->link,
602 				&command);
603 
604 		dal_vector_destruct(&payloads.payloads);
605 	}
606 
607 	return success;
608 }
609 
dal_ddc_submit_aux_command(struct ddc_service * ddc,struct aux_payload * payload)610 bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
611 		struct aux_payload *payload)
612 {
613 	uint32_t retrieved = 0;
614 	bool ret = false;
615 
616 	if (!ddc)
617 		return false;
618 
619 	if (!payload)
620 		return false;
621 
622 	do {
623 		struct aux_payload current_payload;
624 		bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >=
625 				payload->length;
626 		uint32_t payload_length = is_end_of_payload ?
627 				payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
628 
629 		current_payload.address = payload->address;
630 		current_payload.data = &payload->data[retrieved];
631 		current_payload.defer_delay = payload->defer_delay;
632 		current_payload.i2c_over_aux = payload->i2c_over_aux;
633 		current_payload.length = payload_length;
634 		/* set mot (middle of transaction) to false if it is the last payload */
635 		current_payload.mot = is_end_of_payload ? payload->mot:true;
636 		current_payload.write_status_update = false;
637 		current_payload.reply = payload->reply;
638 		current_payload.write = payload->write;
639 
640 		ret = dc_link_aux_transfer_with_retries(ddc, &current_payload);
641 
642 		retrieved += payload_length;
643 	} while (retrieved < payload->length && ret == true);
644 
645 	return ret;
646 }
647 
648 /* dc_link_aux_transfer_raw() - Attempt to transfer
649  * the given aux payload.  This function does not perform
650  * retries or handle error states.  The reply is returned
651  * in the payload->reply and the result through
652  * *operation_result.  Returns the number of bytes transferred,
653  * or -1 on a failure.
654  */
dc_link_aux_transfer_raw(struct ddc_service * ddc,struct aux_payload * payload,enum aux_return_code_type * operation_result)655 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
656 		struct aux_payload *payload,
657 		enum aux_return_code_type *operation_result)
658 {
659 	if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
660 	    !ddc->ddc_pin) {
661 		return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
662 	} else {
663 		return dce_aux_transfer_raw(ddc, payload, operation_result);
664 	}
665 }
666 
667 /* dc_link_aux_transfer_with_retries() - Attempt to submit an
668  * aux payload, retrying on timeouts, defers, and busy states
669  * as outlined in the DP spec.  Returns true if the request
670  * was successful.
671  *
672  * Unless you want to implement your own retry semantics, this
673  * is probably the one you want.
674  */
dc_link_aux_transfer_with_retries(struct ddc_service * ddc,struct aux_payload * payload)675 bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
676 		struct aux_payload *payload)
677 {
678 	return dce_aux_transfer_with_retries(ddc, payload);
679 }
680 
681 
dc_link_aux_try_to_configure_timeout(struct ddc_service * ddc,uint32_t timeout)682 bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
683 		uint32_t timeout)
684 {
685 	bool result = false;
686 	struct ddc *ddc_pin = ddc->ddc_pin;
687 
688 	if ((ddc->link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
689 			!ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&
690 			ASICREV_IS_YELLOW_CARP(ddc->ctx->asic_id.hw_internal_rev)) {
691 		/* Fixed VS workaround for AUX timeout */
692 		const uint32_t fixed_vs_address = 0xF004F;
693 		const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};
694 
695 		core_link_write_dpcd(ddc->link,
696 				fixed_vs_address,
697 				fixed_vs_data,
698 				sizeof(fixed_vs_data));
699 
700 		timeout = 3072;
701 	}
702 
703 	/* Do not try to access nonexistent DDC pin. */
704 	if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)
705 		return true;
706 
707 	if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {
708 		ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
709 		result = true;
710 	}
711 
712 	return result;
713 }
714 
715 /*test only function*/
dal_ddc_service_set_ddc_pin(struct ddc_service * ddc_service,struct ddc * ddc)716 void dal_ddc_service_set_ddc_pin(
717 	struct ddc_service *ddc_service,
718 	struct ddc *ddc)
719 {
720 	ddc_service->ddc_pin = ddc;
721 }
722 
dal_ddc_service_get_ddc_pin(struct ddc_service * ddc_service)723 struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
724 {
725 	return ddc_service->ddc_pin;
726 }
727 
dal_ddc_service_write_scdc_data(struct ddc_service * ddc_service,uint32_t pix_clk,bool lte_340_scramble)728 void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
729 		uint32_t pix_clk,
730 		bool lte_340_scramble)
731 {
732 	bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
733 	uint8_t slave_address = HDMI_SCDC_ADDRESS;
734 	uint8_t offset = HDMI_SCDC_SINK_VERSION;
735 	uint8_t sink_version = 0;
736 	uint8_t write_buffer[2] = {0};
737 	/*Lower than 340 Scramble bit from SCDC caps*/
738 
739 	if (ddc_service->link->local_sink &&
740 		ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
741 		return;
742 
743 	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
744 			sizeof(offset), &sink_version, sizeof(sink_version));
745 	if (sink_version == 1) {
746 		/*Source Version = 1*/
747 		write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
748 		write_buffer[1] = 1;
749 		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
750 				write_buffer, sizeof(write_buffer), NULL, 0);
751 		/*Read Request from SCDC caps*/
752 	}
753 	write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
754 
755 	if (over_340_mhz) {
756 		write_buffer[1] = 3;
757 	} else if (lte_340_scramble) {
758 		write_buffer[1] = 1;
759 	} else {
760 		write_buffer[1] = 0;
761 	}
762 	dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
763 			sizeof(write_buffer), NULL, 0);
764 }
765 
dal_ddc_service_read_scdc_data(struct ddc_service * ddc_service)766 void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
767 {
768 	uint8_t slave_address = HDMI_SCDC_ADDRESS;
769 	uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
770 	uint8_t tmds_config = 0;
771 
772 	if (ddc_service->link->local_sink &&
773 		ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
774 		return;
775 
776 	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
777 			sizeof(offset), &tmds_config, sizeof(tmds_config));
778 	if (tmds_config & 0x1) {
779 		union hdmi_scdc_status_flags_data status_data = {0};
780 		uint8_t scramble_status = 0;
781 
782 		offset = HDMI_SCDC_SCRAMBLER_STATUS;
783 		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
784 				&offset, sizeof(offset), &scramble_status,
785 				sizeof(scramble_status));
786 		offset = HDMI_SCDC_STATUS_FLAGS;
787 		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
788 				&offset, sizeof(offset), &status_data.byte,
789 				sizeof(status_data.byte));
790 	}
791 }
792 
793