1 /*
2  * cxgb4_ptp.c:Chelsio PTP support for T5/T6
3  *
4  * Copyright (c) 2003-2017 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  *
34  * Written by: Atul Gupta (atul.gupta@chelsio.com)
35  */
36 
37 #include <linux/module.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/skbuff.h>
40 #include <linux/netdevice.h>
41 #include <linux/pps_kernel.h>
42 #include <linux/ptp_clock_kernel.h>
43 #include <linux/ptp_classify.h>
44 #include <linux/udp.h>
45 
46 #include "cxgb4.h"
47 #include "t4_hw.h"
48 #include "t4_regs.h"
49 #include "t4_msg.h"
50 #include "t4fw_api.h"
51 #include "cxgb4_ptp.h"
52 
53 /**
54  * cxgb4_ptp_is_ptp_tx - determine whether TX packet is PTP or not
55  * @skb: skb of outgoing ptp request
56  *
57  */
cxgb4_ptp_is_ptp_tx(struct sk_buff * skb)58 bool cxgb4_ptp_is_ptp_tx(struct sk_buff *skb)
59 {
60 	struct udphdr *uh;
61 
62 	uh = udp_hdr(skb);
63 	return skb->len >= PTP_MIN_LENGTH &&
64 		skb->len <= PTP_IN_TRANSMIT_PACKET_MAXNUM &&
65 		likely(skb->protocol == htons(ETH_P_IP)) &&
66 		ip_hdr(skb)->protocol == IPPROTO_UDP &&
67 		uh->dest == htons(PTP_EVENT_PORT);
68 }
69 
is_ptp_enabled(struct sk_buff * skb,struct net_device * dev)70 bool is_ptp_enabled(struct sk_buff *skb, struct net_device *dev)
71 {
72 	struct port_info *pi;
73 
74 	pi = netdev_priv(dev);
75 	return (pi->ptp_enable && cxgb4_xmit_with_hwtstamp(skb) &&
76 		cxgb4_ptp_is_ptp_tx(skb));
77 }
78 
79 /**
80  * cxgb4_ptp_is_ptp_rx - determine whether RX packet is PTP or not
81  * @skb: skb of incoming ptp request
82  *
83  */
cxgb4_ptp_is_ptp_rx(struct sk_buff * skb)84 bool cxgb4_ptp_is_ptp_rx(struct sk_buff *skb)
85 {
86 	struct udphdr *uh = (struct udphdr *)(skb->data + ETH_HLEN +
87 					      IPV4_HLEN(skb->data));
88 
89 	return  uh->dest == htons(PTP_EVENT_PORT) &&
90 		uh->source == htons(PTP_EVENT_PORT);
91 }
92 
93 /**
94  * cxgb4_ptp_read_hwstamp - read timestamp for TX event PTP message
95  * @adapter: board private structure
96  * @pi: port private structure
97  *
98  */
cxgb4_ptp_read_hwstamp(struct adapter * adapter,struct port_info * pi)99 void cxgb4_ptp_read_hwstamp(struct adapter *adapter, struct port_info *pi)
100 {
101 	struct skb_shared_hwtstamps *skb_ts = NULL;
102 	u64 tx_ts;
103 
104 	skb_ts = skb_hwtstamps(adapter->ptp_tx_skb);
105 
106 	tx_ts = t4_read_reg(adapter,
107 			    T5_PORT_REG(pi->port_id, MAC_PORT_TX_TS_VAL_LO));
108 
109 	tx_ts |= (u64)t4_read_reg(adapter,
110 				  T5_PORT_REG(pi->port_id,
111 					      MAC_PORT_TX_TS_VAL_HI)) << 32;
112 	skb_ts->hwtstamp = ns_to_ktime(tx_ts);
113 	skb_tstamp_tx(adapter->ptp_tx_skb, skb_ts);
114 	dev_kfree_skb_any(adapter->ptp_tx_skb);
115 	spin_lock(&adapter->ptp_lock);
116 	adapter->ptp_tx_skb = NULL;
117 	spin_unlock(&adapter->ptp_lock);
118 }
119 
120 /**
121  * cxgb4_ptprx_timestamping - Enable Timestamp for RX PTP event message
122  * @pi: port private structure
123  * @port: pot number
124  * @mode: RX mode
125  *
126  */
cxgb4_ptprx_timestamping(struct port_info * pi,u8 port,u16 mode)127 int cxgb4_ptprx_timestamping(struct port_info *pi, u8 port, u16 mode)
128 {
129 	struct adapter *adapter = pi->adapter;
130 	struct fw_ptp_cmd c;
131 	int err;
132 
133 	memset(&c, 0, sizeof(c));
134 	c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
135 				     FW_CMD_REQUEST_F |
136 				     FW_CMD_WRITE_F |
137 				     FW_PTP_CMD_PORTID_V(port));
138 	c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
139 	c.u.init.sc = FW_PTP_SC_RXTIME_STAMP;
140 	c.u.init.mode = cpu_to_be16(mode);
141 
142 	err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
143 	if (err < 0)
144 		dev_err(adapter->pdev_dev,
145 			"PTP: %s error %d\n", __func__, -err);
146 	return err;
147 }
148 
cxgb4_ptp_txtype(struct adapter * adapter,u8 port)149 int cxgb4_ptp_txtype(struct adapter *adapter, u8 port)
150 {
151 	struct fw_ptp_cmd c;
152 	int err;
153 
154 	memset(&c, 0, sizeof(c));
155 	c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
156 				     FW_CMD_REQUEST_F |
157 				     FW_CMD_WRITE_F |
158 				     FW_PTP_CMD_PORTID_V(port));
159 	c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
160 	c.u.init.sc = FW_PTP_SC_TX_TYPE;
161 	c.u.init.mode = cpu_to_be16(PTP_TS_NONE);
162 
163 	err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
164 	if (err < 0)
165 		dev_err(adapter->pdev_dev,
166 			"PTP: %s error %d\n", __func__, -err);
167 
168 	return err;
169 }
170 
cxgb4_ptp_redirect_rx_packet(struct adapter * adapter,struct port_info * pi)171 int cxgb4_ptp_redirect_rx_packet(struct adapter *adapter, struct port_info *pi)
172 {
173 	struct sge *s = &adapter->sge;
174 	struct sge_eth_rxq *receive_q =  &s->ethrxq[pi->first_qset];
175 	struct fw_ptp_cmd c;
176 	int err;
177 
178 	memset(&c, 0, sizeof(c));
179 	c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
180 				     FW_CMD_REQUEST_F |
181 				     FW_CMD_WRITE_F |
182 				     FW_PTP_CMD_PORTID_V(pi->port_id));
183 
184 	c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
185 	c.u.init.sc = FW_PTP_SC_RDRX_TYPE;
186 	c.u.init.txchan = pi->tx_chan;
187 	c.u.init.absid = cpu_to_be16(receive_q->rspq.abs_id);
188 
189 	err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
190 	if (err < 0)
191 		dev_err(adapter->pdev_dev,
192 			"PTP: %s error %d\n", __func__, -err);
193 	return err;
194 }
195 
196 /**
197  * cxgb4_ptp_adjfreq - Adjust frequency of PHC cycle counter
198  * @ptp: ptp clock structure
199  * @ppb: Desired frequency change in parts per billion
200  *
201  * Adjust the frequency of the PHC cycle counter by the indicated ppb from
202  * the base frequency.
203  */
cxgb4_ptp_adjfreq(struct ptp_clock_info * ptp,s32 ppb)204 static int cxgb4_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
205 {
206 	struct adapter *adapter = (struct adapter *)container_of(ptp,
207 				   struct adapter, ptp_clock_info);
208 	struct fw_ptp_cmd c;
209 	int err;
210 
211 	memset(&c, 0, sizeof(c));
212 	c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
213 				     FW_CMD_REQUEST_F |
214 				     FW_CMD_WRITE_F |
215 				     FW_PTP_CMD_PORTID_V(0));
216 	c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
217 	c.u.ts.sc = FW_PTP_SC_ADJ_FREQ;
218 	c.u.ts.sign = (ppb < 0) ? 1 : 0;
219 	if (ppb < 0)
220 		ppb = -ppb;
221 	c.u.ts.ppb = cpu_to_be32(ppb);
222 
223 	err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
224 	if (err < 0)
225 		dev_err(adapter->pdev_dev,
226 			"PTP: %s error %d\n", __func__, -err);
227 
228 	return err;
229 }
230 
231 /**
232  * cxgb4_ptp_fineadjtime - Shift the time of the hardware clock
233  * @adapter: board private structure
234  * @delta: Desired change in nanoseconds
235  *
236  * Adjust the timer by resetting the timecounter structure.
237  */
cxgb4_ptp_fineadjtime(struct adapter * adapter,s64 delta)238 static int  cxgb4_ptp_fineadjtime(struct adapter *adapter, s64 delta)
239 {
240 	struct fw_ptp_cmd c;
241 	int err;
242 
243 	memset(&c, 0, sizeof(c));
244 	c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
245 			     FW_CMD_REQUEST_F |
246 			     FW_CMD_WRITE_F |
247 			     FW_PTP_CMD_PORTID_V(0));
248 	c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
249 	c.u.ts.sc = FW_PTP_SC_ADJ_FTIME;
250 	c.u.ts.sign = (delta < 0) ? 1 : 0;
251 	if (delta < 0)
252 		delta = -delta;
253 	c.u.ts.tm = cpu_to_be64(delta);
254 
255 	err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
256 	if (err < 0)
257 		dev_err(adapter->pdev_dev,
258 			"PTP: %s error %d\n", __func__, -err);
259 	return err;
260 }
261 
262 /**
263  * cxgb4_ptp_adjtime - Shift the time of the hardware clock
264  * @ptp: ptp clock structure
265  * @delta: Desired change in nanoseconds
266  *
267  * Adjust the timer by resetting the timecounter structure.
268  */
cxgb4_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)269 static int cxgb4_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
270 {
271 	struct adapter *adapter =
272 		(struct adapter *)container_of(ptp, struct adapter,
273 					       ptp_clock_info);
274 	struct fw_ptp_cmd c;
275 	s64 sign = 1;
276 	int err;
277 
278 	if (delta < 0)
279 		sign = -1;
280 
281 	if (delta * sign > PTP_CLOCK_MAX_ADJTIME) {
282 		memset(&c, 0, sizeof(c));
283 		c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
284 					     FW_CMD_REQUEST_F |
285 					     FW_CMD_WRITE_F |
286 					     FW_PTP_CMD_PORTID_V(0));
287 		c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
288 		c.u.ts.sc = FW_PTP_SC_ADJ_TIME;
289 		c.u.ts.sign = (delta < 0) ? 1 : 0;
290 		if (delta < 0)
291 			delta = -delta;
292 		c.u.ts.tm = cpu_to_be64(delta);
293 
294 		err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
295 		if (err < 0)
296 			dev_err(adapter->pdev_dev,
297 				"PTP: %s error %d\n", __func__, -err);
298 	} else {
299 		err = cxgb4_ptp_fineadjtime(adapter, delta);
300 	}
301 
302 	return err;
303 }
304 
305 /**
306  * cxgb4_ptp_gettime - Reads the current time from the hardware clock
307  * @ptp: ptp clock structure
308  * @ts: timespec structure to hold the current time value
309  *
310  * Read the timecounter and return the correct value in ns after converting
311  * it into a struct timespec.
312  */
cxgb4_ptp_gettime(struct ptp_clock_info * ptp,struct timespec64 * ts)313 static int cxgb4_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
314 {
315 	struct adapter *adapter = container_of(ptp, struct adapter,
316 					       ptp_clock_info);
317 	u64 ns;
318 
319 	ns = t4_read_reg(adapter, T5_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
320 	ns |= (u64)t4_read_reg(adapter,
321 			       T5_PORT_REG(0, MAC_PORT_PTP_SUM_HI_A)) << 32;
322 
323 	/* convert to timespec*/
324 	*ts = ns_to_timespec64(ns);
325 	return 0;
326 }
327 
328 /**
329  *  cxgb4_ptp_settime - Set the current time on the hardware clock
330  *  @ptp: ptp clock structure
331  *  @ts: timespec containing the new time for the cycle counter
332  *
333  *  Reset value to new base value instead of the kernel
334  *  wall timer value.
335  */
cxgb4_ptp_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)336 static int cxgb4_ptp_settime(struct ptp_clock_info *ptp,
337 			     const struct timespec64 *ts)
338 {
339 	struct adapter *adapter = (struct adapter *)container_of(ptp,
340 				   struct adapter, ptp_clock_info);
341 	struct fw_ptp_cmd c;
342 	u64 ns;
343 	int err;
344 
345 	memset(&c, 0, sizeof(c));
346 	c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
347 				     FW_CMD_REQUEST_F |
348 				     FW_CMD_WRITE_F |
349 				     FW_PTP_CMD_PORTID_V(0));
350 	c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
351 	c.u.ts.sc = FW_PTP_SC_SET_TIME;
352 
353 	ns = timespec64_to_ns(ts);
354 	c.u.ts.tm = cpu_to_be64(ns);
355 
356 	err =  t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
357 	if (err < 0)
358 		dev_err(adapter->pdev_dev,
359 			"PTP: %s error %d\n", __func__, -err);
360 
361 	return err;
362 }
363 
cxgb4_init_ptp_timer(struct adapter * adapter)364 static void cxgb4_init_ptp_timer(struct adapter *adapter)
365 {
366 	struct fw_ptp_cmd c;
367 	int err;
368 
369 	memset(&c, 0, sizeof(c));
370 	c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
371 				     FW_CMD_REQUEST_F |
372 				     FW_CMD_WRITE_F |
373 				     FW_PTP_CMD_PORTID_V(0));
374 	c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
375 	c.u.scmd.sc = FW_PTP_SC_INIT_TIMER;
376 
377 	err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), NULL);
378 	if (err < 0)
379 		dev_err(adapter->pdev_dev,
380 			"PTP: %s error %d\n", __func__, -err);
381 }
382 
383 /**
384  * cxgb4_ptp_enable - enable or disable an ancillary feature
385  * @ptp: ptp clock structure
386  * @request: Desired resource to enable or disable
387  * @on: Caller passes one to enable or zero to disable
388  *
389  * Enable (or disable) ancillary features of the PHC subsystem.
390  * Currently, no ancillary features are supported.
391  */
cxgb4_ptp_enable(struct ptp_clock_info __always_unused * ptp,struct ptp_clock_request __always_unused * request,int __always_unused on)392 static int cxgb4_ptp_enable(struct ptp_clock_info __always_unused *ptp,
393 			    struct ptp_clock_request __always_unused *request,
394 			    int __always_unused on)
395 {
396 	return -ENOTSUPP;
397 }
398 
399 static const struct ptp_clock_info cxgb4_ptp_clock_info = {
400 	.owner          = THIS_MODULE,
401 	.name           = "cxgb4_clock",
402 	.max_adj        = MAX_PTP_FREQ_ADJ,
403 	.n_alarm        = 0,
404 	.n_ext_ts       = 0,
405 	.n_per_out      = 0,
406 	.pps            = 0,
407 	.adjfreq        = cxgb4_ptp_adjfreq,
408 	.adjtime        = cxgb4_ptp_adjtime,
409 	.gettime64      = cxgb4_ptp_gettime,
410 	.settime64      = cxgb4_ptp_settime,
411 	.enable         = cxgb4_ptp_enable,
412 };
413 
414 /**
415  * cxgb4_ptp_init - initialize PTP for devices which support it
416  * @adapter: board private structure
417  *
418  * This function performs the required steps for enabling PTP support.
419  */
cxgb4_ptp_init(struct adapter * adapter)420 void cxgb4_ptp_init(struct adapter *adapter)
421 {
422 	struct timespec64 now;
423 	 /* no need to create a clock device if we already have one */
424 	if (!IS_ERR_OR_NULL(adapter->ptp_clock))
425 		return;
426 
427 	adapter->ptp_tx_skb = NULL;
428 	adapter->ptp_clock_info = cxgb4_ptp_clock_info;
429 	spin_lock_init(&adapter->ptp_lock);
430 
431 	adapter->ptp_clock = ptp_clock_register(&adapter->ptp_clock_info,
432 						&adapter->pdev->dev);
433 	if (IS_ERR_OR_NULL(adapter->ptp_clock)) {
434 		adapter->ptp_clock = NULL;
435 		dev_err(adapter->pdev_dev,
436 			"PTP %s Clock registration has failed\n", __func__);
437 		return;
438 	}
439 
440 	now = ktime_to_timespec64(ktime_get_real());
441 	cxgb4_init_ptp_timer(adapter);
442 	if (cxgb4_ptp_settime(&adapter->ptp_clock_info, &now) < 0) {
443 		ptp_clock_unregister(adapter->ptp_clock);
444 		adapter->ptp_clock = NULL;
445 	}
446 }
447 
448 /**
449  * cxgb4_ptp_stop - disable PTP device and stop the overflow check
450  * @adapter: board private structure
451  *
452  * Stop the PTP support.
453  */
cxgb4_ptp_stop(struct adapter * adapter)454 void cxgb4_ptp_stop(struct adapter *adapter)
455 {
456 	if (adapter->ptp_tx_skb) {
457 		dev_kfree_skb_any(adapter->ptp_tx_skb);
458 		adapter->ptp_tx_skb = NULL;
459 	}
460 
461 	if (adapter->ptp_clock) {
462 		ptp_clock_unregister(adapter->ptp_clock);
463 		adapter->ptp_clock = NULL;
464 	}
465 }
466