1 /*
2  *  cx18 ADEC audio functions
3  *
4  *  Derived from cx25840-core.c
5  *
6  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
7  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
8  *
9  *  This program is free software; you can redistribute it and/or
10  *  modify it under the terms of the GNU General Public License
11  *  as published by the Free Software Foundation; either version 2
12  *  of the License, or (at your option) any later version.
13  *
14  *  This program is distributed in the hope that it will be useful,
15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *  GNU General Public License for more details.
18  *
19  *  You should have received a copy of the GNU General Public License
20  *  along with this program; if not, write to the Free Software
21  *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22  *  02110-1301, USA.
23  */
24 
25 #include <media/v4l2-chip-ident.h>
26 #include "cx18-driver.h"
27 #include "cx18-io.h"
28 #include "cx18-cards.h"
29 
cx18_av_write(struct cx18 * cx,u16 addr,u8 value)30 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
31 {
32 	u32 reg = 0xc40000 + (addr & ~3);
33 	u32 mask = 0xff;
34 	int shift = (addr & 3) * 8;
35 	u32 x = cx18_read_reg(cx, reg);
36 
37 	x = (x & ~(mask << shift)) | ((u32)value << shift);
38 	cx18_write_reg(cx, x, reg);
39 	return 0;
40 }
41 
cx18_av_write_expect(struct cx18 * cx,u16 addr,u8 value,u8 eval,u8 mask)42 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
43 {
44 	u32 reg = 0xc40000 + (addr & ~3);
45 	int shift = (addr & 3) * 8;
46 	u32 x = cx18_read_reg(cx, reg);
47 
48 	x = (x & ~((u32)0xff << shift)) | ((u32)value << shift);
49 	cx18_write_reg_expect(cx, x, reg,
50 				((u32)eval << shift), ((u32)mask << shift));
51 	return 0;
52 }
53 
cx18_av_write4(struct cx18 * cx,u16 addr,u32 value)54 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
55 {
56 	cx18_write_reg(cx, value, 0xc40000 + addr);
57 	return 0;
58 }
59 
60 int
cx18_av_write4_expect(struct cx18 * cx,u16 addr,u32 value,u32 eval,u32 mask)61 cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
62 {
63 	cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
64 	return 0;
65 }
66 
cx18_av_write4_noretry(struct cx18 * cx,u16 addr,u32 value)67 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
68 {
69 	cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
70 	return 0;
71 }
72 
cx18_av_read(struct cx18 * cx,u16 addr)73 u8 cx18_av_read(struct cx18 *cx, u16 addr)
74 {
75 	u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
76 	int shift = (addr & 3) * 8;
77 
78 	return (x >> shift) & 0xff;
79 }
80 
cx18_av_read4(struct cx18 * cx,u16 addr)81 u32 cx18_av_read4(struct cx18 *cx, u16 addr)
82 {
83 	return cx18_read_reg(cx, 0xc40000 + addr);
84 }
85 
cx18_av_and_or(struct cx18 * cx,u16 addr,unsigned and_mask,u8 or_value)86 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
87 		   u8 or_value)
88 {
89 	return cx18_av_write(cx, addr,
90 			     (cx18_av_read(cx, addr) & and_mask) |
91 			     or_value);
92 }
93 
cx18_av_and_or4(struct cx18 * cx,u16 addr,u32 and_mask,u32 or_value)94 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
95 		   u32 or_value)
96 {
97 	return cx18_av_write4(cx, addr,
98 			     (cx18_av_read4(cx, addr) & and_mask) |
99 			     or_value);
100 }
101 
cx18_av_init(struct cx18 * cx)102 static void cx18_av_init(struct cx18 *cx)
103 {
104 	/*
105 	 * The crystal freq used in calculations in this driver will be
106 	 * 28.636360 MHz.
107 	 * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
108 	 */
109 
110 	/*
111 	 * VDCLK  Integer = 0x0f, Post Divider = 0x04
112 	 * AIMCLK Integer = 0x0e, Post Divider = 0x16
113 	 */
114 	cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
115 
116 	/* VDCLK Fraction = 0x2be2fe */
117 	/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
118 	cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
119 
120 	/* AIMCLK Fraction = 0x05227ad */
121 	/* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
122 	cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
123 
124 	/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
125 	cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
126 }
127 
cx18_av_initialize(struct v4l2_subdev * sd)128 static void cx18_av_initialize(struct v4l2_subdev *sd)
129 {
130 	struct cx18_av_state *state = to_cx18_av_state(sd);
131 	struct cx18 *cx = v4l2_get_subdevdata(sd);
132 	int default_volume;
133 	u32 v;
134 
135 	cx18_av_loadfw(cx);
136 	/* Stop 8051 code execution */
137 	cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
138 						 0x03000000, 0x13000000);
139 
140 	/* initallize the PLL by toggling sleep bit */
141 	v = cx18_av_read4(cx, CXADEC_HOST_REG1);
142 	/* enable sleep mode - register appears to be read only... */
143 	cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
144 	/* disable sleep mode */
145 	cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
146 						    v & 0xfffe, 0xffff);
147 
148 	/* initialize DLLs */
149 	v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
150 	/* disable FLD */
151 	cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
152 	/* enable FLD */
153 	cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
154 
155 	v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
156 	/* disable FLD */
157 	cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
158 	/* enable FLD */
159 	cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
160 
161 	/* set analog bias currents. Set Vreg to 1.20V. */
162 	cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
163 
164 	v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
165 	/* enable TUNE_FIL_RST */
166 	cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
167 	/* disable TUNE_FIL_RST */
168 	cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
169 			      v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
170 
171 	/* enable 656 output */
172 	cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
173 
174 	/* video output drive strength */
175 	cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
176 
177 	/* reset video */
178 	cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
179 	cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
180 
181 	/*
182 	 * Disable Video Auto-config of the Analog Front End and Video PLL.
183 	 *
184 	 * Since we only use BT.656 pixel mode, which works for both 525 and 625
185 	 * line systems, it's just easier for us to set registers
186 	 * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL),
187 	 * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC)
188 	 * ourselves, than to run around cleaning up after the auto-config.
189 	 *
190 	 * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit
191 	 * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL
192 	 * autoconfig either.)
193 	 *
194 	 * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3.
195 	 */
196 	cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000);
197 
198 	/* Setup the Video and and Aux/Audio PLLs */
199 	cx18_av_init(cx);
200 
201 	/* set video to auto-detect */
202 	/* Clear bits 11-12 to enable slow locking mode.  Set autodetect mode */
203 	/* set the comb notch = 1 */
204 	cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
205 
206 	/* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
207 	/* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
208 	cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
209 
210 	/* Set VGA_TRACK_RANGE to 0x20 */
211 	cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
212 
213 	/*
214 	 * Initial VBI setup
215 	 * VIP-1.1, 10 bit mode, enable Raw, disable sliced,
216 	 * don't clamp raw samples when codes are in use, 1 byte user D-words,
217 	 * IDID0 has line #, RP code V bit transition on VBLANK, data during
218 	 * blanking intervals
219 	 */
220 	cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
221 
222 	/* Set the video input.
223 	   The setting in MODE_CTRL gets lost when we do the above setup */
224 	/* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
225 	/* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
226 
227 	/*
228 	 * Analog Front End (AFE)
229 	 * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2
230 	 *  bypass_ch[1-3]     use filter
231 	 *  droop_comp_ch[1-3] disable
232 	 *  clamp_en_ch[1-3]   disable
233 	 *  aud_in_sel         ADC2
234 	 *  luma_in_sel        ADC1
235 	 *  chroma_in_sel      ADC2
236 	 *  clamp_sel_ch[2-3]  midcode
237 	 *  clamp_sel_ch1      video decoder
238 	 *  vga_sel_ch3        audio decoder
239 	 *  vga_sel_ch[1-2]    video decoder
240 	 *  half_bw_ch[1-3]    disable
241 	 *  +12db_ch[1-3]      disable
242 	 */
243 	cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00);
244 
245 /* 	if(dwEnable && dw3DCombAvailable) { */
246 /*      	CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
247 /*    } else { */
248 /*      	CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
249 /*    } */
250 	cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
251 	default_volume = cx18_av_read(cx, 0x8d4);
252 	/*
253 	 * Enforce the legacy volume scale mapping limits to avoid
254 	 * -ERANGE errors when initializing the volume control
255 	 */
256 	if (default_volume > 228) {
257 		/* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */
258 		default_volume = 228;
259 		cx18_av_write(cx, 0x8d4, 228);
260 	} else if (default_volume < 20) {
261 		/* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */
262 		default_volume = 20;
263 		cx18_av_write(cx, 0x8d4, 20);
264 	}
265 	default_volume = (((228 - default_volume) >> 1) + 23) << 9;
266 	state->volume->cur.val = state->volume->default_value = default_volume;
267 	v4l2_ctrl_handler_setup(&state->hdl);
268 }
269 
cx18_av_reset(struct v4l2_subdev * sd,u32 val)270 static int cx18_av_reset(struct v4l2_subdev *sd, u32 val)
271 {
272 	cx18_av_initialize(sd);
273 	return 0;
274 }
275 
cx18_av_load_fw(struct v4l2_subdev * sd)276 static int cx18_av_load_fw(struct v4l2_subdev *sd)
277 {
278 	struct cx18_av_state *state = to_cx18_av_state(sd);
279 
280 	if (!state->is_initialized) {
281 		/* initialize on first use */
282 		state->is_initialized = 1;
283 		cx18_av_initialize(sd);
284 	}
285 	return 0;
286 }
287 
cx18_av_std_setup(struct cx18 * cx)288 void cx18_av_std_setup(struct cx18 *cx)
289 {
290 	struct cx18_av_state *state = &cx->av_state;
291 	struct v4l2_subdev *sd = &state->sd;
292 	v4l2_std_id std = state->std;
293 
294 	/*
295 	 * Video ADC crystal clock to pixel clock SRC decimation ratio
296 	 * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b
297 	 */
298 	const int src_decimation = 0x21f;
299 
300 	int hblank, hactive, burst, vblank, vactive, sc;
301 	int vblank656;
302 	int luma_lpf, uv_lpf, comb;
303 	u32 pll_int, pll_frac, pll_post;
304 
305 	/* datasheet startup, step 8d */
306 	if (std & ~V4L2_STD_NTSC)
307 		cx18_av_write(cx, 0x49f, 0x11);
308 	else
309 		cx18_av_write(cx, 0x49f, 0x14);
310 
311 	/*
312 	 * Note: At the end of a field, there are 3 sets of half line duration
313 	 * (double horizontal rate) pulses:
314 	 *
315 	 * 5 (625) or 6 (525) half-lines to blank for the vertical retrace
316 	 * 5 (625) or 6 (525) vertical sync pulses of half line duration
317 	 * 5 (625) or 6 (525) half-lines of equalization pulses
318 	 */
319 	if (std & V4L2_STD_625_50) {
320 		/*
321 		 * The following relationships of half line counts should hold:
322 		 * 625 = vblank656 + vactive
323 		 * 10 = vblank656 - vblank = vsync pulses + equalization pulses
324 		 *
325 		 * vblank656: half lines after line 625/mid-313 of blanked video
326 		 * vblank:    half lines, after line 5/317, of blanked video
327 		 * vactive:   half lines of active video +
328 		 * 		5 half lines after the end of active video
329 		 *
330 		 * As far as I can tell:
331 		 * vblank656 starts counting from the falling edge of the first
332 		 * 	vsync pulse (start of line 1 or mid-313)
333 		 * vblank starts counting from the after the 5 vsync pulses and
334 		 * 	5 or 4 equalization pulses (start of line 6 or 318)
335 		 *
336 		 * For 625 line systems the driver will extract VBI information
337 		 * from lines 6-23 and lines 318-335 (but the slicer can only
338 		 * handle 17 lines, not the 18 in the vblank region).
339 		 * In addition, we need vblank656 and vblank to be one whole
340 		 * line longer, to cover line 24 and 336, so the SAV/EAV RP
341 		 * codes get generated such that the encoder can actually
342 		 * extract line 23 & 335 (WSS).  We'll lose 1 line in each field
343 		 * at the top of the screen.
344 		 *
345 		 * It appears the 5 half lines that happen after active
346 		 * video must be included in vactive (579 instead of 574),
347 		 * otherwise the colors get badly displayed in various regions
348 		 * of the screen.  I guess the chroma comb filter gets confused
349 		 * without them (at least when a PVR-350 is the PAL source).
350 		 */
351 		vblank656 = 48; /* lines  1 -  24  &  313 - 336 */
352 		vblank = 38;    /* lines  6 -  24  &  318 - 336 */
353 		vactive = 579;  /* lines 24 - 313  &  337 - 626 */
354 
355 		/*
356 		 * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is
357 		 * is 864 pixels = 720 active + 144 blanking.  ITU-R BT.601
358 		 * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after
359 		 * the end of active video to start a horizontal line, so that
360 		 * leaves 132 pixels of hblank to ignore.
361 		 */
362 		hblank = 132;
363 		hactive = 720;
364 
365 		/*
366 		 * Burst gate delay (for 625 line systems)
367 		 * Hsync leading edge to color burst rise = 5.6 us
368 		 * Color burst width = 2.25 us
369 		 * Gate width = 4 pixel clocks
370 		 * (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks
371 		 */
372 		burst = 93;
373 		luma_lpf = 2;
374 		if (std & V4L2_STD_PAL) {
375 			uv_lpf = 1;
376 			comb = 0x20;
377 			/* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
378 			sc = 688700;
379 		} else if (std == V4L2_STD_PAL_Nc) {
380 			uv_lpf = 1;
381 			comb = 0x20;
382 			/* sc = 3582056.25 * src_decimation/28636360 * 2^13 */
383 			sc = 556422;
384 		} else { /* SECAM */
385 			uv_lpf = 0;
386 			comb = 0;
387 			/* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */
388 			/* sc = 4328130 * src_decimation/28636360 * 2^13 */
389 			sc = 672314;
390 		}
391 	} else {
392 		/*
393 		 * The following relationships of half line counts should hold:
394 		 * 525 = prevsync + vblank656 + vactive
395 		 * 12 = vblank656 - vblank = vsync pulses + equalization pulses
396 		 *
397 		 * prevsync:  6 half-lines before the vsync pulses
398 		 * vblank656: half lines, after line 3/mid-266, of blanked video
399 		 * vblank:    half lines, after line 9/272, of blanked video
400 		 * vactive:   half lines of active video
401 		 *
402 		 * As far as I can tell:
403 		 * vblank656 starts counting from the falling edge of the first
404 		 * 	vsync pulse (start of line 4 or mid-266)
405 		 * vblank starts counting from the after the 6 vsync pulses and
406 		 * 	6 or 5 equalization pulses (start of line 10 or 272)
407 		 *
408 		 * For 525 line systems the driver will extract VBI information
409 		 * from lines 10-21 and lines 273-284.
410 		 */
411 		vblank656 = 38; /* lines  4 -  22  &  266 - 284 */
412 		vblank = 26;	/* lines 10 -  22  &  272 - 284 */
413 		vactive = 481;  /* lines 23 - 263  &  285 - 525 */
414 
415 		/*
416 		 * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is
417 		 * is 858 pixels = 720 active + 138 blanking.  The Hsync leading
418 		 * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the
419 		 * end of active video, leaving 122 pixels of hblank to ignore
420 		 * before active video starts.
421 		 */
422 		hactive = 720;
423 		hblank = 122;
424 		luma_lpf = 1;
425 		uv_lpf = 1;
426 
427 		/*
428 		 * Burst gate delay (for 525 line systems)
429 		 * Hsync leading edge to color burst rise = 5.3 us
430 		 * Color burst width = 2.5 us
431 		 * Gate width = 4 pixel clocks
432 		 * (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks
433 		 */
434 		if (std == V4L2_STD_PAL_60) {
435 			burst = 90;
436 			luma_lpf = 2;
437 			comb = 0x20;
438 			/* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
439 			sc = 688700;
440 		} else if (std == V4L2_STD_PAL_M) {
441 			/* The 97 needs to be verified against PAL-M timings */
442 			burst = 97;
443 			comb = 0x20;
444 			/* sc = 3575611.49 * src_decimation/28636360 * 2^13 */
445 			sc = 555421;
446 		} else {
447 			burst = 90;
448 			comb = 0x66;
449 			/* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */
450 			sc = 556032;
451 		}
452 	}
453 
454 	/* DEBUG: Displays configured PLL frequency */
455 	pll_int = cx18_av_read(cx, 0x108);
456 	pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
457 	pll_post = cx18_av_read(cx, 0x109);
458 	CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n",
459 			    pll_int, pll_frac, pll_post);
460 
461 	if (pll_post) {
462 		int fsc, pll;
463 		u64 tmp;
464 
465 		pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
466 		pll /= pll_post;
467 		CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n",
468 				    pll / 1000000, pll % 1000000);
469 		CX18_DEBUG_INFO_DEV(sd, "Pixel rate = %d.%06d Mpixel/sec\n",
470 				    pll / 8000000, (pll / 8) % 1000000);
471 
472 		CX18_DEBUG_INFO_DEV(sd, "ADC XTAL/pixel clock decimation ratio "
473 				    "= %d.%03d\n", src_decimation / 256,
474 				    ((src_decimation % 256) * 1000) / 256);
475 
476 		tmp = 28636360 * (u64) sc;
477 		do_div(tmp, src_decimation);
478 		fsc = tmp >> 13;
479 		CX18_DEBUG_INFO_DEV(sd,
480 				    "Chroma sub-carrier initial freq = %d.%06d "
481 				    "MHz\n", fsc / 1000000, fsc % 1000000);
482 
483 		CX18_DEBUG_INFO_DEV(sd, "hblank %i, hactive %i, vblank %i, "
484 				    "vactive %i, vblank656 %i, src_dec %i, "
485 				    "burst 0x%02x, luma_lpf %i, uv_lpf %i, "
486 				    "comb 0x%02x, sc 0x%06x\n",
487 				    hblank, hactive, vblank, vactive, vblank656,
488 				    src_decimation, burst, luma_lpf, uv_lpf,
489 				    comb, sc);
490 	}
491 
492 	/* Sets horizontal blanking delay and active lines */
493 	cx18_av_write(cx, 0x470, hblank);
494 	cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) |
495 						(hactive << 4)));
496 	cx18_av_write(cx, 0x472, hactive >> 4);
497 
498 	/* Sets burst gate delay */
499 	cx18_av_write(cx, 0x473, burst);
500 
501 	/* Sets vertical blanking delay and active duration */
502 	cx18_av_write(cx, 0x474, vblank);
503 	cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) |
504 						(vactive << 4)));
505 	cx18_av_write(cx, 0x476, vactive >> 4);
506 	cx18_av_write(cx, 0x477, vblank656);
507 
508 	/* Sets src decimation rate */
509 	cx18_av_write(cx, 0x478, 0xff & src_decimation);
510 	cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8));
511 
512 	/* Sets Luma and UV Low pass filters */
513 	cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
514 
515 	/* Enables comb filters */
516 	cx18_av_write(cx, 0x47b, comb);
517 
518 	/* Sets SC Step*/
519 	cx18_av_write(cx, 0x47c, sc);
520 	cx18_av_write(cx, 0x47d, 0xff & sc >> 8);
521 	cx18_av_write(cx, 0x47e, 0xff & sc >> 16);
522 
523 	if (std & V4L2_STD_625_50) {
524 		state->slicer_line_delay = 1;
525 		state->slicer_line_offset = (6 + state->slicer_line_delay - 2);
526 	} else {
527 		state->slicer_line_delay = 0;
528 		state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
529 	}
530 	cx18_av_write(cx, 0x47f, state->slicer_line_delay);
531 }
532 
input_change(struct cx18 * cx)533 static void input_change(struct cx18 *cx)
534 {
535 	struct cx18_av_state *state = &cx->av_state;
536 	v4l2_std_id std = state->std;
537 	u8 v;
538 
539 	/* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
540 	cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
541 	cx18_av_and_or(cx, 0x401, ~0x60, 0);
542 	cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
543 
544 	if (std & V4L2_STD_525_60) {
545 		if (std == V4L2_STD_NTSC_M_JP) {
546 			/* Japan uses EIAJ audio standard */
547 			cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
548 			cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
549 		} else if (std == V4L2_STD_NTSC_M_KR) {
550 			/* South Korea uses A2 audio standard */
551 			cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
552 			cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
553 		} else {
554 			/* Others use the BTSC audio standard */
555 			cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
556 			cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
557 		}
558 	} else if (std & V4L2_STD_PAL) {
559 		/* Follow tuner change procedure for PAL */
560 		cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
561 		cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
562 	} else if (std & V4L2_STD_SECAM) {
563 		/* Select autodetect for SECAM */
564 		cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
565 		cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
566 	}
567 
568 	v = cx18_av_read(cx, 0x803);
569 	if (v & 0x10) {
570 		/* restart audio decoder microcontroller */
571 		v &= ~0x10;
572 		cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
573 		v |= 0x10;
574 		cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
575 	}
576 }
577 
cx18_av_s_frequency(struct v4l2_subdev * sd,struct v4l2_frequency * freq)578 static int cx18_av_s_frequency(struct v4l2_subdev *sd,
579 			       struct v4l2_frequency *freq)
580 {
581 	struct cx18 *cx = v4l2_get_subdevdata(sd);
582 	input_change(cx);
583 	return 0;
584 }
585 
set_input(struct cx18 * cx,enum cx18_av_video_input vid_input,enum cx18_av_audio_input aud_input)586 static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
587 					enum cx18_av_audio_input aud_input)
588 {
589 	struct cx18_av_state *state = &cx->av_state;
590 	struct v4l2_subdev *sd = &state->sd;
591 
592 	enum analog_signal_type {
593 		NONE, CVBS, Y, C, SIF, Pb, Pr
594 	} ch[3] = {NONE, NONE, NONE};
595 
596 	u8 afe_mux_cfg;
597 	u8 adc2_cfg;
598 	u8 input_mode;
599 	u32 afe_cfg;
600 	int i;
601 
602 	CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n",
603 			    vid_input, aud_input);
604 
605 	if (vid_input >= CX18_AV_COMPOSITE1 &&
606 	    vid_input <= CX18_AV_COMPOSITE8) {
607 		afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
608 		ch[0] = CVBS;
609 		input_mode = 0x0;
610 	} else if (vid_input >= CX18_AV_COMPONENT_LUMA1) {
611 		int luma = vid_input & 0xf000;
612 		int r_chroma = vid_input & 0xf0000;
613 		int b_chroma = vid_input & 0xf00000;
614 
615 		if ((vid_input & ~0xfff000) ||
616 		    luma < CX18_AV_COMPONENT_LUMA1 ||
617 		    luma > CX18_AV_COMPONENT_LUMA8 ||
618 		    r_chroma < CX18_AV_COMPONENT_R_CHROMA4 ||
619 		    r_chroma > CX18_AV_COMPONENT_R_CHROMA6 ||
620 		    b_chroma < CX18_AV_COMPONENT_B_CHROMA7 ||
621 		    b_chroma > CX18_AV_COMPONENT_B_CHROMA8) {
622 			CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n",
623 				     vid_input);
624 			return -EINVAL;
625 		}
626 		afe_mux_cfg = (luma - CX18_AV_COMPONENT_LUMA1) >> 12;
627 		ch[0] = Y;
628 		afe_mux_cfg |= (r_chroma - CX18_AV_COMPONENT_R_CHROMA4) >> 12;
629 		ch[1] = Pr;
630 		afe_mux_cfg |= (b_chroma - CX18_AV_COMPONENT_B_CHROMA7) >> 14;
631 		ch[2] = Pb;
632 		input_mode = 0x6;
633 	} else {
634 		int luma = vid_input & 0xf0;
635 		int chroma = vid_input & 0xf00;
636 
637 		if ((vid_input & ~0xff0) ||
638 		    luma < CX18_AV_SVIDEO_LUMA1 ||
639 		    luma > CX18_AV_SVIDEO_LUMA8 ||
640 		    chroma < CX18_AV_SVIDEO_CHROMA4 ||
641 		    chroma > CX18_AV_SVIDEO_CHROMA8) {
642 			CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n",
643 				     vid_input);
644 			return -EINVAL;
645 		}
646 		afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
647 		ch[0] = Y;
648 		if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
649 			afe_mux_cfg &= 0x3f;
650 			afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
651 			ch[2] = C;
652 		} else {
653 			afe_mux_cfg &= 0xcf;
654 			afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
655 			ch[1] = C;
656 		}
657 		input_mode = 0x2;
658 	}
659 
660 	switch (aud_input) {
661 	case CX18_AV_AUDIO_SERIAL1:
662 	case CX18_AV_AUDIO_SERIAL2:
663 		/* do nothing, use serial audio input */
664 		break;
665 	case CX18_AV_AUDIO4:
666 		afe_mux_cfg &= ~0x30;
667 		ch[1] = SIF;
668 		break;
669 	case CX18_AV_AUDIO5:
670 		afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10;
671 		ch[1] = SIF;
672 		break;
673 	case CX18_AV_AUDIO6:
674 		afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20;
675 		ch[1] = SIF;
676 		break;
677 	case CX18_AV_AUDIO7:
678 		afe_mux_cfg &= ~0xc0;
679 		ch[2] = SIF;
680 		break;
681 	case CX18_AV_AUDIO8:
682 		afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40;
683 		ch[2] = SIF;
684 		break;
685 
686 	default:
687 		CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n",
688 			     aud_input);
689 		return -EINVAL;
690 	}
691 
692 	/* Set up analog front end multiplexers */
693 	cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7);
694 	/* Set INPUT_MODE to Composite, S-Video, or Component */
695 	cx18_av_and_or(cx, 0x401, ~0x6, input_mode);
696 
697 	/* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
698 	adc2_cfg = cx18_av_read(cx, 0x102);
699 	if (ch[2] == NONE)
700 		adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */
701 	else
702 		adc2_cfg |= 0x2;  /* Signal on CH3, set ADC2 to CH3 for input */
703 
704 	/* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
705 	if (ch[1] != NONE && ch[2] != NONE)
706 		adc2_cfg |= 0x4; /* Set dual mode */
707 	else
708 		adc2_cfg &= ~0x4; /* Clear dual mode */
709 	cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17);
710 
711 	/* Configure the analog front end */
712 	afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL);
713 	afe_cfg &= 0xff000000;
714 	afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */
715 	if (ch[1] != NONE && ch[2] != NONE)
716 		afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */
717 
718 	for (i = 0; i < 3; i++) {
719 		switch (ch[i]) {
720 		default:
721 		case NONE:
722 			/* CLAMP_SEL = Fixed to midcode clamp level */
723 			afe_cfg |= (0x00000200 << i);
724 			break;
725 		case CVBS:
726 		case Y:
727 			if (i > 0)
728 				afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */
729 			break;
730 		case C:
731 		case Pb:
732 		case Pr:
733 			/* CLAMP_SEL = Fixed to midcode clamp level */
734 			afe_cfg |= (0x00000200 << i);
735 			if (i == 0 && ch[i] == C)
736 				afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */
737 			break;
738 		case SIF:
739 			/*
740 			 * VGA_GAIN_SEL = Audio Decoder
741 			 * CLAMP_SEL = Fixed to midcode clamp level
742 			 */
743 			afe_cfg |= (0x00000240 << i);
744 			if (i == 0)
745 				afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */
746 			break;
747 		}
748 	}
749 
750 	cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg);
751 
752 	state->vid_input = vid_input;
753 	state->aud_input = aud_input;
754 	cx18_av_audio_set_path(cx);
755 	input_change(cx);
756 	return 0;
757 }
758 
cx18_av_s_video_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)759 static int cx18_av_s_video_routing(struct v4l2_subdev *sd,
760 				   u32 input, u32 output, u32 config)
761 {
762 	struct cx18_av_state *state = to_cx18_av_state(sd);
763 	struct cx18 *cx = v4l2_get_subdevdata(sd);
764 	return set_input(cx, input, state->aud_input);
765 }
766 
cx18_av_s_audio_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)767 static int cx18_av_s_audio_routing(struct v4l2_subdev *sd,
768 				   u32 input, u32 output, u32 config)
769 {
770 	struct cx18_av_state *state = to_cx18_av_state(sd);
771 	struct cx18 *cx = v4l2_get_subdevdata(sd);
772 	return set_input(cx, state->vid_input, input);
773 }
774 
cx18_av_g_tuner(struct v4l2_subdev * sd,struct v4l2_tuner * vt)775 static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
776 {
777 	struct cx18_av_state *state = to_cx18_av_state(sd);
778 	struct cx18 *cx = v4l2_get_subdevdata(sd);
779 	u8 vpres;
780 	u8 mode;
781 	int val = 0;
782 
783 	if (state->radio)
784 		return 0;
785 
786 	vpres = cx18_av_read(cx, 0x40e) & 0x20;
787 	vt->signal = vpres ? 0xffff : 0x0;
788 
789 	vt->capability |=
790 		    V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
791 		    V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
792 
793 	mode = cx18_av_read(cx, 0x804);
794 
795 	/* get rxsubchans and audmode */
796 	if ((mode & 0xf) == 1)
797 		val |= V4L2_TUNER_SUB_STEREO;
798 	else
799 		val |= V4L2_TUNER_SUB_MONO;
800 
801 	if (mode == 2 || mode == 4)
802 		val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
803 
804 	if (mode & 0x10)
805 		val |= V4L2_TUNER_SUB_SAP;
806 
807 	vt->rxsubchans = val;
808 	vt->audmode = state->audmode;
809 	return 0;
810 }
811 
cx18_av_s_tuner(struct v4l2_subdev * sd,struct v4l2_tuner * vt)812 static int cx18_av_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
813 {
814 	struct cx18_av_state *state = to_cx18_av_state(sd);
815 	struct cx18 *cx = v4l2_get_subdevdata(sd);
816 	u8 v;
817 
818 	if (state->radio)
819 		return 0;
820 
821 	v = cx18_av_read(cx, 0x809);
822 	v &= ~0xf;
823 
824 	switch (vt->audmode) {
825 	case V4L2_TUNER_MODE_MONO:
826 		/* mono      -> mono
827 		   stereo    -> mono
828 		   bilingual -> lang1 */
829 		break;
830 	case V4L2_TUNER_MODE_STEREO:
831 	case V4L2_TUNER_MODE_LANG1:
832 		/* mono      -> mono
833 		   stereo    -> stereo
834 		   bilingual -> lang1 */
835 		v |= 0x4;
836 		break;
837 	case V4L2_TUNER_MODE_LANG1_LANG2:
838 		/* mono      -> mono
839 		   stereo    -> stereo
840 		   bilingual -> lang1/lang2 */
841 		v |= 0x7;
842 		break;
843 	case V4L2_TUNER_MODE_LANG2:
844 		/* mono      -> mono
845 		   stereo    -> stereo
846 		   bilingual -> lang2 */
847 		v |= 0x1;
848 		break;
849 	default:
850 		return -EINVAL;
851 	}
852 	cx18_av_write_expect(cx, 0x809, v, v, 0xff);
853 	state->audmode = vt->audmode;
854 	return 0;
855 }
856 
cx18_av_s_std(struct v4l2_subdev * sd,v4l2_std_id norm)857 static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
858 {
859 	struct cx18_av_state *state = to_cx18_av_state(sd);
860 	struct cx18 *cx = v4l2_get_subdevdata(sd);
861 
862 	u8 fmt = 0; 	/* zero is autodetect */
863 	u8 pal_m = 0;
864 
865 	if (state->radio == 0 && state->std == norm)
866 		return 0;
867 
868 	state->radio = 0;
869 	state->std = norm;
870 
871 	/* First tests should be against specific std */
872 	if (state->std == V4L2_STD_NTSC_M_JP) {
873 		fmt = 0x2;
874 	} else if (state->std == V4L2_STD_NTSC_443) {
875 		fmt = 0x3;
876 	} else if (state->std == V4L2_STD_PAL_M) {
877 		pal_m = 1;
878 		fmt = 0x5;
879 	} else if (state->std == V4L2_STD_PAL_N) {
880 		fmt = 0x6;
881 	} else if (state->std == V4L2_STD_PAL_Nc) {
882 		fmt = 0x7;
883 	} else if (state->std == V4L2_STD_PAL_60) {
884 		fmt = 0x8;
885 	} else {
886 		/* Then, test against generic ones */
887 		if (state->std & V4L2_STD_NTSC)
888 			fmt = 0x1;
889 		else if (state->std & V4L2_STD_PAL)
890 			fmt = 0x4;
891 		else if (state->std & V4L2_STD_SECAM)
892 			fmt = 0xc;
893 	}
894 
895 	CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt);
896 
897 	/* Follow step 9 of section 3.16 in the cx18_av datasheet.
898 	   Without this PAL may display a vertical ghosting effect.
899 	   This happens for example with the Yuan MPC622. */
900 	if (fmt >= 4 && fmt < 8) {
901 		/* Set format to NTSC-M */
902 		cx18_av_and_or(cx, 0x400, ~0xf, 1);
903 		/* Turn off LCOMB */
904 		cx18_av_and_or(cx, 0x47b, ~6, 0);
905 	}
906 	cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
907 	cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
908 	cx18_av_std_setup(cx);
909 	input_change(cx);
910 	return 0;
911 }
912 
cx18_av_s_radio(struct v4l2_subdev * sd)913 static int cx18_av_s_radio(struct v4l2_subdev *sd)
914 {
915 	struct cx18_av_state *state = to_cx18_av_state(sd);
916 	state->radio = 1;
917 	return 0;
918 }
919 
cx18_av_s_ctrl(struct v4l2_ctrl * ctrl)920 static int cx18_av_s_ctrl(struct v4l2_ctrl *ctrl)
921 {
922 	struct v4l2_subdev *sd = to_sd(ctrl);
923 	struct cx18 *cx = v4l2_get_subdevdata(sd);
924 
925 	switch (ctrl->id) {
926 	case V4L2_CID_BRIGHTNESS:
927 		cx18_av_write(cx, 0x414, ctrl->val - 128);
928 		break;
929 
930 	case V4L2_CID_CONTRAST:
931 		cx18_av_write(cx, 0x415, ctrl->val << 1);
932 		break;
933 
934 	case V4L2_CID_SATURATION:
935 		cx18_av_write(cx, 0x420, ctrl->val << 1);
936 		cx18_av_write(cx, 0x421, ctrl->val << 1);
937 		break;
938 
939 	case V4L2_CID_HUE:
940 		cx18_av_write(cx, 0x422, ctrl->val);
941 		break;
942 
943 	default:
944 		return -EINVAL;
945 	}
946 	return 0;
947 }
948 
cx18_av_s_mbus_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt)949 static int cx18_av_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
950 {
951 	struct cx18_av_state *state = to_cx18_av_state(sd);
952 	struct cx18 *cx = v4l2_get_subdevdata(sd);
953 	int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
954 	int is_50Hz = !(state->std & V4L2_STD_525_60);
955 
956 	if (fmt->code != V4L2_MBUS_FMT_FIXED)
957 		return -EINVAL;
958 
959 	fmt->field = V4L2_FIELD_INTERLACED;
960 	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
961 
962 	Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
963 	Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
964 
965 	Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
966 	Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
967 
968 	/*
969 	 * This adjustment reflects the excess of vactive, set in
970 	 * cx18_av_std_setup(), above standard values:
971 	 *
972 	 * 480 + 1 for 60 Hz systems
973 	 * 576 + 3 for 50 Hz systems
974 	 */
975 	Vlines = fmt->height + (is_50Hz ? 3 : 1);
976 
977 	/*
978 	 * Invalid height and width scaling requests are:
979 	 * 1. width less than 1/16 of the source width
980 	 * 2. width greater than the source width
981 	 * 3. height less than 1/8 of the source height
982 	 * 4. height greater than the source height
983 	 */
984 	if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
985 	    (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
986 		CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n",
987 			     fmt->width, fmt->height);
988 		return -ERANGE;
989 	}
990 
991 	HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
992 	VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
993 	VSC &= 0x1fff;
994 
995 	if (fmt->width >= 385)
996 		filter = 0;
997 	else if (fmt->width > 192)
998 		filter = 1;
999 	else if (fmt->width > 96)
1000 		filter = 2;
1001 	else
1002 		filter = 3;
1003 
1004 	CX18_DEBUG_INFO_DEV(sd,
1005 			    "decoder set size %dx%d -> scale  %ux%u\n",
1006 			    fmt->width, fmt->height, HSC, VSC);
1007 
1008 	/* HSCALE=HSC */
1009 	cx18_av_write(cx, 0x418, HSC & 0xff);
1010 	cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
1011 	cx18_av_write(cx, 0x41a, HSC >> 16);
1012 	/* VSCALE=VSC */
1013 	cx18_av_write(cx, 0x41c, VSC & 0xff);
1014 	cx18_av_write(cx, 0x41d, VSC >> 8);
1015 	/* VS_INTRLACE=1 VFILT=filter */
1016 	cx18_av_write(cx, 0x41e, 0x8 | filter);
1017 	return 0;
1018 }
1019 
cx18_av_s_stream(struct v4l2_subdev * sd,int enable)1020 static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable)
1021 {
1022 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1023 
1024 	CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable");
1025 	if (enable) {
1026 		cx18_av_write(cx, 0x115, 0x8c);
1027 		cx18_av_write(cx, 0x116, 0x07);
1028 	} else {
1029 		cx18_av_write(cx, 0x115, 0x00);
1030 		cx18_av_write(cx, 0x116, 0x00);
1031 	}
1032 	return 0;
1033 }
1034 
log_video_status(struct cx18 * cx)1035 static void log_video_status(struct cx18 *cx)
1036 {
1037 	static const char *const fmt_strs[] = {
1038 		"0x0",
1039 		"NTSC-M", "NTSC-J", "NTSC-4.43",
1040 		"PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1041 		"0x9", "0xA", "0xB",
1042 		"SECAM",
1043 		"0xD", "0xE", "0xF"
1044 	};
1045 
1046 	struct cx18_av_state *state = &cx->av_state;
1047 	struct v4l2_subdev *sd = &state->sd;
1048 	u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
1049 	u8 gen_stat1 = cx18_av_read(cx, 0x40d);
1050 	u8 gen_stat2 = cx18_av_read(cx, 0x40e);
1051 	int vid_input = state->vid_input;
1052 
1053 	CX18_INFO_DEV(sd, "Video signal:              %spresent\n",
1054 		      (gen_stat2 & 0x20) ? "" : "not ");
1055 	CX18_INFO_DEV(sd, "Detected format:           %s\n",
1056 		      fmt_strs[gen_stat1 & 0xf]);
1057 
1058 	CX18_INFO_DEV(sd, "Specified standard:        %s\n",
1059 		      vidfmt_sel ? fmt_strs[vidfmt_sel]
1060 				 : "automatic detection");
1061 
1062 	if (vid_input >= CX18_AV_COMPOSITE1 &&
1063 	    vid_input <= CX18_AV_COMPOSITE8) {
1064 		CX18_INFO_DEV(sd, "Specified video input:     Composite %d\n",
1065 			      vid_input - CX18_AV_COMPOSITE1 + 1);
1066 	} else {
1067 		CX18_INFO_DEV(sd, "Specified video input:     "
1068 			      "S-Video (Luma In%d, Chroma In%d)\n",
1069 			      (vid_input & 0xf0) >> 4,
1070 			      (vid_input & 0xf00) >> 8);
1071 	}
1072 
1073 	CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n",
1074 		      state->audclk_freq);
1075 }
1076 
log_audio_status(struct cx18 * cx)1077 static void log_audio_status(struct cx18 *cx)
1078 {
1079 	struct cx18_av_state *state = &cx->av_state;
1080 	struct v4l2_subdev *sd = &state->sd;
1081 	u8 download_ctl = cx18_av_read(cx, 0x803);
1082 	u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
1083 	u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
1084 	u8 audio_config = cx18_av_read(cx, 0x808);
1085 	u8 pref_mode = cx18_av_read(cx, 0x809);
1086 	u8 afc0 = cx18_av_read(cx, 0x80b);
1087 	u8 mute_ctl = cx18_av_read(cx, 0x8d3);
1088 	int aud_input = state->aud_input;
1089 	char *p;
1090 
1091 	switch (mod_det_stat0) {
1092 	case 0x00: p = "mono"; break;
1093 	case 0x01: p = "stereo"; break;
1094 	case 0x02: p = "dual"; break;
1095 	case 0x04: p = "tri"; break;
1096 	case 0x10: p = "mono with SAP"; break;
1097 	case 0x11: p = "stereo with SAP"; break;
1098 	case 0x12: p = "dual with SAP"; break;
1099 	case 0x14: p = "tri with SAP"; break;
1100 	case 0xfe: p = "forced mode"; break;
1101 	default: p = "not defined"; break;
1102 	}
1103 	CX18_INFO_DEV(sd, "Detected audio mode:       %s\n", p);
1104 
1105 	switch (mod_det_stat1) {
1106 	case 0x00: p = "not defined"; break;
1107 	case 0x01: p = "EIAJ"; break;
1108 	case 0x02: p = "A2-M"; break;
1109 	case 0x03: p = "A2-BG"; break;
1110 	case 0x04: p = "A2-DK1"; break;
1111 	case 0x05: p = "A2-DK2"; break;
1112 	case 0x06: p = "A2-DK3"; break;
1113 	case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1114 	case 0x08: p = "AM-L"; break;
1115 	case 0x09: p = "NICAM-BG"; break;
1116 	case 0x0a: p = "NICAM-DK"; break;
1117 	case 0x0b: p = "NICAM-I"; break;
1118 	case 0x0c: p = "NICAM-L"; break;
1119 	case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1120 	case 0x0e: p = "IF FM Radio"; break;
1121 	case 0x0f: p = "BTSC"; break;
1122 	case 0x10: p = "detected chrominance"; break;
1123 	case 0xfd: p = "unknown audio standard"; break;
1124 	case 0xfe: p = "forced audio standard"; break;
1125 	case 0xff: p = "no detected audio standard"; break;
1126 	default: p = "not defined"; break;
1127 	}
1128 	CX18_INFO_DEV(sd, "Detected audio standard:   %s\n", p);
1129 	CX18_INFO_DEV(sd, "Audio muted:               %s\n",
1130 		      (mute_ctl & 0x2) ? "yes" : "no");
1131 	CX18_INFO_DEV(sd, "Audio microcontroller:     %s\n",
1132 		      (download_ctl & 0x10) ? "running" : "stopped");
1133 
1134 	switch (audio_config >> 4) {
1135 	case 0x00: p = "undefined"; break;
1136 	case 0x01: p = "BTSC"; break;
1137 	case 0x02: p = "EIAJ"; break;
1138 	case 0x03: p = "A2-M"; break;
1139 	case 0x04: p = "A2-BG"; break;
1140 	case 0x05: p = "A2-DK1"; break;
1141 	case 0x06: p = "A2-DK2"; break;
1142 	case 0x07: p = "A2-DK3"; break;
1143 	case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1144 	case 0x09: p = "AM-L"; break;
1145 	case 0x0a: p = "NICAM-BG"; break;
1146 	case 0x0b: p = "NICAM-DK"; break;
1147 	case 0x0c: p = "NICAM-I"; break;
1148 	case 0x0d: p = "NICAM-L"; break;
1149 	case 0x0e: p = "FM radio"; break;
1150 	case 0x0f: p = "automatic detection"; break;
1151 	default: p = "undefined"; break;
1152 	}
1153 	CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p);
1154 
1155 	if ((audio_config >> 4) < 0xF) {
1156 		switch (audio_config & 0xF) {
1157 		case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1158 		case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1159 		case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1160 		case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1161 		case 0x04: p = "STEREO"; break;
1162 		case 0x05: p = "DUAL1 (AC)"; break;
1163 		case 0x06: p = "DUAL2 (BC)"; break;
1164 		case 0x07: p = "DUAL3 (AB)"; break;
1165 		default: p = "undefined";
1166 		}
1167 		CX18_INFO_DEV(sd, "Configured audio mode:     %s\n", p);
1168 	} else {
1169 		switch (audio_config & 0xF) {
1170 		case 0x00: p = "BG"; break;
1171 		case 0x01: p = "DK1"; break;
1172 		case 0x02: p = "DK2"; break;
1173 		case 0x03: p = "DK3"; break;
1174 		case 0x04: p = "I"; break;
1175 		case 0x05: p = "L"; break;
1176 		case 0x06: p = "BTSC"; break;
1177 		case 0x07: p = "EIAJ"; break;
1178 		case 0x08: p = "A2-M"; break;
1179 		case 0x09: p = "FM Radio (4.5 MHz)"; break;
1180 		case 0x0a: p = "FM Radio (5.5 MHz)"; break;
1181 		case 0x0b: p = "S-Video"; break;
1182 		case 0x0f: p = "automatic standard and mode detection"; break;
1183 		default: p = "undefined"; break;
1184 		}
1185 		CX18_INFO_DEV(sd, "Configured audio system:   %s\n", p);
1186 	}
1187 
1188 	if (aud_input)
1189 		CX18_INFO_DEV(sd, "Specified audio input:     Tuner (In%d)\n",
1190 			      aud_input);
1191 	else
1192 		CX18_INFO_DEV(sd, "Specified audio input:     External\n");
1193 
1194 	switch (pref_mode & 0xf) {
1195 	case 0: p = "mono/language A"; break;
1196 	case 1: p = "language B"; break;
1197 	case 2: p = "language C"; break;
1198 	case 3: p = "analog fallback"; break;
1199 	case 4: p = "stereo"; break;
1200 	case 5: p = "language AC"; break;
1201 	case 6: p = "language BC"; break;
1202 	case 7: p = "language AB"; break;
1203 	default: p = "undefined"; break;
1204 	}
1205 	CX18_INFO_DEV(sd, "Preferred audio mode:      %s\n", p);
1206 
1207 	if ((audio_config & 0xf) == 0xf) {
1208 		switch ((afc0 >> 3) & 0x1) {
1209 		case 0: p = "system DK"; break;
1210 		case 1: p = "system L"; break;
1211 		}
1212 		CX18_INFO_DEV(sd, "Selected 65 MHz format:    %s\n", p);
1213 
1214 		switch (afc0 & 0x7) {
1215 		case 0: p = "Chroma"; break;
1216 		case 1: p = "BTSC"; break;
1217 		case 2: p = "EIAJ"; break;
1218 		case 3: p = "A2-M"; break;
1219 		case 4: p = "autodetect"; break;
1220 		default: p = "undefined"; break;
1221 		}
1222 		CX18_INFO_DEV(sd, "Selected 45 MHz format:    %s\n", p);
1223 	}
1224 }
1225 
cx18_av_log_status(struct v4l2_subdev * sd)1226 static int cx18_av_log_status(struct v4l2_subdev *sd)
1227 {
1228 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1229 	log_video_status(cx);
1230 	log_audio_status(cx);
1231 	return 0;
1232 }
1233 
cx18_av_dbg_match(const struct v4l2_dbg_match * match)1234 static inline int cx18_av_dbg_match(const struct v4l2_dbg_match *match)
1235 {
1236 	return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 1;
1237 }
1238 
cx18_av_g_chip_ident(struct v4l2_subdev * sd,struct v4l2_dbg_chip_ident * chip)1239 static int cx18_av_g_chip_ident(struct v4l2_subdev *sd,
1240 				struct v4l2_dbg_chip_ident *chip)
1241 {
1242 	struct cx18_av_state *state = to_cx18_av_state(sd);
1243 
1244 	if (cx18_av_dbg_match(&chip->match)) {
1245 		chip->ident = state->id;
1246 		chip->revision = state->rev;
1247 	}
1248 	return 0;
1249 }
1250 
1251 #ifdef CONFIG_VIDEO_ADV_DEBUG
cx18_av_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)1252 static int cx18_av_g_register(struct v4l2_subdev *sd,
1253 			      struct v4l2_dbg_register *reg)
1254 {
1255 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1256 
1257 	if (!cx18_av_dbg_match(&reg->match))
1258 		return -EINVAL;
1259 	if ((reg->reg & 0x3) != 0)
1260 		return -EINVAL;
1261 	if (!capable(CAP_SYS_ADMIN))
1262 		return -EPERM;
1263 	reg->size = 4;
1264 	reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
1265 	return 0;
1266 }
1267 
cx18_av_s_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)1268 static int cx18_av_s_register(struct v4l2_subdev *sd,
1269 			      struct v4l2_dbg_register *reg)
1270 {
1271 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1272 
1273 	if (!cx18_av_dbg_match(&reg->match))
1274 		return -EINVAL;
1275 	if ((reg->reg & 0x3) != 0)
1276 		return -EINVAL;
1277 	if (!capable(CAP_SYS_ADMIN))
1278 		return -EPERM;
1279 	cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val);
1280 	return 0;
1281 }
1282 #endif
1283 
1284 static const struct v4l2_ctrl_ops cx18_av_ctrl_ops = {
1285 	.s_ctrl = cx18_av_s_ctrl,
1286 };
1287 
1288 static const struct v4l2_subdev_core_ops cx18_av_general_ops = {
1289 	.g_chip_ident = cx18_av_g_chip_ident,
1290 	.log_status = cx18_av_log_status,
1291 	.load_fw = cx18_av_load_fw,
1292 	.reset = cx18_av_reset,
1293 	.g_ctrl = v4l2_subdev_g_ctrl,
1294 	.s_ctrl = v4l2_subdev_s_ctrl,
1295 	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1296 	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1297 	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1298 	.queryctrl = v4l2_subdev_queryctrl,
1299 	.querymenu = v4l2_subdev_querymenu,
1300 	.s_std = cx18_av_s_std,
1301 #ifdef CONFIG_VIDEO_ADV_DEBUG
1302 	.g_register = cx18_av_g_register,
1303 	.s_register = cx18_av_s_register,
1304 #endif
1305 };
1306 
1307 static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = {
1308 	.s_radio = cx18_av_s_radio,
1309 	.s_frequency = cx18_av_s_frequency,
1310 	.g_tuner = cx18_av_g_tuner,
1311 	.s_tuner = cx18_av_s_tuner,
1312 };
1313 
1314 static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = {
1315 	.s_clock_freq = cx18_av_s_clock_freq,
1316 	.s_routing = cx18_av_s_audio_routing,
1317 };
1318 
1319 static const struct v4l2_subdev_video_ops cx18_av_video_ops = {
1320 	.s_routing = cx18_av_s_video_routing,
1321 	.s_stream = cx18_av_s_stream,
1322 	.s_mbus_fmt = cx18_av_s_mbus_fmt,
1323 };
1324 
1325 static const struct v4l2_subdev_vbi_ops cx18_av_vbi_ops = {
1326 	.decode_vbi_line = cx18_av_decode_vbi_line,
1327 	.g_sliced_fmt = cx18_av_g_sliced_fmt,
1328 	.s_sliced_fmt = cx18_av_s_sliced_fmt,
1329 	.s_raw_fmt = cx18_av_s_raw_fmt,
1330 };
1331 
1332 static const struct v4l2_subdev_ops cx18_av_ops = {
1333 	.core = &cx18_av_general_ops,
1334 	.tuner = &cx18_av_tuner_ops,
1335 	.audio = &cx18_av_audio_ops,
1336 	.video = &cx18_av_video_ops,
1337 	.vbi = &cx18_av_vbi_ops,
1338 };
1339 
cx18_av_probe(struct cx18 * cx)1340 int cx18_av_probe(struct cx18 *cx)
1341 {
1342 	struct cx18_av_state *state = &cx->av_state;
1343 	struct v4l2_subdev *sd;
1344 	int err;
1345 
1346 	state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff;
1347 	state->id = ((state->rev >> 4) == CXADEC_CHIP_TYPE_MAKO)
1348 		    ? V4L2_IDENT_CX23418_843 : V4L2_IDENT_UNKNOWN;
1349 
1350 	state->vid_input = CX18_AV_COMPOSITE7;
1351 	state->aud_input = CX18_AV_AUDIO8;
1352 	state->audclk_freq = 48000;
1353 	state->audmode = V4L2_TUNER_MODE_LANG1;
1354 	state->slicer_line_delay = 0;
1355 	state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
1356 
1357 	sd = &state->sd;
1358 	v4l2_subdev_init(sd, &cx18_av_ops);
1359 	v4l2_set_subdevdata(sd, cx);
1360 	snprintf(sd->name, sizeof(sd->name),
1361 		 "%s %03x", cx->v4l2_dev.name, (state->rev >> 4));
1362 	sd->grp_id = CX18_HW_418_AV;
1363 	v4l2_ctrl_handler_init(&state->hdl, 9);
1364 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
1365 			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1366 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
1367 			V4L2_CID_CONTRAST, 0, 127, 1, 64);
1368 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
1369 			V4L2_CID_SATURATION, 0, 127, 1, 64);
1370 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
1371 			V4L2_CID_HUE, -128, 127, 1, 0);
1372 
1373 	state->volume = v4l2_ctrl_new_std(&state->hdl,
1374 			&cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
1375 			0, 65535, 65535 / 100, 0);
1376 	v4l2_ctrl_new_std(&state->hdl,
1377 			&cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE,
1378 			0, 1, 1, 0);
1379 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
1380 			V4L2_CID_AUDIO_BALANCE,
1381 			0, 65535, 65535 / 100, 32768);
1382 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
1383 			V4L2_CID_AUDIO_BASS,
1384 			0, 65535, 65535 / 100, 32768);
1385 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
1386 			V4L2_CID_AUDIO_TREBLE,
1387 			0, 65535, 65535 / 100, 32768);
1388 	sd->ctrl_handler = &state->hdl;
1389 	if (state->hdl.error) {
1390 		int err = state->hdl.error;
1391 
1392 		v4l2_ctrl_handler_free(&state->hdl);
1393 		return err;
1394 	}
1395 	err = v4l2_device_register_subdev(&cx->v4l2_dev, sd);
1396 	if (err)
1397 		v4l2_ctrl_handler_free(&state->hdl);
1398 	else
1399 		cx18_av_init(cx);
1400 	return err;
1401 }
1402