1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_SRXX_DEFS_H__ 29 #define __CVMX_SRXX_DEFS_H__ 30 31 #define CVMX_SRXX_COM_CTL(block_id) \ 32 CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull)) 33 #define CVMX_SRXX_IGN_RX_FULL(block_id) \ 34 CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull)) 35 #define CVMX_SRXX_SPI4_CALX(offset, block_id) \ 36 CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) 37 #define CVMX_SRXX_SPI4_STAT(block_id) \ 38 CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull)) 39 #define CVMX_SRXX_SW_TICK_CTL(block_id) \ 40 CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull)) 41 #define CVMX_SRXX_SW_TICK_DAT(block_id) \ 42 CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull)) 43 44 union cvmx_srxx_com_ctl { 45 uint64_t u64; 46 struct cvmx_srxx_com_ctl_s { 47 uint64_t reserved_8_63:56; 48 uint64_t prts:4; 49 uint64_t st_en:1; 50 uint64_t reserved_1_2:2; 51 uint64_t inf_en:1; 52 } s; 53 struct cvmx_srxx_com_ctl_s cn38xx; 54 struct cvmx_srxx_com_ctl_s cn38xxp2; 55 struct cvmx_srxx_com_ctl_s cn58xx; 56 struct cvmx_srxx_com_ctl_s cn58xxp1; 57 }; 58 59 union cvmx_srxx_ign_rx_full { 60 uint64_t u64; 61 struct cvmx_srxx_ign_rx_full_s { 62 uint64_t reserved_16_63:48; 63 uint64_t ignore:16; 64 } s; 65 struct cvmx_srxx_ign_rx_full_s cn38xx; 66 struct cvmx_srxx_ign_rx_full_s cn38xxp2; 67 struct cvmx_srxx_ign_rx_full_s cn58xx; 68 struct cvmx_srxx_ign_rx_full_s cn58xxp1; 69 }; 70 71 union cvmx_srxx_spi4_calx { 72 uint64_t u64; 73 struct cvmx_srxx_spi4_calx_s { 74 uint64_t reserved_17_63:47; 75 uint64_t oddpar:1; 76 uint64_t prt3:4; 77 uint64_t prt2:4; 78 uint64_t prt1:4; 79 uint64_t prt0:4; 80 } s; 81 struct cvmx_srxx_spi4_calx_s cn38xx; 82 struct cvmx_srxx_spi4_calx_s cn38xxp2; 83 struct cvmx_srxx_spi4_calx_s cn58xx; 84 struct cvmx_srxx_spi4_calx_s cn58xxp1; 85 }; 86 87 union cvmx_srxx_spi4_stat { 88 uint64_t u64; 89 struct cvmx_srxx_spi4_stat_s { 90 uint64_t reserved_16_63:48; 91 uint64_t m:8; 92 uint64_t reserved_7_7:1; 93 uint64_t len:7; 94 } s; 95 struct cvmx_srxx_spi4_stat_s cn38xx; 96 struct cvmx_srxx_spi4_stat_s cn38xxp2; 97 struct cvmx_srxx_spi4_stat_s cn58xx; 98 struct cvmx_srxx_spi4_stat_s cn58xxp1; 99 }; 100 101 union cvmx_srxx_sw_tick_ctl { 102 uint64_t u64; 103 struct cvmx_srxx_sw_tick_ctl_s { 104 uint64_t reserved_14_63:50; 105 uint64_t eop:1; 106 uint64_t sop:1; 107 uint64_t mod:4; 108 uint64_t opc:4; 109 uint64_t adr:4; 110 } s; 111 struct cvmx_srxx_sw_tick_ctl_s cn38xx; 112 struct cvmx_srxx_sw_tick_ctl_s cn58xx; 113 struct cvmx_srxx_sw_tick_ctl_s cn58xxp1; 114 }; 115 116 union cvmx_srxx_sw_tick_dat { 117 uint64_t u64; 118 struct cvmx_srxx_sw_tick_dat_s { 119 uint64_t dat:64; 120 } s; 121 struct cvmx_srxx_sw_tick_dat_s cn38xx; 122 struct cvmx_srxx_sw_tick_dat_s cn58xx; 123 struct cvmx_srxx_sw_tick_dat_s cn58xxp1; 124 }; 125 126 #endif 127