1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Components shared between ASoC and HDA CS35L56 drivers
4 //
5 // Copyright (C) 2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <linux/regmap.h>
9 #include <linux/regulator/consumer.h>
10 #include <linux/types.h>
11
12 #include "cs35l56.h"
13
14 static const struct reg_sequence cs35l56_patch[] = {
15 /* These are not reset by a soft-reset, so patch to defaults. */
16 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
17 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
18 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
19 };
20
cs35l56_set_patch(struct cs35l56_base * cs35l56_base)21 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
22 {
23 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
24 ARRAY_SIZE(cs35l56_patch));
25 }
26 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED);
27
28 static const struct reg_default cs35l56_reg_defaults[] = {
29 { CS35L56_ASP1_ENABLES1, 0x00000000 },
30 { CS35L56_ASP1_CONTROL1, 0x00000028 },
31 { CS35L56_ASP1_CONTROL2, 0x18180200 },
32 { CS35L56_ASP1_CONTROL3, 0x00000002 },
33 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
34 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
35 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
36 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
37
38 /* no defaults for ASP1TX mixer */
39
40 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
41 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
42 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
43 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
44 { CS35L56_IRQ1_CFG, 0x00000000 },
45 { CS35L56_IRQ1_MASK_1, 0x83ffffff },
46 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
47 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
48 { CS35L56_IRQ1_MASK_8, 0xfc000fff },
49 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
50 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
51 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
52 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
53 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
54 };
55
cs35l56_is_dsp_memory(unsigned int reg)56 static bool cs35l56_is_dsp_memory(unsigned int reg)
57 {
58 switch (reg) {
59 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
60 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
61 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
62 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
63 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
64 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
65 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
66 return true;
67 default:
68 return false;
69 }
70 }
71
cs35l56_readable_reg(struct device * dev,unsigned int reg)72 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
73 {
74 switch (reg) {
75 case CS35L56_DEVID:
76 case CS35L56_REVID:
77 case CS35L56_RELID:
78 case CS35L56_OTPID:
79 case CS35L56_SFT_RESET:
80 case CS35L56_GLOBAL_ENABLES:
81 case CS35L56_BLOCK_ENABLES:
82 case CS35L56_BLOCK_ENABLES2:
83 case CS35L56_REFCLK_INPUT:
84 case CS35L56_GLOBAL_SAMPLE_RATE:
85 case CS35L56_ASP1_ENABLES1:
86 case CS35L56_ASP1_CONTROL1:
87 case CS35L56_ASP1_CONTROL2:
88 case CS35L56_ASP1_CONTROL3:
89 case CS35L56_ASP1_FRAME_CONTROL1:
90 case CS35L56_ASP1_FRAME_CONTROL5:
91 case CS35L56_ASP1_DATA_CONTROL1:
92 case CS35L56_ASP1_DATA_CONTROL5:
93 case CS35L56_DACPCM1_INPUT:
94 case CS35L56_DACPCM2_INPUT:
95 case CS35L56_ASP1TX1_INPUT:
96 case CS35L56_ASP1TX2_INPUT:
97 case CS35L56_ASP1TX3_INPUT:
98 case CS35L56_ASP1TX4_INPUT:
99 case CS35L56_DSP1RX1_INPUT:
100 case CS35L56_DSP1RX2_INPUT:
101 case CS35L56_SWIRE_DP3_CH1_INPUT:
102 case CS35L56_SWIRE_DP3_CH2_INPUT:
103 case CS35L56_SWIRE_DP3_CH3_INPUT:
104 case CS35L56_SWIRE_DP3_CH4_INPUT:
105 case CS35L56_IRQ1_CFG:
106 case CS35L56_IRQ1_STATUS:
107 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
108 case CS35L56_IRQ1_EINT_18:
109 case CS35L56_IRQ1_EINT_20:
110 case CS35L56_IRQ1_MASK_1:
111 case CS35L56_IRQ1_MASK_2:
112 case CS35L56_IRQ1_MASK_4:
113 case CS35L56_IRQ1_MASK_8:
114 case CS35L56_IRQ1_MASK_18:
115 case CS35L56_IRQ1_MASK_20:
116 case CS35L56_DSP_VIRTUAL1_MBOX_1:
117 case CS35L56_DSP_VIRTUAL1_MBOX_2:
118 case CS35L56_DSP_VIRTUAL1_MBOX_3:
119 case CS35L56_DSP_VIRTUAL1_MBOX_4:
120 case CS35L56_DSP_VIRTUAL1_MBOX_5:
121 case CS35L56_DSP_VIRTUAL1_MBOX_6:
122 case CS35L56_DSP_VIRTUAL1_MBOX_7:
123 case CS35L56_DSP_VIRTUAL1_MBOX_8:
124 case CS35L56_DSP_RESTRICT_STS1:
125 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
126 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
127 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
128 case CS35L56_DSP1_SCRATCH1:
129 case CS35L56_DSP1_SCRATCH2:
130 case CS35L56_DSP1_SCRATCH3:
131 case CS35L56_DSP1_SCRATCH4:
132 return true;
133 default:
134 return cs35l56_is_dsp_memory(reg);
135 }
136 }
137
cs35l56_precious_reg(struct device * dev,unsigned int reg)138 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
139 {
140 switch (reg) {
141 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
142 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
143 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
144 return true;
145 default:
146 return false;
147 }
148 }
149
cs35l56_volatile_reg(struct device * dev,unsigned int reg)150 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
151 {
152 switch (reg) {
153 case CS35L56_DEVID:
154 case CS35L56_REVID:
155 case CS35L56_RELID:
156 case CS35L56_OTPID:
157 case CS35L56_SFT_RESET:
158 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
159 case CS35L56_BLOCK_ENABLES: /* owned by firmware */
160 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
161 case CS35L56_REFCLK_INPUT: /* owned by firmware */
162 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
163 case CS35L56_DACPCM1_INPUT: /* owned by firmware */
164 case CS35L56_DACPCM2_INPUT: /* owned by firmware */
165 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
166 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
167 case CS35L56_IRQ1_STATUS:
168 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
169 case CS35L56_IRQ1_EINT_18:
170 case CS35L56_IRQ1_EINT_20:
171 case CS35L56_DSP_VIRTUAL1_MBOX_1:
172 case CS35L56_DSP_VIRTUAL1_MBOX_2:
173 case CS35L56_DSP_VIRTUAL1_MBOX_3:
174 case CS35L56_DSP_VIRTUAL1_MBOX_4:
175 case CS35L56_DSP_VIRTUAL1_MBOX_5:
176 case CS35L56_DSP_VIRTUAL1_MBOX_6:
177 case CS35L56_DSP_VIRTUAL1_MBOX_7:
178 case CS35L56_DSP_VIRTUAL1_MBOX_8:
179 case CS35L56_DSP_RESTRICT_STS1:
180 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
181 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
182 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
183 case CS35L56_DSP1_SCRATCH1:
184 case CS35L56_DSP1_SCRATCH2:
185 case CS35L56_DSP1_SCRATCH3:
186 case CS35L56_DSP1_SCRATCH4:
187 return true;
188 case CS35L56_MAIN_RENDER_USER_MUTE:
189 case CS35L56_MAIN_RENDER_USER_VOLUME:
190 case CS35L56_MAIN_POSTURE_NUMBER:
191 return false;
192 default:
193 return cs35l56_is_dsp_memory(reg);
194 }
195 }
196
cs35l56_mbox_send(struct cs35l56_base * cs35l56_base,unsigned int command)197 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
198 {
199 unsigned int val;
200 int ret;
201
202 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
203 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
204 val, (val == 0),
205 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
206 if (ret) {
207 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
208 return ret;
209 }
210
211 return 0;
212 }
213 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED);
214
cs35l56_firmware_shutdown(struct cs35l56_base * cs35l56_base)215 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
216 {
217 int ret;
218 unsigned int reg;
219 unsigned int val;
220
221 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
222 if (ret)
223 return ret;
224
225 if (cs35l56_base->rev < CS35L56_REVID_B0)
226 reg = CS35L56_DSP1_PM_CUR_STATE_A1;
227 else
228 reg = CS35L56_DSP1_PM_CUR_STATE;
229
230 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg,
231 val, (val == CS35L56_HALO_STATE_SHUTDOWN),
232 CS35L56_HALO_STATE_POLL_US,
233 CS35L56_HALO_STATE_TIMEOUT_US);
234 if (ret < 0)
235 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
236 val, ret);
237 return ret;
238 }
239 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED);
240
cs35l56_wait_for_firmware_boot(struct cs35l56_base * cs35l56_base)241 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
242 {
243 unsigned int reg;
244 unsigned int val;
245 int read_ret, poll_ret;
246
247 if (cs35l56_base->rev < CS35L56_REVID_B0)
248 reg = CS35L56_DSP1_HALO_STATE_A1;
249 else
250 reg = CS35L56_DSP1_HALO_STATE;
251
252 /*
253 * This can't be a regmap_read_poll_timeout() because cs35l56 will NAK
254 * I2C until it has booted which would terminate the poll
255 */
256 poll_ret = read_poll_timeout(regmap_read, read_ret,
257 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
258 CS35L56_HALO_STATE_POLL_US,
259 CS35L56_HALO_STATE_TIMEOUT_US,
260 false,
261 cs35l56_base->regmap, reg, &val);
262
263 if (poll_ret) {
264 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
265 read_ret, val);
266 return -EIO;
267 }
268
269 return 0;
270 }
271 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED);
272
cs35l56_wait_control_port_ready(void)273 void cs35l56_wait_control_port_ready(void)
274 {
275 /* Wait for control port to be ready (datasheet tIRS). */
276 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
277 }
278 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED);
279
cs35l56_wait_min_reset_pulse(void)280 void cs35l56_wait_min_reset_pulse(void)
281 {
282 /* Satisfy minimum reset pulse width spec */
283 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
284 }
285 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED);
286
287 static const struct reg_sequence cs35l56_system_reset_seq[] = {
288 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
289 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
290 };
291
cs35l56_system_reset(struct cs35l56_base * cs35l56_base,bool is_soundwire)292 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
293 {
294 /*
295 * Must enter cache-only first so there can't be any more register
296 * accesses other than the controlled system reset sequence below.
297 */
298 regcache_cache_only(cs35l56_base->regmap, true);
299 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
300 cs35l56_system_reset_seq,
301 ARRAY_SIZE(cs35l56_system_reset_seq));
302
303 /* On SoundWire the registers won't be accessible until it re-enumerates. */
304 if (is_soundwire)
305 return;
306
307 cs35l56_wait_control_port_ready();
308 regcache_cache_only(cs35l56_base->regmap, false);
309 }
310 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED);
311
cs35l56_irq_request(struct cs35l56_base * cs35l56_base,int irq)312 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
313 {
314 int ret;
315
316 if (!irq)
317 return 0;
318
319 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
320 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
321 "cs35l56", cs35l56_base);
322 if (!ret)
323 cs35l56_base->irq = irq;
324 else
325 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
326
327 return ret;
328 }
329 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED);
330
cs35l56_irq(int irq,void * data)331 irqreturn_t cs35l56_irq(int irq, void *data)
332 {
333 struct cs35l56_base *cs35l56_base = data;
334 unsigned int status1 = 0, status8 = 0, status20 = 0;
335 unsigned int mask1, mask8, mask20;
336 unsigned int val;
337 int rv;
338
339 irqreturn_t ret = IRQ_NONE;
340
341 if (!cs35l56_base->init_done)
342 return IRQ_NONE;
343
344 mutex_lock(&cs35l56_base->irq_lock);
345
346 rv = pm_runtime_resume_and_get(cs35l56_base->dev);
347 if (rv < 0) {
348 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
349 goto err_unlock;
350 }
351
352 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
353 if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
354 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
355 goto err;
356 }
357
358 /* Ack interrupts */
359 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
360 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
361 status1 &= ~mask1;
362 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
363
364 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
365 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
366 status8 &= ~mask8;
367 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
368
369 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
370 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
371 status20 &= ~mask20;
372 /* We don't want EINT20 but they default to unmasked: force mask */
373 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
374
375 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
376
377 /* Check to see if unmasked bits are active */
378 if (!status1 && !status8 && !status20)
379 goto err;
380
381 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
382 dev_crit(cs35l56_base->dev, "Amp short error\n");
383
384 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
385 dev_crit(cs35l56_base->dev, "Overtemp error\n");
386
387 ret = IRQ_HANDLED;
388
389 err:
390 pm_runtime_put(cs35l56_base->dev);
391 err_unlock:
392 mutex_unlock(&cs35l56_base->irq_lock);
393
394 return ret;
395 }
396 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED);
397
cs35l56_is_fw_reload_needed(struct cs35l56_base * cs35l56_base)398 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
399 {
400 unsigned int val;
401 int ret;
402
403 /* Nothing to re-patch if we haven't done any patching yet. */
404 if (!cs35l56_base->fw_patched)
405 return false;
406
407 /*
408 * If we have control of RESET we will have asserted it so the firmware
409 * will need re-patching.
410 */
411 if (cs35l56_base->reset_gpio)
412 return true;
413
414 /*
415 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
416 * can't be used here to test for memory retention.
417 * Assume that tuning must be re-loaded.
418 */
419 if (cs35l56_base->secured)
420 return true;
421
422 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
423 if (ret) {
424 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
425 return ret;
426 }
427
428 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val);
429 if (ret)
430 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
431 else
432 ret = !!(val & CS35L56_FIRMWARE_MISSING);
433
434 pm_runtime_put_autosuspend(cs35l56_base->dev);
435
436 return ret;
437 }
438 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED);
439
440 static const struct reg_sequence cs35l56_hibernate_seq[] = {
441 /* This must be the last register access */
442 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW),
443 };
444
445 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
446 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
447 };
448
cs35l56_runtime_suspend_common(struct cs35l56_base * cs35l56_base)449 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
450 {
451 unsigned int val;
452 int ret;
453
454 if (!cs35l56_base->init_done)
455 return 0;
456
457 /* Firmware must have entered a power-save state */
458 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
459 CS35L56_TRANSDUCER_ACTUAL_PS,
460 val, (val >= CS35L56_PS3),
461 CS35L56_PS3_POLL_US,
462 CS35L56_PS3_TIMEOUT_US);
463 if (ret)
464 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
465
466 /* Clear BOOT_DONE so it can be used to detect a reboot */
467 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
468
469 if (!cs35l56_base->can_hibernate) {
470 regcache_cache_only(cs35l56_base->regmap, true);
471 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
472
473 return 0;
474 }
475
476 /*
477 * Enable auto-hibernate. If it is woken by some other wake source
478 * it will automatically return to hibernate.
479 */
480 cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE);
481
482 /*
483 * Must enter cache-only first so there can't be any more register
484 * accesses other than the controlled hibernate sequence below.
485 */
486 regcache_cache_only(cs35l56_base->regmap, true);
487
488 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
489 cs35l56_hibernate_seq,
490 ARRAY_SIZE(cs35l56_hibernate_seq));
491
492 dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
493
494 return 0;
495 }
496 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED);
497
cs35l56_runtime_resume_common(struct cs35l56_base * cs35l56_base,bool is_soundwire)498 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
499 {
500 unsigned int val;
501 int ret;
502
503 if (!cs35l56_base->init_done)
504 return 0;
505
506 if (!cs35l56_base->can_hibernate)
507 goto out_sync;
508
509 if (!is_soundwire) {
510 /*
511 * Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C.
512 * Must be done before releasing cache-only.
513 */
514 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
515 cs35l56_hibernate_wake_seq,
516 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
517
518 cs35l56_wait_control_port_ready();
519 }
520
521 out_sync:
522 regcache_cache_only(cs35l56_base->regmap, false);
523
524 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
525 if (ret) {
526 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
527 goto err;
528 }
529
530 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
531 if (ret)
532 goto err;
533
534 /* BOOT_DONE will be 1 if the amp reset */
535 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
536 if (val & CS35L56_OTP_BOOT_DONE_MASK) {
537 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
538 regcache_mark_dirty(cs35l56_base->regmap);
539 }
540
541 regcache_sync(cs35l56_base->regmap);
542
543 dev_dbg(cs35l56_base->dev, "Resumed");
544
545 return 0;
546
547 err:
548 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
549 CS35L56_MBOX_CMD_HIBERNATE_NOW);
550
551 regcache_cache_only(cs35l56_base->regmap, true);
552
553 return ret;
554 }
555 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED);
556
557 static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
558 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
559 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
560 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
561 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
562 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
563 };
564
cs35l56_init_cs_dsp(struct cs35l56_base * cs35l56_base,struct cs_dsp * cs_dsp)565 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
566 {
567 cs_dsp->num = 1;
568 cs_dsp->type = WMFW_HALO;
569 cs_dsp->rev = 0;
570 cs_dsp->dev = cs35l56_base->dev;
571 cs_dsp->regmap = cs35l56_base->regmap;
572 cs_dsp->base = CS35L56_DSP1_CORE_BASE;
573 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
574 cs_dsp->mem = cs35l56_dsp1_regions;
575 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
576 cs_dsp->no_core_startstop = true;
577 }
578 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED);
579
cs35l56_hw_init(struct cs35l56_base * cs35l56_base)580 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
581 {
582 int ret;
583 unsigned int devid, revid, otpid, secured;
584
585 /*
586 * If the system is not using a reset_gpio then issue a
587 * dummy read to force a wakeup.
588 */
589 if (!cs35l56_base->reset_gpio)
590 regmap_read(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid);
591
592 cs35l56_wait_control_port_ready();
593
594 /*
595 * The HALO_STATE register is in different locations on Ax and B0
596 * devices so the REVID needs to be determined before waiting for the
597 * firmware to boot.
598 */
599 ret = regmap_read(cs35l56_base->regmap, CS35L56_REVID, &revid);
600 if (ret < 0) {
601 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
602 return ret;
603 }
604 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
605
606 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
607 if (ret)
608 return ret;
609
610 ret = regmap_read(cs35l56_base->regmap, CS35L56_DEVID, &devid);
611 if (ret < 0) {
612 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
613 return ret;
614 }
615 devid &= CS35L56_DEVID_MASK;
616
617 switch (devid) {
618 case 0x35A56:
619 break;
620 default:
621 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
622 return ret;
623 }
624
625 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
626 if (ret) {
627 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
628 return ret;
629 }
630
631 /* When any bus is restricted treat the device as secured */
632 if (secured & CS35L56_RESTRICTED_MASK)
633 cs35l56_base->secured = true;
634
635 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
636 if (ret < 0) {
637 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
638 return ret;
639 }
640
641 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n",
642 cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid);
643
644 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
645 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
646 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
647 CS35L56_AMP_SHORT_ERR_EINT1_MASK,
648 0);
649 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
650 CS35L56_TEMP_ERR_EINT1_MASK,
651 0);
652
653 return 0;
654 }
655 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED);
656
657 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
658 [0x0C] = 128000,
659 [0x0F] = 256000,
660 [0x11] = 384000,
661 [0x12] = 512000,
662 [0x15] = 768000,
663 [0x17] = 1024000,
664 [0x1A] = 1500000,
665 [0x1B] = 1536000,
666 [0x1C] = 2000000,
667 [0x1D] = 2048000,
668 [0x1E] = 2400000,
669 [0x20] = 3000000,
670 [0x21] = 3072000,
671 [0x23] = 4000000,
672 [0x24] = 4096000,
673 [0x25] = 4800000,
674 [0x27] = 6000000,
675 [0x28] = 6144000,
676 [0x29] = 6250000,
677 [0x2A] = 6400000,
678 [0x2E] = 8000000,
679 [0x2F] = 8192000,
680 [0x30] = 9600000,
681 [0x32] = 12000000,
682 [0x33] = 12288000,
683 [0x37] = 13500000,
684 [0x38] = 19200000,
685 [0x39] = 22579200,
686 [0x3B] = 24576000,
687 };
688
cs35l56_get_bclk_freq_id(unsigned int freq)689 int cs35l56_get_bclk_freq_id(unsigned int freq)
690 {
691 int i;
692
693 if (freq == 0)
694 return -EINVAL;
695
696 /* The BCLK frequency must be a valid PLL REFCLK */
697 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
698 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
699 return i;
700 }
701
702 return -EINVAL;
703 }
704 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
705
706 static const char * const cs35l56_supplies[/* auto-sized */] = {
707 "VDD_P",
708 "VDD_IO",
709 "VDD_A",
710 };
711
cs35l56_fill_supply_names(struct regulator_bulk_data * data)712 void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
713 {
714 int i;
715
716 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
717 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
718 data[i].supply = cs35l56_supplies[i];
719 }
720 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
721
722 const char * const cs35l56_tx_input_texts[] = {
723 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
724 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
725 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
726 "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
727 };
728 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
729
730 const unsigned int cs35l56_tx_input_values[] = {
731 CS35L56_INPUT_SRC_NONE,
732 CS35L56_INPUT_SRC_ASP1RX1,
733 CS35L56_INPUT_SRC_ASP1RX2,
734 CS35L56_INPUT_SRC_VMON,
735 CS35L56_INPUT_SRC_IMON,
736 CS35L56_INPUT_SRC_ERR_VOL,
737 CS35L56_INPUT_SRC_CLASSH,
738 CS35L56_INPUT_SRC_VDDBMON,
739 CS35L56_INPUT_SRC_VBSTMON,
740 CS35L56_INPUT_SRC_DSP1TX1,
741 CS35L56_INPUT_SRC_DSP1TX2,
742 CS35L56_INPUT_SRC_DSP1TX3,
743 CS35L56_INPUT_SRC_DSP1TX4,
744 CS35L56_INPUT_SRC_DSP1TX5,
745 CS35L56_INPUT_SRC_DSP1TX6,
746 CS35L56_INPUT_SRC_DSP1TX7,
747 CS35L56_INPUT_SRC_DSP1TX8,
748 CS35L56_INPUT_SRC_TEMPMON,
749 CS35L56_INPUT_SRC_INTERPOLATOR,
750 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
751 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
752 };
753 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
754
755 struct regmap_config cs35l56_regmap_i2c = {
756 .reg_bits = 32,
757 .val_bits = 32,
758 .reg_stride = 4,
759 .reg_format_endian = REGMAP_ENDIAN_BIG,
760 .val_format_endian = REGMAP_ENDIAN_BIG,
761 .max_register = CS35L56_DSP1_PMEM_5114,
762 .reg_defaults = cs35l56_reg_defaults,
763 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
764 .volatile_reg = cs35l56_volatile_reg,
765 .readable_reg = cs35l56_readable_reg,
766 .precious_reg = cs35l56_precious_reg,
767 .cache_type = REGCACHE_MAPLE,
768 };
769 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
770
771 struct regmap_config cs35l56_regmap_spi = {
772 .reg_bits = 32,
773 .val_bits = 32,
774 .pad_bits = 16,
775 .reg_stride = 4,
776 .reg_format_endian = REGMAP_ENDIAN_BIG,
777 .val_format_endian = REGMAP_ENDIAN_BIG,
778 .max_register = CS35L56_DSP1_PMEM_5114,
779 .reg_defaults = cs35l56_reg_defaults,
780 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
781 .volatile_reg = cs35l56_volatile_reg,
782 .readable_reg = cs35l56_readable_reg,
783 .precious_reg = cs35l56_precious_reg,
784 .cache_type = REGCACHE_MAPLE,
785 };
786 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
787
788 struct regmap_config cs35l56_regmap_sdw = {
789 .reg_bits = 32,
790 .val_bits = 32,
791 .reg_stride = 4,
792 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
793 .val_format_endian = REGMAP_ENDIAN_BIG,
794 .max_register = CS35L56_DSP1_PMEM_5114,
795 .reg_defaults = cs35l56_reg_defaults,
796 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
797 .volatile_reg = cs35l56_volatile_reg,
798 .readable_reg = cs35l56_readable_reg,
799 .precious_reg = cs35l56_precious_reg,
800 .cache_type = REGCACHE_MAPLE,
801 };
802 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
803
804 MODULE_DESCRIPTION("ASoC CS35L56 Shared");
805 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
806 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
807 MODULE_LICENSE("GPL");
808