1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Record and handle CPU attributes.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7 #include <asm/arch_timer.h>
8 #include <asm/cache.h>
9 #include <asm/cpu.h>
10 #include <asm/cputype.h>
11 #include <asm/cpufeature.h>
12 #include <asm/fpsimd.h>
13
14 #include <linux/bitops.h>
15 #include <linux/bug.h>
16 #include <linux/compat.h>
17 #include <linux/elf.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/personality.h>
21 #include <linux/preempt.h>
22 #include <linux/printk.h>
23 #include <linux/seq_file.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/delay.h>
27
28 /*
29 * In case the boot CPU is hotpluggable, we record its initial state and
30 * current state separately. Certain system registers may contain different
31 * values depending on configuration at or after reset.
32 */
33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
34 static struct cpuinfo_arm64 boot_cpu_data;
35
icache_policy_str(int l1ip)36 static inline const char *icache_policy_str(int l1ip)
37 {
38 switch (l1ip) {
39 case CTR_EL0_L1Ip_VPIPT:
40 return "VPIPT";
41 case CTR_EL0_L1Ip_VIPT:
42 return "VIPT";
43 case CTR_EL0_L1Ip_PIPT:
44 return "PIPT";
45 default:
46 return "RESERVED/UNKNOWN";
47 }
48 }
49
50 unsigned long __icache_flags;
51
52 static const char *const hwcap_str[] = {
53 [KERNEL_HWCAP_FP] = "fp",
54 [KERNEL_HWCAP_ASIMD] = "asimd",
55 [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
56 [KERNEL_HWCAP_AES] = "aes",
57 [KERNEL_HWCAP_PMULL] = "pmull",
58 [KERNEL_HWCAP_SHA1] = "sha1",
59 [KERNEL_HWCAP_SHA2] = "sha2",
60 [KERNEL_HWCAP_CRC32] = "crc32",
61 [KERNEL_HWCAP_ATOMICS] = "atomics",
62 [KERNEL_HWCAP_FPHP] = "fphp",
63 [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
64 [KERNEL_HWCAP_CPUID] = "cpuid",
65 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
66 [KERNEL_HWCAP_JSCVT] = "jscvt",
67 [KERNEL_HWCAP_FCMA] = "fcma",
68 [KERNEL_HWCAP_LRCPC] = "lrcpc",
69 [KERNEL_HWCAP_DCPOP] = "dcpop",
70 [KERNEL_HWCAP_SHA3] = "sha3",
71 [KERNEL_HWCAP_SM3] = "sm3",
72 [KERNEL_HWCAP_SM4] = "sm4",
73 [KERNEL_HWCAP_ASIMDDP] = "asimddp",
74 [KERNEL_HWCAP_SHA512] = "sha512",
75 [KERNEL_HWCAP_SVE] = "sve",
76 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
77 [KERNEL_HWCAP_DIT] = "dit",
78 [KERNEL_HWCAP_USCAT] = "uscat",
79 [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
80 [KERNEL_HWCAP_FLAGM] = "flagm",
81 [KERNEL_HWCAP_SSBS] = "ssbs",
82 [KERNEL_HWCAP_SB] = "sb",
83 [KERNEL_HWCAP_PACA] = "paca",
84 [KERNEL_HWCAP_PACG] = "pacg",
85 [KERNEL_HWCAP_DCPODP] = "dcpodp",
86 [KERNEL_HWCAP_SVE2] = "sve2",
87 [KERNEL_HWCAP_SVEAES] = "sveaes",
88 [KERNEL_HWCAP_SVEPMULL] = "svepmull",
89 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
90 [KERNEL_HWCAP_SVESHA3] = "svesha3",
91 [KERNEL_HWCAP_SVESM4] = "svesm4",
92 [KERNEL_HWCAP_FLAGM2] = "flagm2",
93 [KERNEL_HWCAP_FRINT] = "frint",
94 [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
95 [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
96 [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
97 [KERNEL_HWCAP_SVEBF16] = "svebf16",
98 [KERNEL_HWCAP_I8MM] = "i8mm",
99 [KERNEL_HWCAP_BF16] = "bf16",
100 [KERNEL_HWCAP_DGH] = "dgh",
101 [KERNEL_HWCAP_RNG] = "rng",
102 [KERNEL_HWCAP_BTI] = "bti",
103 [KERNEL_HWCAP_MTE] = "mte",
104 [KERNEL_HWCAP_ECV] = "ecv",
105 [KERNEL_HWCAP_AFP] = "afp",
106 [KERNEL_HWCAP_RPRES] = "rpres",
107 [KERNEL_HWCAP_MTE3] = "mte3",
108 [KERNEL_HWCAP_SME] = "sme",
109 [KERNEL_HWCAP_SME_I16I64] = "smei16i64",
110 [KERNEL_HWCAP_SME_F64F64] = "smef64f64",
111 [KERNEL_HWCAP_SME_I8I32] = "smei8i32",
112 [KERNEL_HWCAP_SME_F16F32] = "smef16f32",
113 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32",
114 [KERNEL_HWCAP_SME_F32F32] = "smef32f32",
115 [KERNEL_HWCAP_SME_FA64] = "smefa64",
116 [KERNEL_HWCAP_WFXT] = "wfxt",
117 [KERNEL_HWCAP_EBF16] = "ebf16",
118 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
119 };
120
121 #ifdef CONFIG_COMPAT
122 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
123 static const char *const compat_hwcap_str[] = {
124 [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
125 [COMPAT_KERNEL_HWCAP(HALF)] = "half",
126 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
127 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
128 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
129 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
130 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
131 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
132 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
133 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
134 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
135 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
136 [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
137 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
138 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
139 [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
140 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
141 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
142 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
143 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
144 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
145 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
146 };
147
148 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
149 static const char *const compat_hwcap2_str[] = {
150 [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
151 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
152 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
153 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
154 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
155 };
156 #endif /* CONFIG_COMPAT */
157
c_show(struct seq_file * m,void * v)158 static int c_show(struct seq_file *m, void *v)
159 {
160 int i, j;
161 bool compat = personality(current->personality) == PER_LINUX32;
162
163 for_each_online_cpu(i) {
164 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
165 u32 midr = cpuinfo->reg_midr;
166
167 /*
168 * glibc reads /proc/cpuinfo to determine the number of
169 * online processors, looking for lines beginning with
170 * "processor". Give glibc what it expects.
171 */
172 seq_printf(m, "processor\t: %d\n", i);
173 if (compat)
174 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
175 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
176
177 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
178 loops_per_jiffy / (500000UL/HZ),
179 loops_per_jiffy / (5000UL/HZ) % 100);
180
181 /*
182 * Dump out the common processor features in a single line.
183 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
184 * rather than attempting to parse this, but there's a body of
185 * software which does already (at least for 32-bit).
186 */
187 seq_puts(m, "Features\t:");
188 if (compat) {
189 #ifdef CONFIG_COMPAT
190 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
191 if (compat_elf_hwcap & (1 << j)) {
192 /*
193 * Warn once if any feature should not
194 * have been present on arm64 platform.
195 */
196 if (WARN_ON_ONCE(!compat_hwcap_str[j]))
197 continue;
198
199 seq_printf(m, " %s", compat_hwcap_str[j]);
200 }
201 }
202
203 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
204 if (compat_elf_hwcap2 & (1 << j))
205 seq_printf(m, " %s", compat_hwcap2_str[j]);
206 #endif /* CONFIG_COMPAT */
207 } else {
208 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
209 if (cpu_have_feature(j))
210 seq_printf(m, " %s", hwcap_str[j]);
211 }
212 seq_puts(m, "\n");
213
214 seq_printf(m, "CPU implementer\t: 0x%02x\n",
215 MIDR_IMPLEMENTOR(midr));
216 seq_printf(m, "CPU architecture: 8\n");
217 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
218 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
219 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
220 }
221
222 return 0;
223 }
224
c_start(struct seq_file * m,loff_t * pos)225 static void *c_start(struct seq_file *m, loff_t *pos)
226 {
227 return *pos < 1 ? (void *)1 : NULL;
228 }
229
c_next(struct seq_file * m,void * v,loff_t * pos)230 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
231 {
232 ++*pos;
233 return NULL;
234 }
235
c_stop(struct seq_file * m,void * v)236 static void c_stop(struct seq_file *m, void *v)
237 {
238 }
239
240 const struct seq_operations cpuinfo_op = {
241 .start = c_start,
242 .next = c_next,
243 .stop = c_stop,
244 .show = c_show
245 };
246
247
248 static struct kobj_type cpuregs_kobj_type = {
249 .sysfs_ops = &kobj_sysfs_ops,
250 };
251
252 /*
253 * The ARM ARM uses the phrase "32-bit register" to describe a register
254 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
255 * no statement is made as to whether the upper 32 bits will or will not
256 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
257 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
258 *
259 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
260 * registers, we expose them both as 64 bit values to cater for possible
261 * future expansion without an ABI break.
262 */
263 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
264 #define CPUREGS_ATTR_RO(_name, _field) \
265 static ssize_t _name##_show(struct kobject *kobj, \
266 struct kobj_attribute *attr, char *buf) \
267 { \
268 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
269 \
270 if (info->reg_midr) \
271 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
272 else \
273 return 0; \
274 } \
275 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
276
277 CPUREGS_ATTR_RO(midr_el1, midr);
278 CPUREGS_ATTR_RO(revidr_el1, revidr);
279 CPUREGS_ATTR_RO(smidr_el1, smidr);
280
281 static struct attribute *cpuregs_id_attrs[] = {
282 &cpuregs_attr_midr_el1.attr,
283 &cpuregs_attr_revidr_el1.attr,
284 NULL
285 };
286
287 static const struct attribute_group cpuregs_attr_group = {
288 .attrs = cpuregs_id_attrs,
289 .name = "identification"
290 };
291
292 static struct attribute *sme_cpuregs_id_attrs[] = {
293 &cpuregs_attr_smidr_el1.attr,
294 NULL
295 };
296
297 static const struct attribute_group sme_cpuregs_attr_group = {
298 .attrs = sme_cpuregs_id_attrs,
299 .name = "identification"
300 };
301
cpuid_cpu_online(unsigned int cpu)302 static int cpuid_cpu_online(unsigned int cpu)
303 {
304 int rc;
305 struct device *dev;
306 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
307
308 dev = get_cpu_device(cpu);
309 if (!dev) {
310 rc = -ENODEV;
311 goto out;
312 }
313 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
314 if (rc)
315 goto out;
316 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
317 if (rc)
318 kobject_del(&info->kobj);
319 if (system_supports_sme())
320 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);
321 out:
322 return rc;
323 }
324
cpuid_cpu_offline(unsigned int cpu)325 static int cpuid_cpu_offline(unsigned int cpu)
326 {
327 struct device *dev;
328 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
329
330 dev = get_cpu_device(cpu);
331 if (!dev)
332 return -ENODEV;
333 if (info->kobj.parent) {
334 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
335 kobject_del(&info->kobj);
336 }
337
338 return 0;
339 }
340
cpuinfo_regs_init(void)341 static int __init cpuinfo_regs_init(void)
342 {
343 int cpu, ret;
344
345 for_each_possible_cpu(cpu) {
346 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
347
348 kobject_init(&info->kobj, &cpuregs_kobj_type);
349 }
350
351 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
352 cpuid_cpu_online, cpuid_cpu_offline);
353 if (ret < 0) {
354 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
355 return ret;
356 }
357 return 0;
358 }
359 device_initcall(cpuinfo_regs_init);
360
cpuinfo_detect_icache_policy(struct cpuinfo_arm64 * info)361 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
362 {
363 unsigned int cpu = smp_processor_id();
364 u32 l1ip = CTR_L1IP(info->reg_ctr);
365
366 switch (l1ip) {
367 case CTR_EL0_L1Ip_PIPT:
368 break;
369 case CTR_EL0_L1Ip_VPIPT:
370 set_bit(ICACHEF_VPIPT, &__icache_flags);
371 break;
372 case CTR_EL0_L1Ip_VIPT:
373 default:
374 /* Assume aliasing */
375 set_bit(ICACHEF_ALIASING, &__icache_flags);
376 break;
377 }
378
379 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
380 }
381
__cpuinfo_store_cpu_32bit(struct cpuinfo_32bit * info)382 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
383 {
384 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
385 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
386 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
387 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
388 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
389 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
390 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
391 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
392 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
393 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
394 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
395 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
396 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
397 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
398 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
399 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
400 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
401 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
402
403 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
404 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
405 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
406 }
407
__cpuinfo_store_cpu(struct cpuinfo_arm64 * info)408 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
409 {
410 info->reg_cntfrq = arch_timer_get_cntfrq();
411 /*
412 * Use the effective value of the CTR_EL0 than the raw value
413 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
414 * with the CLIDR_EL1 fields to avoid triggering false warnings
415 * when there is a mismatch across the CPUs. Keep track of the
416 * effective value of the CTR_EL0 in our internal records for
417 * accurate sanity check and feature enablement.
418 */
419 info->reg_ctr = read_cpuid_effective_cachetype();
420 info->reg_dczid = read_cpuid(DCZID_EL0);
421 info->reg_midr = read_cpuid_id();
422 info->reg_revidr = read_cpuid(REVIDR_EL1);
423
424 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
425 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
426 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
427 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
428 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
429 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
430 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
431 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
432 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
433 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
434 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
435 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
436
437 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
438 info->reg_gmid = read_cpuid(GMID_EL1);
439
440 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
441 __cpuinfo_store_cpu_32bit(&info->aarch32);
442
443 cpuinfo_detect_icache_policy(info);
444 }
445
cpuinfo_store_cpu(void)446 void cpuinfo_store_cpu(void)
447 {
448 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
449 __cpuinfo_store_cpu(info);
450 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
451 }
452
cpuinfo_store_boot_cpu(void)453 void __init cpuinfo_store_boot_cpu(void)
454 {
455 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
456 __cpuinfo_store_cpu(info);
457
458 boot_cpu_data = *info;
459 init_cpu_features(&boot_cpu_data);
460 }
461