1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * General Purpose functions for the global management of the
4  * Communication Processor Module.
5  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
6  *
7  * In addition to the individual control of the communication
8  * channels, there are a few functions that globally affect the
9  * communication processor.
10  *
11  * Buffer descriptors must be allocated from the dual ported memory
12  * space.  The allocator for that is here.  When the communication
13  * process is reset, we reclaim the memory available.  There is
14  * currently no deallocator for this memory.
15  * The amount of space available is platform dependent.  On the
16  * MBX, the EPPC software loads additional microcode into the
17  * communication processor, and uses some of the DP ram for this
18  * purpose.  Current, the first 512 bytes and the last 256 bytes of
19  * memory are used.  Right now I am conservative and only use the
20  * memory that can never be used for microcode.  If there are
21  * applications that require more DP ram, we can expand the boundaries
22  * but then we have to be careful of any downloaded microcode.
23  */
24 #include <linux/errno.h>
25 #include <linux/sched.h>
26 #include <linux/kernel.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/param.h>
29 #include <linux/string.h>
30 #include <linux/mm.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/module.h>
34 #include <linux/spinlock.h>
35 #include <linux/slab.h>
36 #include <linux/of_irq.h>
37 #include <asm/page.h>
38 #include <asm/8xx_immap.h>
39 #include <asm/cpm1.h>
40 #include <asm/io.h>
41 #include <asm/rheap.h>
42 #include <asm/cpm.h>
43 
44 #include <asm/fs_pd.h>
45 
46 #ifdef CONFIG_8xx_GPIO
47 #include <linux/of_gpio.h>
48 #endif
49 
50 #define CPM_MAP_SIZE    (0x4000)
51 
52 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
53 immap_t __iomem *mpc8xx_immr = (void __iomem *)VIRT_IMMR_BASE;
54 
cpm_reset(void)55 void __init cpm_reset(void)
56 {
57 	sysconf8xx_t __iomem *siu_conf;
58 
59 	cpmp = &mpc8xx_immr->im_cpm;
60 
61 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
62 	/* Perform a reset. */
63 	out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
64 
65 	/* Wait for it. */
66 	while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
67 #endif
68 
69 #ifdef CONFIG_UCODE_PATCH
70 	cpm_load_patch(cpmp);
71 #endif
72 
73 	/*
74 	 * Set SDMA Bus Request priority 5.
75 	 * On 860T, this also enables FEC priority 6.  I am not sure
76 	 * this is what we really want for some applications, but the
77 	 * manual recommends it.
78 	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
79 	 */
80 	siu_conf = immr_map(im_siu_conf);
81 	if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
82 		out_be32(&siu_conf->sc_sdcr, 0x40);
83 	else
84 		out_be32(&siu_conf->sc_sdcr, 1);
85 	immr_unmap(siu_conf);
86 }
87 
88 static DEFINE_SPINLOCK(cmd_lock);
89 
90 #define MAX_CR_CMD_LOOPS        10000
91 
cpm_command(u32 command,u8 opcode)92 int cpm_command(u32 command, u8 opcode)
93 {
94 	int i, ret;
95 	unsigned long flags;
96 
97 	if (command & 0xffffff0f)
98 		return -EINVAL;
99 
100 	spin_lock_irqsave(&cmd_lock, flags);
101 
102 	ret = 0;
103 	out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
104 	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
105 		if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
106 			goto out;
107 
108 	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
109 	ret = -EIO;
110 out:
111 	spin_unlock_irqrestore(&cmd_lock, flags);
112 	return ret;
113 }
114 EXPORT_SYMBOL(cpm_command);
115 
116 /*
117  * Set a baud rate generator.  This needs lots of work.  There are
118  * four BRGs, any of which can be wired to any channel.
119  * The internal baud rate clock is the system clock divided by 16.
120  * This assumes the baudrate is 16x oversampled by the uart.
121  */
122 #define BRG_INT_CLK		(get_brgfreq())
123 #define BRG_UART_CLK		(BRG_INT_CLK/16)
124 #define BRG_UART_CLK_DIV16	(BRG_UART_CLK/16)
125 
126 void
cpm_setbrg(uint brg,uint rate)127 cpm_setbrg(uint brg, uint rate)
128 {
129 	u32 __iomem *bp;
130 
131 	/* This is good enough to get SMCs running..... */
132 	bp = &cpmp->cp_brgc1;
133 	bp += brg;
134 	/*
135 	 * The BRG has a 12-bit counter.  For really slow baud rates (or
136 	 * really fast processors), we may have to further divide by 16.
137 	 */
138 	if (((BRG_UART_CLK / rate) - 1) < 4096)
139 		out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
140 	else
141 		out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
142 			      CPM_BRG_EN | CPM_BRG_DIV16);
143 }
144 EXPORT_SYMBOL(cpm_setbrg);
145 
146 struct cpm_ioport16 {
147 	__be16 dir, par, odr_sor, dat, intr;
148 	__be16 res[3];
149 };
150 
151 struct cpm_ioport32b {
152 	__be32 dir, par, odr, dat;
153 };
154 
155 struct cpm_ioport32e {
156 	__be32 dir, par, sor, odr, dat;
157 };
158 
cpm1_set_pin32(int port,int pin,int flags)159 static void __init cpm1_set_pin32(int port, int pin, int flags)
160 {
161 	struct cpm_ioport32e __iomem *iop;
162 	pin = 1 << (31 - pin);
163 
164 	if (port == CPM_PORTB)
165 		iop = (struct cpm_ioport32e __iomem *)
166 		      &mpc8xx_immr->im_cpm.cp_pbdir;
167 	else
168 		iop = (struct cpm_ioport32e __iomem *)
169 		      &mpc8xx_immr->im_cpm.cp_pedir;
170 
171 	if (flags & CPM_PIN_OUTPUT)
172 		setbits32(&iop->dir, pin);
173 	else
174 		clrbits32(&iop->dir, pin);
175 
176 	if (!(flags & CPM_PIN_GPIO))
177 		setbits32(&iop->par, pin);
178 	else
179 		clrbits32(&iop->par, pin);
180 
181 	if (port == CPM_PORTB) {
182 		if (flags & CPM_PIN_OPENDRAIN)
183 			setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
184 		else
185 			clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
186 	}
187 
188 	if (port == CPM_PORTE) {
189 		if (flags & CPM_PIN_SECONDARY)
190 			setbits32(&iop->sor, pin);
191 		else
192 			clrbits32(&iop->sor, pin);
193 
194 		if (flags & CPM_PIN_OPENDRAIN)
195 			setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
196 		else
197 			clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
198 	}
199 }
200 
cpm1_set_pin16(int port,int pin,int flags)201 static void __init cpm1_set_pin16(int port, int pin, int flags)
202 {
203 	struct cpm_ioport16 __iomem *iop =
204 		(struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
205 
206 	pin = 1 << (15 - pin);
207 
208 	if (port != 0)
209 		iop += port - 1;
210 
211 	if (flags & CPM_PIN_OUTPUT)
212 		setbits16(&iop->dir, pin);
213 	else
214 		clrbits16(&iop->dir, pin);
215 
216 	if (!(flags & CPM_PIN_GPIO))
217 		setbits16(&iop->par, pin);
218 	else
219 		clrbits16(&iop->par, pin);
220 
221 	if (port == CPM_PORTA) {
222 		if (flags & CPM_PIN_OPENDRAIN)
223 			setbits16(&iop->odr_sor, pin);
224 		else
225 			clrbits16(&iop->odr_sor, pin);
226 	}
227 	if (port == CPM_PORTC) {
228 		if (flags & CPM_PIN_SECONDARY)
229 			setbits16(&iop->odr_sor, pin);
230 		else
231 			clrbits16(&iop->odr_sor, pin);
232 		if (flags & CPM_PIN_FALLEDGE)
233 			setbits16(&iop->intr, pin);
234 		else
235 			clrbits16(&iop->intr, pin);
236 	}
237 }
238 
cpm1_set_pin(enum cpm_port port,int pin,int flags)239 void __init cpm1_set_pin(enum cpm_port port, int pin, int flags)
240 {
241 	if (port == CPM_PORTB || port == CPM_PORTE)
242 		cpm1_set_pin32(port, pin, flags);
243 	else
244 		cpm1_set_pin16(port, pin, flags);
245 }
246 
cpm1_clk_setup(enum cpm_clk_target target,int clock,int mode)247 int __init cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
248 {
249 	int shift;
250 	int i, bits = 0;
251 	u32 __iomem *reg;
252 	u32 mask = 7;
253 
254 	u8 clk_map[][3] = {
255 		{CPM_CLK_SCC1, CPM_BRG1, 0},
256 		{CPM_CLK_SCC1, CPM_BRG2, 1},
257 		{CPM_CLK_SCC1, CPM_BRG3, 2},
258 		{CPM_CLK_SCC1, CPM_BRG4, 3},
259 		{CPM_CLK_SCC1, CPM_CLK1, 4},
260 		{CPM_CLK_SCC1, CPM_CLK2, 5},
261 		{CPM_CLK_SCC1, CPM_CLK3, 6},
262 		{CPM_CLK_SCC1, CPM_CLK4, 7},
263 
264 		{CPM_CLK_SCC2, CPM_BRG1, 0},
265 		{CPM_CLK_SCC2, CPM_BRG2, 1},
266 		{CPM_CLK_SCC2, CPM_BRG3, 2},
267 		{CPM_CLK_SCC2, CPM_BRG4, 3},
268 		{CPM_CLK_SCC2, CPM_CLK1, 4},
269 		{CPM_CLK_SCC2, CPM_CLK2, 5},
270 		{CPM_CLK_SCC2, CPM_CLK3, 6},
271 		{CPM_CLK_SCC2, CPM_CLK4, 7},
272 
273 		{CPM_CLK_SCC3, CPM_BRG1, 0},
274 		{CPM_CLK_SCC3, CPM_BRG2, 1},
275 		{CPM_CLK_SCC3, CPM_BRG3, 2},
276 		{CPM_CLK_SCC3, CPM_BRG4, 3},
277 		{CPM_CLK_SCC3, CPM_CLK5, 4},
278 		{CPM_CLK_SCC3, CPM_CLK6, 5},
279 		{CPM_CLK_SCC3, CPM_CLK7, 6},
280 		{CPM_CLK_SCC3, CPM_CLK8, 7},
281 
282 		{CPM_CLK_SCC4, CPM_BRG1, 0},
283 		{CPM_CLK_SCC4, CPM_BRG2, 1},
284 		{CPM_CLK_SCC4, CPM_BRG3, 2},
285 		{CPM_CLK_SCC4, CPM_BRG4, 3},
286 		{CPM_CLK_SCC4, CPM_CLK5, 4},
287 		{CPM_CLK_SCC4, CPM_CLK6, 5},
288 		{CPM_CLK_SCC4, CPM_CLK7, 6},
289 		{CPM_CLK_SCC4, CPM_CLK8, 7},
290 
291 		{CPM_CLK_SMC1, CPM_BRG1, 0},
292 		{CPM_CLK_SMC1, CPM_BRG2, 1},
293 		{CPM_CLK_SMC1, CPM_BRG3, 2},
294 		{CPM_CLK_SMC1, CPM_BRG4, 3},
295 		{CPM_CLK_SMC1, CPM_CLK1, 4},
296 		{CPM_CLK_SMC1, CPM_CLK2, 5},
297 		{CPM_CLK_SMC1, CPM_CLK3, 6},
298 		{CPM_CLK_SMC1, CPM_CLK4, 7},
299 
300 		{CPM_CLK_SMC2, CPM_BRG1, 0},
301 		{CPM_CLK_SMC2, CPM_BRG2, 1},
302 		{CPM_CLK_SMC2, CPM_BRG3, 2},
303 		{CPM_CLK_SMC2, CPM_BRG4, 3},
304 		{CPM_CLK_SMC2, CPM_CLK5, 4},
305 		{CPM_CLK_SMC2, CPM_CLK6, 5},
306 		{CPM_CLK_SMC2, CPM_CLK7, 6},
307 		{CPM_CLK_SMC2, CPM_CLK8, 7},
308 	};
309 
310 	switch (target) {
311 	case CPM_CLK_SCC1:
312 		reg = &mpc8xx_immr->im_cpm.cp_sicr;
313 		shift = 0;
314 		break;
315 
316 	case CPM_CLK_SCC2:
317 		reg = &mpc8xx_immr->im_cpm.cp_sicr;
318 		shift = 8;
319 		break;
320 
321 	case CPM_CLK_SCC3:
322 		reg = &mpc8xx_immr->im_cpm.cp_sicr;
323 		shift = 16;
324 		break;
325 
326 	case CPM_CLK_SCC4:
327 		reg = &mpc8xx_immr->im_cpm.cp_sicr;
328 		shift = 24;
329 		break;
330 
331 	case CPM_CLK_SMC1:
332 		reg = &mpc8xx_immr->im_cpm.cp_simode;
333 		shift = 12;
334 		break;
335 
336 	case CPM_CLK_SMC2:
337 		reg = &mpc8xx_immr->im_cpm.cp_simode;
338 		shift = 28;
339 		break;
340 
341 	default:
342 		printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
343 		return -EINVAL;
344 	}
345 
346 	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
347 		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
348 			bits = clk_map[i][2];
349 			break;
350 		}
351 	}
352 
353 	if (i == ARRAY_SIZE(clk_map)) {
354 		printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
355 		return -EINVAL;
356 	}
357 
358 	bits <<= shift;
359 	mask <<= shift;
360 
361 	if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
362 		if (mode == CPM_CLK_RTX) {
363 			bits |= bits << 3;
364 			mask |= mask << 3;
365 		} else if (mode == CPM_CLK_RX) {
366 			bits <<= 3;
367 			mask <<= 3;
368 		}
369 	}
370 
371 	out_be32(reg, (in_be32(reg) & ~mask) | bits);
372 
373 	return 0;
374 }
375 
376 /*
377  * GPIO LIB API implementation
378  */
379 #ifdef CONFIG_8xx_GPIO
380 
381 struct cpm1_gpio16_chip {
382 	struct of_mm_gpio_chip mm_gc;
383 	spinlock_t lock;
384 
385 	/* shadowed data register to clear/set bits safely */
386 	u16 cpdata;
387 
388 	/* IRQ associated with Pins when relevant */
389 	int irq[16];
390 };
391 
cpm1_gpio16_save_regs(struct of_mm_gpio_chip * mm_gc)392 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
393 {
394 	struct cpm1_gpio16_chip *cpm1_gc =
395 		container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
396 	struct cpm_ioport16 __iomem *iop = mm_gc->regs;
397 
398 	cpm1_gc->cpdata = in_be16(&iop->dat);
399 }
400 
cpm1_gpio16_get(struct gpio_chip * gc,unsigned int gpio)401 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
402 {
403 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
404 	struct cpm_ioport16 __iomem *iop = mm_gc->regs;
405 	u16 pin_mask;
406 
407 	pin_mask = 1 << (15 - gpio);
408 
409 	return !!(in_be16(&iop->dat) & pin_mask);
410 }
411 
__cpm1_gpio16_set(struct of_mm_gpio_chip * mm_gc,u16 pin_mask,int value)412 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
413 	int value)
414 {
415 	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
416 	struct cpm_ioport16 __iomem *iop = mm_gc->regs;
417 
418 	if (value)
419 		cpm1_gc->cpdata |= pin_mask;
420 	else
421 		cpm1_gc->cpdata &= ~pin_mask;
422 
423 	out_be16(&iop->dat, cpm1_gc->cpdata);
424 }
425 
cpm1_gpio16_set(struct gpio_chip * gc,unsigned int gpio,int value)426 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
427 {
428 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
429 	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
430 	unsigned long flags;
431 	u16 pin_mask = 1 << (15 - gpio);
432 
433 	spin_lock_irqsave(&cpm1_gc->lock, flags);
434 
435 	__cpm1_gpio16_set(mm_gc, pin_mask, value);
436 
437 	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
438 }
439 
cpm1_gpio16_to_irq(struct gpio_chip * gc,unsigned int gpio)440 static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
441 {
442 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
443 	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
444 
445 	return cpm1_gc->irq[gpio] ? : -ENXIO;
446 }
447 
cpm1_gpio16_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)448 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
449 {
450 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
451 	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
452 	struct cpm_ioport16 __iomem *iop = mm_gc->regs;
453 	unsigned long flags;
454 	u16 pin_mask = 1 << (15 - gpio);
455 
456 	spin_lock_irqsave(&cpm1_gc->lock, flags);
457 
458 	setbits16(&iop->dir, pin_mask);
459 	__cpm1_gpio16_set(mm_gc, pin_mask, val);
460 
461 	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
462 
463 	return 0;
464 }
465 
cpm1_gpio16_dir_in(struct gpio_chip * gc,unsigned int gpio)466 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
467 {
468 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
469 	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
470 	struct cpm_ioport16 __iomem *iop = mm_gc->regs;
471 	unsigned long flags;
472 	u16 pin_mask = 1 << (15 - gpio);
473 
474 	spin_lock_irqsave(&cpm1_gc->lock, flags);
475 
476 	clrbits16(&iop->dir, pin_mask);
477 
478 	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
479 
480 	return 0;
481 }
482 
cpm1_gpiochip_add16(struct device * dev)483 int cpm1_gpiochip_add16(struct device *dev)
484 {
485 	struct device_node *np = dev->of_node;
486 	struct cpm1_gpio16_chip *cpm1_gc;
487 	struct of_mm_gpio_chip *mm_gc;
488 	struct gpio_chip *gc;
489 	u16 mask;
490 
491 	cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
492 	if (!cpm1_gc)
493 		return -ENOMEM;
494 
495 	spin_lock_init(&cpm1_gc->lock);
496 
497 	if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
498 		int i, j;
499 
500 		for (i = 0, j = 0; i < 16; i++)
501 			if (mask & (1 << (15 - i)))
502 				cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
503 	}
504 
505 	mm_gc = &cpm1_gc->mm_gc;
506 	gc = &mm_gc->gc;
507 
508 	mm_gc->save_regs = cpm1_gpio16_save_regs;
509 	gc->ngpio = 16;
510 	gc->direction_input = cpm1_gpio16_dir_in;
511 	gc->direction_output = cpm1_gpio16_dir_out;
512 	gc->get = cpm1_gpio16_get;
513 	gc->set = cpm1_gpio16_set;
514 	gc->to_irq = cpm1_gpio16_to_irq;
515 	gc->parent = dev;
516 	gc->owner = THIS_MODULE;
517 
518 	return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
519 }
520 
521 struct cpm1_gpio32_chip {
522 	struct of_mm_gpio_chip mm_gc;
523 	spinlock_t lock;
524 
525 	/* shadowed data register to clear/set bits safely */
526 	u32 cpdata;
527 };
528 
cpm1_gpio32_save_regs(struct of_mm_gpio_chip * mm_gc)529 static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
530 {
531 	struct cpm1_gpio32_chip *cpm1_gc =
532 		container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
533 	struct cpm_ioport32b __iomem *iop = mm_gc->regs;
534 
535 	cpm1_gc->cpdata = in_be32(&iop->dat);
536 }
537 
cpm1_gpio32_get(struct gpio_chip * gc,unsigned int gpio)538 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
539 {
540 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
541 	struct cpm_ioport32b __iomem *iop = mm_gc->regs;
542 	u32 pin_mask;
543 
544 	pin_mask = 1 << (31 - gpio);
545 
546 	return !!(in_be32(&iop->dat) & pin_mask);
547 }
548 
__cpm1_gpio32_set(struct of_mm_gpio_chip * mm_gc,u32 pin_mask,int value)549 static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
550 	int value)
551 {
552 	struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
553 	struct cpm_ioport32b __iomem *iop = mm_gc->regs;
554 
555 	if (value)
556 		cpm1_gc->cpdata |= pin_mask;
557 	else
558 		cpm1_gc->cpdata &= ~pin_mask;
559 
560 	out_be32(&iop->dat, cpm1_gc->cpdata);
561 }
562 
cpm1_gpio32_set(struct gpio_chip * gc,unsigned int gpio,int value)563 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
564 {
565 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
566 	struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
567 	unsigned long flags;
568 	u32 pin_mask = 1 << (31 - gpio);
569 
570 	spin_lock_irqsave(&cpm1_gc->lock, flags);
571 
572 	__cpm1_gpio32_set(mm_gc, pin_mask, value);
573 
574 	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
575 }
576 
cpm1_gpio32_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)577 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
578 {
579 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
580 	struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
581 	struct cpm_ioport32b __iomem *iop = mm_gc->regs;
582 	unsigned long flags;
583 	u32 pin_mask = 1 << (31 - gpio);
584 
585 	spin_lock_irqsave(&cpm1_gc->lock, flags);
586 
587 	setbits32(&iop->dir, pin_mask);
588 	__cpm1_gpio32_set(mm_gc, pin_mask, val);
589 
590 	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
591 
592 	return 0;
593 }
594 
cpm1_gpio32_dir_in(struct gpio_chip * gc,unsigned int gpio)595 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
596 {
597 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
598 	struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
599 	struct cpm_ioport32b __iomem *iop = mm_gc->regs;
600 	unsigned long flags;
601 	u32 pin_mask = 1 << (31 - gpio);
602 
603 	spin_lock_irqsave(&cpm1_gc->lock, flags);
604 
605 	clrbits32(&iop->dir, pin_mask);
606 
607 	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
608 
609 	return 0;
610 }
611 
cpm1_gpiochip_add32(struct device * dev)612 int cpm1_gpiochip_add32(struct device *dev)
613 {
614 	struct device_node *np = dev->of_node;
615 	struct cpm1_gpio32_chip *cpm1_gc;
616 	struct of_mm_gpio_chip *mm_gc;
617 	struct gpio_chip *gc;
618 
619 	cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
620 	if (!cpm1_gc)
621 		return -ENOMEM;
622 
623 	spin_lock_init(&cpm1_gc->lock);
624 
625 	mm_gc = &cpm1_gc->mm_gc;
626 	gc = &mm_gc->gc;
627 
628 	mm_gc->save_regs = cpm1_gpio32_save_regs;
629 	gc->ngpio = 32;
630 	gc->direction_input = cpm1_gpio32_dir_in;
631 	gc->direction_output = cpm1_gpio32_dir_out;
632 	gc->get = cpm1_gpio32_get;
633 	gc->set = cpm1_gpio32_set;
634 	gc->parent = dev;
635 	gc->owner = THIS_MODULE;
636 
637 	return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
638 }
639 
640 #endif /* CONFIG_8xx_GPIO */
641