1 /******************************************************** 2 * Header file for eata_dma.c and eata_pio.c * 3 * Linux EATA SCSI drivers * 4 * (c) 1993-96 Michael Neuffer * 5 * mike@i-Connect.Net * 6 * neuffer@mail.uni-mainz.de * 7 ********************************************************* 8 * last change: 96/08/14 * 9 ********************************************************/ 10 11 12 #ifndef _EATA_GENERIC_H 13 #define _EATA_GENERIC_H 14 15 16 17 /********************************************* 18 * Misc. definitions * 19 *********************************************/ 20 21 #ifndef TRUE 22 #define TRUE 1 23 #endif 24 #ifndef FALSE 25 #define FALSE 0 26 #endif 27 28 #define R_LIMIT 0x20000 29 30 #define MAXISA 4 31 #define MAXEISA 16 32 #define MAXPCI 16 33 #define MAXIRQ 16 34 #define MAXTARGET 16 35 #define MAXCHANNEL 3 36 37 #define IS_ISA 'I' 38 #define IS_EISA 'E' 39 #define IS_PCI 'P' 40 41 #define BROKEN_INQUIRY 1 42 43 #define BUSMASTER 0xff 44 #define PIO 0xfe 45 46 #define EATA_SIGNATURE 0x45415441 /* BIG ENDIAN coded "EATA" sig. */ 47 48 #define DPT_ID1 0x12 49 #define DPT_ID2 0x14 50 51 #define ATT_ID1 0x06 52 #define ATT_ID2 0x94 53 #define ATT_ID3 0x0 54 55 #define NEC_ID1 0x38 56 #define NEC_ID2 0xa3 57 #define NEC_ID3 0x82 58 59 60 #define EATA_CP_SIZE 44 61 62 #define MAX_PCI_DEVICES 32 /* Maximum # Of Devices Per Bus */ 63 #define MAX_METHOD_2 16 /* Max Devices For Method 2 */ 64 #define MAX_PCI_BUS 16 /* Maximum # Of Busses Allowed */ 65 66 #define SG_SIZE 64 67 #define SG_SIZE_BIG 252 /* max. 8096 elements, 64k */ 68 69 #define UPPER_DEVICE_QUEUE_LIMIT 64 /* The limit we have to set for the 70 * device queue to keep the broken 71 * midlevel SCSI code from producing 72 * bogus timeouts 73 */ 74 75 #define TYPE_DISK_QUEUE 16 76 #define TYPE_TAPE_QUEUE 4 77 #define TYPE_ROM_QUEUE 4 78 #define TYPE_OTHER_QUEUE 2 79 80 #define FREE 0 81 #define OK 0 82 #define NO_TIMEOUT 0 83 #define USED 1 84 #define TIMEOUT 2 85 #define RESET 4 86 #define LOCKED 8 87 #define ABORTED 16 88 89 #define READ 0 90 #define WRITE 1 91 #define OTHER 2 92 93 #define HD(cmd) ((hostdata *)&(cmd->host->hostdata)) 94 #define CD(cmd) ((struct eata_ccb *)(cmd->host_scribble)) 95 #define SD(host) ((hostdata *)&(host->hostdata)) 96 97 #define DELAY(x) { ulong flags, i; \ 98 save_flags(flags); sti(); \ 99 i = jiffies + (x * HZ); \ 100 while (time_before(jiffies, i)) cpu_relax(); \ 101 restore_flags(flags); } 102 103 /*********************************************** 104 * EATA Command & Register definitions * 105 ***********************************************/ 106 #define PCI_REG_DPTconfig 0x40 107 #define PCI_REG_PumpModeAddress 0x44 108 #define PCI_REG_PumpModeData 0x48 109 #define PCI_REG_ConfigParam1 0x50 110 #define PCI_REG_ConfigParam2 0x54 111 112 113 #define EATA_CMD_PIO_SETUPTEST 0xc6 114 #define EATA_CMD_PIO_READ_CONFIG 0xf0 115 #define EATA_CMD_PIO_SET_CONFIG 0xf1 116 #define EATA_CMD_PIO_SEND_CP 0xf2 117 #define EATA_CMD_PIO_RECEIVE_SP 0xf3 118 #define EATA_CMD_PIO_TRUNC 0xf4 119 120 #define EATA_CMD_RESET 0xf9 121 #define EATA_CMD_IMMEDIATE 0xfa 122 123 #define EATA_CMD_DMA_READ_CONFIG 0xfd 124 #define EATA_CMD_DMA_SET_CONFIG 0xfe 125 #define EATA_CMD_DMA_SEND_CP 0xff 126 127 #define ECS_EMULATE_SENSE 0xd4 128 129 #define EATA_GENERIC_ABORT 0x00 130 #define EATA_SPECIFIC_RESET 0x01 131 #define EATA_BUS_RESET 0x02 132 #define EATA_SPECIFIC_ABORT 0x03 133 #define EATA_QUIET_INTR 0x04 134 #define EATA_COLD_BOOT_HBA 0x06 /* Only as a last resort */ 135 #define EATA_FORCE_IO 0x07 136 137 #define HA_CTRLREG 0x206 /* control register for HBA */ 138 #define HA_CTRL_DISINT 0x02 /* CTRLREG: disable interrupts */ 139 #define HA_CTRL_RESCPU 0x04 /* CTRLREG: reset processor */ 140 #define HA_CTRL_8HEADS 0x08 /* CTRLREG: set for drives with* 141 * >=8 heads (WD1003 rudimentary :-) */ 142 143 #define HA_WCOMMAND 0x07 /* command register offset */ 144 #define HA_WIFC 0x06 /* immediate command offset */ 145 #define HA_WCODE 0x05 146 #define HA_WCODE2 0x04 147 #define HA_WDMAADDR 0x02 /* DMA address LSB offset */ 148 #define HA_RAUXSTAT 0x08 /* aux status register offset*/ 149 #define HA_RSTATUS 0x07 /* status register offset */ 150 #define HA_RDATA 0x00 /* data register (16bit) */ 151 #define HA_WDATA 0x00 /* data register (16bit) */ 152 153 #define HA_ABUSY 0x01 /* aux busy bit */ 154 #define HA_AIRQ 0x02 /* aux IRQ pending bit */ 155 #define HA_SERROR 0x01 /* pr. command ended in error*/ 156 #define HA_SMORE 0x02 /* more data soon to come */ 157 #define HA_SCORR 0x04 /* data corrected */ 158 #define HA_SDRQ 0x08 /* data request active */ 159 #define HA_SSC 0x10 /* seek complete */ 160 #define HA_SFAULT 0x20 /* write fault */ 161 #define HA_SREADY 0x40 /* drive ready */ 162 #define HA_SBUSY 0x80 /* drive busy */ 163 #define HA_SDRDY HA_SSC+HA_SREADY+HA_SDRQ 164 165 /********************************************** 166 * Message definitions * 167 **********************************************/ 168 169 #define HA_NO_ERROR 0x00 /* No Error */ 170 #define HA_ERR_SEL_TO 0x01 /* Selection Timeout */ 171 #define HA_ERR_CMD_TO 0x02 /* Command Timeout */ 172 #define HA_BUS_RESET 0x03 /* SCSI Bus Reset Received */ 173 #define HA_INIT_POWERUP 0x04 /* Initial Controller Power-up */ 174 #define HA_UNX_BUSPHASE 0x05 /* Unexpected Bus Phase */ 175 #define HA_UNX_BUS_FREE 0x06 /* Unexpected Bus Free */ 176 #define HA_BUS_PARITY 0x07 /* Bus Parity Error */ 177 #define HA_SCSI_HUNG 0x08 /* SCSI Hung */ 178 #define HA_UNX_MSGRJCT 0x09 /* Unexpected Message Rejected */ 179 #define HA_RESET_STUCK 0x0a /* SCSI Bus Reset Stuck */ 180 #define HA_RSENSE_FAIL 0x0b /* Auto Request-Sense Failed */ 181 #define HA_PARITY_ERR 0x0c /* Controller Ram Parity Error */ 182 #define HA_CP_ABORT_NA 0x0d /* Abort Message sent to non-active cmd */ 183 #define HA_CP_ABORTED 0x0e /* Abort Message sent to active cmd */ 184 #define HA_CP_RESET_NA 0x0f /* Reset Message sent to non-active cmd */ 185 #define HA_CP_RESET 0x10 /* Reset Message sent to active cmd */ 186 #define HA_ECC_ERR 0x11 /* Controller Ram ECC Error */ 187 #define HA_PCI_PARITY 0x12 /* PCI Parity Error */ 188 #define HA_PCI_MABORT 0x13 /* PCI Master Abort */ 189 #define HA_PCI_TABORT 0x14 /* PCI Target Abort */ 190 #define HA_PCI_STABORT 0x15 /* PCI Signaled Target Abort */ 191 192 /********************************************** 193 * Other definitions * 194 **********************************************/ 195 196 struct reg_bit { /* reading this one will clear the interrupt */ 197 __u8 error:1; /* previous command ended in an error */ 198 __u8 more:1; /* more DATA coming soon, poll BSY & DRQ (PIO) */ 199 __u8 corr:1; /* data read was successfully corrected with ECC*/ 200 __u8 drq:1; /* data request active */ 201 __u8 sc:1; /* seek complete */ 202 __u8 fault:1; /* write fault */ 203 __u8 ready:1; /* drive ready */ 204 __u8 busy:1; /* controller busy */ 205 }; 206 207 struct reg_abit { /* reading this won't clear the interrupt */ 208 __u8 abusy:1; /* auxiliary busy */ 209 __u8 irq:1; /* set when drive interrupt is asserted */ 210 __u8 dummy:6; 211 }; 212 213 struct eata_register { /* EATA register set */ 214 __u8 data_reg[2]; /* R, couldn't figure this one out */ 215 __u8 cp_addr[4]; /* W, CP address register */ 216 union { 217 __u8 command; /* W, command code: [read|set] conf, send CP*/ 218 struct reg_bit status; /* R, see register_bit1 */ 219 __u8 statusbyte; 220 } ovr; 221 struct reg_abit aux_stat; /* R, see register_bit2 */ 222 }; 223 224 struct get_conf { /* Read Configuration Array */ 225 __u32 len; /* Should return 0x22, 0x24, etc */ 226 __u32 signature; /* Signature MUST be "EATA" */ 227 __u8 version2:4, 228 version:4; /* EATA Version level */ 229 __u8 OCS_enabled:1, /* Overlap Command Support enabled */ 230 TAR_support:1, /* SCSI Target Mode supported */ 231 TRNXFR:1, /* Truncate Transfer Cmd not necessary * 232 * Only used in PIO Mode */ 233 MORE_support:1, /* MORE supported (only PIO Mode) */ 234 DMA_support:1, /* DMA supported Driver uses only * 235 * this mode */ 236 DMA_valid:1, /* DRQ value in Byte 30 is valid */ 237 ATA:1, /* ATA device connected (not supported) */ 238 HAA_valid:1; /* Hostadapter Address is valid */ 239 240 __u16 cppadlen; /* Number of pad bytes send after CD data * 241 * set to zero for DMA commands */ 242 __u8 scsi_id[4]; /* SCSI ID of controller 2-0 Byte 0 res. * 243 * if not, zero is returned */ 244 __u32 cplen; /* CP length: number of valid cp bytes */ 245 __u32 splen; /* Number of bytes returned after * 246 * Receive SP command */ 247 __u16 queuesiz; /* max number of queueable CPs */ 248 __u16 dummy; 249 __u16 SGsiz; /* max number of SG table entries */ 250 __u8 IRQ:4, /* IRQ used this HA */ 251 IRQ_TR:1, /* IRQ Trigger: 0=edge, 1=level */ 252 SECOND:1, /* This is a secondary controller */ 253 DMA_channel:2; /* DRQ index, DRQ is 2comp of DRQX */ 254 __u8 sync; /* device at ID 7 tru 0 is running in * 255 * synchronous mode, this will disappear */ 256 __u8 DSBLE:1, /* ISA i/o addressing is disabled */ 257 FORCADR:1, /* i/o address has been forced */ 258 SG_64K:1, 259 SG_UAE:1, 260 :4; 261 __u8 MAX_ID:5, /* Max number of SCSI target IDs */ 262 MAX_CHAN:3; /* Number of SCSI busses on HBA */ 263 __u8 MAX_LUN; /* Max number of LUNs */ 264 __u8 :3, 265 AUTOTRM:1, 266 M1_inst:1, 267 ID_qest:1, /* Raidnum ID is questionable */ 268 is_PCI:1, /* HBA is PCI */ 269 is_EISA:1; /* HBA is EISA */ 270 __u8 RAIDNUM; /* unique HBA identifier */ 271 __u8 unused[474]; 272 }; 273 274 struct eata_sg_list 275 { 276 __u32 data; 277 __u32 len; 278 }; 279 280 struct eata_ccb { /* Send Command Packet structure */ 281 282 __u8 SCSI_Reset:1, /* Cause a SCSI Bus reset on the cmd */ 283 HBA_Init:1, /* Cause Controller to reinitialize */ 284 Auto_Req_Sen:1, /* Do Auto Request Sense on errors */ 285 scatter:1, /* Data Ptr points to a SG Packet */ 286 Resrvd:1, /* RFU */ 287 Interpret:1, /* Interpret the SCSI cdb of own use */ 288 DataOut:1, /* Data Out phase with command */ 289 DataIn:1; /* Data In phase with command */ 290 __u8 reqlen; /* Request Sense Length * 291 * Valid if Auto_Req_Sen=1 */ 292 __u8 unused[3]; 293 __u8 FWNEST:1, /* send cmd to phys RAID component */ 294 unused2:7; 295 __u8 Phsunit:1, /* physical unit on mirrored pair */ 296 I_AT:1, /* inhibit address translation */ 297 I_HBA_C:1, /* HBA inhibit caching */ 298 unused3:5; 299 300 __u8 cp_id:5, /* SCSI Device ID of target */ 301 cp_channel:3; /* SCSI Channel # of HBA */ 302 __u8 cp_lun:3, 303 :2, 304 cp_luntar:1, /* CP is for target ROUTINE */ 305 cp_dispri:1, /* Grant disconnect privilege */ 306 cp_identify:1; /* Always TRUE */ 307 __u8 cp_msg1; /* Message bytes 0-3 */ 308 __u8 cp_msg2; 309 __u8 cp_msg3; 310 __u8 cp_cdb[12]; /* Command Descriptor Block */ 311 __u32 cp_datalen; /* Data Transfer Length * 312 * If scatter=1 len of sg package */ 313 void *cp_viraddr; /* address of this ccb */ 314 __u32 cp_dataDMA; /* Data Address, if scatter=1 * 315 * address of scatter packet */ 316 __u32 cp_statDMA; /* address for Status Packet */ 317 __u32 cp_reqDMA; /* Request Sense Address, used if * 318 * CP command ends with error */ 319 /* Additional CP info begins here */ 320 __u32 timestamp; /* Needed to measure command latency */ 321 __u32 timeout; 322 __u8 sizeindex; 323 __u8 rw_latency; 324 __u8 retries; 325 __u8 status; /* status of this queueslot */ 326 Scsi_Cmnd *cmd; /* address of cmd */ 327 struct eata_sg_list *sg_list; 328 }; 329 330 331 struct eata_sp { 332 __u8 hba_stat:7, /* HBA status */ 333 EOC:1; /* True if command finished */ 334 __u8 scsi_stat; /* Target SCSI status */ 335 __u8 reserved[2]; 336 __u32 residue_len; /* Number of bytes not transferred */ 337 struct eata_ccb *ccb; /* Address set in COMMAND PACKET */ 338 __u8 msg[12]; 339 }; 340 341 typedef struct hstd { 342 __u8 vendor[9]; 343 __u8 name[18]; 344 __u8 revision[6]; 345 __u8 EATA_revision; 346 __u32 firmware_revision; 347 __u8 HBA_number; 348 __u8 bustype; /* bustype of HBA */ 349 __u8 channel; /* # of avail. scsi channels */ 350 __u8 state; /* state of HBA */ 351 __u8 primary; /* true if primary */ 352 __u8 more_support:1, /* HBA supports MORE flag */ 353 immediate_support:1, /* HBA supports IMMEDIATE CMDs*/ 354 broken_INQUIRY:1; /* This is an EISA HBA with * 355 * broken INQUIRY */ 356 __u8 do_latency; /* Latency measurement flag */ 357 __u32 reads[13]; 358 __u32 writes[13]; 359 __u32 reads_lat[12][4]; 360 __u32 writes_lat[12][4]; 361 __u32 all_lat[4]; 362 __u8 resetlevel[MAXCHANNEL]; 363 __u32 last_ccb; /* Last used ccb */ 364 __u32 cplen; /* size of CP in words */ 365 __u16 cppadlen; /* pad length of cp in words */ 366 __u16 queuesize; 367 __u16 sgsize; /* # of entries in the SG list*/ 368 __u16 devflags; /* bits set for detected devices */ 369 __u8 hostid; /* SCSI ID of HBA */ 370 __u8 moresupport; /* HBA supports MORE flag */ 371 struct Scsi_Host *next; 372 struct Scsi_Host *prev; 373 struct eata_sp sp; /* status packet */ 374 struct eata_ccb ccb[0]; /* ccb array begins here */ 375 }hostdata; 376 377 /* structure for max. 2 emulated drives */ 378 struct drive_geom_emul { 379 __u8 trans; /* translation flag 1=transl */ 380 __u8 channel; /* SCSI channel number */ 381 __u8 HBA; /* HBA number (prim/sec) */ 382 __u8 id; /* drive id */ 383 __u8 lun; /* drive lun */ 384 __u32 heads; /* number of heads */ 385 __u32 sectors; /* number of sectors */ 386 __u32 cylinder; /* number of cylinders */ 387 }; 388 389 struct geom_emul { 390 __u8 bios_drives; /* number of emulated drives */ 391 struct drive_geom_emul drv[2]; /* drive structures */ 392 }; 393 394 #endif /* _EATA_GENERIC_H */ 395 396 /* 397 * Overrides for Emacs so that we almost follow Linus's tabbing style. 398 * Emacs will notice this stuff at the end of the file and automatically 399 * adjust the settings for this buffer only. This must remain at the end 400 * of the file. 401 * --------------------------------------------------------------------------- 402 * Local variables: 403 * c-indent-level: 4 404 * c-brace-imaginary-offset: 0 405 * c-brace-offset: -4 406 * c-argdecl-indent: 4 407 * c-label-offset: -4 408 * c-continued-statement-offset: 4 409 * c-continued-brace-offset: 0 410 * tab-width: 8 411 * End: 412 */ 413