1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <linux/tcp.h>
35 #include <linux/in.h>
36 #include <linux/init.h>
37 #include <linux/delay.h>
38 #include <linux/if_vlan.h>
39 #include <linux/prefetch.h>
40 #include <linux/mii.h>
41
42 #include <asm/bitops.h>
43 #include <asm/byteorder.h>
44 #include <asm/io.h>
45 #include <asm/irq.h>
46
47 #include "skge_backport.h"
48 #include "sky2.h"
49
50 #define DRV_NAME "sky2"
51 #define DRV_VERSION "1.5 classic"
52 #define PFX DRV_NAME " "
53
54 /*
55 * The Yukon II chipset takes 64 bit command blocks (called list elements)
56 * that are organized into three (receive, transmit, status) different rings
57 * similar to Tigon3. A transmit can require several elements;
58 * a receive requires one (or two if using 64 bit dma).
59 */
60
61 #define RX_LE_SIZE 512
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define ETH_JUMBO_MTU 9000
76 #define TX_WATCHDOG (5 * HZ)
77
78 #define PHY_RETRIES 1000
79
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86
87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
91 static int copybreak = 256;
92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
95 static const struct pci_device_id sky2_id_table[] = {
96 { PCI_DEVICE(0x1148, 0x9000) },
97 { PCI_DEVICE(0x1148, 0x9E00) },
98 { PCI_DEVICE(0x1186, 0x4b00) }, /* DGE-560T */
99 { PCI_DEVICE(0x11ab, 0x4340) },
100 { PCI_DEVICE(0x11ab, 0x4341) },
101 { PCI_DEVICE(0x11ab, 0x4342) },
102 { PCI_DEVICE(0x11ab, 0x4343) },
103 { PCI_DEVICE(0x11ab, 0x4344) },
104 { PCI_DEVICE(0x11ab, 0x4345) },
105 { PCI_DEVICE(0x11ab, 0x4346) },
106 { PCI_DEVICE(0x11ab, 0x4347) },
107 { PCI_DEVICE(0x11ab, 0x4350) },
108 { PCI_DEVICE(0x11ab, 0x4351) },
109 { PCI_DEVICE(0x11ab, 0x4352) },
110 { PCI_DEVICE(0x11ab, 0x4360) },
111 { PCI_DEVICE(0x11ab, 0x4361) },
112 { PCI_DEVICE(0x11ab, 0x4362) },
113 { PCI_DEVICE(0x11ab, 0x4363) },
114 { PCI_DEVICE(0x11ab, 0x4364) },
115 { PCI_DEVICE(0x11ab, 0x4365) },
116 { PCI_DEVICE(0x11ab, 0x4366) },
117 { PCI_DEVICE(0x11ab, 0x4367) },
118 { PCI_DEVICE(0x11ab, 0x4368) },
119 { 0 }
120 };
121
122 MODULE_DEVICE_TABLE(pci, sky2_id_table);
123
124 /* Avoid conditionals by using array */
125 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
126 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
127 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
128
129 /* This driver supports yukon2 chipset only */
130 static const char *yukon2_name[] = {
131 "XL", /* 0xb3 */
132 "EC Ultra", /* 0xb4 */
133 "UNKNOWN", /* 0xb5 */
134 "EC", /* 0xb6 */
135 "FE", /* 0xb7 */
136 };
137
138 /* Access to external PHY */
gm_phy_write(struct sky2_hw * hw,unsigned port,u16 reg,u16 val)139 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
140 {
141 int i;
142
143 gma_write16(hw, port, GM_SMI_DATA, val);
144 gma_write16(hw, port, GM_SMI_CTRL,
145 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
146
147 for (i = 0; i < PHY_RETRIES; i++) {
148 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
149 return 0;
150 udelay(1);
151 }
152
153 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
154 return -ETIMEDOUT;
155 }
156
__gm_phy_read(struct sky2_hw * hw,unsigned port,u16 reg,u16 * val)157 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
158 {
159 int i;
160
161 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
162 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
163
164 for (i = 0; i < PHY_RETRIES; i++) {
165 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
166 *val = gma_read16(hw, port, GM_SMI_DATA);
167 return 0;
168 }
169
170 udelay(1);
171 }
172
173 return -ETIMEDOUT;
174 }
175
gm_phy_read(struct sky2_hw * hw,unsigned port,u16 reg)176 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
177 {
178 u16 v;
179
180 if (__gm_phy_read(hw, port, reg, &v) != 0)
181 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
182 return v;
183 }
184
sky2_set_power_state(struct sky2_hw * hw,pci_power_t state)185 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
186 {
187 u16 power_control;
188 u32 reg1;
189 int vaux;
190
191 pr_debug("sky2_set_power_state %d\n", state);
192 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
193
194 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
195 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
196 (power_control & PCI_PM_CAP_PME_D3cold);
197
198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
199
200 power_control |= PCI_PM_CTRL_PME_STATUS;
201 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
202
203 switch (state) {
204 case PCI_D0:
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw, B0_POWER_CTRL,
207 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
208
209 /* disable Core Clock Division, */
210 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
211
212 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
213 /* enable bits are inverted */
214 sky2_write8(hw, B2_Y2_CLK_GATE,
215 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
216 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
217 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 else
219 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
220
221 /* Turn off phy power saving */
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
223 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
224
225 /* looks like this XL is back asswards .. */
226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
227 reg1 |= PCI_Y2_PHY1_COMA;
228 if (hw->ports > 1)
229 reg1 |= PCI_Y2_PHY2_COMA;
230 }
231
232 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
235 reg1 &= P_ASPM_CONTROL_MSK;
236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
238 }
239
240 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
241 udelay(100);
242
243 break;
244
245 case PCI_D3hot:
246 case PCI_D3cold:
247 /* Turn on phy power saving */
248 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
251 else
252 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
253 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
254 udelay(100);
255
256 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
257 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
258 else
259 /* enable bits are inverted */
260 sky2_write8(hw, B2_Y2_CLK_GATE,
261 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
262 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
263 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
264
265 /* switch power to VAUX */
266 if (vaux && state != PCI_D3cold)
267 sky2_write8(hw, B0_POWER_CTRL,
268 (PC_VAUX_ENA | PC_VCC_ENA |
269 PC_VAUX_ON | PC_VCC_OFF));
270 break;
271 default:
272 printk(KERN_ERR PFX "Unknown power state %d\n", state);
273 }
274
275 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
276 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
277 }
278
sky2_phy_reset(struct sky2_hw * hw,unsigned port)279 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
280 {
281 u16 reg;
282
283 /* disable all GMAC IRQ's */
284 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
285 /* disable PHY IRQs */
286 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
287
288 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
289 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
290 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
291 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
292
293 reg = gma_read16(hw, port, GM_RX_CTRL);
294 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
295 gma_write16(hw, port, GM_RX_CTRL, reg);
296 }
297
sky2_phy_init(struct sky2_hw * hw,unsigned port)298 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
299 {
300 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
301 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
302
303 if (sky2->autoneg == AUTONEG_ENABLE &&
304 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
305 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
306
307 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
308 PHY_M_EC_MAC_S_MSK);
309 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
310
311 if (hw->chip_id == CHIP_ID_YUKON_EC)
312 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
313 else
314 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
315
316 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
317 }
318
319 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
320 if (hw->copper) {
321 if (hw->chip_id == CHIP_ID_YUKON_FE) {
322 /* enable automatic crossover */
323 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
324 } else {
325 /* disable energy detect */
326 ctrl &= ~PHY_M_PC_EN_DET_MSK;
327
328 /* enable automatic crossover */
329 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
330
331 if (sky2->autoneg == AUTONEG_ENABLE &&
332 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
333 ctrl &= ~PHY_M_PC_DSC_MSK;
334 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
335 }
336 }
337 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338 } else {
339 /* workaround for deviation #4.88 (CRC errors) */
340 /* disable Automatic Crossover */
341
342 ctrl &= ~PHY_M_PC_MDIX_MSK;
343 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
344
345 if (hw->chip_id == CHIP_ID_YUKON_XL) {
346 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
348 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
349 ctrl &= ~PHY_M_MAC_MD_MSK;
350 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
351 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
352
353 /* select page 1 to access Fiber registers */
354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
355 }
356 }
357
358 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
359 if (sky2->autoneg == AUTONEG_DISABLE)
360 ctrl &= ~PHY_CT_ANE;
361 else
362 ctrl |= PHY_CT_ANE;
363
364 ctrl |= PHY_CT_RESET;
365 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
366
367 ctrl = 0;
368 ct1000 = 0;
369 adv = PHY_AN_CSMA;
370
371 if (sky2->autoneg == AUTONEG_ENABLE) {
372 if (hw->copper) {
373 if (sky2->advertising & ADVERTISED_1000baseT_Full)
374 ct1000 |= PHY_M_1000C_AFD;
375 if (sky2->advertising & ADVERTISED_1000baseT_Half)
376 ct1000 |= PHY_M_1000C_AHD;
377 if (sky2->advertising & ADVERTISED_100baseT_Full)
378 adv |= PHY_M_AN_100_FD;
379 if (sky2->advertising & ADVERTISED_100baseT_Half)
380 adv |= PHY_M_AN_100_HD;
381 if (sky2->advertising & ADVERTISED_10baseT_Full)
382 adv |= PHY_M_AN_10_FD;
383 if (sky2->advertising & ADVERTISED_10baseT_Half)
384 adv |= PHY_M_AN_10_HD;
385 } else /* special defines for FIBER (88E1011S only) */
386 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
387
388 /* Set Flow-control capabilities */
389 if (sky2->tx_pause && sky2->rx_pause)
390 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
391 else if (sky2->rx_pause && !sky2->tx_pause)
392 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
393 else if (!sky2->rx_pause && sky2->tx_pause)
394 adv |= PHY_AN_PAUSE_ASYM; /* local */
395
396 /* Restart Auto-negotiation */
397 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
398 } else {
399 /* forced speed/duplex settings */
400 ct1000 = PHY_M_1000C_MSE;
401
402 if (sky2->duplex == DUPLEX_FULL)
403 ctrl |= PHY_CT_DUP_MD;
404
405 switch (sky2->speed) {
406 case SPEED_1000:
407 ctrl |= PHY_CT_SP1000;
408 break;
409 case SPEED_100:
410 ctrl |= PHY_CT_SP100;
411 break;
412 }
413
414 ctrl |= PHY_CT_RESET;
415 }
416
417 if (hw->chip_id != CHIP_ID_YUKON_FE)
418 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
419
420 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
421 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
422
423 /* Setup Phy LED's */
424 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
425 ledover = 0;
426
427 switch (hw->chip_id) {
428 case CHIP_ID_YUKON_FE:
429 /* on 88E3082 these bits are at 11..9 (shifted left) */
430 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
431
432 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
433
434 /* delete ACT LED control bits */
435 ctrl &= ~PHY_M_FELP_LED1_MSK;
436 /* change ACT LED control to blink mode */
437 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
438 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
439 break;
440
441 case CHIP_ID_YUKON_XL:
442 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
443
444 /* select page 3 to access LED control register */
445 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
446
447 /* set LED Function Control register */
448 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
449 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
450 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
451 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
452 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
453
454 /* set Polarity Control register */
455 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
456 (PHY_M_POLC_LS1_P_MIX(4) |
457 PHY_M_POLC_IS0_P_MIX(4) |
458 PHY_M_POLC_LOS_CTRL(2) |
459 PHY_M_POLC_INIT_CTRL(2) |
460 PHY_M_POLC_STA1_CTRL(2) |
461 PHY_M_POLC_STA0_CTRL(2)));
462
463 /* restore page register */
464 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
465 break;
466 case CHIP_ID_YUKON_EC_U:
467 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
468
469 /* select page 3 to access LED control register */
470 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
471
472 /* set LED Function Control register */
473 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
474 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
475 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
476 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
477 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
478
479 /* set Blink Rate in LED Timer Control Register */
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
481 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
482 /* restore page register */
483 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
484 break;
485
486 default:
487 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
488 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
489 /* turn off the Rx LED (LED_RX) */
490 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
491 }
492
493 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
494 /* apply fixes in PHY AFE */
495 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
496 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
497
498 /* increase differential signal amplitude in 10BASE-T */
499 gm_phy_write(hw, port, 0x18, 0xaa99);
500 gm_phy_write(hw, port, 0x17, 0x2011);
501
502 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
503 gm_phy_write(hw, port, 0x18, 0xa204);
504 gm_phy_write(hw, port, 0x17, 0x2002);
505
506 /* set page register to 0 */
507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
508 } else {
509 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
510
511 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
512 /* turn on 100 Mbps LED (LED_LINK100) */
513 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
514 }
515
516 if (ledover)
517 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
518
519 }
520 /* Enable phy interrupt on auto-negotiation complete (or link up) */
521 if (sky2->autoneg == AUTONEG_ENABLE)
522 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
523 else
524 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
525 }
526
527 /* Force a renegotiation */
sky2_phy_reinit(struct sky2_port * sky2)528 static void sky2_phy_reinit(struct sky2_port *sky2)
529 {
530 spin_lock_bh(&sky2->phy_lock);
531 sky2_phy_init(sky2->hw, sky2->port);
532 spin_unlock_bh(&sky2->phy_lock);
533 }
534
sky2_mac_init(struct sky2_hw * hw,unsigned port)535 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
536 {
537 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
538 u16 reg;
539 int i;
540 const u8 *addr = hw->dev[port]->dev_addr;
541
542 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
543 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
544
545 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
546
547 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
548 /* WA DEV_472 -- looks like crossed wires on port 2 */
549 /* clear GMAC 1 Control reset */
550 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
551 do {
552 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
553 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
554 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
555 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
556 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
557 }
558
559 if (sky2->autoneg == AUTONEG_DISABLE) {
560 reg = gma_read16(hw, port, GM_GP_CTRL);
561 reg |= GM_GPCR_AU_ALL_DIS;
562 gma_write16(hw, port, GM_GP_CTRL, reg);
563 gma_read16(hw, port, GM_GP_CTRL);
564
565 switch (sky2->speed) {
566 case SPEED_1000:
567 reg &= ~GM_GPCR_SPEED_100;
568 reg |= GM_GPCR_SPEED_1000;
569 break;
570 case SPEED_100:
571 reg &= ~GM_GPCR_SPEED_1000;
572 reg |= GM_GPCR_SPEED_100;
573 break;
574 case SPEED_10:
575 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
576 break;
577 }
578
579 if (sky2->duplex == DUPLEX_FULL)
580 reg |= GM_GPCR_DUP_FULL;
581
582 /* turn off pause in 10/100mbps half duplex */
583 else if (sky2->speed != SPEED_1000 &&
584 hw->chip_id != CHIP_ID_YUKON_EC_U)
585 sky2->tx_pause = sky2->rx_pause = 0;
586 } else
587 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
588
589 if (!sky2->tx_pause && !sky2->rx_pause) {
590 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
591 reg |=
592 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
593 } else if (sky2->tx_pause && !sky2->rx_pause) {
594 /* disable Rx flow-control */
595 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
596 }
597
598 gma_write16(hw, port, GM_GP_CTRL, reg);
599
600 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
601
602 spin_lock_bh(&sky2->phy_lock);
603 sky2_phy_init(hw, port);
604 spin_unlock_bh(&sky2->phy_lock);
605
606 /* MIB clear */
607 reg = gma_read16(hw, port, GM_PHY_ADDR);
608 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
609
610 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
611 gma_read16(hw, port, i);
612 gma_write16(hw, port, GM_PHY_ADDR, reg);
613
614 /* transmit control */
615 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
616
617 /* receive control reg: unicast + multicast + no FCS */
618 gma_write16(hw, port, GM_RX_CTRL,
619 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
620
621 /* transmit flow control */
622 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
623
624 /* transmit parameter */
625 gma_write16(hw, port, GM_TX_PARAM,
626 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
627 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
628 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
629 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
630
631 /* serial mode register */
632 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
633 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
634
635 if (hw->dev[port]->mtu > ETH_DATA_LEN)
636 reg |= GM_SMOD_JUMBO_ENA;
637
638 gma_write16(hw, port, GM_SERIAL_MODE, reg);
639
640 /* virtual address for data */
641 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
642
643 /* physical address: used for pause frames */
644 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
645
646 /* ignore counter overflows */
647 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
648 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
649 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
650
651 /* Configure Rx MAC FIFO */
652 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
653 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
654 GMF_OPER_ON | GMF_RX_F_FL_ON);
655
656 /* Flush Rx MAC FIFO on any flow control or error */
657 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
658
659 /* Set threshold to 0xa (64 bytes)
660 * ASF disabled so no need to do WA dev #4.30
661 */
662 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
663
664 /* Configure Tx MAC FIFO */
665 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
666 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
667
668 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
669 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
670 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
671 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
672 /* set Tx GMAC FIFO Almost Empty Threshold */
673 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
674 /* Disable Store & Forward mode for TX */
675 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
676 }
677 }
678
679 }
680
681 /* Assign Ram Buffer allocation.
682 * start and end are in units of 4k bytes
683 * ram registers are in units of 64bit words
684 */
sky2_ramset(struct sky2_hw * hw,u16 q,u8 startk,u8 endk)685 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
686 {
687 u32 start, end;
688
689 start = startk * 4096/8;
690 end = (endk * 4096/8) - 1;
691
692 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
693 sky2_write32(hw, RB_ADDR(q, RB_START), start);
694 sky2_write32(hw, RB_ADDR(q, RB_END), end);
695 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
696 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
697
698 if (q == Q_R1 || q == Q_R2) {
699 u32 space = (endk - startk) * 4096/8;
700 u32 tp = space - space/4;
701
702 /* On receive queue's set the thresholds
703 * give receiver priority when > 3/4 full
704 * send pause when down to 2K
705 */
706 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
707 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
708
709 tp = space - 2048/8;
710 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
711 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
712 } else {
713 /* Enable store & forward on Tx queue's because
714 * Tx FIFO is only 1K on Yukon
715 */
716 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
717 }
718
719 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
720 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
721 }
722
723 /* Setup Bus Memory Interface */
sky2_qset(struct sky2_hw * hw,u16 q)724 static void sky2_qset(struct sky2_hw *hw, u16 q)
725 {
726 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
727 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
728 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
729 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
730 }
731
732 /* Setup prefetch unit registers. This is the interface between
733 * hardware and driver list elements
734 */
sky2_prefetch_init(struct sky2_hw * hw,u32 qaddr,u64 addr,u32 last)735 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
736 u64 addr, u32 last)
737 {
738 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
739 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
740 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
741 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
742 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
744
745 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
746 }
747
get_tx_le(struct sky2_port * sky2)748 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
749 {
750 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
751
752 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
753 return le;
754 }
755
756 /* Update chip's next pointer */
sky2_put_idx(struct sky2_hw * hw,unsigned q,u16 idx)757 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
758 {
759 wmb();
760 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
761 sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX));
762 }
763
764
sky2_next_rx(struct sky2_port * sky2)765 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
766 {
767 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
768 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
769 return le;
770 }
771
772 /* Return high part of DMA address (could be 32 or 64 bit) */
high32(dma_addr_t a)773 static inline u32 high32(dma_addr_t a)
774 {
775 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
776 }
777
778 /* Build description to hardware about buffer */
sky2_rx_add(struct sky2_port * sky2,dma_addr_t map)779 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
780 {
781 struct sky2_rx_le *le;
782 u32 hi = high32(map);
783 u16 len = sky2->rx_bufsize;
784
785 if (sky2->rx_addr64 != hi) {
786 le = sky2_next_rx(sky2);
787 le->addr = cpu_to_le32(hi);
788 le->ctrl = 0;
789 le->opcode = OP_ADDR64 | HW_OWNER;
790 sky2->rx_addr64 = high32(map + len);
791 }
792
793 le = sky2_next_rx(sky2);
794 le->addr = cpu_to_le32((u32) map);
795 le->length = cpu_to_le16(len);
796 le->ctrl = 0;
797 le->opcode = OP_PACKET | HW_OWNER;
798 }
799
800
801 /* Tell chip where to start receive checksum.
802 * Actually has two checksums, but set both same to avoid possible byte
803 * order problems.
804 */
rx_set_checksum(struct sky2_port * sky2)805 static void rx_set_checksum(struct sky2_port *sky2)
806 {
807 struct sky2_rx_le *le;
808
809 le = sky2_next_rx(sky2);
810 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
811 le->ctrl = 0;
812 le->opcode = OP_TCPSTART | HW_OWNER;
813
814 sky2_write32(sky2->hw,
815 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
816 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
817
818 }
819
820 /*
821 * The RX Stop command will not work for Yukon-2 if the BMU does not
822 * reach the end of packet and since we can't make sure that we have
823 * incoming data, we must reset the BMU while it is not doing a DMA
824 * transfer. Since it is possible that the RX path is still active,
825 * the RX RAM buffer will be stopped first, so any possible incoming
826 * data will not trigger a DMA. After the RAM buffer is stopped, the
827 * BMU is polled until any DMA in progress is ended and only then it
828 * will be reset.
829 */
sky2_rx_stop(struct sky2_port * sky2)830 static void sky2_rx_stop(struct sky2_port *sky2)
831 {
832 struct sky2_hw *hw = sky2->hw;
833 unsigned rxq = rxqaddr[sky2->port];
834 int i;
835
836 /* disable the RAM Buffer receive queue */
837 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
838
839 for (i = 0; i < 0xffff; i++)
840 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
841 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
842 goto stopped;
843
844 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
845 sky2->netdev->name);
846 stopped:
847 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
848
849 /* reset the Rx prefetch unit */
850 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
851 }
852
853 /* Clean out receive buffer area, assumes receiver hardware stopped */
sky2_rx_clean(struct sky2_port * sky2)854 static void sky2_rx_clean(struct sky2_port *sky2)
855 {
856 unsigned i;
857
858 memset(sky2->rx_le, 0, RX_LE_BYTES);
859 for (i = 0; i < sky2->rx_pending; i++) {
860 struct ring_info *re = sky2->rx_ring + i;
861
862 if (re->skb) {
863 pci_unmap_single(sky2->hw->pdev,
864 re->mapaddr, sky2->rx_bufsize,
865 PCI_DMA_FROMDEVICE);
866 kfree_skb(re->skb);
867 re->skb = NULL;
868 }
869 }
870 }
871
872 /* Basic MII support */
sky2_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)873 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
874 {
875 struct mii_ioctl_data *data;
876 struct sky2_port *sky2 = netdev_priv(dev);
877 struct sky2_hw *hw = sky2->hw;
878 int err = -EOPNOTSUPP;
879
880 if (!netif_running(dev))
881 return -ENODEV; /* Phy still in reset */
882
883 data = (struct mii_ioctl_data *) &ifr->ifr_ifru;
884 switch (cmd) {
885 case SIOCGMIIPHY:
886 data->phy_id = PHY_ADDR_MARV;
887
888 /* fallthru */
889 case SIOCGMIIREG: {
890 u16 val = 0;
891
892 spin_lock_bh(&sky2->phy_lock);
893 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
894 spin_unlock_bh(&sky2->phy_lock);
895
896 data->val_out = val;
897 break;
898 }
899
900 case SIOCSMIIREG:
901 if (!capable(CAP_NET_ADMIN))
902 return -EPERM;
903
904 spin_lock_bh(&sky2->phy_lock);
905 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
906 data->val_in);
907 spin_unlock_bh(&sky2->phy_lock);
908 break;
909 }
910 return err;
911 }
912
913
914 /*
915 * It appears the hardware has a bug in the FIFO logic that
916 * cause it to hang if the FIFO gets overrun and the receive buffer
917 * is not aligned. Also alloc_skb() won't align properly if slab
918 * debugging is enabled.
919 */
sky2_alloc_skb(unsigned int size)920 static inline struct sk_buff *sky2_alloc_skb(unsigned int size)
921 {
922 struct sk_buff *skb;
923
924 skb = alloc_skb(size + RX_SKB_ALIGN, GFP_ATOMIC);
925 if (likely(skb != NULL)) {
926 unsigned long p = (unsigned long) skb->data;
927 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
928 }
929
930 return skb;
931 }
932
933 /*
934 * Allocate and setup receiver buffer pool.
935 * In case of 64 bit dma, there are 2X as many list elements
936 * available as ring entries
937 * and need to reserve one list element so we don't wrap around.
938 */
sky2_rx_start(struct sky2_port * sky2)939 static int sky2_rx_start(struct sky2_port *sky2)
940 {
941 struct sky2_hw *hw = sky2->hw;
942 unsigned rxq = rxqaddr[sky2->port];
943 int i;
944 unsigned thresh;
945
946 sky2->rx_put = sky2->rx_next = 0;
947 sky2_qset(hw, rxq);
948
949 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
950 /* MAC Rx RAM Read is controlled by hardware */
951 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
952 }
953
954 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
955
956 rx_set_checksum(sky2);
957 for (i = 0; i < sky2->rx_pending; i++) {
958 struct ring_info *re = sky2->rx_ring + i;
959
960 re->skb = sky2_alloc_skb(sky2->rx_bufsize);
961 if (!re->skb)
962 goto nomem;
963
964 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
965 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
966 sky2_rx_add(sky2, re->mapaddr);
967 }
968
969
970 /*
971 * The receiver hangs if it receives frames larger than the
972 * packet buffer. As a workaround, truncate oversize frames, but
973 * the register is limited to 9 bits, so if you do frames > 2052
974 * you better get the MTU right!
975 */
976 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
977 if (thresh > 0x1ff)
978 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
979 else {
980 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
981 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
982 }
983
984
985 /* Tell chip about available buffers */
986 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
987 return 0;
988 nomem:
989 sky2_rx_clean(sky2);
990 return -ENOMEM;
991 }
992
993 /* Bring up network interface. */
sky2_up(struct net_device * dev)994 static int sky2_up(struct net_device *dev)
995 {
996 struct sky2_port *sky2 = netdev_priv(dev);
997 struct sky2_hw *hw = sky2->hw;
998 unsigned port = sky2->port;
999 u32 ramsize, rxspace, imask;
1000 int cap, err = -ENOMEM;
1001 struct net_device *otherdev = hw->dev[sky2->port^1];
1002
1003 /*
1004 * On dual port PCI-X card, there is an problem where status
1005 * can be received out of order due to split transactions
1006 */
1007 if (otherdev && netif_running(otherdev) &&
1008 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1009 struct sky2_port *osky2 = netdev_priv(otherdev);
1010 u16 cmd;
1011
1012 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1013 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1014 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1015
1016 sky2->rx_csum = 0;
1017 osky2->rx_csum = 0;
1018 }
1019
1020 if (netif_msg_ifup(sky2))
1021 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1022
1023 /* must be power of 2 */
1024 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1025 TX_RING_SIZE *
1026 sizeof(struct sky2_tx_le),
1027 &sky2->tx_le_map);
1028 if (!sky2->tx_le)
1029 goto err_out;
1030
1031 sky2->tx_ring = kmalloc(TX_RING_SIZE * sizeof(struct tx_ring_info),
1032 GFP_KERNEL);
1033 if (!sky2->tx_ring)
1034 goto err_out;
1035 memset(sky2->tx_ring, 0, TX_RING_SIZE * sizeof(struct tx_ring_info));
1036 sky2->tx_prod = sky2->tx_cons = 0;
1037
1038 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1039 &sky2->rx_le_map);
1040 if (!sky2->rx_le)
1041 goto err_out;
1042 memset(sky2->rx_le, 0, RX_LE_BYTES);
1043
1044 sky2->rx_ring = kmalloc(sky2->rx_pending * sizeof(struct ring_info),
1045 GFP_KERNEL);
1046 if (!sky2->rx_ring)
1047 goto err_out;
1048
1049 memset(sky2->rx_ring, 0, sky2->rx_pending * sizeof(struct ring_info));
1050 sky2_mac_init(hw, port);
1051
1052 /* Determine available ram buffer space (in 4K blocks).
1053 * Note: not sure about the FE setting below yet
1054 */
1055 if (hw->chip_id == CHIP_ID_YUKON_FE)
1056 ramsize = 4;
1057 else
1058 ramsize = sky2_read8(hw, B2_E_0);
1059
1060 /* Give transmitter one third (rounded up) */
1061 rxspace = ramsize - (ramsize + 2) / 3;
1062
1063 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1064 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1065
1066 /* Make sure SyncQ is disabled */
1067 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1068 RB_RST_SET);
1069
1070 sky2_qset(hw, txqaddr[port]);
1071
1072 /* Set almost empty threshold */
1073 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1074 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1075
1076 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1077 TX_RING_SIZE - 1);
1078
1079 err = sky2_rx_start(sky2);
1080 if (err)
1081 goto err_out;
1082
1083 /* Enable interrupts from phy/mac for port */
1084 imask = sky2_read32(hw, B0_IMSK);
1085 imask |= portirq_msk[port];
1086 sky2_write32(hw, B0_IMSK, imask);
1087
1088 return 0;
1089
1090 err_out:
1091 if (sky2->rx_le) {
1092 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1093 sky2->rx_le, sky2->rx_le_map);
1094 sky2->rx_le = NULL;
1095 }
1096 if (sky2->tx_le) {
1097 pci_free_consistent(hw->pdev,
1098 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1099 sky2->tx_le, sky2->tx_le_map);
1100 sky2->tx_le = NULL;
1101 }
1102 kfree(sky2->tx_ring);
1103 kfree(sky2->rx_ring);
1104
1105 sky2->tx_ring = NULL;
1106 sky2->rx_ring = NULL;
1107 return err;
1108 }
1109
1110 /* Modular subtraction in ring */
tx_dist(unsigned tail,unsigned head)1111 static inline int tx_dist(unsigned tail, unsigned head)
1112 {
1113 return (head - tail) & (TX_RING_SIZE - 1);
1114 }
1115
1116 /* Number of list elements available for next tx */
tx_avail(const struct sky2_port * sky2)1117 static inline int tx_avail(const struct sky2_port *sky2)
1118 {
1119 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1120 }
1121
1122 /* Estimate of number of transmit list elements required */
tx_le_req(const struct sk_buff * skb)1123 static inline unsigned tx_le_req(const struct sk_buff *skb)
1124 {
1125 unsigned count;
1126
1127 count = sizeof(dma_addr_t) / sizeof(u32);
1128 count += skb_shinfo(skb)->nr_frags * count;
1129
1130 #ifdef NETIF_F_TSO
1131 if (skb_shinfo(skb)->tso_size)
1132 ++count;
1133 #endif
1134
1135 if (skb->ip_summed == CHECKSUM_HW)
1136 ++count;
1137
1138 return count;
1139 }
1140
1141 /*
1142 * Put one packet in ring for transmit.
1143 * A single packet can generate multiple list elements, and
1144 * the number of ring elements will probably be less than the number
1145 * of list elements used.
1146 *
1147 * No BH disabling for tx_lock here (like tg3)
1148 */
sky2_xmit_frame(struct sk_buff * skb,struct net_device * dev)1149 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1150 {
1151 struct sky2_port *sky2 = netdev_priv(dev);
1152 struct sky2_hw *hw = sky2->hw;
1153 struct sky2_tx_le *le = NULL;
1154 struct tx_ring_info *re;
1155 unsigned long flags;
1156 unsigned i, len;
1157 int avail;
1158 dma_addr_t mapping;
1159 u32 addr64;
1160 u16 mss = 0;
1161 u8 ctrl;
1162
1163 spin_lock_irqsave(&sky2->tx_lock, flags);
1164
1165 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1166 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1167 return NETDEV_TX_BUSY;
1168 }
1169
1170 if (unlikely(netif_msg_tx_queued(sky2)))
1171 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1172 dev->name, sky2->tx_prod, skb->len);
1173
1174 len = skb_headlen(skb);
1175 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1176 addr64 = high32(mapping);
1177
1178 re = sky2->tx_ring + sky2->tx_prod;
1179
1180 /* Send high bits if changed or crosses boundary */
1181 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1182 le = get_tx_le(sky2);
1183 le->tx.addr = cpu_to_le32(addr64);
1184 le->ctrl = 0;
1185 le->opcode = OP_ADDR64 | HW_OWNER;
1186 sky2->tx_addr64 = high32(mapping + len);
1187 }
1188
1189 #ifdef NETIF_F_TSO
1190 /* Check for TCP Segmentation Offload */
1191 mss = skb_shinfo(skb)->tso_size;
1192 if (mss != 0) {
1193 #ifdef SKB_DATAREF_MASK
1194 /* just drop the packet if non-linear expansion fails */
1195 if (skb_header_cloned(skb) &&
1196 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1197 dev_kfree_skb(skb);
1198 goto out_unlock;
1199 }
1200 #endif
1201 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1202 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1203 mss += ETH_HLEN;
1204 }
1205
1206 if (mss != sky2->tx_last_mss) {
1207 le = get_tx_le(sky2);
1208 le->tx.tso.size = cpu_to_le16(mss);
1209 le->tx.tso.rsvd = 0;
1210 le->opcode = OP_LRGLEN | HW_OWNER;
1211 le->ctrl = 0;
1212 sky2->tx_last_mss = mss;
1213 }
1214 #endif
1215
1216 ctrl = 0;
1217
1218 /* Handle TCP checksum offload */
1219 if (skb->ip_summed == CHECKSUM_HW) {
1220 u16 hdr = skb->h.raw - skb->data;
1221 u16 offset = hdr + skb->csum;
1222
1223 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1224 if (skb->nh.iph->protocol == IPPROTO_UDP)
1225 ctrl |= UDPTCP;
1226
1227 le = get_tx_le(sky2);
1228 le->tx.csum.start = cpu_to_le16(hdr);
1229 le->tx.csum.offset = cpu_to_le16(offset);
1230 le->length = 0; /* initial checksum value */
1231 le->ctrl = 1; /* one packet */
1232 le->opcode = OP_TCPLISW | HW_OWNER;
1233 }
1234
1235 le = get_tx_le(sky2);
1236 le->tx.addr = cpu_to_le32((u32) mapping);
1237 le->length = cpu_to_le16(len);
1238 le->ctrl = ctrl;
1239 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1240
1241 /* Record the transmit mapping info */
1242 re->skb = skb;
1243 pci_unmap_addr_set(re, mapaddr, mapping);
1244
1245 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1246 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1247 struct tx_ring_info *fre;
1248
1249 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1250 frag->size, PCI_DMA_TODEVICE);
1251 addr64 = high32(mapping);
1252 if (addr64 != sky2->tx_addr64) {
1253 le = get_tx_le(sky2);
1254 le->tx.addr = cpu_to_le32(addr64);
1255 le->ctrl = 0;
1256 le->opcode = OP_ADDR64 | HW_OWNER;
1257 sky2->tx_addr64 = addr64;
1258 }
1259
1260 le = get_tx_le(sky2);
1261 le->tx.addr = cpu_to_le32((u32) mapping);
1262 le->length = cpu_to_le16(frag->size);
1263 le->ctrl = ctrl;
1264 le->opcode = OP_BUFFER | HW_OWNER;
1265
1266 fre = sky2->tx_ring
1267 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1268 pci_unmap_addr_set(fre, mapaddr, mapping);
1269 }
1270
1271 re->idx = sky2->tx_prod;
1272 le->ctrl |= EOP;
1273
1274 avail = tx_avail(sky2);
1275 if (mss != 0 || avail < TX_MIN_PENDING) {
1276 le->ctrl |= FRC_STAT;
1277 if (avail <= MAX_SKB_TX_LE)
1278 netif_stop_queue(dev);
1279 }
1280
1281 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1282
1283 out_unlock:
1284 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1285
1286 dev->trans_start = jiffies;
1287 return NETDEV_TX_OK;
1288 }
1289
1290 /*
1291 * Free ring elements from starting at tx_cons until "done"
1292 *
1293 * NB: the hardware will tell us about partial completion of multi-part
1294 * buffers; these are deferred until completion.
1295 */
sky2_tx_complete(struct sky2_port * sky2,u16 done)1296 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1297 {
1298 struct net_device *dev = sky2->netdev;
1299 struct pci_dev *pdev = sky2->hw->pdev;
1300 u16 nxt, put;
1301 unsigned i;
1302
1303 BUG_ON(done >= TX_RING_SIZE);
1304
1305 if (unlikely(netif_msg_tx_done(sky2)))
1306 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1307 dev->name, done);
1308
1309 for (put = sky2->tx_cons; put != done; put = nxt) {
1310 struct tx_ring_info *re = sky2->tx_ring + put;
1311 struct sk_buff *skb = re->skb;
1312
1313 nxt = re->idx;
1314 BUG_ON(nxt >= TX_RING_SIZE);
1315 prefetch(sky2->tx_ring + nxt);
1316
1317 /* Check for partial status */
1318 if (tx_dist(put, done) < tx_dist(put, nxt))
1319 break;
1320
1321 skb = re->skb;
1322 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1323 skb_headlen(skb), PCI_DMA_TODEVICE);
1324
1325 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1326 struct tx_ring_info *fre;
1327 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
1328 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1329 skb_shinfo(skb)->frags[i].size,
1330 PCI_DMA_TODEVICE);
1331 }
1332
1333 dev_kfree_skb_any(skb);
1334 }
1335
1336 sky2->tx_cons = put;
1337 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1338 netif_wake_queue(dev);
1339 }
1340
1341 /* Cleanup all untransmitted buffers, assume transmitter not running */
sky2_tx_clean(struct sky2_port * sky2)1342 static void sky2_tx_clean(struct sky2_port *sky2)
1343 {
1344 spin_lock_bh(&sky2->tx_lock);
1345 sky2_tx_complete(sky2, sky2->tx_prod);
1346 spin_unlock_bh(&sky2->tx_lock);
1347 }
1348
1349 /* Network shutdown */
sky2_down(struct net_device * dev)1350 static int sky2_down(struct net_device *dev)
1351 {
1352 struct sky2_port *sky2 = netdev_priv(dev);
1353 struct sky2_hw *hw = sky2->hw;
1354 unsigned port = sky2->port;
1355 u16 ctrl;
1356 u32 imask;
1357
1358 /* Never really got started! */
1359 if (!sky2->tx_le)
1360 return 0;
1361
1362 if (netif_msg_ifdown(sky2))
1363 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1364
1365 /* Stop more packets from being queued */
1366 netif_stop_queue(dev);
1367
1368 sky2_phy_reset(hw, port);
1369
1370 /* Stop transmitter */
1371 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1372 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1373
1374 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1375 RB_RST_SET | RB_DIS_OP_MD);
1376
1377 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1378 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1379 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1380
1381 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1382
1383 /* Workaround shared GMAC reset */
1384 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1385 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1386 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1387
1388 /* Disable Force Sync bit and Enable Alloc bit */
1389 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1390 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1391
1392 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1393 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1394 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1395
1396 /* Reset the PCI FIFO of the async Tx queue */
1397 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1398 BMU_RST_SET | BMU_FIFO_RST);
1399
1400 /* Reset the Tx prefetch units */
1401 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1402 PREF_UNIT_RST_SET);
1403
1404 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1405
1406 sky2_rx_stop(sky2);
1407
1408 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1409 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1410
1411 /* Disable port IRQ */
1412 imask = sky2_read32(hw, B0_IMSK);
1413 imask &= ~portirq_msk[port];
1414 sky2_write32(hw, B0_IMSK, imask);
1415
1416 /* turn off LED's */
1417 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1418
1419 sky2_tx_clean(sky2);
1420 sky2_rx_clean(sky2);
1421
1422 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1423 sky2->rx_le, sky2->rx_le_map);
1424 kfree(sky2->rx_ring);
1425
1426 pci_free_consistent(hw->pdev,
1427 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1428 sky2->tx_le, sky2->tx_le_map);
1429 kfree(sky2->tx_ring);
1430
1431 sky2->tx_le = NULL;
1432 sky2->rx_le = NULL;
1433
1434 sky2->rx_ring = NULL;
1435 sky2->tx_ring = NULL;
1436
1437 return 0;
1438 }
1439
sky2_phy_speed(const struct sky2_hw * hw,u16 aux)1440 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1441 {
1442 if (!hw->copper)
1443 return SPEED_1000;
1444
1445 if (hw->chip_id == CHIP_ID_YUKON_FE)
1446 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1447
1448 switch (aux & PHY_M_PS_SPEED_MSK) {
1449 case PHY_M_PS_SPEED_1000:
1450 return SPEED_1000;
1451 case PHY_M_PS_SPEED_100:
1452 return SPEED_100;
1453 default:
1454 return SPEED_10;
1455 }
1456 }
1457
sky2_link_up(struct sky2_port * sky2)1458 static void sky2_link_up(struct sky2_port *sky2)
1459 {
1460 struct sky2_hw *hw = sky2->hw;
1461 unsigned port = sky2->port;
1462 u16 reg;
1463
1464 /* Enable Transmit FIFO Underrun */
1465 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1466
1467 reg = gma_read16(hw, port, GM_GP_CTRL);
1468 if (sky2->autoneg == AUTONEG_DISABLE) {
1469 reg |= GM_GPCR_AU_ALL_DIS;
1470
1471 /* Is write/read necessary? Copied from sky2_mac_init */
1472 gma_write16(hw, port, GM_GP_CTRL, reg);
1473 gma_read16(hw, port, GM_GP_CTRL);
1474
1475 switch (sky2->speed) {
1476 case SPEED_1000:
1477 reg &= ~GM_GPCR_SPEED_100;
1478 reg |= GM_GPCR_SPEED_1000;
1479 break;
1480 case SPEED_100:
1481 reg &= ~GM_GPCR_SPEED_1000;
1482 reg |= GM_GPCR_SPEED_100;
1483 break;
1484 case SPEED_10:
1485 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1486 break;
1487 }
1488 } else
1489 reg &= ~GM_GPCR_AU_ALL_DIS;
1490
1491 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1492 reg |= GM_GPCR_DUP_FULL;
1493
1494 /* enable Rx/Tx */
1495 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1496 gma_write16(hw, port, GM_GP_CTRL, reg);
1497 gma_read16(hw, port, GM_GP_CTRL);
1498
1499 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1500
1501 netif_carrier_on(sky2->netdev);
1502 netif_wake_queue(sky2->netdev);
1503
1504 /* Turn on link LED */
1505 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1506 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1507
1508 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1509 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1510 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1511
1512 switch(sky2->speed) {
1513 case SPEED_10:
1514 led |= PHY_M_LEDC_INIT_CTRL(7);
1515 break;
1516
1517 case SPEED_100:
1518 led |= PHY_M_LEDC_STA1_CTRL(7);
1519 break;
1520
1521 case SPEED_1000:
1522 led |= PHY_M_LEDC_STA0_CTRL(7);
1523 break;
1524 }
1525
1526 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1529 }
1530
1531 if (netif_msg_link(sky2))
1532 printk(KERN_INFO PFX
1533 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1534 sky2->netdev->name, sky2->speed,
1535 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1536 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1537 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1538 }
1539
sky2_link_down(struct sky2_port * sky2)1540 static void sky2_link_down(struct sky2_port *sky2)
1541 {
1542 struct sky2_hw *hw = sky2->hw;
1543 unsigned port = sky2->port;
1544 u16 reg;
1545
1546 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1547
1548 reg = gma_read16(hw, port, GM_GP_CTRL);
1549 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1550 gma_write16(hw, port, GM_GP_CTRL, reg);
1551 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1552
1553 if (sky2->rx_pause && !sky2->tx_pause) {
1554 /* restore Asymmetric Pause bit */
1555 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1556 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1557 | PHY_M_AN_ASP);
1558 }
1559
1560 netif_carrier_off(sky2->netdev);
1561 netif_stop_queue(sky2->netdev);
1562
1563 /* Turn on link LED */
1564 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1565
1566 if (netif_msg_link(sky2))
1567 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1568 sky2_phy_init(hw, port);
1569 }
1570
sky2_autoneg_done(struct sky2_port * sky2,u16 aux)1571 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1572 {
1573 struct sky2_hw *hw = sky2->hw;
1574 unsigned port = sky2->port;
1575 u16 lpa;
1576
1577 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1578
1579 if (lpa & PHY_M_AN_RF) {
1580 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1581 return -1;
1582 }
1583
1584 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1585 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1586 printk(KERN_ERR PFX "%s: master/slave fault",
1587 sky2->netdev->name);
1588 return -1;
1589 }
1590
1591 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1592 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1593 sky2->netdev->name);
1594 return -1;
1595 }
1596
1597 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1598
1599 sky2->speed = sky2_phy_speed(hw, aux);
1600
1601 /* Pause bits are offset (9..8) */
1602 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1603 aux >>= 6;
1604
1605 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1606 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1607
1608 if ((sky2->tx_pause || sky2->rx_pause)
1609 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1610 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1611 else
1612 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1613
1614 return 0;
1615 }
1616
1617 /* Interrupt from PHY */
sky2_phy_intr(struct sky2_hw * hw,unsigned port)1618 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1619 {
1620 struct net_device *dev = hw->dev[port];
1621 struct sky2_port *sky2 = netdev_priv(dev);
1622 u16 istatus, phystat;
1623
1624 spin_lock(&sky2->phy_lock);
1625 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1626 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1627
1628 if (!netif_running(dev))
1629 goto out;
1630
1631 if (netif_msg_intr(sky2))
1632 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1633 sky2->netdev->name, istatus, phystat);
1634
1635 if (istatus & PHY_M_IS_AN_COMPL) {
1636 if (sky2_autoneg_done(sky2, phystat) == 0)
1637 sky2_link_up(sky2);
1638 goto out;
1639 }
1640
1641 if (istatus & PHY_M_IS_LSP_CHANGE)
1642 sky2->speed = sky2_phy_speed(hw, phystat);
1643
1644 if (istatus & PHY_M_IS_DUP_CHANGE)
1645 sky2->duplex =
1646 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1647
1648 if (istatus & PHY_M_IS_LST_CHANGE) {
1649 if (phystat & PHY_M_PS_LINK_UP)
1650 sky2_link_up(sky2);
1651 else
1652 sky2_link_down(sky2);
1653 }
1654 out:
1655 spin_unlock(&sky2->phy_lock);
1656 }
1657
1658
1659 /* Transmit timeout is only called if we are running, carries is up
1660 * and tx queue is full (stopped).
1661 */
sky2_tx_timeout(struct net_device * dev)1662 static void sky2_tx_timeout(struct net_device *dev)
1663 {
1664 struct sky2_port *sky2 = netdev_priv(dev);
1665 struct sky2_hw *hw = sky2->hw;
1666 unsigned txq = txqaddr[sky2->port];
1667 u16 report, done;
1668
1669 if (netif_msg_timer(sky2))
1670 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1671
1672 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1673 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1674
1675 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1676 dev->name,
1677 sky2->tx_cons, sky2->tx_prod, report, done);
1678
1679 if (report != done) {
1680 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1681
1682 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1683 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1684 } else if (report != sky2->tx_cons) {
1685 printk(KERN_INFO PFX "status report lost?\n");
1686
1687 spin_lock_bh(&sky2->tx_lock);
1688 sky2_tx_complete(sky2, report);
1689 spin_unlock_bh(&sky2->tx_lock);
1690 } else {
1691 printk(KERN_INFO PFX "hardware hung? flushing\n");
1692
1693 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1694 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1695
1696 sky2_tx_clean(sky2);
1697
1698 sky2_qset(hw, txq);
1699 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1700 }
1701 }
1702
1703
1704 /* Want receive buffer size to be multiple of 64 bits
1705 * and incl room for vlan and truncation
1706 */
sky2_buf_size(int mtu)1707 static inline unsigned sky2_buf_size(int mtu)
1708 {
1709 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1710 }
1711
sky2_change_mtu(struct net_device * dev,int new_mtu)1712 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1713 {
1714 struct sky2_port *sky2 = netdev_priv(dev);
1715 struct sky2_hw *hw = sky2->hw;
1716 int err;
1717 u16 ctl, mode;
1718 u32 imask;
1719
1720 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1721 return -EINVAL;
1722
1723 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1724 return -EINVAL;
1725
1726 if (!netif_running(dev)) {
1727 dev->mtu = new_mtu;
1728 return 0;
1729 }
1730
1731 imask = sky2_read32(hw, B0_IMSK);
1732 sky2_write32(hw, B0_IMSK, 0);
1733
1734 dev->trans_start = jiffies; /* prevent tx timeout */
1735 netif_stop_queue(dev);
1736
1737 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1738 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1739 sky2_rx_stop(sky2);
1740 sky2_rx_clean(sky2);
1741
1742 dev->mtu = new_mtu;
1743 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1744 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1745 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1746
1747 if (dev->mtu > ETH_DATA_LEN)
1748 mode |= GM_SMOD_JUMBO_ENA;
1749
1750 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1751
1752 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1753
1754 err = sky2_rx_start(sky2);
1755 sky2_write32(hw, B0_IMSK, imask);
1756
1757 if (err)
1758 dev_close(dev);
1759 else {
1760 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1761
1762 netif_wake_queue(dev);
1763 }
1764
1765 return err;
1766 }
1767
1768 /*
1769 * Receive one packet.
1770 * For small packets or errors, just reuse existing skb.
1771 * For larger packets, get new buffer.
1772 */
sky2_receive(struct sky2_port * sky2,u16 length,u32 status)1773 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1774 u16 length, u32 status)
1775 {
1776 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1777 struct sk_buff *skb = NULL;
1778
1779 if (unlikely(netif_msg_rx_status(sky2)))
1780 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1781 sky2->netdev->name, sky2->rx_next, status, length);
1782
1783 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1784 prefetch(sky2->rx_ring + sky2->rx_next);
1785
1786 if (status & GMR_FS_ANY_ERR)
1787 goto error;
1788
1789 if (!(status & GMR_FS_RX_OK))
1790 goto resubmit;
1791
1792 if (length > sky2->netdev->mtu + ETH_HLEN)
1793 goto oversize;
1794
1795 if (length < copybreak) {
1796 skb = alloc_skb(length + 2, GFP_ATOMIC);
1797 if (!skb)
1798 goto resubmit;
1799
1800 skb_reserve(skb, 2);
1801 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1802 length, PCI_DMA_FROMDEVICE);
1803 memcpy(skb->data, re->skb->data, length);
1804 skb->ip_summed = re->skb->ip_summed;
1805 skb->csum = re->skb->csum;
1806 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1807 length, PCI_DMA_FROMDEVICE);
1808 } else {
1809 struct sk_buff *nskb;
1810
1811 nskb = sky2_alloc_skb(sky2->rx_bufsize);
1812 if (!nskb)
1813 goto resubmit;
1814
1815 skb = re->skb;
1816 re->skb = nskb;
1817 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1818 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1819 prefetch(skb->data);
1820
1821 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1822 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1823 }
1824
1825 skb_put(skb, length);
1826 resubmit:
1827 re->skb->ip_summed = CHECKSUM_NONE;
1828 sky2_rx_add(sky2, re->mapaddr);
1829
1830 return skb;
1831
1832 oversize:
1833 ++sky2->net_stats.rx_over_errors;
1834 goto resubmit;
1835
1836 error:
1837 ++sky2->net_stats.rx_errors;
1838
1839 if (netif_msg_rx_err(sky2) && net_ratelimit())
1840 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1841 sky2->netdev->name, status, length);
1842
1843 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1844 sky2->net_stats.rx_length_errors++;
1845 if (status & GMR_FS_FRAGMENT)
1846 sky2->net_stats.rx_frame_errors++;
1847 if (status & GMR_FS_CRC_ERR)
1848 sky2->net_stats.rx_crc_errors++;
1849 if (status & GMR_FS_RX_FF_OV)
1850 sky2->net_stats.rx_fifo_errors++;
1851
1852 goto resubmit;
1853 }
1854
1855 /* Transmit complete */
sky2_tx_done(struct net_device * dev,u16 last)1856 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1857 {
1858 struct sky2_port *sky2 = netdev_priv(dev);
1859
1860 if (netif_running(dev)) {
1861 spin_lock(&sky2->tx_lock);
1862 sky2_tx_complete(sky2, last);
1863 spin_unlock(&sky2->tx_lock);
1864 }
1865 }
1866
1867 /* Is status ring empty or is there more to do? */
sky2_more_work(const struct sky2_hw * hw)1868 static inline int sky2_more_work(const struct sky2_hw *hw)
1869 {
1870 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1871 }
1872
1873
1874 /* Process status response ring */
sky2_status_intr(struct sky2_hw * hw)1875 static void sky2_status_intr(struct sky2_hw *hw)
1876 {
1877 struct sky2_port *sky2;
1878 unsigned buf_write[2] = { 0, 0 };
1879 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1880
1881 rmb();
1882
1883 while (hw->st_idx != hwidx) {
1884 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1885 struct net_device *dev;
1886 struct sk_buff *skb;
1887 u32 status;
1888 u16 length;
1889
1890 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1891
1892 BUG_ON(le->link >= 2);
1893 dev = hw->dev[le->link];
1894
1895 sky2 = netdev_priv(dev);
1896 length = le->length;
1897 status = le->status;
1898
1899 switch (le->opcode & ~HW_OWNER) {
1900 case OP_RXSTAT:
1901 skb = sky2_receive(sky2, length, status);
1902 if (!skb)
1903 break;
1904
1905 skb->dev = dev;
1906 skb->protocol = eth_type_trans(skb, dev);
1907 dev->last_rx = jiffies;
1908
1909 netif_rx(skb);
1910
1911 /* Update receiver after 16 frames */
1912 if (++buf_write[le->link] == RX_BUF_WRITE) {
1913 sky2_put_idx(hw, rxqaddr[le->link],
1914 sky2->rx_put);
1915 buf_write[le->link] = 0;
1916 }
1917 break;
1918
1919 case OP_RXCHKS:
1920 skb = sky2->rx_ring[sky2->rx_next].skb;
1921 skb->ip_summed = CHECKSUM_HW;
1922 skb->csum = le16_to_cpu(status);
1923 break;
1924
1925 case OP_TXINDEXLE:
1926 /* TX index reports status for both ports */
1927 sky2_tx_done(hw->dev[0], status & 0xfff);
1928 if (hw->dev[1])
1929 sky2_tx_done(hw->dev[1],
1930 ((status >> 24) & 0xff)
1931 | (u16)(length & 0xf) << 8);
1932 break;
1933
1934 default:
1935 if (net_ratelimit())
1936 printk(KERN_WARNING PFX
1937 "unknown status opcode 0x%x\n", le->opcode);
1938 goto exit_loop;
1939 }
1940 }
1941
1942 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1943
1944 exit_loop:
1945 if (buf_write[0]) {
1946 sky2 = netdev_priv(hw->dev[0]);
1947 sky2_put_idx(hw, Q_R1, sky2->rx_put);
1948 }
1949
1950 if (buf_write[1]) {
1951 sky2 = netdev_priv(hw->dev[1]);
1952 sky2_put_idx(hw, Q_R2, sky2->rx_put);
1953 }
1954
1955 }
1956
sky2_hw_error(struct sky2_hw * hw,unsigned port,u32 status)1957 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1958 {
1959 struct net_device *dev = hw->dev[port];
1960
1961 if (net_ratelimit())
1962 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1963 dev->name, status);
1964
1965 if (status & Y2_IS_PAR_RD1) {
1966 if (net_ratelimit())
1967 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1968 dev->name);
1969 /* Clear IRQ */
1970 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1971 }
1972
1973 if (status & Y2_IS_PAR_WR1) {
1974 if (net_ratelimit())
1975 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1976 dev->name);
1977
1978 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1979 }
1980
1981 if (status & Y2_IS_PAR_MAC1) {
1982 if (net_ratelimit())
1983 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1984 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1985 }
1986
1987 if (status & Y2_IS_PAR_RX1) {
1988 if (net_ratelimit())
1989 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1990 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1991 }
1992
1993 if (status & Y2_IS_TCP_TXA1) {
1994 if (net_ratelimit())
1995 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1996 dev->name);
1997 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1998 }
1999 }
2000
sky2_hw_intr(struct sky2_hw * hw)2001 static void sky2_hw_intr(struct sky2_hw *hw)
2002 {
2003 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2004
2005 if (status & Y2_IS_TIST_OV)
2006 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2007
2008 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2009 u16 pci_err;
2010
2011 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2012 if (net_ratelimit())
2013 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2014 pci_name(hw->pdev), pci_err);
2015
2016 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2017 sky2_pci_write16(hw, PCI_STATUS,
2018 pci_err | PCI_STATUS_ERROR_BITS);
2019 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2020 }
2021
2022 if (status & Y2_IS_PCI_EXP) {
2023 /* PCI-Express uncorrectable Error occurred */
2024 u32 pex_err;
2025
2026 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2027
2028 if (net_ratelimit())
2029 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2030 pci_name(hw->pdev), pex_err);
2031
2032 /* clear the interrupt */
2033 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2034 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2035 0xffffffffUL);
2036 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2037
2038 if (pex_err & PEX_FATAL_ERRORS) {
2039 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2040 hwmsk &= ~Y2_IS_PCI_EXP;
2041 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2042 }
2043 }
2044
2045 if (status & Y2_HWE_L1_MASK)
2046 sky2_hw_error(hw, 0, status);
2047 status >>= 8;
2048 if (status & Y2_HWE_L1_MASK)
2049 sky2_hw_error(hw, 1, status);
2050 }
2051
sky2_mac_intr(struct sky2_hw * hw,unsigned port)2052 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2053 {
2054 struct net_device *dev = hw->dev[port];
2055 struct sky2_port *sky2 = netdev_priv(dev);
2056 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2057
2058 if (netif_msg_intr(sky2))
2059 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2060 dev->name, status);
2061
2062 if (status & GM_IS_RX_FF_OR) {
2063 ++sky2->net_stats.rx_fifo_errors;
2064 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2065 }
2066
2067 if (status & GM_IS_TX_FF_UR) {
2068 ++sky2->net_stats.tx_fifo_errors;
2069 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2070 }
2071 }
2072
2073 /* This should never happen it is a fatal situation */
sky2_descriptor_error(struct sky2_hw * hw,unsigned port,const char * rxtx,u32 mask)2074 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2075 const char *rxtx, u32 mask)
2076 {
2077 struct net_device *dev = hw->dev[port];
2078 struct sky2_port *sky2 = netdev_priv(dev);
2079 u32 imask;
2080
2081 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2082 dev ? dev->name : "<not registered>", rxtx);
2083
2084 imask = sky2_read32(hw, B0_IMSK);
2085 imask &= ~mask;
2086 sky2_write32(hw, B0_IMSK, imask);
2087
2088 if (dev) {
2089 spin_lock(&sky2->phy_lock);
2090 sky2_link_down(sky2);
2091 spin_unlock(&sky2->phy_lock);
2092 }
2093 }
2094
sky2_intr(int irq,void * dev_id,struct pt_regs * regs)2095 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2096 {
2097 struct sky2_hw *hw = dev_id;
2098 u32 status;
2099
2100 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2101 if (status == 0 || status == ~0)
2102 return IRQ_NONE;
2103
2104 pr_debug("sky2_intr %#x\n", status);
2105
2106 if (status & Y2_IS_HW_ERR)
2107 sky2_hw_intr(hw);
2108
2109 if (status & Y2_IS_IRQ_PHY1)
2110 sky2_phy_intr(hw, 0);
2111
2112 if (status & Y2_IS_IRQ_PHY2)
2113 sky2_phy_intr(hw, 1);
2114
2115 if (status & Y2_IS_IRQ_MAC1)
2116 sky2_mac_intr(hw, 0);
2117
2118 if (status & Y2_IS_IRQ_MAC2)
2119 sky2_mac_intr(hw, 1);
2120
2121 if (status & Y2_IS_CHK_RX1)
2122 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2123
2124 if (status & Y2_IS_CHK_RX2)
2125 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2126
2127 if (status & Y2_IS_CHK_TXA1)
2128 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2129
2130 if (status & Y2_IS_CHK_TXA2)
2131 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2132
2133 if (status & Y2_IS_STAT_BMU)
2134 sky2_status_intr(hw);
2135
2136 sky2_read32(hw, B0_Y2_SP_LISR);
2137
2138 return IRQ_HANDLED;
2139 }
2140
2141 /* Chip internal frequency for clock calculations */
sky2_mhz(const struct sky2_hw * hw)2142 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2143 {
2144 switch (hw->chip_id) {
2145 case CHIP_ID_YUKON_EC:
2146 case CHIP_ID_YUKON_EC_U:
2147 return 125; /* 125 Mhz */
2148 case CHIP_ID_YUKON_FE:
2149 return 100; /* 100 Mhz */
2150 default: /* YUKON_XL */
2151 return 156; /* 156 Mhz */
2152 }
2153 }
2154
sky2_us2clk(const struct sky2_hw * hw,u32 us)2155 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2156 {
2157 return sky2_mhz(hw) * us;
2158 }
2159
sky2_clk2us(const struct sky2_hw * hw,u32 clk)2160 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2161 {
2162 return clk / sky2_mhz(hw);
2163 }
2164
2165
sky2_reset(struct sky2_hw * hw)2166 static int sky2_reset(struct sky2_hw *hw)
2167 {
2168 u16 status;
2169 u8 t8, pmd_type;
2170 int i;
2171
2172 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2173
2174 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2175 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2176 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2177 pci_name(hw->pdev), hw->chip_id);
2178 return -EOPNOTSUPP;
2179 }
2180
2181 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2182
2183 /* This rev is really old, and requires untested workarounds */
2184 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2185 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2186 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2187 hw->chip_id, hw->chip_rev);
2188 return -EOPNOTSUPP;
2189 }
2190
2191 /* disable ASF */
2192 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2193 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2194 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2195 }
2196
2197 /* do a SW reset */
2198 sky2_write8(hw, B0_CTST, CS_RST_SET);
2199 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2200
2201 /* clear PCI errors, if any */
2202 status = sky2_pci_read16(hw, PCI_STATUS);
2203
2204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2205 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2206
2207
2208 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2209
2210 /* clear any PEX errors */
2211 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2212 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2213
2214
2215 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2216 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2217
2218 hw->ports = 1;
2219 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2220 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2221 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2222 ++hw->ports;
2223 }
2224
2225 sky2_set_power_state(hw, PCI_D0);
2226
2227 for (i = 0; i < hw->ports; i++) {
2228 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2229 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2230 }
2231
2232 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2233
2234 /* Clear I2C IRQ noise */
2235 sky2_write32(hw, B2_I2C_IRQ, 1);
2236
2237 /* turn off hardware timer (unused) */
2238 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2239 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2240
2241 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2242
2243 /* Turn off descriptor polling */
2244 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2245
2246 /* Turn off receive timestamp */
2247 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2248 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2249
2250 /* enable the Tx Arbiters */
2251 for (i = 0; i < hw->ports; i++)
2252 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2253
2254 /* Initialize ram interface */
2255 for (i = 0; i < hw->ports; i++) {
2256 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2257
2258 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2259 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2260 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2261 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2262 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2263 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2264 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2265 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2266 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2267 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2268 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2269 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2270 }
2271
2272 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2273
2274 for (i = 0; i < hw->ports; i++)
2275 sky2_phy_reset(hw, i);
2276
2277 memset(hw->st_le, 0, STATUS_LE_BYTES);
2278 hw->st_idx = 0;
2279
2280 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2281 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2282
2283 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2284 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2285
2286 /* Set the list last index */
2287 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2288
2289 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2290 sky2_write8(hw, STAT_FIFO_WM, 16);
2291
2292 /* set Status-FIFO ISR watermark */
2293 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2294 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2295 else
2296 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2297
2298 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2299 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2300 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2301
2302 /* enable status unit */
2303 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2304
2305 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2306 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2307 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2308
2309 return 0;
2310 }
2311
sky2_supported_modes(const struct sky2_hw * hw)2312 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2313 {
2314 u32 modes;
2315 if (hw->copper) {
2316 modes = SUPPORTED_10baseT_Half
2317 | SUPPORTED_10baseT_Full
2318 | SUPPORTED_100baseT_Half
2319 | SUPPORTED_100baseT_Full
2320 | SUPPORTED_Autoneg | SUPPORTED_TP;
2321
2322 if (hw->chip_id != CHIP_ID_YUKON_FE)
2323 modes |= SUPPORTED_1000baseT_Half
2324 | SUPPORTED_1000baseT_Full;
2325 } else
2326 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2327 | SUPPORTED_Autoneg;
2328 return modes;
2329 }
2330
sky2_get_settings(struct net_device * dev,struct ethtool_cmd * ecmd)2331 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2332 {
2333 struct sky2_port *sky2 = netdev_priv(dev);
2334 struct sky2_hw *hw = sky2->hw;
2335
2336 ecmd->transceiver = XCVR_INTERNAL;
2337 ecmd->supported = sky2_supported_modes(hw);
2338 ecmd->phy_address = PHY_ADDR_MARV;
2339 if (hw->copper) {
2340 ecmd->supported = SUPPORTED_10baseT_Half
2341 | SUPPORTED_10baseT_Full
2342 | SUPPORTED_100baseT_Half
2343 | SUPPORTED_100baseT_Full
2344 | SUPPORTED_1000baseT_Half
2345 | SUPPORTED_1000baseT_Full
2346 | SUPPORTED_Autoneg | SUPPORTED_TP;
2347 ecmd->port = PORT_TP;
2348 } else
2349 ecmd->port = PORT_FIBRE;
2350
2351 ecmd->advertising = sky2->advertising;
2352 ecmd->autoneg = sky2->autoneg;
2353 ecmd->speed = sky2->speed;
2354 ecmd->duplex = sky2->duplex;
2355 return 0;
2356 }
2357
sky2_set_settings(struct net_device * dev,struct ethtool_cmd * ecmd)2358 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2359 {
2360 struct sky2_port *sky2 = netdev_priv(dev);
2361 const struct sky2_hw *hw = sky2->hw;
2362 u32 supported = sky2_supported_modes(hw);
2363
2364 if (ecmd->autoneg == AUTONEG_ENABLE) {
2365 ecmd->advertising = supported;
2366 sky2->duplex = -1;
2367 sky2->speed = -1;
2368 } else {
2369 u32 setting;
2370
2371 switch (ecmd->speed) {
2372 case SPEED_1000:
2373 if (ecmd->duplex == DUPLEX_FULL)
2374 setting = SUPPORTED_1000baseT_Full;
2375 else if (ecmd->duplex == DUPLEX_HALF)
2376 setting = SUPPORTED_1000baseT_Half;
2377 else
2378 return -EINVAL;
2379 break;
2380 case SPEED_100:
2381 if (ecmd->duplex == DUPLEX_FULL)
2382 setting = SUPPORTED_100baseT_Full;
2383 else if (ecmd->duplex == DUPLEX_HALF)
2384 setting = SUPPORTED_100baseT_Half;
2385 else
2386 return -EINVAL;
2387 break;
2388
2389 case SPEED_10:
2390 if (ecmd->duplex == DUPLEX_FULL)
2391 setting = SUPPORTED_10baseT_Full;
2392 else if (ecmd->duplex == DUPLEX_HALF)
2393 setting = SUPPORTED_10baseT_Half;
2394 else
2395 return -EINVAL;
2396 break;
2397 default:
2398 return -EINVAL;
2399 }
2400
2401 if ((setting & supported) == 0)
2402 return -EINVAL;
2403
2404 sky2->speed = ecmd->speed;
2405 sky2->duplex = ecmd->duplex;
2406 }
2407
2408 sky2->autoneg = ecmd->autoneg;
2409 sky2->advertising = ecmd->advertising;
2410
2411 if (netif_running(dev))
2412 sky2_phy_reinit(sky2);
2413
2414 return 0;
2415 }
2416
sky2_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)2417 static void sky2_get_drvinfo(struct net_device *dev,
2418 struct ethtool_drvinfo *info)
2419 {
2420 struct sky2_port *sky2 = netdev_priv(dev);
2421
2422 strcpy(info->driver, DRV_NAME);
2423 strcpy(info->version, DRV_VERSION);
2424 strcpy(info->fw_version, "N/A");
2425 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2426 }
2427
2428 static const struct sky2_stat {
2429 char name[ETH_GSTRING_LEN];
2430 u16 offset;
2431 } sky2_stats[] = {
2432 { "tx_bytes", GM_TXO_OK_HI },
2433 { "rx_bytes", GM_RXO_OK_HI },
2434 { "tx_broadcast", GM_TXF_BC_OK },
2435 { "rx_broadcast", GM_RXF_BC_OK },
2436 { "tx_multicast", GM_TXF_MC_OK },
2437 { "rx_multicast", GM_RXF_MC_OK },
2438 { "tx_unicast", GM_TXF_UC_OK },
2439 { "rx_unicast", GM_RXF_UC_OK },
2440 { "tx_mac_pause", GM_TXF_MPAUSE },
2441 { "rx_mac_pause", GM_RXF_MPAUSE },
2442 { "collisions", GM_TXF_COL },
2443 { "late_collision",GM_TXF_LAT_COL },
2444 { "aborted", GM_TXF_ABO_COL },
2445 { "single_collisions", GM_TXF_SNG_COL },
2446 { "multi_collisions", GM_TXF_MUL_COL },
2447
2448 { "rx_short", GM_RXF_SHT },
2449 { "rx_runt", GM_RXE_FRAG },
2450 { "rx_64_byte_packets", GM_RXF_64B },
2451 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2452 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2453 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2454 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2455 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2456 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2457 { "rx_too_long", GM_RXF_LNG_ERR },
2458 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2459 { "rx_jabber", GM_RXF_JAB_PKT },
2460 { "rx_fcs_error", GM_RXF_FCS_ERR },
2461
2462 { "tx_64_byte_packets", GM_TXF_64B },
2463 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2464 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2465 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2466 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2467 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2468 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2469 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2470 };
2471
sky2_get_rx_csum(struct net_device * dev)2472 static u32 sky2_get_rx_csum(struct net_device *dev)
2473 {
2474 struct sky2_port *sky2 = netdev_priv(dev);
2475
2476 return sky2->rx_csum;
2477 }
2478
sky2_set_rx_csum(struct net_device * dev,u32 data)2479 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2480 {
2481 struct sky2_port *sky2 = netdev_priv(dev);
2482
2483 sky2->rx_csum = data;
2484
2485 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2486 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2487
2488 return 0;
2489 }
2490
sky2_get_msglevel(struct net_device * netdev)2491 static u32 sky2_get_msglevel(struct net_device *netdev)
2492 {
2493 struct sky2_port *sky2 = netdev_priv(netdev);
2494 return sky2->msg_enable;
2495 }
2496
sky2_nway_reset(struct net_device * dev)2497 static int sky2_nway_reset(struct net_device *dev)
2498 {
2499 struct sky2_port *sky2 = netdev_priv(dev);
2500
2501 if (sky2->autoneg != AUTONEG_ENABLE)
2502 return -EINVAL;
2503
2504 sky2_phy_reinit(sky2);
2505
2506 return 0;
2507 }
2508
sky2_phy_stats(struct sky2_port * sky2,u64 * data,unsigned count)2509 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2510 {
2511 struct sky2_hw *hw = sky2->hw;
2512 unsigned port = sky2->port;
2513 int i;
2514
2515 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2516 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2517 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2518 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2519
2520 for (i = 2; i < count; i++)
2521 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2522 }
2523
sky2_set_msglevel(struct net_device * netdev,u32 value)2524 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2525 {
2526 struct sky2_port *sky2 = netdev_priv(netdev);
2527 sky2->msg_enable = value;
2528 }
2529
sky2_get_stats_count(struct net_device * dev)2530 static int sky2_get_stats_count(struct net_device *dev)
2531 {
2532 return ARRAY_SIZE(sky2_stats);
2533 }
2534
sky2_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2535 static void sky2_get_ethtool_stats(struct net_device *dev,
2536 struct ethtool_stats *stats, u64 * data)
2537 {
2538 struct sky2_port *sky2 = netdev_priv(dev);
2539
2540 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2541 }
2542
sky2_get_strings(struct net_device * dev,u32 stringset,u8 * data)2543 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2544 {
2545 int i;
2546
2547 switch (stringset) {
2548 case ETH_SS_STATS:
2549 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2550 memcpy(data + i * ETH_GSTRING_LEN,
2551 sky2_stats[i].name, ETH_GSTRING_LEN);
2552 break;
2553 }
2554 }
2555
2556 /* Use hardware MIB variables for critical path statistics and
2557 * transmit feedback not reported at interrupt.
2558 * Other errors are accounted for in interrupt handler.
2559 */
sky2_get_stats(struct net_device * dev)2560 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2561 {
2562 struct sky2_port *sky2 = netdev_priv(dev);
2563 u64 data[13];
2564
2565 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2566
2567 sky2->net_stats.tx_bytes = data[0];
2568 sky2->net_stats.rx_bytes = data[1];
2569 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2570 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2571 sky2->net_stats.multicast = data[3] + data[5];
2572 sky2->net_stats.collisions = data[10];
2573 sky2->net_stats.tx_aborted_errors = data[12];
2574
2575 return &sky2->net_stats;
2576 }
2577
sky2_set_mac_address(struct net_device * dev,void * p)2578 static int sky2_set_mac_address(struct net_device *dev, void *p)
2579 {
2580 struct sky2_port *sky2 = netdev_priv(dev);
2581 struct sky2_hw *hw = sky2->hw;
2582 unsigned port = sky2->port;
2583 const struct sockaddr *addr = p;
2584
2585 if (addr->sa_data[0] & 0x1)
2586 return -EADDRNOTAVAIL;
2587
2588 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2589 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2590 dev->dev_addr, ETH_ALEN);
2591 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2592 dev->dev_addr, ETH_ALEN);
2593
2594 /* virtual address for data */
2595 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2596
2597 /* physical address: used for pause frames */
2598 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2599
2600 return 0;
2601 }
2602
sky2_set_multicast(struct net_device * dev)2603 static void sky2_set_multicast(struct net_device *dev)
2604 {
2605 struct sky2_port *sky2 = netdev_priv(dev);
2606 struct sky2_hw *hw = sky2->hw;
2607 unsigned port = sky2->port;
2608 struct dev_mc_list *list = dev->mc_list;
2609 u16 reg;
2610 u8 filter[8];
2611
2612 memset(filter, 0, sizeof(filter));
2613
2614 reg = gma_read16(hw, port, GM_RX_CTRL);
2615 reg |= GM_RXCR_UCF_ENA;
2616
2617 if (dev->flags & IFF_PROMISC) /* promiscuous */
2618 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2619 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2620 memset(filter, 0xff, sizeof(filter));
2621 else if (dev->mc_count == 0) /* no multicast */
2622 reg &= ~GM_RXCR_MCF_ENA;
2623 else {
2624 int i;
2625 reg |= GM_RXCR_MCF_ENA;
2626
2627 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2628 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2629 filter[bit / 8] |= 1 << (bit % 8);
2630 }
2631 }
2632
2633 gma_write16(hw, port, GM_MC_ADDR_H1,
2634 (u16) filter[0] | ((u16) filter[1] << 8));
2635 gma_write16(hw, port, GM_MC_ADDR_H2,
2636 (u16) filter[2] | ((u16) filter[3] << 8));
2637 gma_write16(hw, port, GM_MC_ADDR_H3,
2638 (u16) filter[4] | ((u16) filter[5] << 8));
2639 gma_write16(hw, port, GM_MC_ADDR_H4,
2640 (u16) filter[6] | ((u16) filter[7] << 8));
2641
2642 gma_write16(hw, port, GM_RX_CTRL, reg);
2643 }
2644
2645 /* Can have one global because blinking is controlled by
2646 * ethtool and that is always under RTNL mutex
2647 */
sky2_led(struct sky2_hw * hw,unsigned port,int on)2648 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2649 {
2650 u16 pg;
2651
2652 switch (hw->chip_id) {
2653 case CHIP_ID_YUKON_XL:
2654 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2655 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2657 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2658 PHY_M_LEDC_INIT_CTRL(7) |
2659 PHY_M_LEDC_STA1_CTRL(7) |
2660 PHY_M_LEDC_STA0_CTRL(7))
2661 : 0);
2662
2663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2664 break;
2665
2666 default:
2667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2668 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2669 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2670 PHY_M_LED_MO_10(MO_LED_ON) |
2671 PHY_M_LED_MO_100(MO_LED_ON) |
2672 PHY_M_LED_MO_1000(MO_LED_ON) |
2673 PHY_M_LED_MO_RX(MO_LED_ON)
2674 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2675 PHY_M_LED_MO_10(MO_LED_OFF) |
2676 PHY_M_LED_MO_100(MO_LED_OFF) |
2677 PHY_M_LED_MO_1000(MO_LED_OFF) |
2678 PHY_M_LED_MO_RX(MO_LED_OFF));
2679
2680 }
2681 }
2682
2683 /* blink LED's for finding board */
sky2_phys_id(struct net_device * dev,u32 data)2684 static int sky2_phys_id(struct net_device *dev, u32 data)
2685 {
2686 struct sky2_port *sky2 = netdev_priv(dev);
2687 struct sky2_hw *hw = sky2->hw;
2688 unsigned port = sky2->port;
2689 u16 ledctrl, ledover = 0;
2690 long ms;
2691 int interrupted;
2692 int onoff = 1;
2693
2694 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2695 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2696 else
2697 ms = data * 1000;
2698
2699 /* save initial values */
2700 spin_lock_bh(&sky2->phy_lock);
2701 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2702 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2703 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2704 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2706 } else {
2707 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2708 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2709 }
2710
2711 interrupted = 0;
2712 while (!interrupted && ms > 0) {
2713 sky2_led(hw, port, onoff);
2714 onoff = !onoff;
2715
2716 spin_unlock_bh(&sky2->phy_lock);
2717 interrupted = msleep_interruptible(250);
2718 spin_lock_bh(&sky2->phy_lock);
2719
2720 ms -= 250;
2721 }
2722
2723 /* resume regularly scheduled programming */
2724 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2725 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2726 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2727 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2728 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2729 } else {
2730 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2731 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2732 }
2733 spin_unlock_bh(&sky2->phy_lock);
2734
2735 return 0;
2736 }
2737
sky2_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * ecmd)2738 static void sky2_get_pauseparam(struct net_device *dev,
2739 struct ethtool_pauseparam *ecmd)
2740 {
2741 struct sky2_port *sky2 = netdev_priv(dev);
2742
2743 ecmd->tx_pause = sky2->tx_pause;
2744 ecmd->rx_pause = sky2->rx_pause;
2745 ecmd->autoneg = sky2->autoneg;
2746 }
2747
sky2_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * ecmd)2748 static int sky2_set_pauseparam(struct net_device *dev,
2749 struct ethtool_pauseparam *ecmd)
2750 {
2751 struct sky2_port *sky2 = netdev_priv(dev);
2752 int err = 0;
2753
2754 sky2->autoneg = ecmd->autoneg;
2755 sky2->tx_pause = ecmd->tx_pause != 0;
2756 sky2->rx_pause = ecmd->rx_pause != 0;
2757
2758 sky2_phy_reinit(sky2);
2759
2760 return err;
2761 }
2762
sky2_get_tx_csum(struct net_device * dev)2763 static u32 sky2_get_tx_csum(struct net_device *dev)
2764 {
2765 return (dev->features & NETIF_F_HW_CSUM) != 0;
2766 }
2767
2768
sky2_set_tx_csum(struct net_device * netdev,uint32_t data)2769 static int sky2_set_tx_csum(struct net_device *netdev, uint32_t data)
2770 {
2771 if (data)
2772 netdev->features |= NETIF_F_HW_CSUM;
2773 else
2774 netdev->features &= ~NETIF_F_HW_CSUM;
2775
2776 return 0;
2777 }
2778
sky2_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ecmd)2779 static int sky2_get_coalesce(struct net_device *dev,
2780 struct ethtool_coalesce *ecmd)
2781 {
2782 struct sky2_port *sky2 = netdev_priv(dev);
2783 struct sky2_hw *hw = sky2->hw;
2784
2785 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2786 ecmd->tx_coalesce_usecs = 0;
2787 else {
2788 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2789 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2790 }
2791 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2792
2793 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2794 ecmd->rx_coalesce_usecs = 0;
2795 else {
2796 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2797 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2798 }
2799 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2800
2801 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2802 ecmd->rx_coalesce_usecs_irq = 0;
2803 else {
2804 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2805 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2806 }
2807
2808 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2809
2810 return 0;
2811 }
2812
2813 /* Note: this affect both ports */
sky2_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ecmd)2814 static int sky2_set_coalesce(struct net_device *dev,
2815 struct ethtool_coalesce *ecmd)
2816 {
2817 struct sky2_port *sky2 = netdev_priv(dev);
2818 struct sky2_hw *hw = sky2->hw;
2819 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2820
2821 if (ecmd->tx_coalesce_usecs > tmax ||
2822 ecmd->rx_coalesce_usecs > tmax ||
2823 ecmd->rx_coalesce_usecs_irq > tmax)
2824 return -EINVAL;
2825
2826 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2827 return -EINVAL;
2828 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2829 return -EINVAL;
2830 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2831 return -EINVAL;
2832
2833 if (ecmd->tx_coalesce_usecs == 0)
2834 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2835 else {
2836 sky2_write32(hw, STAT_TX_TIMER_INI,
2837 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2838 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2839 }
2840 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2841
2842 if (ecmd->rx_coalesce_usecs == 0)
2843 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2844 else {
2845 sky2_write32(hw, STAT_LEV_TIMER_INI,
2846 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2847 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2848 }
2849 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2850
2851 if (ecmd->rx_coalesce_usecs_irq == 0)
2852 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2853 else {
2854 sky2_write32(hw, STAT_ISR_TIMER_INI,
2855 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2856 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2857 }
2858 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2859 return 0;
2860 }
2861
sky2_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ering)2862 static void sky2_get_ringparam(struct net_device *dev,
2863 struct ethtool_ringparam *ering)
2864 {
2865 struct sky2_port *sky2 = netdev_priv(dev);
2866
2867 ering->rx_max_pending = RX_MAX_PENDING;
2868 ering->rx_mini_max_pending = 0;
2869 ering->rx_jumbo_max_pending = 0;
2870 ering->tx_max_pending = TX_RING_SIZE - 1;
2871
2872 ering->rx_pending = sky2->rx_pending;
2873 ering->rx_mini_pending = 0;
2874 ering->rx_jumbo_pending = 0;
2875 ering->tx_pending = sky2->tx_pending;
2876 }
2877
sky2_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ering)2878 static int sky2_set_ringparam(struct net_device *dev,
2879 struct ethtool_ringparam *ering)
2880 {
2881 struct sky2_port *sky2 = netdev_priv(dev);
2882 int err = 0;
2883
2884 if (ering->rx_pending > RX_MAX_PENDING ||
2885 ering->rx_pending < 8 ||
2886 ering->tx_pending < MAX_SKB_TX_LE ||
2887 ering->tx_pending > TX_RING_SIZE - 1)
2888 return -EINVAL;
2889
2890 if (netif_running(dev))
2891 sky2_down(dev);
2892
2893 sky2->rx_pending = ering->rx_pending;
2894 sky2->tx_pending = ering->tx_pending;
2895
2896 if (netif_running(dev)) {
2897 err = sky2_up(dev);
2898 if (err)
2899 dev_close(dev);
2900 else
2901 sky2_set_multicast(dev);
2902 }
2903
2904 return err;
2905 }
2906
sky2_get_regs_len(struct net_device * dev)2907 static int sky2_get_regs_len(struct net_device *dev)
2908 {
2909 return 0x4000;
2910 }
2911
2912 /*
2913 * Returns copy of control register region
2914 * Note: access to the RAM address register set will cause timeouts.
2915 */
sky2_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)2916 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2917 void *p)
2918 {
2919 const struct sky2_port *sky2 = netdev_priv(dev);
2920 const void __iomem *io = sky2->hw->regs;
2921
2922 BUG_ON(regs->len < B3_RI_WTO_R1);
2923 regs->version = 1;
2924 memset(p, 0, regs->len);
2925
2926 memcpy_fromio(p, io, B3_RAM_ADDR);
2927
2928 memcpy_fromio(p + B3_RI_WTO_R1,
2929 io + B3_RI_WTO_R1,
2930 regs->len - B3_RI_WTO_R1);
2931 }
2932
2933 static struct ethtool_ops sky2_ethtool_ops = {
2934 .get_settings = sky2_get_settings,
2935 .set_settings = sky2_set_settings,
2936 .get_drvinfo = sky2_get_drvinfo,
2937 .get_msglevel = sky2_get_msglevel,
2938 .set_msglevel = sky2_set_msglevel,
2939 .nway_reset = sky2_nway_reset,
2940 .get_regs_len = sky2_get_regs_len,
2941 .get_regs = sky2_get_regs,
2942 .get_link = ethtool_op_get_link,
2943 .get_sg = ethtool_op_get_sg,
2944 .set_sg = ethtool_op_set_sg,
2945 .get_tx_csum = sky2_get_tx_csum,
2946 .set_tx_csum = sky2_set_tx_csum,
2947 #ifdef NETIF_F_TSO
2948 .get_tso = ethtool_op_get_tso,
2949 .set_tso = ethtool_op_set_tso,
2950 #endif
2951 .get_rx_csum = sky2_get_rx_csum,
2952 .set_rx_csum = sky2_set_rx_csum,
2953 .get_strings = sky2_get_strings,
2954 .get_coalesce = sky2_get_coalesce,
2955 .set_coalesce = sky2_set_coalesce,
2956 .get_ringparam = sky2_get_ringparam,
2957 .set_ringparam = sky2_set_ringparam,
2958 .get_pauseparam = sky2_get_pauseparam,
2959 .set_pauseparam = sky2_set_pauseparam,
2960 .phys_id = sky2_phys_id,
2961 .get_stats_count = sky2_get_stats_count,
2962 .get_ethtool_stats = sky2_get_ethtool_stats,
2963 };
2964
2965 /* Initialize network device */
sky2_init_netdev(struct sky2_hw * hw,unsigned port,int highmem)2966 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2967 unsigned port, int highmem)
2968 {
2969 struct sky2_port *sky2;
2970 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2971
2972 if (!dev) {
2973 printk(KERN_ERR "sky2 etherdev alloc failed");
2974 return NULL;
2975 }
2976
2977 SET_MODULE_OWNER(dev);
2978 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2979 dev->irq = hw->pdev->irq;
2980 dev->open = sky2_up;
2981 dev->stop = sky2_down;
2982 dev->do_ioctl = sky2_ioctl;
2983 dev->hard_start_xmit = sky2_xmit_frame;
2984 dev->get_stats = sky2_get_stats;
2985 dev->set_multicast_list = sky2_set_multicast;
2986 dev->set_mac_address = sky2_set_mac_address;
2987 dev->change_mtu = sky2_change_mtu;
2988 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2989 dev->tx_timeout = sky2_tx_timeout;
2990 dev->watchdog_timeo = TX_WATCHDOG;
2991
2992 sky2 = netdev_priv(dev);
2993 sky2->netdev = dev;
2994 sky2->hw = hw;
2995 sky2->msg_enable = netif_msg_init(debug, default_msg);
2996
2997 spin_lock_init(&sky2->tx_lock);
2998 /* Auto speed and flow control */
2999 sky2->autoneg = AUTONEG_ENABLE;
3000 sky2->tx_pause = 1;
3001 sky2->rx_pause = 1;
3002 sky2->duplex = -1;
3003 sky2->speed = -1;
3004 sky2->advertising = sky2_supported_modes(hw);
3005 sky2->rx_csum = 0;
3006
3007 spin_lock_init(&sky2->phy_lock);
3008 sky2->tx_pending = TX_DEF_PENDING;
3009 sky2->rx_pending = RX_DEF_PENDING;
3010 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3011
3012 hw->dev[port] = dev;
3013
3014 sky2->port = port;
3015
3016 if (highmem)
3017 dev->features |= NETIF_F_HIGHDMA;
3018 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3019
3020 /* read the mac address */
3021 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3022
3023 /* device is off until link detection */
3024 netif_carrier_off(dev);
3025 netif_stop_queue(dev);
3026
3027 return dev;
3028 }
3029
sky2_show_addr(struct net_device * dev)3030 static void __devinit sky2_show_addr(struct net_device *dev)
3031 {
3032 const struct sky2_port *sky2 = netdev_priv(dev);
3033
3034 if (netif_msg_probe(sky2))
3035 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3036 dev->name,
3037 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3038 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3039 }
3040
sky2_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3041 static int __devinit sky2_probe(struct pci_dev *pdev,
3042 const struct pci_device_id *ent)
3043 {
3044 struct net_device *dev, *dev1 = NULL;
3045 struct sky2_hw *hw;
3046 int err, pm_cap, using_dac = 0;
3047
3048 err = pci_enable_device(pdev);
3049 if (err) {
3050 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3051 pci_name(pdev));
3052 goto err_out;
3053 }
3054
3055 err = pci_request_regions(pdev, DRV_NAME);
3056 if (err) {
3057 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3058 pci_name(pdev));
3059 goto err_out;
3060 }
3061
3062 pci_set_master(pdev);
3063
3064 /* Find power-management capability. */
3065 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3066 if (pm_cap == 0) {
3067 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3068 "aborting.\n");
3069 err = -EIO;
3070 goto err_out_free_regions;
3071 }
3072
3073 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3074 if (!err)
3075 using_dac = 1;
3076 else {
3077 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3078 if (err) {
3079 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3080 pci_name(pdev));
3081 goto err_out_free_regions;
3082 }
3083 }
3084
3085 err = -ENOMEM;
3086 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3087 if (!hw) {
3088 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3089 pci_name(pdev));
3090 goto err_out_free_regions;
3091 }
3092 memset(hw, 0, sizeof(*hw));
3093
3094 hw->pdev = pdev;
3095
3096 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3097 if (!hw->regs) {
3098 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3099 pci_name(pdev));
3100 goto err_out_free_hw;
3101 }
3102 hw->pm_cap = pm_cap;
3103
3104 #ifdef __BIG_ENDIAN
3105 /* byte swap descriptors in hardware */
3106 {
3107 u32 reg;
3108
3109 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3110 reg |= PCI_REV_DESC;
3111 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3112 }
3113 #endif
3114
3115 /* ring for status responses */
3116 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3117 &hw->st_dma);
3118 if (!hw->st_le)
3119 goto err_out_iounmap;
3120
3121 err = sky2_reset(hw);
3122 if (err)
3123 goto err_out_iounmap;
3124
3125 printk(KERN_INFO PFX "(%s) addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3126 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3127 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3128 hw->chip_id, hw->chip_rev);
3129
3130 dev = sky2_init_netdev(hw, 0, using_dac);
3131 if (!dev)
3132 goto err_out_free_pci;
3133
3134 err = register_netdev(dev);
3135 if (err) {
3136 printk(KERN_ERR PFX "%s: cannot register net device\n",
3137 pci_name(pdev));
3138 goto err_out_free_netdev;
3139 }
3140
3141 sky2_show_addr(dev);
3142
3143 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3144 if (register_netdev(dev1) == 0)
3145 sky2_show_addr(dev1);
3146 else {
3147 /* Failure to register second port need not be fatal */
3148 printk(KERN_WARNING PFX
3149 "register of second port failed\n");
3150 hw->dev[1] = NULL;
3151 free_netdev(dev1);
3152 }
3153 }
3154
3155 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
3156 DRV_NAME, hw);
3157 if (err) {
3158 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3159 pci_name(pdev), pdev->irq);
3160 goto err_out_unregister;
3161 }
3162
3163 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3164
3165 pci_set_drvdata(pdev, hw);
3166
3167 return 0;
3168
3169 err_out_unregister:
3170 if (dev1) {
3171 unregister_netdev(dev1);
3172 free_netdev(dev1);
3173 }
3174 unregister_netdev(dev);
3175 err_out_free_netdev:
3176 free_netdev(dev);
3177 err_out_free_pci:
3178 sky2_write8(hw, B0_CTST, CS_RST_SET);
3179 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3180 err_out_iounmap:
3181 iounmap(hw->regs);
3182 err_out_free_hw:
3183 kfree(hw);
3184 err_out_free_regions:
3185 pci_release_regions(pdev);
3186 pci_disable_device(pdev);
3187 err_out:
3188 return err;
3189 }
3190
sky2_remove(struct pci_dev * pdev)3191 static void __devexit sky2_remove(struct pci_dev *pdev)
3192 {
3193 struct sky2_hw *hw = pci_get_drvdata(pdev);
3194 struct net_device *dev0, *dev1;
3195
3196 if (!hw)
3197 return;
3198
3199 sky2_write32(hw, B0_IMSK, 0);
3200
3201 dev0 = hw->dev[0];
3202 dev1 = hw->dev[1];
3203 if (dev1)
3204 unregister_netdev(dev1);
3205 unregister_netdev(dev0);
3206
3207 sky2_set_power_state(hw, PCI_D3hot);
3208 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3209 sky2_write8(hw, B0_CTST, CS_RST_SET);
3210 sky2_read8(hw, B0_CTST);
3211
3212 free_irq(pdev->irq, hw);
3213 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3214 pci_release_regions(pdev);
3215 pci_disable_device(pdev);
3216
3217 if (dev1)
3218 free_netdev(dev1);
3219 free_netdev(dev0);
3220 iounmap(hw->regs);
3221 kfree(hw);
3222
3223 pci_set_drvdata(pdev, NULL);
3224 }
3225
3226
3227 static struct pci_driver sky2_driver = {
3228 .name = DRV_NAME,
3229 .id_table = sky2_id_table,
3230 .probe = sky2_probe,
3231 .remove = __devexit_p(sky2_remove),
3232 };
3233
sky2_init_module(void)3234 static int __init sky2_init_module(void)
3235 {
3236 return pci_module_init(&sky2_driver);
3237 }
3238
sky2_cleanup_module(void)3239 static void __exit sky2_cleanup_module(void)
3240 {
3241 pci_unregister_driver(&sky2_driver);
3242 }
3243
3244 module_init(sky2_init_module);
3245 module_exit(sky2_cleanup_module);
3246
3247 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3248 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3249 MODULE_LICENSE("GPL");
3250
3251