1 /*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30 #ifndef RADEON_MODE_H
31 #define RADEON_MODE_H
32
33 #include <drm/display/drm_dp_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fixed.h>
38 #include <drm/drm_modeset_helper_vtables.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41
42 struct radeon_bo;
43 struct radeon_device;
44
45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48
49 #define RADEON_MAX_HPD_PINS 7
50 #define RADEON_MAX_CRTCS 6
51 #define RADEON_MAX_AFMT_BLOCKS 7
52
53 enum radeon_rmx_type {
54 RMX_OFF,
55 RMX_FULL,
56 RMX_CENTER,
57 RMX_ASPECT
58 };
59
60 enum radeon_tv_std {
61 TV_STD_NTSC,
62 TV_STD_PAL,
63 TV_STD_PAL_M,
64 TV_STD_PAL_60,
65 TV_STD_NTSC_J,
66 TV_STD_SCART_PAL,
67 TV_STD_SECAM,
68 TV_STD_PAL_CN,
69 TV_STD_PAL_N,
70 };
71
72 enum radeon_underscan_type {
73 UNDERSCAN_OFF,
74 UNDERSCAN_ON,
75 UNDERSCAN_AUTO,
76 };
77
78 enum radeon_hpd_id {
79 RADEON_HPD_1 = 0,
80 RADEON_HPD_2,
81 RADEON_HPD_3,
82 RADEON_HPD_4,
83 RADEON_HPD_5,
84 RADEON_HPD_6,
85 RADEON_HPD_NONE = 0xff,
86 };
87
88 enum radeon_output_csc {
89 RADEON_OUTPUT_CSC_BYPASS = 0,
90 RADEON_OUTPUT_CSC_TVRGB = 1,
91 RADEON_OUTPUT_CSC_YCBCR601 = 2,
92 RADEON_OUTPUT_CSC_YCBCR709 = 3,
93 };
94
95 #define RADEON_MAX_I2C_BUS 16
96
97 /* radeon gpio-based i2c
98 * 1. "mask" reg and bits
99 * grabs the gpio pins for software use
100 * 0=not held 1=held
101 * 2. "a" reg and bits
102 * output pin value
103 * 0=low 1=high
104 * 3. "en" reg and bits
105 * sets the pin direction
106 * 0=input 1=output
107 * 4. "y" reg and bits
108 * input pin value
109 * 0=low 1=high
110 */
111 struct radeon_i2c_bus_rec {
112 bool valid;
113 /* id used by atom */
114 uint8_t i2c_id;
115 /* id used by atom */
116 enum radeon_hpd_id hpd;
117 /* can be used with hw i2c engine */
118 bool hw_capable;
119 /* uses multi-media i2c engine */
120 bool mm_i2c;
121 /* regs and bits */
122 uint32_t mask_clk_reg;
123 uint32_t mask_data_reg;
124 uint32_t a_clk_reg;
125 uint32_t a_data_reg;
126 uint32_t en_clk_reg;
127 uint32_t en_data_reg;
128 uint32_t y_clk_reg;
129 uint32_t y_data_reg;
130 uint32_t mask_clk_mask;
131 uint32_t mask_data_mask;
132 uint32_t a_clk_mask;
133 uint32_t a_data_mask;
134 uint32_t en_clk_mask;
135 uint32_t en_data_mask;
136 uint32_t y_clk_mask;
137 uint32_t y_data_mask;
138 };
139
140 struct radeon_tmds_pll {
141 uint32_t freq;
142 uint32_t value;
143 };
144
145 #define RADEON_MAX_BIOS_CONNECTOR 16
146
147 /* pll flags */
148 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
149 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
150 #define RADEON_PLL_USE_REF_DIV (1 << 2)
151 #define RADEON_PLL_LEGACY (1 << 3)
152 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
153 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
154 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
155 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
156 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
157 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
158 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
159 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
160 #define RADEON_PLL_USE_POST_DIV (1 << 12)
161 #define RADEON_PLL_IS_LCD (1 << 13)
162 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
163
164 struct radeon_pll {
165 /* reference frequency */
166 uint32_t reference_freq;
167
168 /* fixed dividers */
169 uint32_t reference_div;
170 uint32_t post_div;
171
172 /* pll in/out limits */
173 uint32_t pll_in_min;
174 uint32_t pll_in_max;
175 uint32_t pll_out_min;
176 uint32_t pll_out_max;
177 uint32_t lcd_pll_out_min;
178 uint32_t lcd_pll_out_max;
179 uint32_t best_vco;
180
181 /* divider limits */
182 uint32_t min_ref_div;
183 uint32_t max_ref_div;
184 uint32_t min_post_div;
185 uint32_t max_post_div;
186 uint32_t min_feedback_div;
187 uint32_t max_feedback_div;
188 uint32_t min_frac_feedback_div;
189 uint32_t max_frac_feedback_div;
190
191 /* flags for the current clock */
192 uint32_t flags;
193
194 /* pll id */
195 uint32_t id;
196 };
197
198 struct radeon_i2c_chan {
199 struct i2c_adapter adapter;
200 struct drm_device *dev;
201 struct i2c_algo_bit_data bit;
202 struct radeon_i2c_bus_rec rec;
203 struct drm_dp_aux aux;
204 bool has_aux;
205 struct mutex mutex;
206 };
207
208 /* mostly for macs, but really any system without connector tables */
209 enum radeon_connector_table {
210 CT_NONE = 0,
211 CT_GENERIC,
212 CT_IBOOK,
213 CT_POWERBOOK_EXTERNAL,
214 CT_POWERBOOK_INTERNAL,
215 CT_POWERBOOK_VGA,
216 CT_MINI_EXTERNAL,
217 CT_MINI_INTERNAL,
218 CT_IMAC_G5_ISIGHT,
219 CT_EMAC,
220 CT_RN50_POWER,
221 CT_MAC_X800,
222 CT_MAC_G5_9600,
223 CT_SAM440EP,
224 CT_MAC_G4_SILVER
225 };
226
227 enum radeon_dvo_chip {
228 DVO_SIL164,
229 DVO_SIL1178,
230 };
231
232 struct radeon_afmt {
233 bool enabled;
234 int offset;
235 bool last_buffer_filled_status;
236 int id;
237 };
238
239 struct radeon_mode_info {
240 struct atom_context *atom_context;
241 struct card_info *atom_card_info;
242 enum radeon_connector_table connector_table;
243 bool mode_config_initialized;
244 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
245 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
246 /* DVI-I properties */
247 struct drm_property *coherent_mode_property;
248 /* DAC enable load detect */
249 struct drm_property *load_detect_property;
250 /* TV standard */
251 struct drm_property *tv_std_property;
252 /* legacy TMDS PLL detect */
253 struct drm_property *tmds_pll_property;
254 /* underscan */
255 struct drm_property *underscan_property;
256 struct drm_property *underscan_hborder_property;
257 struct drm_property *underscan_vborder_property;
258 /* audio */
259 struct drm_property *audio_property;
260 /* FMT dithering */
261 struct drm_property *dither_property;
262 /* Output CSC */
263 struct drm_property *output_csc_property;
264 /* hardcoded DFP edid from BIOS */
265 struct edid *bios_hardcoded_edid;
266 int bios_hardcoded_edid_size;
267
268 /* firmware flags */
269 u16 firmware_flags;
270 /* pointer to backlight encoder */
271 struct radeon_encoder *bl_encoder;
272
273 /* bitmask for active encoder frontends */
274 uint32_t active_encoders;
275 };
276
277 #define RADEON_MAX_BL_LEVEL 0xFF
278
279 struct radeon_backlight_privdata {
280 struct radeon_encoder *encoder;
281 uint8_t negative;
282 };
283
284 #define MAX_H_CODE_TIMING_LEN 32
285 #define MAX_V_CODE_TIMING_LEN 32
286
287 /* need to store these as reading
288 back code tables is excessive */
289 struct radeon_tv_regs {
290 uint32_t tv_uv_adr;
291 uint32_t timing_cntl;
292 uint32_t hrestart;
293 uint32_t vrestart;
294 uint32_t frestart;
295 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
296 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
297 };
298
299 struct radeon_atom_ss {
300 uint16_t percentage;
301 uint16_t percentage_divider;
302 uint8_t type;
303 uint16_t step;
304 uint8_t delay;
305 uint8_t range;
306 uint8_t refdiv;
307 /* asic_ss */
308 uint16_t rate;
309 uint16_t amount;
310 };
311
312 enum radeon_flip_status {
313 RADEON_FLIP_NONE,
314 RADEON_FLIP_PENDING,
315 RADEON_FLIP_SUBMITTED
316 };
317
318 struct radeon_crtc {
319 struct drm_crtc base;
320 int crtc_id;
321 bool enabled;
322 bool can_tile;
323 bool cursor_out_of_bounds;
324 uint32_t crtc_offset;
325 struct drm_gem_object *cursor_bo;
326 uint64_t cursor_addr;
327 int cursor_x;
328 int cursor_y;
329 int cursor_hot_x;
330 int cursor_hot_y;
331 int cursor_width;
332 int cursor_height;
333 int max_cursor_width;
334 int max_cursor_height;
335 uint32_t legacy_display_base_addr;
336 enum radeon_rmx_type rmx_type;
337 u8 h_border;
338 u8 v_border;
339 fixed20_12 vsc;
340 fixed20_12 hsc;
341 struct drm_display_mode native_mode;
342 int pll_id;
343 /* page flipping */
344 struct workqueue_struct *flip_queue;
345 struct radeon_flip_work *flip_work;
346 enum radeon_flip_status flip_status;
347 /* pll sharing */
348 struct radeon_atom_ss ss;
349 bool ss_enabled;
350 u32 adjusted_clock;
351 int bpc;
352 u32 pll_reference_div;
353 u32 pll_post_div;
354 u32 pll_flags;
355 struct drm_encoder *encoder;
356 struct drm_connector *connector;
357 /* for dpm */
358 u32 line_time;
359 u32 wm_low;
360 u32 wm_high;
361 u32 lb_vblank_lead_lines;
362 struct drm_display_mode hw_mode;
363 enum radeon_output_csc output_csc;
364 };
365
366 struct radeon_encoder_primary_dac {
367 /* legacy primary dac */
368 uint32_t ps2_pdac_adj;
369 };
370
371 struct radeon_encoder_lvds {
372 /* legacy lvds */
373 uint16_t panel_vcc_delay;
374 uint8_t panel_pwr_delay;
375 uint8_t panel_digon_delay;
376 uint8_t panel_blon_delay;
377 uint16_t panel_ref_divider;
378 uint8_t panel_post_divider;
379 uint16_t panel_fb_divider;
380 bool use_bios_dividers;
381 uint32_t lvds_gen_cntl;
382 /* panel mode */
383 struct drm_display_mode native_mode;
384 struct backlight_device *bl_dev;
385 int dpms_mode;
386 uint8_t backlight_level;
387 };
388
389 struct radeon_encoder_tv_dac {
390 /* legacy tv dac */
391 uint32_t ps2_tvdac_adj;
392 uint32_t ntsc_tvdac_adj;
393 uint32_t pal_tvdac_adj;
394
395 int h_pos;
396 int v_pos;
397 int h_size;
398 int supported_tv_stds;
399 bool tv_on;
400 enum radeon_tv_std tv_std;
401 struct radeon_tv_regs tv;
402 };
403
404 struct radeon_encoder_int_tmds {
405 /* legacy int tmds */
406 struct radeon_tmds_pll tmds_pll[4];
407 };
408
409 struct radeon_encoder_ext_tmds {
410 /* tmds over dvo */
411 struct radeon_i2c_chan *i2c_bus;
412 uint8_t slave_addr;
413 enum radeon_dvo_chip dvo_chip;
414 };
415
416 /* spread spectrum */
417 struct radeon_encoder_atom_dig {
418 bool linkb;
419 /* atom dig */
420 bool coherent_mode;
421 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
422 /* atom lvds/edp */
423 uint32_t lcd_misc;
424 uint16_t panel_pwr_delay;
425 uint32_t lcd_ss_id;
426 /* panel mode */
427 struct drm_display_mode native_mode;
428 struct backlight_device *bl_dev;
429 int dpms_mode;
430 uint8_t backlight_level;
431 int panel_mode;
432 struct radeon_afmt *afmt;
433 struct r600_audio_pin *pin;
434 };
435
436 struct radeon_encoder_atom_dac {
437 enum radeon_tv_std tv_std;
438 };
439
440 struct radeon_encoder {
441 struct drm_encoder base;
442 uint32_t encoder_enum;
443 uint32_t encoder_id;
444 uint32_t devices;
445 uint32_t active_device;
446 uint32_t flags;
447 uint32_t pixel_clock;
448 enum radeon_rmx_type rmx_type;
449 enum radeon_underscan_type underscan_type;
450 uint32_t underscan_hborder;
451 uint32_t underscan_vborder;
452 struct drm_display_mode native_mode;
453 void *enc_priv;
454 int audio_polling_active;
455 bool is_ext_encoder;
456 u16 caps;
457 struct radeon_audio_funcs *audio;
458 enum radeon_output_csc output_csc;
459 bool can_mst;
460 uint32_t offset;
461 };
462
463 struct radeon_connector_atom_dig {
464 uint32_t igp_lane_info;
465 /* displayport */
466 u8 dpcd[DP_RECEIVER_CAP_SIZE];
467 u8 dp_sink_type;
468 int dp_clock;
469 int dp_lane_count;
470 bool edp_on;
471 };
472
473 struct radeon_gpio_rec {
474 bool valid;
475 u8 id;
476 u32 reg;
477 u32 mask;
478 u32 shift;
479 };
480
481 struct radeon_hpd {
482 enum radeon_hpd_id hpd;
483 u8 plugged_state;
484 struct radeon_gpio_rec gpio;
485 };
486
487 struct radeon_router {
488 u32 router_id;
489 struct radeon_i2c_bus_rec i2c_info;
490 u8 i2c_addr;
491 /* i2c mux */
492 bool ddc_valid;
493 u8 ddc_mux_type;
494 u8 ddc_mux_control_pin;
495 u8 ddc_mux_state;
496 /* clock/data mux */
497 bool cd_valid;
498 u8 cd_mux_type;
499 u8 cd_mux_control_pin;
500 u8 cd_mux_state;
501 };
502
503 enum radeon_connector_audio {
504 RADEON_AUDIO_DISABLE = 0,
505 RADEON_AUDIO_ENABLE = 1,
506 RADEON_AUDIO_AUTO = 2
507 };
508
509 enum radeon_connector_dither {
510 RADEON_FMT_DITHER_DISABLE = 0,
511 RADEON_FMT_DITHER_ENABLE = 1,
512 };
513
514 struct radeon_connector {
515 struct drm_connector base;
516 uint32_t connector_id;
517 uint32_t devices;
518 struct radeon_i2c_chan *ddc_bus;
519 /* some systems have an hdmi and vga port with a shared ddc line */
520 bool shared_ddc;
521 bool use_digital;
522 /* we need to mind the EDID between detect
523 and get modes due to analog/digital/tvencoder */
524 struct edid *edid;
525 void *con_priv;
526 bool dac_load_detect;
527 bool detected_by_load; /* if the connection status was determined by load */
528 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
529 uint16_t connector_object_id;
530 struct radeon_hpd hpd;
531 struct radeon_router router;
532 struct radeon_i2c_chan *router_bus;
533 enum radeon_connector_audio audio;
534 enum radeon_connector_dither dither;
535 int pixelclock_for_modeset;
536 };
537
538 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
539 ((em) == ATOM_ENCODER_MODE_DP_MST))
540
541 struct atom_clock_dividers {
542 u32 post_div;
543 union {
544 struct {
545 #ifdef __BIG_ENDIAN
546 u32 reserved : 6;
547 u32 whole_fb_div : 12;
548 u32 frac_fb_div : 14;
549 #else
550 u32 frac_fb_div : 14;
551 u32 whole_fb_div : 12;
552 u32 reserved : 6;
553 #endif
554 };
555 u32 fb_div;
556 };
557 u32 ref_div;
558 bool enable_post_div;
559 bool enable_dithen;
560 u32 vco_mode;
561 u32 real_clock;
562 /* added for CI */
563 u32 post_divider;
564 u32 flags;
565 };
566
567 struct atom_mpll_param {
568 union {
569 struct {
570 #ifdef __BIG_ENDIAN
571 u32 reserved : 8;
572 u32 clkfrac : 12;
573 u32 clkf : 12;
574 #else
575 u32 clkf : 12;
576 u32 clkfrac : 12;
577 u32 reserved : 8;
578 #endif
579 };
580 u32 fb_div;
581 };
582 u32 post_div;
583 u32 bwcntl;
584 u32 dll_speed;
585 u32 vco_mode;
586 u32 yclk_sel;
587 u32 qdr;
588 u32 half_rate;
589 };
590
591 #define MEM_TYPE_GDDR5 0x50
592 #define MEM_TYPE_GDDR4 0x40
593 #define MEM_TYPE_GDDR3 0x30
594 #define MEM_TYPE_DDR2 0x20
595 #define MEM_TYPE_GDDR1 0x10
596 #define MEM_TYPE_DDR3 0xb0
597 #define MEM_TYPE_MASK 0xf0
598
599 struct atom_memory_info {
600 u8 mem_vendor;
601 u8 mem_type;
602 };
603
604 #define MAX_AC_TIMING_ENTRIES 16
605
606 struct atom_memory_clock_range_table
607 {
608 u8 num_entries;
609 u8 rsv[3];
610 u32 mclk[MAX_AC_TIMING_ENTRIES];
611 };
612
613 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
614 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
615
616 struct atom_mc_reg_entry {
617 u32 mclk_max;
618 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
619 };
620
621 struct atom_mc_register_address {
622 u16 s1;
623 u8 pre_reg_data;
624 };
625
626 struct atom_mc_reg_table {
627 u8 last;
628 u8 num_entries;
629 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
630 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
631 };
632
633 #define MAX_VOLTAGE_ENTRIES 32
634
635 struct atom_voltage_table_entry
636 {
637 u16 value;
638 u32 smio_low;
639 };
640
641 struct atom_voltage_table
642 {
643 u32 count;
644 u32 mask_low;
645 u32 phase_delay;
646 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
647 };
648
649 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
650 #define DRM_SCANOUTPOS_VALID (1 << 0)
651 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
652 #define DRM_SCANOUTPOS_ACCURATE (1 << 2)
653 #define USE_REAL_VBLANKSTART (1 << 30)
654 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
655
656 extern void
657 radeon_add_atom_connector(struct drm_device *dev,
658 uint32_t connector_id,
659 uint32_t supported_device,
660 int connector_type,
661 struct radeon_i2c_bus_rec *i2c_bus,
662 uint32_t igp_lane_info,
663 uint16_t connector_object_id,
664 struct radeon_hpd *hpd,
665 struct radeon_router *router);
666 extern void
667 radeon_add_legacy_connector(struct drm_device *dev,
668 uint32_t connector_id,
669 uint32_t supported_device,
670 int connector_type,
671 struct radeon_i2c_bus_rec *i2c_bus,
672 uint16_t connector_object_id,
673 struct radeon_hpd *hpd);
674 extern uint32_t
675 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
676 uint8_t dac);
677 extern void radeon_link_encoder_connector(struct drm_device *dev);
678
679 extern enum radeon_tv_std
680 radeon_combios_get_tv_info(struct radeon_device *rdev);
681 extern enum radeon_tv_std
682 radeon_atombios_get_tv_info(struct radeon_device *rdev);
683 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
684 u16 *vddc, u16 *vddci, u16 *mvdd);
685
686 extern void
687 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
688 struct drm_encoder *encoder,
689 bool connected);
690 extern void
691 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
692 struct drm_encoder *encoder,
693 bool connected);
694
695 extern struct drm_connector *
696 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
697 extern struct drm_connector *
698 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
699 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
700 u32 pixel_clock);
701
702 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
703 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
704 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
705 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
706
707 extern struct edid *radeon_connector_edid(struct drm_connector *connector);
708
709 extern void radeon_connector_hotplug(struct drm_connector *connector);
710 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
711 struct drm_display_mode *mode);
712 extern void radeon_dp_set_link_config(struct drm_connector *connector,
713 const struct drm_display_mode *mode);
714 extern void radeon_dp_link_train(struct drm_encoder *encoder,
715 struct drm_connector *connector);
716 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
717 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
718 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
719 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
720 struct drm_connector *connector);
721 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
722 u8 power_state);
723 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
724 extern ssize_t
725 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
726
727 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
728 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
729 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
730 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
731 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
732 int action, uint8_t lane_num,
733 uint8_t lane_set);
734 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
735 int action, uint8_t lane_num,
736 uint8_t lane_set, int fe);
737 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
738 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
739 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
740
741 extern void radeon_i2c_init(struct radeon_device *rdev);
742 extern void radeon_i2c_fini(struct radeon_device *rdev);
743 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
744 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
745 extern void radeon_i2c_add(struct radeon_device *rdev,
746 struct radeon_i2c_bus_rec *rec,
747 const char *name);
748 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
749 struct radeon_i2c_bus_rec *i2c_bus);
750 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
751 struct radeon_i2c_bus_rec *rec,
752 const char *name);
753 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
754 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
755 u8 slave_addr,
756 u8 addr,
757 u8 *val);
758 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
759 u8 slave_addr,
760 u8 addr,
761 u8 val);
762 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
763 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
764 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
765
766 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
767 struct radeon_atom_ss *ss,
768 int id);
769 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
770 struct radeon_atom_ss *ss,
771 int id, u32 clock);
772 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
773 u8 id);
774
775 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
776 uint64_t freq,
777 uint32_t *dot_clock_p,
778 uint32_t *fb_div_p,
779 uint32_t *frac_fb_div_p,
780 uint32_t *ref_div_p,
781 uint32_t *post_div_p);
782
783 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
784 u32 freq,
785 u32 *dot_clock_p,
786 u32 *fb_div_p,
787 u32 *frac_fb_div_p,
788 u32 *ref_div_p,
789 u32 *post_div_p);
790
791 extern void radeon_setup_encoder_clones(struct drm_device *dev);
792
793 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
794 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
795 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
796 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
797 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
798 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
799 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
800 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
801 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
802 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
803 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
804
805 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
806 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
807 struct drm_framebuffer *old_fb);
808 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
809 struct drm_framebuffer *fb,
810 int x, int y,
811 enum mode_set_atomic state);
812 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
813 struct drm_display_mode *mode,
814 struct drm_display_mode *adjusted_mode,
815 int x, int y,
816 struct drm_framebuffer *old_fb);
817 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
818
819 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
820 struct drm_framebuffer *old_fb);
821 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
822 struct drm_framebuffer *fb,
823 int x, int y,
824 enum mode_set_atomic state);
825 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
826 struct drm_framebuffer *fb,
827 int x, int y, int atomic);
828 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
829 struct drm_file *file_priv,
830 uint32_t handle,
831 uint32_t width,
832 uint32_t height,
833 int32_t hot_x,
834 int32_t hot_y);
835 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
836 int x, int y);
837 extern void radeon_cursor_reset(struct drm_crtc *crtc);
838
839 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
840 unsigned int flags, int *vpos, int *hpos,
841 ktime_t *stime, ktime_t *etime,
842 const struct drm_display_mode *mode);
843
844 extern bool
845 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
846 int *vpos, int *hpos,
847 ktime_t *stime, ktime_t *etime,
848 const struct drm_display_mode *mode);
849
850 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
851 extern struct edid *
852 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
853 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
854 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
855 extern struct radeon_encoder_atom_dig *
856 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
857 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
858 struct radeon_encoder_int_tmds *tmds);
859 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
860 struct radeon_encoder_int_tmds *tmds);
861 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
862 struct radeon_encoder_int_tmds *tmds);
863 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
864 struct radeon_encoder_ext_tmds *tmds);
865 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
866 struct radeon_encoder_ext_tmds *tmds);
867 extern struct radeon_encoder_primary_dac *
868 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
869 extern struct radeon_encoder_tv_dac *
870 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
871 extern struct radeon_encoder_lvds *
872 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
873 extern struct radeon_encoder_tv_dac *
874 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
875 extern struct radeon_encoder_primary_dac *
876 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
877 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
878 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
879 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
880 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
881 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
882 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
883 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
884 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
885 extern void
886 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
887 extern void
888 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
889 extern void
890 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
891 extern void
892 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
893 int radeon_framebuffer_init(struct drm_device *dev,
894 struct drm_framebuffer *rfb,
895 const struct drm_mode_fb_cmd2 *mode_cmd,
896 struct drm_gem_object *obj);
897
898 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
899 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
900 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
901 void radeon_atombios_init_crtc(struct drm_device *dev,
902 struct radeon_crtc *radeon_crtc);
903 void radeon_legacy_init_crtc(struct drm_device *dev,
904 struct radeon_crtc *radeon_crtc);
905
906 void radeon_get_clock_info(struct drm_device *dev);
907
908 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
909 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
910
911 void radeon_enc_destroy(struct drm_encoder *encoder);
912 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
913 void radeon_combios_asic_init(struct drm_device *dev);
914 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
915 const struct drm_display_mode *mode,
916 struct drm_display_mode *adjusted_mode);
917 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
918 struct drm_display_mode *adjusted_mode);
919 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
920
921 /* legacy tv */
922 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
923 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
924 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
925 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
926 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
927 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
928 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
929 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
930 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
931 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
932 struct drm_display_mode *mode,
933 struct drm_display_mode *adjusted_mode);
934
935 /* fmt blocks */
936 void avivo_program_fmt(struct drm_encoder *encoder);
937 void dce3_program_fmt(struct drm_encoder *encoder);
938 void dce4_program_fmt(struct drm_encoder *encoder);
939 void dce8_program_fmt(struct drm_encoder *encoder);
940
941 /* fbdev layer */
942 #if defined(CONFIG_DRM_FBDEV_EMULATION)
943 void radeon_fbdev_setup(struct radeon_device *rdev);
944 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
945 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
946 #else
radeon_fbdev_setup(struct radeon_device * rdev)947 static inline void radeon_fbdev_setup(struct radeon_device *rdev)
948 { }
radeon_fbdev_set_suspend(struct radeon_device * rdev,int state)949 static inline void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
950 { }
radeon_fbdev_robj_is_fb(struct radeon_device * rdev,struct radeon_bo * robj)951 static inline bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
952 {
953 return false;
954 }
955 #endif
956
957 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
958
959 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
960
961 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
962 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
963 #endif
964