1 /*
2 * CNS3xxx common devices
3 *
4 * Copyright 2008 Cavium Networks
5 * Scott Shu
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/io.h>
15 #include <linux/init.h>
16 #include <linux/compiler.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <mach/cns3xxx.h>
20 #include <mach/irqs.h>
21 #include <mach/pm.h>
22 #include "core.h"
23 #include "devices.h"
24
25 /*
26 * AHCI
27 */
28 static struct resource cns3xxx_ahci_resource[] = {
29 [0] = {
30 .start = CNS3XXX_SATA2_BASE,
31 .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .start = IRQ_CNS3XXX_SATA,
36 .end = IRQ_CNS3XXX_SATA,
37 .flags = IORESOURCE_IRQ,
38 },
39 };
40
41 static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
42
43 static struct platform_device cns3xxx_ahci_pdev = {
44 .name = "ahci",
45 .id = 0,
46 .resource = cns3xxx_ahci_resource,
47 .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
48 .dev = {
49 .dma_mask = &cns3xxx_ahci_dmamask,
50 .coherent_dma_mask = DMA_BIT_MASK(32),
51 },
52 };
53
cns3xxx_ahci_init(void)54 void __init cns3xxx_ahci_init(void)
55 {
56 u32 tmp;
57
58 tmp = __raw_readl(MISC_SATA_POWER_MODE);
59 tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
60 tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
61 __raw_writel(tmp, MISC_SATA_POWER_MODE);
62
63 /* Enable SATA PHY */
64 cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
65 cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
66
67 /* Enable SATA Clock */
68 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
69
70 /* De-Asscer SATA Reset */
71 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
72
73 platform_device_register(&cns3xxx_ahci_pdev);
74 }
75
76 /*
77 * SDHCI
78 */
79 static struct resource cns3xxx_sdhci_resources[] = {
80 [0] = {
81 .start = CNS3XXX_SDIO_BASE,
82 .end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
83 .flags = IORESOURCE_MEM,
84 },
85 [1] = {
86 .start = IRQ_CNS3XXX_SDIO,
87 .end = IRQ_CNS3XXX_SDIO,
88 .flags = IORESOURCE_IRQ,
89 },
90 };
91
92 static struct platform_device cns3xxx_sdhci_pdev = {
93 .name = "sdhci-cns3xxx",
94 .id = 0,
95 .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources),
96 .resource = cns3xxx_sdhci_resources,
97 };
98
cns3xxx_sdhci_init(void)99 void __init cns3xxx_sdhci_init(void)
100 {
101 u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
102 u32 gpioa_pins = __raw_readl(gpioa);
103
104 /* MMC/SD pins share with GPIOA */
105 gpioa_pins |= 0x1fff0004;
106 __raw_writel(gpioa_pins, gpioa);
107
108 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
109 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
110
111 platform_device_register(&cns3xxx_sdhci_pdev);
112 }
113