1 /* $Id: isac.c,v 1.1.4.1 2001/11/20 14:19:36 kai Exp $
2 *
3 * ISAC specific routines
4 *
5 * Author Karsten Keil
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 * For changes and modifications please read
12 * ../../../Documentation/isdn/HiSax.cert
13 *
14 */
15
16 #define __NO_VERSION__
17 #include "hisax.h"
18 #include "isac.h"
19 #include "arcofi.h"
20 #include "isdnl1.h"
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23
24 #define DBUSY_TIMER_VALUE 80
25 #define ARCOFI_USE 1
26
27 static char *ISACVer[] __devinitdata =
28 {"2086/2186 V1.1", "2085 B1", "2085 B2",
29 "2085 V2.3"};
30
31 void
ISACVersion(struct IsdnCardState * cs,char * s)32 ISACVersion(struct IsdnCardState *cs, char *s)
33 {
34 int val;
35
36 val = cs->readisac(cs, ISAC_RBCH);
37 printk(KERN_INFO "%s ISAC version (%x): %s\n", s, val, ISACVer[(val >> 5) & 3]);
38 }
39
40 static void
ph_command(struct IsdnCardState * cs,unsigned int command)41 ph_command(struct IsdnCardState *cs, unsigned int command)
42 {
43 if (cs->debug & L1_DEB_ISAC)
44 debugl1(cs, "ph_command %x", command);
45 cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3);
46 }
47
48
49 static void
isac_new_ph(struct IsdnCardState * cs)50 isac_new_ph(struct IsdnCardState *cs)
51 {
52 switch (cs->dc.isac.ph_state) {
53 case (ISAC_IND_RS):
54 case (ISAC_IND_EI):
55 ph_command(cs, ISAC_CMD_DUI);
56 l1_msg(cs, HW_RESET | INDICATION, NULL);
57 break;
58 case (ISAC_IND_DID):
59 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
60 break;
61 case (ISAC_IND_DR):
62 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
63 break;
64 case (ISAC_IND_PU):
65 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
66 break;
67 case (ISAC_IND_RSY):
68 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
69 break;
70 case (ISAC_IND_ARD):
71 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
72 break;
73 case (ISAC_IND_AI8):
74 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
75 break;
76 case (ISAC_IND_AI10):
77 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
78 break;
79 default:
80 break;
81 }
82 }
83
84 static void
isac_bh(struct IsdnCardState * cs)85 isac_bh(struct IsdnCardState *cs)
86 {
87 struct PStack *stptr;
88
89 if (!cs)
90 return;
91 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
92 if (cs->debug)
93 debugl1(cs, "D-Channel Busy cleared");
94 stptr = cs->stlist;
95 while (stptr != NULL) {
96 stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
97 stptr = stptr->next;
98 }
99 }
100 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
101 isac_new_ph(cs);
102 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
103 DChannel_proc_rcv(cs);
104 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
105 DChannel_proc_xmt(cs);
106 #if ARCOFI_USE
107 if (!test_bit(HW_ARCOFI, &cs->HW_Flags))
108 return;
109 if (test_and_clear_bit(D_RX_MON1, &cs->event))
110 arcofi_fsm(cs, ARCOFI_RX_END, NULL);
111 if (test_and_clear_bit(D_TX_MON1, &cs->event))
112 arcofi_fsm(cs, ARCOFI_TX_END, NULL);
113 #endif
114 }
115
116 void
isac_empty_fifo(struct IsdnCardState * cs,int count)117 isac_empty_fifo(struct IsdnCardState *cs, int count)
118 {
119 u_char *ptr;
120 long flags;
121
122 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
123 debugl1(cs, "isac_empty_fifo");
124
125 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
126 if (cs->debug & L1_DEB_WARN)
127 debugl1(cs, "isac_empty_fifo overrun %d",
128 cs->rcvidx + count);
129 cs->writeisac(cs, ISAC_CMDR, 0x80);
130 cs->rcvidx = 0;
131 return;
132 }
133 ptr = cs->rcvbuf + cs->rcvidx;
134 cs->rcvidx += count;
135 save_flags(flags);
136 cli();
137 cs->readisacfifo(cs, ptr, count);
138 cs->writeisac(cs, ISAC_CMDR, 0x80);
139 restore_flags(flags);
140 if (cs->debug & L1_DEB_ISAC_FIFO) {
141 char *t = cs->dlog;
142
143 t += sprintf(t, "isac_empty_fifo cnt %d", count);
144 QuickHex(t, ptr, count);
145 debugl1(cs, cs->dlog);
146 }
147 }
148
149 static void
isac_fill_fifo(struct IsdnCardState * cs)150 isac_fill_fifo(struct IsdnCardState *cs)
151 {
152 int count, more;
153 u_char *ptr;
154 long flags;
155
156 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
157 debugl1(cs, "isac_fill_fifo");
158
159 if (!cs->tx_skb)
160 return;
161
162 count = cs->tx_skb->len;
163 if (count <= 0)
164 return;
165
166 more = 0;
167 if (count > 32) {
168 more = !0;
169 count = 32;
170 }
171 save_flags(flags);
172 cli();
173 ptr = cs->tx_skb->data;
174 skb_pull(cs->tx_skb, count);
175 cs->tx_cnt += count;
176 cs->writeisacfifo(cs, ptr, count);
177 cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);
178 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
179 debugl1(cs, "isac_fill_fifo dbusytimer running");
180 del_timer(&cs->dbusytimer);
181 }
182 init_timer(&cs->dbusytimer);
183 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
184 add_timer(&cs->dbusytimer);
185 restore_flags(flags);
186 if (cs->debug & L1_DEB_ISAC_FIFO) {
187 char *t = cs->dlog;
188
189 t += sprintf(t, "isac_fill_fifo cnt %d", count);
190 QuickHex(t, ptr, count);
191 debugl1(cs, cs->dlog);
192 }
193 }
194
195 void
isac_sched_event(struct IsdnCardState * cs,int event)196 isac_sched_event(struct IsdnCardState *cs, int event)
197 {
198 test_and_set_bit(event, &cs->event);
199 queue_task(&cs->tqueue, &tq_immediate);
200 mark_bh(IMMEDIATE_BH);
201 }
202
203 void
isac_interrupt(struct IsdnCardState * cs,u_char val)204 isac_interrupt(struct IsdnCardState *cs, u_char val)
205 {
206 u_char exval, v1;
207 struct sk_buff *skb;
208 unsigned int count;
209 long flags;
210
211 if (cs->debug & L1_DEB_ISAC)
212 debugl1(cs, "ISAC interrupt %x", val);
213 if (val & 0x80) { /* RME */
214 exval = cs->readisac(cs, ISAC_RSTA);
215 if ((exval & 0x70) != 0x20) {
216 if (exval & 0x40) {
217 if (cs->debug & L1_DEB_WARN)
218 debugl1(cs, "ISAC RDO");
219 #ifdef ERROR_STATISTIC
220 cs->err_rx++;
221 #endif
222 }
223 if (!(exval & 0x20)) {
224 if (cs->debug & L1_DEB_WARN)
225 debugl1(cs, "ISAC CRC error");
226 #ifdef ERROR_STATISTIC
227 cs->err_crc++;
228 #endif
229 }
230 cs->writeisac(cs, ISAC_CMDR, 0x80);
231 } else {
232 count = cs->readisac(cs, ISAC_RBCL) & 0x1f;
233 if (count == 0)
234 count = 32;
235 isac_empty_fifo(cs, count);
236 save_flags(flags);
237 cli();
238 if ((count = cs->rcvidx) > 0) {
239 cs->rcvidx = 0;
240 if (!(skb = alloc_skb(count, GFP_ATOMIC)))
241 printk(KERN_WARNING "HiSax: D receive out of memory\n");
242 else {
243 memcpy(skb_put(skb, count), cs->rcvbuf, count);
244 skb_queue_tail(&cs->rq, skb);
245 }
246 }
247 restore_flags(flags);
248 }
249 cs->rcvidx = 0;
250 isac_sched_event(cs, D_RCVBUFREADY);
251 }
252 if (val & 0x40) { /* RPF */
253 isac_empty_fifo(cs, 32);
254 }
255 if (val & 0x20) { /* RSC */
256 /* never */
257 if (cs->debug & L1_DEB_WARN)
258 debugl1(cs, "ISAC RSC interrupt");
259 }
260 if (val & 0x10) { /* XPR */
261 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
262 del_timer(&cs->dbusytimer);
263 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
264 isac_sched_event(cs, D_CLEARBUSY);
265 if (cs->tx_skb) {
266 if (cs->tx_skb->len) {
267 isac_fill_fifo(cs);
268 goto afterXPR;
269 } else {
270 dev_kfree_skb_irq(cs->tx_skb);
271 cs->tx_cnt = 0;
272 cs->tx_skb = NULL;
273 }
274 }
275 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
276 cs->tx_cnt = 0;
277 isac_fill_fifo(cs);
278 } else
279 isac_sched_event(cs, D_XMTBUFREADY);
280 }
281 afterXPR:
282 if (val & 0x04) { /* CISQ */
283 exval = cs->readisac(cs, ISAC_CIR0);
284 if (cs->debug & L1_DEB_ISAC)
285 debugl1(cs, "ISAC CIR0 %02X", exval );
286 if (exval & 2) {
287 cs->dc.isac.ph_state = (exval >> 2) & 0xf;
288 if (cs->debug & L1_DEB_ISAC)
289 debugl1(cs, "ph_state change %x", cs->dc.isac.ph_state);
290 isac_sched_event(cs, D_L1STATECHANGE);
291 }
292 if (exval & 1) {
293 exval = cs->readisac(cs, ISAC_CIR1);
294 if (cs->debug & L1_DEB_ISAC)
295 debugl1(cs, "ISAC CIR1 %02X", exval );
296 }
297 }
298 if (val & 0x02) { /* SIN */
299 /* never */
300 if (cs->debug & L1_DEB_WARN)
301 debugl1(cs, "ISAC SIN interrupt");
302 }
303 if (val & 0x01) { /* EXI */
304 exval = cs->readisac(cs, ISAC_EXIR);
305 if (cs->debug & L1_DEB_WARN)
306 debugl1(cs, "ISAC EXIR %02x", exval);
307 if (exval & 0x80) { /* XMR */
308 debugl1(cs, "ISAC XMR");
309 printk(KERN_WARNING "HiSax: ISAC XMR\n");
310 }
311 if (exval & 0x40) { /* XDU */
312 debugl1(cs, "ISAC XDU");
313 printk(KERN_WARNING "HiSax: ISAC XDU\n");
314 #ifdef ERROR_STATISTIC
315 cs->err_tx++;
316 #endif
317 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
318 del_timer(&cs->dbusytimer);
319 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
320 isac_sched_event(cs, D_CLEARBUSY);
321 if (cs->tx_skb) { /* Restart frame */
322 skb_push(cs->tx_skb, cs->tx_cnt);
323 cs->tx_cnt = 0;
324 isac_fill_fifo(cs);
325 } else {
326 printk(KERN_WARNING "HiSax: ISAC XDU no skb\n");
327 debugl1(cs, "ISAC XDU no skb");
328 }
329 }
330 if (exval & 0x04) { /* MOS */
331 v1 = cs->readisac(cs, ISAC_MOSR);
332 if (cs->debug & L1_DEB_MONITOR)
333 debugl1(cs, "ISAC MOSR %02x", v1);
334 #if ARCOFI_USE
335 if (v1 & 0x08) {
336 if (!cs->dc.isac.mon_rx) {
337 if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
338 if (cs->debug & L1_DEB_WARN)
339 debugl1(cs, "ISAC MON RX out of memory!");
340 cs->dc.isac.mocr &= 0xf0;
341 cs->dc.isac.mocr |= 0x0a;
342 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
343 goto afterMONR0;
344 } else
345 cs->dc.isac.mon_rxp = 0;
346 }
347 if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
348 cs->dc.isac.mocr &= 0xf0;
349 cs->dc.isac.mocr |= 0x0a;
350 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
351 cs->dc.isac.mon_rxp = 0;
352 if (cs->debug & L1_DEB_WARN)
353 debugl1(cs, "ISAC MON RX overflow!");
354 goto afterMONR0;
355 }
356 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR0);
357 if (cs->debug & L1_DEB_MONITOR)
358 debugl1(cs, "ISAC MOR0 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]);
359 if (cs->dc.isac.mon_rxp == 1) {
360 cs->dc.isac.mocr |= 0x04;
361 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
362 }
363 }
364 afterMONR0:
365 if (v1 & 0x80) {
366 if (!cs->dc.isac.mon_rx) {
367 if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
368 if (cs->debug & L1_DEB_WARN)
369 debugl1(cs, "ISAC MON RX out of memory!");
370 cs->dc.isac.mocr &= 0x0f;
371 cs->dc.isac.mocr |= 0xa0;
372 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
373 goto afterMONR1;
374 } else
375 cs->dc.isac.mon_rxp = 0;
376 }
377 if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
378 cs->dc.isac.mocr &= 0x0f;
379 cs->dc.isac.mocr |= 0xa0;
380 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
381 cs->dc.isac.mon_rxp = 0;
382 if (cs->debug & L1_DEB_WARN)
383 debugl1(cs, "ISAC MON RX overflow!");
384 goto afterMONR1;
385 }
386 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR1);
387 if (cs->debug & L1_DEB_MONITOR)
388 debugl1(cs, "ISAC MOR1 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]);
389 cs->dc.isac.mocr |= 0x40;
390 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
391 }
392 afterMONR1:
393 if (v1 & 0x04) {
394 cs->dc.isac.mocr &= 0xf0;
395 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
396 cs->dc.isac.mocr |= 0x0a;
397 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
398 isac_sched_event(cs, D_RX_MON0);
399 }
400 if (v1 & 0x40) {
401 cs->dc.isac.mocr &= 0x0f;
402 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
403 cs->dc.isac.mocr |= 0xa0;
404 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
405 isac_sched_event(cs, D_RX_MON1);
406 }
407 if (v1 & 0x02) {
408 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
409 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
410 !(v1 & 0x08))) {
411 cs->dc.isac.mocr &= 0xf0;
412 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
413 cs->dc.isac.mocr |= 0x0a;
414 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
415 if (cs->dc.isac.mon_txc &&
416 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
417 isac_sched_event(cs, D_TX_MON0);
418 goto AfterMOX0;
419 }
420 if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) {
421 isac_sched_event(cs, D_TX_MON0);
422 goto AfterMOX0;
423 }
424 cs->writeisac(cs, ISAC_MOX0,
425 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
426 if (cs->debug & L1_DEB_MONITOR)
427 debugl1(cs, "ISAC %02x -> MOX0", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]);
428 }
429 AfterMOX0:
430 if (v1 & 0x20) {
431 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
432 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
433 !(v1 & 0x80))) {
434 cs->dc.isac.mocr &= 0x0f;
435 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
436 cs->dc.isac.mocr |= 0xa0;
437 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
438 if (cs->dc.isac.mon_txc &&
439 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
440 isac_sched_event(cs, D_TX_MON1);
441 goto AfterMOX1;
442 }
443 if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) {
444 isac_sched_event(cs, D_TX_MON1);
445 goto AfterMOX1;
446 }
447 cs->writeisac(cs, ISAC_MOX1,
448 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
449 if (cs->debug & L1_DEB_MONITOR)
450 debugl1(cs, "ISAC %02x -> MOX1", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]);
451 }
452 AfterMOX1:;
453 #endif
454 }
455 }
456 }
457
458 static void
ISAC_l1hw(struct PStack * st,int pr,void * arg)459 ISAC_l1hw(struct PStack *st, int pr, void *arg)
460 {
461 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
462 struct sk_buff *skb = arg;
463 int val;
464
465 switch (pr) {
466 case (PH_DATA |REQUEST):
467 if (cs->debug & DEB_DLOG_HEX)
468 LogFrame(cs, skb->data, skb->len);
469 if (cs->debug & DEB_DLOG_VERBOSE)
470 dlogframe(cs, skb, 0);
471 if (cs->tx_skb) {
472 skb_queue_tail(&cs->sq, skb);
473 #ifdef L2FRAME_DEBUG /* psa */
474 if (cs->debug & L1_DEB_LAPD)
475 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
476 #endif
477 } else {
478 cs->tx_skb = skb;
479 cs->tx_cnt = 0;
480 #ifdef L2FRAME_DEBUG /* psa */
481 if (cs->debug & L1_DEB_LAPD)
482 Logl2Frame(cs, skb, "PH_DATA", 0);
483 #endif
484 isac_fill_fifo(cs);
485 }
486 break;
487 case (PH_PULL |INDICATION):
488 if (cs->tx_skb) {
489 if (cs->debug & L1_DEB_WARN)
490 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
491 skb_queue_tail(&cs->sq, skb);
492 break;
493 }
494 if (cs->debug & DEB_DLOG_HEX)
495 LogFrame(cs, skb->data, skb->len);
496 if (cs->debug & DEB_DLOG_VERBOSE)
497 dlogframe(cs, skb, 0);
498 cs->tx_skb = skb;
499 cs->tx_cnt = 0;
500 #ifdef L2FRAME_DEBUG /* psa */
501 if (cs->debug & L1_DEB_LAPD)
502 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
503 #endif
504 isac_fill_fifo(cs);
505 break;
506 case (PH_PULL | REQUEST):
507 #ifdef L2FRAME_DEBUG /* psa */
508 if (cs->debug & L1_DEB_LAPD)
509 debugl1(cs, "-> PH_REQUEST_PULL");
510 #endif
511 if (!cs->tx_skb) {
512 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
513 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
514 } else
515 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
516 break;
517 case (HW_RESET | REQUEST):
518 if ((cs->dc.isac.ph_state == ISAC_IND_EI) ||
519 (cs->dc.isac.ph_state == ISAC_IND_DR) ||
520 (cs->dc.isac.ph_state == ISAC_IND_RS))
521 ph_command(cs, ISAC_CMD_TIM);
522 else
523 ph_command(cs, ISAC_CMD_RS);
524 break;
525 case (HW_ENABLE | REQUEST):
526 ph_command(cs, ISAC_CMD_TIM);
527 break;
528 case (HW_INFO3 | REQUEST):
529 ph_command(cs, ISAC_CMD_AR8);
530 break;
531 case (HW_TESTLOOP | REQUEST):
532 val = 0;
533 if (1 & (long) arg)
534 val |= 0x0c;
535 if (2 & (long) arg)
536 val |= 0x3;
537 if (test_bit(HW_IOM1, &cs->HW_Flags)) {
538 /* IOM 1 Mode */
539 if (!val) {
540 cs->writeisac(cs, ISAC_SPCR, 0xa);
541 cs->writeisac(cs, ISAC_ADF1, 0x2);
542 } else {
543 cs->writeisac(cs, ISAC_SPCR, val);
544 cs->writeisac(cs, ISAC_ADF1, 0xa);
545 }
546 } else {
547 /* IOM 2 Mode */
548 cs->writeisac(cs, ISAC_SPCR, val);
549 if (val)
550 cs->writeisac(cs, ISAC_ADF1, 0x8);
551 else
552 cs->writeisac(cs, ISAC_ADF1, 0x0);
553 }
554 break;
555 case (HW_DEACTIVATE | RESPONSE):
556 skb_queue_purge(&cs->rq);
557 skb_queue_purge(&cs->sq);
558 if (cs->tx_skb) {
559 dev_kfree_skb_any(cs->tx_skb);
560 cs->tx_skb = NULL;
561 }
562 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
563 del_timer(&cs->dbusytimer);
564 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
565 isac_sched_event(cs, D_CLEARBUSY);
566 break;
567 default:
568 if (cs->debug & L1_DEB_WARN)
569 debugl1(cs, "isac_l1hw unknown %04x", pr);
570 break;
571 }
572 }
573
574 void
setstack_isac(struct PStack * st,struct IsdnCardState * cs)575 setstack_isac(struct PStack *st, struct IsdnCardState *cs)
576 {
577 st->l1.l1hw = ISAC_l1hw;
578 }
579
580 void
DC_Close_isac(struct IsdnCardState * cs)581 DC_Close_isac(struct IsdnCardState *cs) {
582 if (cs->dc.isac.mon_rx) {
583 kfree(cs->dc.isac.mon_rx);
584 cs->dc.isac.mon_rx = NULL;
585 }
586 if (cs->dc.isac.mon_tx) {
587 kfree(cs->dc.isac.mon_tx);
588 cs->dc.isac.mon_tx = NULL;
589 }
590 }
591
592 static void
dbusy_timer_handler(struct IsdnCardState * cs)593 dbusy_timer_handler(struct IsdnCardState *cs)
594 {
595 struct PStack *stptr;
596 int rbch, star;
597
598 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
599 rbch = cs->readisac(cs, ISAC_RBCH);
600 star = cs->readisac(cs, ISAC_STAR);
601 if (cs->debug)
602 debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
603 rbch, star);
604 if (rbch & ISAC_RBCH_XAC) { /* D-Channel Busy */
605 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
606 stptr = cs->stlist;
607 while (stptr != NULL) {
608 stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
609 stptr = stptr->next;
610 }
611 } else {
612 /* discard frame; reset transceiver */
613 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
614 if (cs->tx_skb) {
615 dev_kfree_skb_any(cs->tx_skb);
616 cs->tx_cnt = 0;
617 cs->tx_skb = NULL;
618 } else {
619 printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
620 debugl1(cs, "D-Channel Busy no skb");
621 }
622 cs->writeisac(cs, ISAC_CMDR, 0x01); /* Transmitter reset */
623 cs->irq_func(cs->irq, cs, NULL);
624 }
625 }
626 }
627
628 void __devinit
initisac(struct IsdnCardState * cs)629 initisac(struct IsdnCardState *cs)
630 {
631 cs->tqueue.routine = (void *) (void *) isac_bh;
632 cs->setstack_d = setstack_isac;
633 cs->DC_Close = DC_Close_isac;
634 cs->dc.isac.mon_tx = NULL;
635 cs->dc.isac.mon_rx = NULL;
636 cs->dbusytimer.function = (void *) dbusy_timer_handler;
637 cs->dbusytimer.data = (long) cs;
638 init_timer(&cs->dbusytimer);
639 cs->writeisac(cs, ISAC_MASK, 0xff);
640 cs->dc.isac.mocr = 0xaa;
641 if (test_bit(HW_IOM1, &cs->HW_Flags)) {
642 /* IOM 1 Mode */
643 cs->writeisac(cs, ISAC_ADF2, 0x0);
644 cs->writeisac(cs, ISAC_SPCR, 0xa);
645 cs->writeisac(cs, ISAC_ADF1, 0x2);
646 cs->writeisac(cs, ISAC_STCR, 0x70);
647 cs->writeisac(cs, ISAC_MODE, 0xc9);
648 } else {
649 /* IOM 2 Mode */
650 if (!cs->dc.isac.adf2)
651 cs->dc.isac.adf2 = 0x80;
652 cs->writeisac(cs, ISAC_ADF2, cs->dc.isac.adf2);
653 cs->writeisac(cs, ISAC_SQXR, 0x2f);
654 cs->writeisac(cs, ISAC_SPCR, 0x00);
655 cs->writeisac(cs, ISAC_STCR, 0x70);
656 cs->writeisac(cs, ISAC_MODE, 0xc9);
657 cs->writeisac(cs, ISAC_TIMR, 0x00);
658 cs->writeisac(cs, ISAC_ADF1, 0x00);
659 }
660 ph_command(cs, ISAC_CMD_RS);
661 cs->writeisac(cs, ISAC_MASK, 0x0);
662 }
663
664 void __devinit
clear_pending_isac_ints(struct IsdnCardState * cs)665 clear_pending_isac_ints(struct IsdnCardState *cs)
666 {
667 int val, eval;
668
669 val = cs->readisac(cs, ISAC_STAR);
670 debugl1(cs, "ISAC STAR %x", val);
671 val = cs->readisac(cs, ISAC_MODE);
672 debugl1(cs, "ISAC MODE %x", val);
673 val = cs->readisac(cs, ISAC_ADF2);
674 debugl1(cs, "ISAC ADF2 %x", val);
675 val = cs->readisac(cs, ISAC_ISTA);
676 debugl1(cs, "ISAC ISTA %x", val);
677 if (val & 0x01) {
678 eval = cs->readisac(cs, ISAC_EXIR);
679 debugl1(cs, "ISAC EXIR %x", eval);
680 }
681 val = cs->readisac(cs, ISAC_CIR0);
682 debugl1(cs, "ISAC CIR0 %x", val);
683 cs->dc.isac.ph_state = (val >> 2) & 0xf;
684 isac_sched_event(cs, D_L1STATECHANGE);
685 /* Disable all IRQ */
686 cs->writeisac(cs, ISAC_MASK, 0xFF);
687 }
688