1 /*
2 * CHRP pci routines.
3 */
4
5 #include <linux/config.h>
6 #include <linux/kernel.h>
7 #include <linux/pci.h>
8 #include <linux/delay.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/ide.h>
12 #include <linux/bootmem.h>
13
14 #include <asm/io.h>
15 #include <asm/pgtable.h>
16 #include <asm/irq.h>
17 #include <asm/hydra.h>
18 #include <asm/prom.h>
19 #include <asm/gg2.h>
20 #include <asm/machdep.h>
21 #include <asm/sections.h>
22 #include <asm/pci-bridge.h>
23 #include <asm/open_pic.h>
24
25 /* LongTrail */
26 unsigned long gg2_pci_config_base __chrpdata;
27
28 #define pci_config_addr(dev, offset) \
29 (gg2_pci_config_base + ((dev->bus->number<<16) | (dev->devfn<<8) | offset))
30
31 volatile struct Hydra *Hydra __chrpdata = NULL;
32
33 /* BriQ */
34 extern int chrp_is_briq;
35
36 /*
37 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
38 * limit the bus number to 3 bits
39 */
40
41 #define cfg_read(val, addr, type, op) *val = op((type)(addr))
42 #define cfg_write(val, addr, type, op) op((type *)(addr), (val))
43
44 #define cfg_read_bad(val, size) *val = bad_##size;
45 #define cfg_write_bad(val, size)
46
47 #define bad_byte 0xff
48 #define bad_word 0xffff
49 #define bad_dword 0xffffffffU
50
51 #define GG2_PCI_OP(rw, size, type, op) \
52 int __chrp gg2_##rw##_config_##size(struct pci_dev *dev, int off, type val) \
53 { \
54 if (dev->bus->number > 7) { \
55 cfg_##rw##_bad(val, size) \
56 return PCIBIOS_DEVICE_NOT_FOUND; \
57 } \
58 cfg_##rw(val, pci_config_addr(dev, off), type, op); \
59 return PCIBIOS_SUCCESSFUL; \
60 }
61
62 GG2_PCI_OP(read, byte, u8 *, in_8)
63 GG2_PCI_OP(read, word, u16 *, in_le16)
64 GG2_PCI_OP(read, dword, u32 *, in_le32)
65 GG2_PCI_OP(write, byte, u8, out_8)
66 GG2_PCI_OP(write, word, u16, out_le16)
67 GG2_PCI_OP(write, dword, u32, out_le32)
68
69 static struct pci_ops gg2_pci_ops __chrpdata =
70 {
71 gg2_read_config_byte,
72 gg2_read_config_word,
73 gg2_read_config_dword,
74 gg2_write_config_byte,
75 gg2_write_config_word,
76 gg2_write_config_dword
77 };
78
79 /*
80 * Access functions for PCI config space on IBM "python" host bridges.
81 */
82 #define PYTHON_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
83 | (((o) & ~3) << 24))
84
85 #define PYTHON_PCI_OP(rw, size, type, op, mask) \
86 int __chrp \
87 python_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
88 { \
89 struct pci_controller *hose = dev->sysdata; \
90 \
91 out_be32(hose->cfg_addr, \
92 PYTHON_CFA(dev->bus->number, dev->devfn, offset)); \
93 cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
94 return PCIBIOS_SUCCESSFUL; \
95 }
96
97 PYTHON_PCI_OP(read, byte, u8 *, in_8, 3)
98 PYTHON_PCI_OP(read, word, u16 *, in_le16, 2)
99 PYTHON_PCI_OP(read, dword, u32 *, in_le32, 0)
100 PYTHON_PCI_OP(write, byte, u8, out_8, 3)
101 PYTHON_PCI_OP(write, word, u16, out_le16, 2)
102 PYTHON_PCI_OP(write, dword, u32, out_le32, 0)
103
104 static struct pci_ops python_pci_ops __chrpdata =
105 {
106 python_read_config_byte,
107 python_read_config_word,
108 python_read_config_dword,
109 python_write_config_byte,
110 python_write_config_word,
111 python_write_config_dword
112 };
113
114 /*
115 * Access functions for PCI config space using RTAS calls.
116 */
117 #define RTAS_PCI_READ_OP(size, type, nbytes) \
118 int __chrp \
119 rtas_read_config_##size(struct pci_dev *dev, int offset, type val) \
120 { \
121 unsigned long addr = (offset & 0xff) | ((dev->devfn & 0xff) << 8) \
122 | ((dev->bus->number & 0xff) << 16); \
123 unsigned long ret = ~0UL; \
124 int rval; \
125 \
126 rval = call_rtas("read-pci-config", 2, 2, &ret, addr, nbytes); \
127 *val = ret; \
128 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; \
129 }
130
131 #define RTAS_PCI_WRITE_OP(size, type, nbytes) \
132 int __chrp \
133 rtas_write_config_##size(struct pci_dev *dev, int offset, type val) \
134 { \
135 unsigned long addr = (offset & 0xff) | ((dev->devfn & 0xff) << 8) \
136 | ((dev->bus->number & 0xff) << 16); \
137 int rval; \
138 \
139 rval = call_rtas("write-pci-config", 3, 1, NULL, \
140 addr, nbytes, (ulong)val); \
141 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; \
142 }
143
144 RTAS_PCI_READ_OP(byte, u8 *, 1)
145 RTAS_PCI_READ_OP(word, u16 *, 2)
146 RTAS_PCI_READ_OP(dword, u32 *, 4)
147 RTAS_PCI_WRITE_OP(byte, u8, 1)
148 RTAS_PCI_WRITE_OP(word, u16, 2)
149 RTAS_PCI_WRITE_OP(dword, u32, 4)
150
151 static struct pci_ops rtas_pci_ops __chrpdata =
152 {
153 rtas_read_config_byte,
154 rtas_read_config_word,
155 rtas_read_config_dword,
156 rtas_write_config_byte,
157 rtas_write_config_word,
158 rtas_write_config_dword
159 };
160
161 int __init
hydra_init(void)162 hydra_init(void)
163 {
164 struct device_node *np;
165
166 np = find_devices("mac-io");
167 if (np == NULL || np->n_addrs == 0)
168 return 0;
169 Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
170 printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
171 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
172 HYDRA_FC_SCSI_CELL_EN |
173 HYDRA_FC_SCCA_ENABLE |
174 HYDRA_FC_SCCB_ENABLE |
175 HYDRA_FC_ARB_BYPASS |
176 HYDRA_FC_MPIC_ENABLE |
177 HYDRA_FC_SLOW_SCC_PCLK |
178 HYDRA_FC_MPIC_IS_MASTER));
179 return 1;
180 }
181
182 void __init
chrp_pcibios_fixup(void)183 chrp_pcibios_fixup(void)
184 {
185 struct pci_dev *dev;
186 struct device_node *np;
187
188 /* PCI interrupts are controlled by the OpenPIC */
189 pci_for_each_dev(dev) {
190 np = pci_device_to_OF_node(dev);
191 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
192 dev->irq = np->intrs[0].line;
193 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
194 }
195 }
196
197 /* W83C553 IDE Interrupt Routing Control Register */
198 #define W83C553_IDEIRCR 0x43
199
200 /* SL82C105 IDE Control/Status Register */
201 #define SL82C105_IDECSR 0x40
202
203 static void __init
longtrail_pcibios_fixup(void)204 longtrail_pcibios_fixup(void)
205 {
206 struct pci_dev *w83c553, *sl82c105;
207 u8 progif;
208
209 chrp_pcibios_fixup();
210
211 /*
212 * Open Firmware may have left the SL82C105 IDE interface in the
213 * W83C553 PCI/ISA bridge in legacy mode
214 */
215 if ((w83c553 = pci_find_device(PCI_VENDOR_ID_WINBOND,
216 PCI_DEVICE_ID_WINBOND_83C553, 0)) &&
217 (sl82c105 = pci_find_device(PCI_VENDOR_ID_WINBOND,
218 PCI_DEVICE_ID_WINBOND_82C105,
219 w83c553)) &&
220 (sl82c105->class & 5) != 5) {
221 printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
222 /* Enable W83C553 legacy interrupt internal routing to INTC#, */
223 /* which is connected to HYDRA_INT_EXT5 */
224 pci_write_config_byte(w83c553, W83C553_IDEIRCR, 0x00);
225 /* Enable SL82C105 PCI native IDE mode */
226 pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
227 pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
228 sl82c105->class |= 0x05;
229 /* Enable SL82C105 legacy interrupts & both channels */
230 pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0833);
231 }
232 }
233
234 static void __init
briq_pcibios_fixup(void)235 briq_pcibios_fixup(void)
236 {
237 struct pci_dev *w83c553, *sl82c105;
238 u8 progif;
239
240 chrp_pcibios_fixup();
241
242 /*
243 * Open Firmware may have left the SL82C105 IDE interface in the
244 * W83C553 PCI/ISA bridge in legacy mode
245 */
246 if ((w83c553 = pci_find_device(PCI_VENDOR_ID_WINBOND,
247 PCI_DEVICE_ID_WINBOND_83C553, 0)) &&
248 (sl82c105 = pci_find_device(PCI_VENDOR_ID_WINBOND,
249 PCI_DEVICE_ID_WINBOND_82C105,
250 w83c553)) &&
251 (sl82c105->class & 5) != 5) {
252 printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
253 /* Enable SL82C105 PCI native IDE mode */
254 pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
255 pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
256 sl82c105->class |= 0x05;
257 /* Disable SL82C105 second port */
258 pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
259 }
260 }
261
262 #define PRG_CL_RESET_VALID 0x00010000
263
264 static void __init
setup_python(struct pci_controller * hose,struct device_node * dev)265 setup_python(struct pci_controller *hose, struct device_node *dev)
266 {
267 u32 *reg, val;
268 volatile unsigned char *cfg;
269
270 hose->ops = &python_pci_ops;
271 cfg = ioremap(dev->addrs[0].address + 0xf8000, 0x20);
272 hose->cfg_addr = (volatile unsigned int *) cfg;
273 hose->cfg_data = cfg + 0x10;
274
275 /* Clear the magic go-slow bit */
276 reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40);
277 val = in_be32(®[12]);
278 if (val & PRG_CL_RESET_VALID) {
279 out_be32(®[12], val & ~PRG_CL_RESET_VALID);
280 in_be32(®[12]);
281 }
282 iounmap(reg);
283 }
284
285 void __init
chrp_find_bridges(void)286 chrp_find_bridges(void)
287 {
288 struct device_node *dev;
289 int *bus_range;
290 int len, index = -1;
291 struct pci_controller *hose;
292 unsigned int *dma;
293 char *model, *machine;
294 int is_longtrail = 0, is_mot = 0;
295 struct device_node *root = find_path_device("/");
296
297 /*
298 * The PCI host bridge nodes on some machines don't have
299 * properties to adequately identify them, so we have to
300 * look at what sort of machine this is as well.
301 */
302 machine = get_property(root, "model", NULL);
303 if (machine != NULL) {
304 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
305 is_mot = strncmp(machine, "MOT", 3) == 0;
306 }
307 for (dev = root->child; dev != NULL; dev = dev->sibling) {
308 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
309 continue;
310 ++index;
311 /* The GG2 bridge on the LongTrail doesn't have an address */
312 if (dev->n_addrs < 1 && !is_longtrail) {
313 printk(KERN_WARNING "Can't use %s: no address\n",
314 dev->full_name);
315 continue;
316 }
317 bus_range = (int *) get_property(dev, "bus-range", &len);
318 if (bus_range == NULL || len < 2 * sizeof(int)) {
319 printk(KERN_WARNING "Can't get bus-range for %s\n",
320 dev->full_name);
321 continue;
322 }
323 if (bus_range[1] == bus_range[0])
324 printk(KERN_INFO "PCI bus %d", bus_range[0]);
325 else
326 printk(KERN_INFO "PCI buses %d..%d",
327 bus_range[0], bus_range[1]);
328 printk(" controlled by %s", dev->type);
329 if (dev->n_addrs > 0)
330 printk(" at %x", dev->addrs[0].address);
331 printk("\n");
332
333 hose = pcibios_alloc_controller();
334 if (!hose) {
335 printk("Can't allocate PCI controller structure for %s\n",
336 dev->full_name);
337 continue;
338 }
339 hose->arch_data = dev;
340 hose->first_busno = bus_range[0];
341 hose->last_busno = bus_range[1];
342
343 model = get_property(dev, "model", NULL);
344 if (model == NULL)
345 model = "<none>";
346 if (device_is_compatible(dev, "IBM,python")) {
347 setup_python(hose, dev);
348 } else if (is_mot
349 || strncmp(model, "Motorola, Grackle", 17) == 0) {
350 setup_grackle(hose);
351 } else if (is_longtrail) {
352 hose->ops = &gg2_pci_ops;
353 gg2_pci_config_base = (unsigned long)
354 ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
355 } else if (!strncmp(model, "IBM,CPC710", 10)) {
356 setup_indirect_pci(hose,
357 dev->addrs[0].address + 0x000f8000,
358 dev->addrs[0].address + 0x000f8010);
359 if (index == 0) {
360 dma = (unsigned int *)
361 get_property(dev, "system-dma-base", &len);
362 if (dma && len >= sizeof(*dma)) {
363 dma = (unsigned int *)(((unsigned long)dma) +
364 len - sizeof(*dma));
365 pci_dram_offset = *dma;
366 }
367 }
368 } else {
369 printk("No methods for %s (model %s), using RTAS\n",
370 dev->full_name, model);
371 hose->ops = &rtas_pci_ops;
372 }
373
374 pci_process_bridge_OF_ranges(hose, dev, index == 0);
375
376 /* check the first bridge for a property that we can
377 use to set pci_dram_offset */
378 dma = (unsigned int *)
379 get_property(dev, "ibm,dma-ranges", &len);
380 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
381 pci_dram_offset = dma[2] - dma[3];
382 printk("pci_dram_offset = %lx\n", pci_dram_offset);
383 }
384 }
385
386 if (is_longtrail)
387 ppc_md.pcibios_fixup = longtrail_pcibios_fixup;
388 else if (chrp_is_briq)
389 ppc_md.pcibios_fixup = briq_pcibios_fixup;
390 else
391 ppc_md.pcibios_fixup = chrp_pcibios_fixup;
392 }
393