1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #ifndef __MSM_GPU_H__
8 #define __MSM_GPU_H__
9 
10 #include <linux/adreno-smmu-priv.h>
11 #include <linux/clk.h>
12 #include <linux/devfreq.h>
13 #include <linux/interconnect.h>
14 #include <linux/pm_opp.h>
15 #include <linux/regulator/consumer.h>
16 
17 #include "msm_drv.h"
18 #include "msm_fence.h"
19 #include "msm_ringbuffer.h"
20 #include "msm_gem.h"
21 
22 struct msm_gem_submit;
23 struct msm_gpu_perfcntr;
24 struct msm_gpu_state;
25 struct msm_file_private;
26 
27 struct msm_gpu_config {
28 	const char *ioname;
29 	unsigned int nr_rings;
30 };
31 
32 /* So far, with hardware that I've seen to date, we can have:
33  *  + zero, one, or two z180 2d cores
34  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
35  *    for the CP seems to implement some different PM4 packet types
36  *    but the basics of cmdstream submission are the same)
37  *
38  * Which means that the eventual complete "class" hierarchy, once
39  * support for all past and present hw is in place, becomes:
40  *  + msm_gpu
41  *    + adreno_gpu
42  *      + a3xx_gpu
43  *      + a2xx_gpu
44  *    + z180_gpu
45  */
46 struct msm_gpu_funcs {
47 	int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
48 			 uint32_t param, uint64_t *value, uint32_t *len);
49 	int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
50 			 uint32_t param, uint64_t value, uint32_t len);
51 	int (*hw_init)(struct msm_gpu *gpu);
52 	int (*pm_suspend)(struct msm_gpu *gpu);
53 	int (*pm_resume)(struct msm_gpu *gpu);
54 	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
55 	void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
56 	irqreturn_t (*irq)(struct msm_gpu *irq);
57 	struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
58 	void (*recover)(struct msm_gpu *gpu);
59 	void (*destroy)(struct msm_gpu *gpu);
60 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
61 	/* show GPU status in debugfs: */
62 	void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
63 			struct drm_printer *p);
64 	/* for generation specific debugfs: */
65 	void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
66 #endif
67 	/* note: gpu_busy() can assume that we have been pm_resumed */
68 	u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
69 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
70 	int (*gpu_state_put)(struct msm_gpu_state *state);
71 	unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
72 	/* note: gpu_set_freq() can assume that we have been pm_resumed */
73 	void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
74 			     bool suspended);
75 	struct msm_gem_address_space *(*create_address_space)
76 		(struct msm_gpu *gpu, struct platform_device *pdev);
77 	struct msm_gem_address_space *(*create_private_address_space)
78 		(struct msm_gpu *gpu);
79 	uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
80 };
81 
82 /* Additional state for iommu faults: */
83 struct msm_gpu_fault_info {
84 	u64 ttbr0;
85 	unsigned long iova;
86 	int flags;
87 	const char *type;
88 	const char *block;
89 };
90 
91 /**
92  * struct msm_gpu_devfreq - devfreq related state
93  */
94 struct msm_gpu_devfreq {
95 	/** devfreq: devfreq instance */
96 	struct devfreq *devfreq;
97 
98 	/** lock: lock for "suspended", "busy_cycles", and "time" */
99 	struct mutex lock;
100 
101 	/**
102 	 * idle_constraint:
103 	 *
104 	 * A PM QoS constraint to limit max freq while the GPU is idle.
105 	 */
106 	struct dev_pm_qos_request idle_freq;
107 
108 	/**
109 	 * boost_constraint:
110 	 *
111 	 * A PM QoS constraint to boost min freq for a period of time
112 	 * until the boost expires.
113 	 */
114 	struct dev_pm_qos_request boost_freq;
115 
116 	/**
117 	 * busy_cycles: Last busy counter value, for calculating elapsed busy
118 	 * cycles since last sampling period.
119 	 */
120 	u64 busy_cycles;
121 
122 	/** time: Time of last sampling period. */
123 	ktime_t time;
124 
125 	/** idle_time: Time of last transition to idle: */
126 	ktime_t idle_time;
127 
128 	struct devfreq_dev_status average_status;
129 
130 	/**
131 	 * idle_work:
132 	 *
133 	 * Used to delay clamping to idle freq on active->idle transition.
134 	 */
135 	struct msm_hrtimer_work idle_work;
136 
137 	/**
138 	 * boost_work:
139 	 *
140 	 * Used to reset the boost_constraint after the boost period has
141 	 * elapsed
142 	 */
143 	struct msm_hrtimer_work boost_work;
144 
145 	/** suspended: tracks if we're suspended */
146 	bool suspended;
147 };
148 
149 struct msm_gpu {
150 	const char *name;
151 	struct drm_device *dev;
152 	struct platform_device *pdev;
153 	const struct msm_gpu_funcs *funcs;
154 
155 	struct adreno_smmu_priv adreno_smmu;
156 
157 	/* performance counters (hw & sw): */
158 	spinlock_t perf_lock;
159 	bool perfcntr_active;
160 	struct {
161 		bool active;
162 		ktime_t time;
163 	} last_sample;
164 	uint32_t totaltime, activetime;    /* sw counters */
165 	uint32_t last_cntrs[5];            /* hw counters */
166 	const struct msm_gpu_perfcntr *perfcntrs;
167 	uint32_t num_perfcntrs;
168 
169 	struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
170 	int nr_rings;
171 
172 	/**
173 	 * sysprof_active:
174 	 *
175 	 * The count of contexts that have enabled system profiling.
176 	 */
177 	refcount_t sysprof_active;
178 
179 	/**
180 	 * cur_ctx_seqno:
181 	 *
182 	 * The ctx->seqno value of the last context to submit rendering,
183 	 * and the one with current pgtables installed (for generations
184 	 * that support per-context pgtables).  Tracked by seqno rather
185 	 * than pointer value to avoid dangling pointers, and cases where
186 	 * a ctx can be freed and a new one created with the same address.
187 	 */
188 	int cur_ctx_seqno;
189 
190 	/*
191 	 * List of GEM active objects on this gpu.  Protected by
192 	 * msm_drm_private::mm_lock
193 	 */
194 	struct list_head active_list;
195 
196 	/**
197 	 * lock:
198 	 *
199 	 * General lock for serializing all the gpu things.
200 	 *
201 	 * TODO move to per-ring locking where feasible (ie. submit/retire
202 	 * path, etc)
203 	 */
204 	struct mutex lock;
205 
206 	/**
207 	 * active_submits:
208 	 *
209 	 * The number of submitted but not yet retired submits, used to
210 	 * determine transitions between active and idle.
211 	 *
212 	 * Protected by active_lock
213 	 */
214 	int active_submits;
215 
216 	/** lock: protects active_submits and idle/active transitions */
217 	struct mutex active_lock;
218 
219 	/* does gpu need hw_init? */
220 	bool needs_hw_init;
221 
222 	/**
223 	 * global_faults: number of GPU hangs not attributed to a particular
224 	 * address space
225 	 */
226 	int global_faults;
227 
228 	void __iomem *mmio;
229 	int irq;
230 
231 	struct msm_gem_address_space *aspace;
232 
233 	/* Power Control: */
234 	struct regulator *gpu_reg, *gpu_cx;
235 	struct clk_bulk_data *grp_clks;
236 	int nr_clocks;
237 	struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
238 	uint32_t fast_rate;
239 
240 	/* Hang and Inactivity Detection:
241 	 */
242 #define DRM_MSM_INACTIVE_PERIOD   66 /* in ms (roughly four frames) */
243 
244 #define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
245 	struct timer_list hangcheck_timer;
246 
247 	/* Fault info for most recent iova fault: */
248 	struct msm_gpu_fault_info fault_info;
249 
250 	/* work for handling GPU ioval faults: */
251 	struct kthread_work fault_work;
252 
253 	/* work for handling GPU recovery: */
254 	struct kthread_work recover_work;
255 
256 	/** retire_event: notified when submits are retired: */
257 	wait_queue_head_t retire_event;
258 
259 	/* work for handling active-list retiring: */
260 	struct kthread_work retire_work;
261 
262 	/* worker for retire/recover: */
263 	struct kthread_worker *worker;
264 
265 	struct drm_gem_object *memptrs_bo;
266 
267 	struct msm_gpu_devfreq devfreq;
268 
269 	uint32_t suspend_count;
270 
271 	struct msm_gpu_state *crashstate;
272 
273 	/* Enable clamping to idle freq when inactive: */
274 	bool clamp_to_idle;
275 
276 	/* True if the hardware supports expanded apriv (a650 and newer) */
277 	bool hw_apriv;
278 
279 	struct thermal_cooling_device *cooling;
280 };
281 
dev_to_gpu(struct device * dev)282 static inline struct msm_gpu *dev_to_gpu(struct device *dev)
283 {
284 	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
285 	return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
286 }
287 
288 /* It turns out that all targets use the same ringbuffer size */
289 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
290 #define MSM_GPU_RINGBUFFER_BLKSIZE 32
291 
292 #define MSM_GPU_RB_CNTL_DEFAULT \
293 		(AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
294 		AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
295 
msm_gpu_active(struct msm_gpu * gpu)296 static inline bool msm_gpu_active(struct msm_gpu *gpu)
297 {
298 	int i;
299 
300 	for (i = 0; i < gpu->nr_rings; i++) {
301 		struct msm_ringbuffer *ring = gpu->rb[i];
302 
303 		if (fence_after(ring->fctx->last_fence, ring->memptrs->fence))
304 			return true;
305 	}
306 
307 	return false;
308 }
309 
310 /* Perf-Counters:
311  * The select_reg and select_val are just there for the benefit of the child
312  * class that actually enables the perf counter..  but msm_gpu base class
313  * will handle sampling/displaying the counters.
314  */
315 
316 struct msm_gpu_perfcntr {
317 	uint32_t select_reg;
318 	uint32_t sample_reg;
319 	uint32_t select_val;
320 	const char *name;
321 };
322 
323 /*
324  * The number of priority levels provided by drm gpu scheduler.  The
325  * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some
326  * cases, so we don't use it (no need for kernel generated jobs).
327  */
328 #define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_HIGH - DRM_SCHED_PRIORITY_MIN)
329 
330 /**
331  * struct msm_file_private - per-drm_file context
332  *
333  * @queuelock:    synchronizes access to submitqueues list
334  * @submitqueues: list of &msm_gpu_submitqueue created by userspace
335  * @queueid:      counter incremented each time a submitqueue is created,
336  *                used to assign &msm_gpu_submitqueue.id
337  * @aspace:       the per-process GPU address-space
338  * @ref:          reference count
339  * @seqno:        unique per process seqno
340  */
341 struct msm_file_private {
342 	rwlock_t queuelock;
343 	struct list_head submitqueues;
344 	int queueid;
345 	struct msm_gem_address_space *aspace;
346 	struct kref ref;
347 	int seqno;
348 
349 	/**
350 	 * sysprof:
351 	 *
352 	 * The value of MSM_PARAM_SYSPROF set by userspace.  This is
353 	 * intended to be used by system profiling tools like Mesa's
354 	 * pps-producer (perfetto), and restricted to CAP_SYS_ADMIN.
355 	 *
356 	 * Setting a value of 1 will preserve performance counters across
357 	 * context switches.  Setting a value of 2 will in addition
358 	 * suppress suspend.  (Performance counters lose state across
359 	 * power collapse, which is undesirable for profiling in some
360 	 * cases.)
361 	 *
362 	 * The value automatically reverts to zero when the drm device
363 	 * file is closed.
364 	 */
365 	int sysprof;
366 
367 	/** comm: Overridden task comm, see MSM_PARAM_COMM */
368 	char *comm;
369 
370 	/** cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE */
371 	char *cmdline;
372 
373 	/**
374 	 * entities:
375 	 *
376 	 * Table of per-priority-level sched entities used by submitqueues
377 	 * associated with this &drm_file.  Because some userspace apps
378 	 * make assumptions about rendering from multiple gl contexts
379 	 * (of the same priority) within the process happening in FIFO
380 	 * order without requiring any fencing beyond MakeCurrent(), we
381 	 * create at most one &drm_sched_entity per-process per-priority-
382 	 * level.
383 	 */
384 	struct drm_sched_entity *entities[NR_SCHED_PRIORITIES * MSM_GPU_MAX_RINGS];
385 };
386 
387 /**
388  * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority
389  *
390  * @gpu:        the gpu instance
391  * @prio:       the userspace priority level
392  * @ring_nr:    [out] the ringbuffer the userspace priority maps to
393  * @sched_prio: [out] the gpu scheduler priority level which the userspace
394  *              priority maps to
395  *
396  * With drm/scheduler providing it's own level of prioritization, our total
397  * number of available priority levels is (nr_rings * NR_SCHED_PRIORITIES).
398  * Each ring is associated with it's own scheduler instance.  However, our
399  * UABI is that lower numerical values are higher priority.  So mapping the
400  * single userspace priority level into ring_nr and sched_prio takes some
401  * care.  The userspace provided priority (when a submitqueue is created)
402  * is mapped to ring nr and scheduler priority as such:
403  *
404  *   ring_nr    = userspace_prio / NR_SCHED_PRIORITIES
405  *   sched_prio = NR_SCHED_PRIORITIES -
406  *                (userspace_prio % NR_SCHED_PRIORITIES) - 1
407  *
408  * This allows generations without preemption (nr_rings==1) to have some
409  * amount of prioritization, and provides more priority levels for gens
410  * that do have preemption.
411  */
msm_gpu_convert_priority(struct msm_gpu * gpu,int prio,unsigned * ring_nr,enum drm_sched_priority * sched_prio)412 static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,
413 		unsigned *ring_nr, enum drm_sched_priority *sched_prio)
414 {
415 	unsigned rn, sp;
416 
417 	rn = div_u64_rem(prio, NR_SCHED_PRIORITIES, &sp);
418 
419 	/* invert sched priority to map to higher-numeric-is-higher-
420 	 * priority convention
421 	 */
422 	sp = NR_SCHED_PRIORITIES - sp - 1;
423 
424 	if (rn >= gpu->nr_rings)
425 		return -EINVAL;
426 
427 	*ring_nr = rn;
428 	*sched_prio = sp;
429 
430 	return 0;
431 }
432 
433 /**
434  * struct msm_gpu_submitqueues - Userspace created context.
435  *
436  * A submitqueue is associated with a gl context or vk queue (or equiv)
437  * in userspace.
438  *
439  * @id:        userspace id for the submitqueue, unique within the drm_file
440  * @flags:     userspace flags for the submitqueue, specified at creation
441  *             (currently unusued)
442  * @ring_nr:   the ringbuffer used by this submitqueue, which is determined
443  *             by the submitqueue's priority
444  * @faults:    the number of GPU hangs associated with this submitqueue
445  * @last_fence: the sequence number of the last allocated fence (for error
446  *             checking)
447  * @ctx:       the per-drm_file context associated with the submitqueue (ie.
448  *             which set of pgtables do submits jobs associated with the
449  *             submitqueue use)
450  * @node:      node in the context's list of submitqueues
451  * @fence_idr: maps fence-id to dma_fence for userspace visible fence
452  *             seqno, protected by submitqueue lock
453  * @lock:      submitqueue lock
454  * @ref:       reference count
455  * @entity:    the submit job-queue
456  */
457 struct msm_gpu_submitqueue {
458 	int id;
459 	u32 flags;
460 	u32 ring_nr;
461 	int faults;
462 	uint32_t last_fence;
463 	struct msm_file_private *ctx;
464 	struct list_head node;
465 	struct idr fence_idr;
466 	struct mutex lock;
467 	struct kref ref;
468 	struct drm_sched_entity *entity;
469 };
470 
471 struct msm_gpu_state_bo {
472 	u64 iova;
473 	size_t size;
474 	void *data;
475 	bool encoded;
476 };
477 
478 struct msm_gpu_state {
479 	struct kref ref;
480 	struct timespec64 time;
481 
482 	struct {
483 		u64 iova;
484 		u32 fence;
485 		u32 seqno;
486 		u32 rptr;
487 		u32 wptr;
488 		void *data;
489 		int data_size;
490 		bool encoded;
491 	} ring[MSM_GPU_MAX_RINGS];
492 
493 	int nr_registers;
494 	u32 *registers;
495 
496 	u32 rbbm_status;
497 
498 	char *comm;
499 	char *cmd;
500 
501 	struct msm_gpu_fault_info fault_info;
502 
503 	int nr_bos;
504 	struct msm_gpu_state_bo *bos;
505 };
506 
gpu_write(struct msm_gpu * gpu,u32 reg,u32 data)507 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
508 {
509 	msm_writel(data, gpu->mmio + (reg << 2));
510 }
511 
gpu_read(struct msm_gpu * gpu,u32 reg)512 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
513 {
514 	return msm_readl(gpu->mmio + (reg << 2));
515 }
516 
gpu_rmw(struct msm_gpu * gpu,u32 reg,u32 mask,u32 or)517 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
518 {
519 	msm_rmw(gpu->mmio + (reg << 2), mask, or);
520 }
521 
gpu_read64(struct msm_gpu * gpu,u32 lo,u32 hi)522 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
523 {
524 	u64 val;
525 
526 	/*
527 	 * Why not a readq here? Two reasons: 1) many of the LO registers are
528 	 * not quad word aligned and 2) the GPU hardware designers have a bit
529 	 * of a history of putting registers where they fit, especially in
530 	 * spins. The longer a GPU family goes the higher the chance that
531 	 * we'll get burned.  We could do a series of validity checks if we
532 	 * wanted to, but really is a readq() that much better? Nah.
533 	 */
534 
535 	/*
536 	 * For some lo/hi registers (like perfcounters), the hi value is latched
537 	 * when the lo is read, so make sure to read the lo first to trigger
538 	 * that
539 	 */
540 	val = (u64) msm_readl(gpu->mmio + (lo << 2));
541 	val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
542 
543 	return val;
544 }
545 
gpu_write64(struct msm_gpu * gpu,u32 lo,u32 hi,u64 val)546 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
547 {
548 	/* Why not a writeq here? Read the screed above */
549 	msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
550 	msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
551 }
552 
553 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
554 int msm_gpu_pm_resume(struct msm_gpu *gpu);
555 
556 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
557 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
558 		u32 id);
559 int msm_submitqueue_create(struct drm_device *drm,
560 		struct msm_file_private *ctx,
561 		u32 prio, u32 flags, u32 *id);
562 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
563 		struct drm_msm_submitqueue_query *args);
564 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
565 void msm_submitqueue_close(struct msm_file_private *ctx);
566 
567 void msm_submitqueue_destroy(struct kref *kref);
568 
569 int msm_file_private_set_sysprof(struct msm_file_private *ctx,
570 				 struct msm_gpu *gpu, int sysprof);
571 void __msm_file_private_destroy(struct kref *kref);
572 
msm_file_private_put(struct msm_file_private * ctx)573 static inline void msm_file_private_put(struct msm_file_private *ctx)
574 {
575 	kref_put(&ctx->ref, __msm_file_private_destroy);
576 }
577 
msm_file_private_get(struct msm_file_private * ctx)578 static inline struct msm_file_private *msm_file_private_get(
579 	struct msm_file_private *ctx)
580 {
581 	kref_get(&ctx->ref);
582 	return ctx;
583 }
584 
585 void msm_devfreq_init(struct msm_gpu *gpu);
586 void msm_devfreq_cleanup(struct msm_gpu *gpu);
587 void msm_devfreq_resume(struct msm_gpu *gpu);
588 void msm_devfreq_suspend(struct msm_gpu *gpu);
589 void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
590 void msm_devfreq_active(struct msm_gpu *gpu);
591 void msm_devfreq_idle(struct msm_gpu *gpu);
592 
593 int msm_gpu_hw_init(struct msm_gpu *gpu);
594 
595 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
596 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
597 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
598 		uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
599 
600 void msm_gpu_retire(struct msm_gpu *gpu);
601 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
602 
603 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
604 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
605 		const char *name, struct msm_gpu_config *config);
606 
607 struct msm_gem_address_space *
608 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
609 
610 void msm_gpu_cleanup(struct msm_gpu *gpu);
611 
612 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
613 void __init adreno_register(void);
614 void __exit adreno_unregister(void);
615 
msm_submitqueue_put(struct msm_gpu_submitqueue * queue)616 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
617 {
618 	if (queue)
619 		kref_put(&queue->ref, msm_submitqueue_destroy);
620 }
621 
msm_gpu_crashstate_get(struct msm_gpu * gpu)622 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
623 {
624 	struct msm_gpu_state *state = NULL;
625 
626 	mutex_lock(&gpu->lock);
627 
628 	if (gpu->crashstate) {
629 		kref_get(&gpu->crashstate->ref);
630 		state = gpu->crashstate;
631 	}
632 
633 	mutex_unlock(&gpu->lock);
634 
635 	return state;
636 }
637 
msm_gpu_crashstate_put(struct msm_gpu * gpu)638 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
639 {
640 	mutex_lock(&gpu->lock);
641 
642 	if (gpu->crashstate) {
643 		if (gpu->funcs->gpu_state_put(gpu->crashstate))
644 			gpu->crashstate = NULL;
645 	}
646 
647 	mutex_unlock(&gpu->lock);
648 }
649 
650 /*
651  * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
652  * support expanded privileges
653  */
654 #define check_apriv(gpu, flags) \
655 	(((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
656 
657 
658 #endif /* __MSM_GPU_H__ */
659