1 /*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 *
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/i2c.h>
27 #include <linux/slab.h>
28 #include "cx25821.h"
29 #include "cx25821-sram.h"
30 #include "cx25821-video.h"
31
32 MODULE_DESCRIPTION("Driver for Athena cards");
33 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
34 MODULE_LICENSE("GPL");
35
36 static unsigned int debug;
37 module_param(debug, int, 0644);
38 MODULE_PARM_DESC(debug, "enable debug messages");
39
40 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
41 module_param_array(card, int, NULL, 0444);
42 MODULE_PARM_DESC(card, "card type");
43
44 static unsigned int cx25821_devcount;
45
46 DEFINE_MUTEX(cx25821_devlist_mutex);
47 EXPORT_SYMBOL(cx25821_devlist_mutex);
48 LIST_HEAD(cx25821_devlist);
49 EXPORT_SYMBOL(cx25821_devlist);
50
51 struct sram_channel cx25821_sram_channels[] = {
52 [SRAM_CH00] = {
53 .i = SRAM_CH00,
54 .name = "VID A",
55 .cmds_start = VID_A_DOWN_CMDS,
56 .ctrl_start = VID_A_IQ,
57 .cdt = VID_A_CDT,
58 .fifo_start = VID_A_DOWN_CLUSTER_1,
59 .fifo_size = (VID_CLUSTER_SIZE << 2),
60 .ptr1_reg = DMA1_PTR1,
61 .ptr2_reg = DMA1_PTR2,
62 .cnt1_reg = DMA1_CNT1,
63 .cnt2_reg = DMA1_CNT2,
64 .int_msk = VID_A_INT_MSK,
65 .int_stat = VID_A_INT_STAT,
66 .int_mstat = VID_A_INT_MSTAT,
67 .dma_ctl = VID_DST_A_DMA_CTL,
68 .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
69 .gpcnt = VID_DST_A_GPCNT,
70 .vip_ctl = VID_DST_A_VIP_CTL,
71 .pix_frmt = VID_DST_A_PIX_FRMT,
72 },
73
74 [SRAM_CH01] = {
75 .i = SRAM_CH01,
76 .name = "VID B",
77 .cmds_start = VID_B_DOWN_CMDS,
78 .ctrl_start = VID_B_IQ,
79 .cdt = VID_B_CDT,
80 .fifo_start = VID_B_DOWN_CLUSTER_1,
81 .fifo_size = (VID_CLUSTER_SIZE << 2),
82 .ptr1_reg = DMA2_PTR1,
83 .ptr2_reg = DMA2_PTR2,
84 .cnt1_reg = DMA2_CNT1,
85 .cnt2_reg = DMA2_CNT2,
86 .int_msk = VID_B_INT_MSK,
87 .int_stat = VID_B_INT_STAT,
88 .int_mstat = VID_B_INT_MSTAT,
89 .dma_ctl = VID_DST_B_DMA_CTL,
90 .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
91 .gpcnt = VID_DST_B_GPCNT,
92 .vip_ctl = VID_DST_B_VIP_CTL,
93 .pix_frmt = VID_DST_B_PIX_FRMT,
94 },
95
96 [SRAM_CH02] = {
97 .i = SRAM_CH02,
98 .name = "VID C",
99 .cmds_start = VID_C_DOWN_CMDS,
100 .ctrl_start = VID_C_IQ,
101 .cdt = VID_C_CDT,
102 .fifo_start = VID_C_DOWN_CLUSTER_1,
103 .fifo_size = (VID_CLUSTER_SIZE << 2),
104 .ptr1_reg = DMA3_PTR1,
105 .ptr2_reg = DMA3_PTR2,
106 .cnt1_reg = DMA3_CNT1,
107 .cnt2_reg = DMA3_CNT2,
108 .int_msk = VID_C_INT_MSK,
109 .int_stat = VID_C_INT_STAT,
110 .int_mstat = VID_C_INT_MSTAT,
111 .dma_ctl = VID_DST_C_DMA_CTL,
112 .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
113 .gpcnt = VID_DST_C_GPCNT,
114 .vip_ctl = VID_DST_C_VIP_CTL,
115 .pix_frmt = VID_DST_C_PIX_FRMT,
116 },
117
118 [SRAM_CH03] = {
119 .i = SRAM_CH03,
120 .name = "VID D",
121 .cmds_start = VID_D_DOWN_CMDS,
122 .ctrl_start = VID_D_IQ,
123 .cdt = VID_D_CDT,
124 .fifo_start = VID_D_DOWN_CLUSTER_1,
125 .fifo_size = (VID_CLUSTER_SIZE << 2),
126 .ptr1_reg = DMA4_PTR1,
127 .ptr2_reg = DMA4_PTR2,
128 .cnt1_reg = DMA4_CNT1,
129 .cnt2_reg = DMA4_CNT2,
130 .int_msk = VID_D_INT_MSK,
131 .int_stat = VID_D_INT_STAT,
132 .int_mstat = VID_D_INT_MSTAT,
133 .dma_ctl = VID_DST_D_DMA_CTL,
134 .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
135 .gpcnt = VID_DST_D_GPCNT,
136 .vip_ctl = VID_DST_D_VIP_CTL,
137 .pix_frmt = VID_DST_D_PIX_FRMT,
138 },
139
140 [SRAM_CH04] = {
141 .i = SRAM_CH04,
142 .name = "VID E",
143 .cmds_start = VID_E_DOWN_CMDS,
144 .ctrl_start = VID_E_IQ,
145 .cdt = VID_E_CDT,
146 .fifo_start = VID_E_DOWN_CLUSTER_1,
147 .fifo_size = (VID_CLUSTER_SIZE << 2),
148 .ptr1_reg = DMA5_PTR1,
149 .ptr2_reg = DMA5_PTR2,
150 .cnt1_reg = DMA5_CNT1,
151 .cnt2_reg = DMA5_CNT2,
152 .int_msk = VID_E_INT_MSK,
153 .int_stat = VID_E_INT_STAT,
154 .int_mstat = VID_E_INT_MSTAT,
155 .dma_ctl = VID_DST_E_DMA_CTL,
156 .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
157 .gpcnt = VID_DST_E_GPCNT,
158 .vip_ctl = VID_DST_E_VIP_CTL,
159 .pix_frmt = VID_DST_E_PIX_FRMT,
160 },
161
162 [SRAM_CH05] = {
163 .i = SRAM_CH05,
164 .name = "VID F",
165 .cmds_start = VID_F_DOWN_CMDS,
166 .ctrl_start = VID_F_IQ,
167 .cdt = VID_F_CDT,
168 .fifo_start = VID_F_DOWN_CLUSTER_1,
169 .fifo_size = (VID_CLUSTER_SIZE << 2),
170 .ptr1_reg = DMA6_PTR1,
171 .ptr2_reg = DMA6_PTR2,
172 .cnt1_reg = DMA6_CNT1,
173 .cnt2_reg = DMA6_CNT2,
174 .int_msk = VID_F_INT_MSK,
175 .int_stat = VID_F_INT_STAT,
176 .int_mstat = VID_F_INT_MSTAT,
177 .dma_ctl = VID_DST_F_DMA_CTL,
178 .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
179 .gpcnt = VID_DST_F_GPCNT,
180 .vip_ctl = VID_DST_F_VIP_CTL,
181 .pix_frmt = VID_DST_F_PIX_FRMT,
182 },
183
184 [SRAM_CH06] = {
185 .i = SRAM_CH06,
186 .name = "VID G",
187 .cmds_start = VID_G_DOWN_CMDS,
188 .ctrl_start = VID_G_IQ,
189 .cdt = VID_G_CDT,
190 .fifo_start = VID_G_DOWN_CLUSTER_1,
191 .fifo_size = (VID_CLUSTER_SIZE << 2),
192 .ptr1_reg = DMA7_PTR1,
193 .ptr2_reg = DMA7_PTR2,
194 .cnt1_reg = DMA7_CNT1,
195 .cnt2_reg = DMA7_CNT2,
196 .int_msk = VID_G_INT_MSK,
197 .int_stat = VID_G_INT_STAT,
198 .int_mstat = VID_G_INT_MSTAT,
199 .dma_ctl = VID_DST_G_DMA_CTL,
200 .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
201 .gpcnt = VID_DST_G_GPCNT,
202 .vip_ctl = VID_DST_G_VIP_CTL,
203 .pix_frmt = VID_DST_G_PIX_FRMT,
204 },
205
206 [SRAM_CH07] = {
207 .i = SRAM_CH07,
208 .name = "VID H",
209 .cmds_start = VID_H_DOWN_CMDS,
210 .ctrl_start = VID_H_IQ,
211 .cdt = VID_H_CDT,
212 .fifo_start = VID_H_DOWN_CLUSTER_1,
213 .fifo_size = (VID_CLUSTER_SIZE << 2),
214 .ptr1_reg = DMA8_PTR1,
215 .ptr2_reg = DMA8_PTR2,
216 .cnt1_reg = DMA8_CNT1,
217 .cnt2_reg = DMA8_CNT2,
218 .int_msk = VID_H_INT_MSK,
219 .int_stat = VID_H_INT_STAT,
220 .int_mstat = VID_H_INT_MSTAT,
221 .dma_ctl = VID_DST_H_DMA_CTL,
222 .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
223 .gpcnt = VID_DST_H_GPCNT,
224 .vip_ctl = VID_DST_H_VIP_CTL,
225 .pix_frmt = VID_DST_H_PIX_FRMT,
226 },
227
228 [SRAM_CH08] = {
229 .name = "audio from",
230 .cmds_start = AUD_A_DOWN_CMDS,
231 .ctrl_start = AUD_A_IQ,
232 .cdt = AUD_A_CDT,
233 .fifo_start = AUD_A_DOWN_CLUSTER_1,
234 .fifo_size = AUDIO_CLUSTER_SIZE * 3,
235 .ptr1_reg = DMA17_PTR1,
236 .ptr2_reg = DMA17_PTR2,
237 .cnt1_reg = DMA17_CNT1,
238 .cnt2_reg = DMA17_CNT2,
239 },
240
241 [SRAM_CH09] = {
242 .i = SRAM_CH09,
243 .name = "VID Upstream I",
244 .cmds_start = VID_I_UP_CMDS,
245 .ctrl_start = VID_I_IQ,
246 .cdt = VID_I_CDT,
247 .fifo_start = VID_I_UP_CLUSTER_1,
248 .fifo_size = (VID_CLUSTER_SIZE << 2),
249 .ptr1_reg = DMA15_PTR1,
250 .ptr2_reg = DMA15_PTR2,
251 .cnt1_reg = DMA15_CNT1,
252 .cnt2_reg = DMA15_CNT2,
253 .int_msk = VID_I_INT_MSK,
254 .int_stat = VID_I_INT_STAT,
255 .int_mstat = VID_I_INT_MSTAT,
256 .dma_ctl = VID_SRC_I_DMA_CTL,
257 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
258 .gpcnt = VID_SRC_I_GPCNT,
259
260 .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
261 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
262 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
263 .vid_cdt_size = VID_SRC_I_CDT_SZ,
264 .irq_bit = 8,
265 },
266
267 [SRAM_CH10] = {
268 .i = SRAM_CH10,
269 .name = "VID Upstream J",
270 .cmds_start = VID_J_UP_CMDS,
271 .ctrl_start = VID_J_IQ,
272 .cdt = VID_J_CDT,
273 .fifo_start = VID_J_UP_CLUSTER_1,
274 .fifo_size = (VID_CLUSTER_SIZE << 2),
275 .ptr1_reg = DMA16_PTR1,
276 .ptr2_reg = DMA16_PTR2,
277 .cnt1_reg = DMA16_CNT1,
278 .cnt2_reg = DMA16_CNT2,
279 .int_msk = VID_J_INT_MSK,
280 .int_stat = VID_J_INT_STAT,
281 .int_mstat = VID_J_INT_MSTAT,
282 .dma_ctl = VID_SRC_J_DMA_CTL,
283 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
284 .gpcnt = VID_SRC_J_GPCNT,
285
286 .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
287 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
288 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
289 .vid_cdt_size = VID_SRC_J_CDT_SZ,
290 .irq_bit = 9,
291 },
292
293 [SRAM_CH11] = {
294 .i = SRAM_CH11,
295 .name = "Audio Upstream Channel B",
296 .cmds_start = AUD_B_UP_CMDS,
297 .ctrl_start = AUD_B_IQ,
298 .cdt = AUD_B_CDT,
299 .fifo_start = AUD_B_UP_CLUSTER_1,
300 .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
301 .ptr1_reg = DMA22_PTR1,
302 .ptr2_reg = DMA22_PTR2,
303 .cnt1_reg = DMA22_CNT1,
304 .cnt2_reg = DMA22_CNT2,
305 .int_msk = AUD_B_INT_MSK,
306 .int_stat = AUD_B_INT_STAT,
307 .int_mstat = AUD_B_INT_MSTAT,
308 .dma_ctl = AUD_INT_DMA_CTL,
309 .gpcnt_ctl = AUD_B_GPCNT_CTL,
310 .gpcnt = AUD_B_GPCNT,
311 .aud_length = AUD_B_LNGTH,
312 .aud_cfg = AUD_B_CFG,
313 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
314 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
315 .irq_bit = 11,
316 },
317 };
318 EXPORT_SYMBOL(cx25821_sram_channels);
319
320 struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00];
321 struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01];
322 struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02];
323 struct sram_channel *channel3 = &cx25821_sram_channels[SRAM_CH03];
324 struct sram_channel *channel4 = &cx25821_sram_channels[SRAM_CH04];
325 struct sram_channel *channel5 = &cx25821_sram_channels[SRAM_CH05];
326 struct sram_channel *channel6 = &cx25821_sram_channels[SRAM_CH06];
327 struct sram_channel *channel7 = &cx25821_sram_channels[SRAM_CH07];
328 struct sram_channel *channel9 = &cx25821_sram_channels[SRAM_CH09];
329 struct sram_channel *channel10 = &cx25821_sram_channels[SRAM_CH10];
330 struct sram_channel *channel11 = &cx25821_sram_channels[SRAM_CH11];
331
332 struct cx25821_dmaqueue mpegq;
333
cx25821_risc_decode(u32 risc)334 static int cx25821_risc_decode(u32 risc)
335 {
336 static const char * const instr[16] = {
337 [RISC_SYNC >> 28] = "sync",
338 [RISC_WRITE >> 28] = "write",
339 [RISC_WRITEC >> 28] = "writec",
340 [RISC_READ >> 28] = "read",
341 [RISC_READC >> 28] = "readc",
342 [RISC_JUMP >> 28] = "jump",
343 [RISC_SKIP >> 28] = "skip",
344 [RISC_WRITERM >> 28] = "writerm",
345 [RISC_WRITECM >> 28] = "writecm",
346 [RISC_WRITECR >> 28] = "writecr",
347 };
348 static const int incr[16] = {
349 [RISC_WRITE >> 28] = 3,
350 [RISC_JUMP >> 28] = 3,
351 [RISC_SKIP >> 28] = 1,
352 [RISC_SYNC >> 28] = 1,
353 [RISC_WRITERM >> 28] = 3,
354 [RISC_WRITECM >> 28] = 3,
355 [RISC_WRITECR >> 28] = 4,
356 };
357 static const char * const bits[] = {
358 "12", "13", "14", "resync",
359 "cnt0", "cnt1", "18", "19",
360 "20", "21", "22", "23",
361 "irq1", "irq2", "eol", "sol",
362 };
363 int i;
364
365 pr_cont("0x%08x [ %s",
366 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
367 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
368 if (risc & (1 << (i + 12)))
369 pr_cont(" %s", bits[i]);
370 }
371 pr_cont(" count=%d ]\n", risc & 0xfff);
372 return incr[risc >> 28] ? incr[risc >> 28] : 1;
373 }
374
i2c_slave_did_ack(struct i2c_adapter * i2c_adap)375 static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
376 {
377 struct cx25821_i2c *bus = i2c_adap->algo_data;
378 struct cx25821_dev *dev = bus->dev;
379 return cx_read(bus->reg_stat) & 0x01;
380 }
381
cx_i2c_read_print(struct cx25821_dev * dev,u32 reg,const char * reg_string)382 void cx_i2c_read_print(struct cx25821_dev *dev, u32 reg, const char *reg_string)
383 {
384 int tmp = 0;
385 u32 value = 0;
386
387 value = cx25821_i2c_read(&dev->i2c_bus[0], reg, &tmp);
388 }
389
cx25821_registers_init(struct cx25821_dev * dev)390 static void cx25821_registers_init(struct cx25821_dev *dev)
391 {
392 u32 tmp;
393
394 /* enable RUN_RISC in Pecos */
395 cx_write(DEV_CNTRL2, 0x20);
396
397 /* Set the master PCI interrupt masks to enable video, audio, MBIF,
398 * and GPIO interrupts
399 * I2C interrupt masking is handled by the I2C objects themselves. */
400 cx_write(PCI_INT_MSK, 0x2001FFFF);
401
402 tmp = cx_read(RDR_TLCTL0);
403 tmp &= ~FLD_CFG_RCB_CK_EN; /* Clear the RCB_CK_EN bit */
404 cx_write(RDR_TLCTL0, tmp);
405
406 /* PLL-A setting for the Audio Master Clock */
407 cx_write(PLL_A_INT_FRAC, 0x9807A58B);
408
409 /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
410 cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
411
412 /* clear reset bit [31] */
413 tmp = cx_read(PLL_A_INT_FRAC);
414 cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
415
416 /* PLL-B setting for Mobilygen Host Bus Interface */
417 cx_write(PLL_B_INT_FRAC, 0x9883A86F);
418
419 /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
420 cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
421
422 /* clear reset bit [31] */
423 tmp = cx_read(PLL_B_INT_FRAC);
424 cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
425
426 /* PLL-C setting for video upstream channel */
427 cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
428
429 /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
430 cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
431
432 /* clear reset bit [31] */
433 tmp = cx_read(PLL_C_INT_FRAC);
434 cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
435
436 /* PLL-D setting for audio upstream channel */
437 cx_write(PLL_D_INT_FRAC, 0x98757F5B);
438
439 /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
440 cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
441
442 /* clear reset bit [31] */
443 tmp = cx_read(PLL_D_INT_FRAC);
444 cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
445
446 /* This selects the PLL C clock source for the video upstream channel
447 * I and J */
448 tmp = cx_read(VID_CH_CLK_SEL);
449 cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
450
451 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
452 * channel A-C
453 * select 656/VIP DST for downstream Channel A - C */
454 tmp = cx_read(VID_CH_MODE_SEL);
455 /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
456 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
457
458 /* enables 656 port I and J as output */
459 tmp = cx_read(CLK_RST);
460 /* use external ALT_PLL_REF pin as its reference clock instead */
461 tmp |= FLD_USE_ALT_PLL_REF;
462 cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
463
464 mdelay(100);
465 }
466
cx25821_sram_channel_setup(struct cx25821_dev * dev,struct sram_channel * ch,unsigned int bpl,u32 risc)467 int cx25821_sram_channel_setup(struct cx25821_dev *dev,
468 struct sram_channel *ch,
469 unsigned int bpl, u32 risc)
470 {
471 unsigned int i, lines;
472 u32 cdt;
473
474 if (ch->cmds_start == 0) {
475 cx_write(ch->ptr1_reg, 0);
476 cx_write(ch->ptr2_reg, 0);
477 cx_write(ch->cnt2_reg, 0);
478 cx_write(ch->cnt1_reg, 0);
479 return 0;
480 }
481
482 bpl = (bpl + 7) & ~7; /* alignment */
483 cdt = ch->cdt;
484 lines = ch->fifo_size / bpl;
485
486 if (lines > 4)
487 lines = 4;
488
489 BUG_ON(lines < 2);
490
491 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
492 cx_write(8 + 4, 8);
493 cx_write(8 + 8, 0);
494
495 /* write CDT */
496 for (i = 0; i < lines; i++) {
497 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
498 cx_write(cdt + 16 * i + 4, 0);
499 cx_write(cdt + 16 * i + 8, 0);
500 cx_write(cdt + 16 * i + 12, 0);
501 }
502
503 /* init the first cdt buffer */
504 for (i = 0; i < 128; i++)
505 cx_write(ch->fifo_start + 4 * i, i);
506
507 /* write CMDS */
508 if (ch->jumponly)
509 cx_write(ch->cmds_start + 0, 8);
510 else
511 cx_write(ch->cmds_start + 0, risc);
512
513 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
514 cx_write(ch->cmds_start + 8, cdt);
515 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
516 cx_write(ch->cmds_start + 16, ch->ctrl_start);
517
518 if (ch->jumponly)
519 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
520 else
521 cx_write(ch->cmds_start + 20, 64 >> 2);
522
523 for (i = 24; i < 80; i += 4)
524 cx_write(ch->cmds_start + i, 0);
525
526 /* fill registers */
527 cx_write(ch->ptr1_reg, ch->fifo_start);
528 cx_write(ch->ptr2_reg, cdt);
529 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
530 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
531
532 return 0;
533 }
534 EXPORT_SYMBOL(cx25821_sram_channel_setup);
535
cx25821_sram_channel_setup_audio(struct cx25821_dev * dev,struct sram_channel * ch,unsigned int bpl,u32 risc)536 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
537 struct sram_channel *ch,
538 unsigned int bpl, u32 risc)
539 {
540 unsigned int i, lines;
541 u32 cdt;
542
543 if (ch->cmds_start == 0) {
544 cx_write(ch->ptr1_reg, 0);
545 cx_write(ch->ptr2_reg, 0);
546 cx_write(ch->cnt2_reg, 0);
547 cx_write(ch->cnt1_reg, 0);
548 return 0;
549 }
550
551 bpl = (bpl + 7) & ~7; /* alignment */
552 cdt = ch->cdt;
553 lines = ch->fifo_size / bpl;
554
555 if (lines > 3)
556 lines = 3; /* for AUDIO */
557
558 BUG_ON(lines < 2);
559
560 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
561 cx_write(8 + 4, 8);
562 cx_write(8 + 8, 0);
563
564 /* write CDT */
565 for (i = 0; i < lines; i++) {
566 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
567 cx_write(cdt + 16 * i + 4, 0);
568 cx_write(cdt + 16 * i + 8, 0);
569 cx_write(cdt + 16 * i + 12, 0);
570 }
571
572 /* write CMDS */
573 if (ch->jumponly)
574 cx_write(ch->cmds_start + 0, 8);
575 else
576 cx_write(ch->cmds_start + 0, risc);
577
578 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
579 cx_write(ch->cmds_start + 8, cdt);
580 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
581 cx_write(ch->cmds_start + 16, ch->ctrl_start);
582
583 /* IQ size */
584 if (ch->jumponly)
585 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
586 else
587 cx_write(ch->cmds_start + 20, 64 >> 2);
588
589 /* zero out */
590 for (i = 24; i < 80; i += 4)
591 cx_write(ch->cmds_start + i, 0);
592
593 /* fill registers */
594 cx_write(ch->ptr1_reg, ch->fifo_start);
595 cx_write(ch->ptr2_reg, cdt);
596 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
597 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
598
599 return 0;
600 }
601 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
602
cx25821_sram_channel_dump(struct cx25821_dev * dev,struct sram_channel * ch)603 void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch)
604 {
605 static char *name[] = {
606 "init risc lo",
607 "init risc hi",
608 "cdt base",
609 "cdt size",
610 "iq base",
611 "iq size",
612 "risc pc lo",
613 "risc pc hi",
614 "iq wr ptr",
615 "iq rd ptr",
616 "cdt current",
617 "pci target lo",
618 "pci target hi",
619 "line / byte",
620 };
621 u32 risc;
622 unsigned int i, j, n;
623
624 pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
625 for (i = 0; i < ARRAY_SIZE(name); i++)
626 pr_warn("cmds + 0x%2x: %-15s: 0x%08x\n",
627 i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
628
629 j = i * 4;
630 for (i = 0; i < 4;) {
631 risc = cx_read(ch->cmds_start + 4 * (i + 14));
632 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i);
633 i += cx25821_risc_decode(risc);
634 }
635
636 for (i = 0; i < (64 >> 2); i += n) {
637 risc = cx_read(ch->ctrl_start + 4 * i);
638 /* No consideration for bits 63-32 */
639
640 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
641 i * 4, ch->ctrl_start + 4 * i, i);
642 n = cx25821_risc_decode(risc);
643 for (j = 1; j < n; j++) {
644 risc = cx_read(ch->ctrl_start + 4 * (i + j));
645 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
646 4 * (i + j), i + j, risc, j);
647 }
648 }
649
650 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
651 ch->fifo_start, ch->fifo_start + ch->fifo_size);
652 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
653 ch->ctrl_start, ch->ctrl_start + 6 * 16);
654 pr_warn(" : ptr1_reg: 0x%08x\n",
655 cx_read(ch->ptr1_reg));
656 pr_warn(" : ptr2_reg: 0x%08x\n",
657 cx_read(ch->ptr2_reg));
658 pr_warn(" : cnt1_reg: 0x%08x\n",
659 cx_read(ch->cnt1_reg));
660 pr_warn(" : cnt2_reg: 0x%08x\n",
661 cx_read(ch->cnt2_reg));
662 }
663 EXPORT_SYMBOL(cx25821_sram_channel_dump);
664
cx25821_sram_channel_dump_audio(struct cx25821_dev * dev,struct sram_channel * ch)665 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
666 struct sram_channel *ch)
667 {
668 static const char * const name[] = {
669 "init risc lo",
670 "init risc hi",
671 "cdt base",
672 "cdt size",
673 "iq base",
674 "iq size",
675 "risc pc lo",
676 "risc pc hi",
677 "iq wr ptr",
678 "iq rd ptr",
679 "cdt current",
680 "pci target lo",
681 "pci target hi",
682 "line / byte",
683 };
684
685 u32 risc, value, tmp;
686 unsigned int i, j, n;
687
688 pr_info("\n%s: %s - dma Audio channel status dump\n",
689 dev->name, ch->name);
690
691 for (i = 0; i < ARRAY_SIZE(name); i++)
692 pr_info("%s: cmds + 0x%2x: %-15s: 0x%08x\n",
693 dev->name, i * 4, name[i],
694 cx_read(ch->cmds_start + 4 * i));
695
696 j = i * 4;
697 for (i = 0; i < 4;) {
698 risc = cx_read(ch->cmds_start + 4 * (i + 14));
699 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i);
700 i += cx25821_risc_decode(risc);
701 }
702
703 for (i = 0; i < (64 >> 2); i += n) {
704 risc = cx_read(ch->ctrl_start + 4 * i);
705 /* No consideration for bits 63-32 */
706
707 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
708 i * 4, ch->ctrl_start + 4 * i, i);
709 n = cx25821_risc_decode(risc);
710
711 for (j = 1; j < n; j++) {
712 risc = cx_read(ch->ctrl_start + 4 * (i + j));
713 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
714 4 * (i + j), i + j, risc, j);
715 }
716 }
717
718 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
719 ch->fifo_start, ch->fifo_start + ch->fifo_size);
720 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
721 ch->ctrl_start, ch->ctrl_start + 6 * 16);
722 pr_warn(" : ptr1_reg: 0x%08x\n",
723 cx_read(ch->ptr1_reg));
724 pr_warn(" : ptr2_reg: 0x%08x\n",
725 cx_read(ch->ptr2_reg));
726 pr_warn(" : cnt1_reg: 0x%08x\n",
727 cx_read(ch->cnt1_reg));
728 pr_warn(" : cnt2_reg: 0x%08x\n",
729 cx_read(ch->cnt2_reg));
730
731 for (i = 0; i < 4; i++) {
732 risc = cx_read(ch->cmds_start + 56 + (i * 4));
733 pr_warn("instruction %d = 0x%x\n", i, risc);
734 }
735
736 /* read data from the first cdt buffer */
737 risc = cx_read(AUD_A_CDT);
738 pr_warn("\nread cdt loc=0x%x\n", risc);
739 for (i = 0; i < 8; i++) {
740 n = cx_read(risc + i * 4);
741 pr_cont("0x%x ", n);
742 }
743 pr_cont("\n\n");
744
745 value = cx_read(CLK_RST);
746 CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
747
748 value = cx_read(PLL_A_POST_STAT_BIST);
749 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
750 value = cx_read(PLL_A_INT_FRAC);
751 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
752
753 value = cx_read(PLL_B_POST_STAT_BIST);
754 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
755 value = cx_read(PLL_B_INT_FRAC);
756 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
757
758 value = cx_read(PLL_C_POST_STAT_BIST);
759 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
760 value = cx_read(PLL_C_INT_FRAC);
761 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
762
763 value = cx_read(PLL_D_POST_STAT_BIST);
764 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
765 value = cx_read(PLL_D_INT_FRAC);
766 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
767
768 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
769 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
770 }
771 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
772
cx25821_shutdown(struct cx25821_dev * dev)773 static void cx25821_shutdown(struct cx25821_dev *dev)
774 {
775 int i;
776
777 /* disable RISC controller */
778 cx_write(DEV_CNTRL2, 0);
779
780 /* Disable Video A/B activity */
781 for (i = 0; i < VID_CHANNEL_NUM; i++) {
782 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
783 cx_write(dev->channels[i].sram_channels->int_msk, 0);
784 }
785
786 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
787 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
788 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
789 cx_write(dev->channels[i].sram_channels->int_msk, 0);
790 }
791
792 /* Disable Audio activity */
793 cx_write(AUD_INT_DMA_CTL, 0);
794
795 /* Disable Serial port */
796 cx_write(UART_CTL, 0);
797
798 /* Disable Interrupts */
799 cx_write(PCI_INT_MSK, 0);
800 cx_write(AUD_A_INT_MSK, 0);
801 }
802
cx25821_set_pixel_format(struct cx25821_dev * dev,int channel_select,u32 format)803 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
804 u32 format)
805 {
806 if (channel_select <= 7 && channel_select >= 0) {
807 cx_write(dev->channels[channel_select].sram_channels->pix_frmt,
808 format);
809 dev->channels[channel_select].pixel_formats = format;
810 }
811 }
812
cx25821_set_vip_mode(struct cx25821_dev * dev,struct sram_channel * ch)813 static void cx25821_set_vip_mode(struct cx25821_dev *dev,
814 struct sram_channel *ch)
815 {
816 cx_write(ch->pix_frmt, PIXEL_FRMT_422);
817 cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
818 }
819
cx25821_initialize(struct cx25821_dev * dev)820 static void cx25821_initialize(struct cx25821_dev *dev)
821 {
822 int i;
823
824 dprintk(1, "%s()\n", __func__);
825
826 cx25821_shutdown(dev);
827 cx_write(PCI_INT_STAT, 0xffffffff);
828
829 for (i = 0; i < VID_CHANNEL_NUM; i++)
830 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
831
832 cx_write(AUD_A_INT_STAT, 0xffffffff);
833 cx_write(AUD_B_INT_STAT, 0xffffffff);
834 cx_write(AUD_C_INT_STAT, 0xffffffff);
835 cx_write(AUD_D_INT_STAT, 0xffffffff);
836 cx_write(AUD_E_INT_STAT, 0xffffffff);
837
838 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
839 cx_write(PAD_CTRL, 0x12); /* for I2C */
840 cx25821_registers_init(dev); /* init Pecos registers */
841 mdelay(100);
842
843 for (i = 0; i < VID_CHANNEL_NUM; i++) {
844 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
845 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
846 1440, 0);
847 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
848 dev->channels[i].use_cif_resolution = FALSE;
849 }
850
851 /* Probably only affect Downstream */
852 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
853 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
854 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
855 }
856
857 cx25821_sram_channel_setup_audio(dev,
858 dev->channels[SRAM_CH08].sram_channels, 128, 0);
859
860 cx25821_gpio_init(dev);
861 }
862
cx25821_get_resources(struct cx25821_dev * dev)863 static int cx25821_get_resources(struct cx25821_dev *dev)
864 {
865 if (request_mem_region(pci_resource_start(dev->pci, 0),
866 pci_resource_len(dev->pci, 0), dev->name))
867 return 0;
868
869 pr_err("%s: can't get MMIO memory @ 0x%llx\n",
870 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
871
872 return -EBUSY;
873 }
874
cx25821_dev_checkrevision(struct cx25821_dev * dev)875 static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
876 {
877 dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
878
879 pr_info("%s(): Hardware revision = 0x%02x\n",
880 __func__, dev->hwrevision);
881 }
882
cx25821_iounmap(struct cx25821_dev * dev)883 static void cx25821_iounmap(struct cx25821_dev *dev)
884 {
885 if (dev == NULL)
886 return;
887
888 /* Releasing IO memory */
889 if (dev->lmmio != NULL) {
890 CX25821_INFO("Releasing lmmio.\n");
891 iounmap(dev->lmmio);
892 dev->lmmio = NULL;
893 }
894 }
895
cx25821_dev_setup(struct cx25821_dev * dev)896 static int cx25821_dev_setup(struct cx25821_dev *dev)
897 {
898 int io_size = 0, i;
899
900 pr_info("\n***********************************\n");
901 pr_info("cx25821 set up\n");
902 pr_info("***********************************\n\n");
903
904 mutex_init(&dev->lock);
905
906 atomic_inc(&dev->refcount);
907
908 dev->nr = ++cx25821_devcount;
909 sprintf(dev->name, "cx25821[%d]", dev->nr);
910
911 mutex_lock(&cx25821_devlist_mutex);
912 list_add_tail(&dev->devlist, &cx25821_devlist);
913 mutex_unlock(&cx25821_devlist_mutex);
914
915 if (dev->pci->device != 0x8210) {
916 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
917 __func__, dev->pci->device);
918 return -1;
919 } else {
920 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
921 }
922
923 /* Apply a sensible clock frequency for the PCIe bridge */
924 dev->clk_freq = 28000000;
925 for (i = 0; i < MAX_VID_CHANNEL_NUM; i++)
926 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
927
928 if (dev->nr > 1)
929 CX25821_INFO("dev->nr > 1!");
930
931 /* board config */
932 dev->board = 1; /* card[dev->nr]; */
933 dev->_max_num_decoders = MAX_DECODERS;
934
935 dev->pci_bus = dev->pci->bus->number;
936 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
937 dev->pci_irqmask = 0x001f00;
938
939 /* External Master 1 Bus */
940 dev->i2c_bus[0].nr = 0;
941 dev->i2c_bus[0].dev = dev;
942 dev->i2c_bus[0].reg_stat = I2C1_STAT;
943 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
944 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
945 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
946 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
947 dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */
948
949 if (cx25821_get_resources(dev) < 0) {
950 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
951 dev->name, dev->pci->subsystem_vendor,
952 dev->pci->subsystem_device);
953
954 cx25821_devcount--;
955 return -EBUSY;
956 }
957
958 /* PCIe stuff */
959 dev->base_io_addr = pci_resource_start(dev->pci, 0);
960 io_size = pci_resource_len(dev->pci, 0);
961
962 if (!dev->base_io_addr) {
963 CX25821_ERR("No PCI Memory resources, exiting!\n");
964 return -ENODEV;
965 }
966
967 dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
968
969 if (!dev->lmmio) {
970 CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
971 cx25821_iounmap(dev);
972 return -ENOMEM;
973 }
974
975 dev->bmmio = (u8 __iomem *) dev->lmmio;
976
977 pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
978 dev->name, dev->pci->subsystem_vendor,
979 dev->pci->subsystem_device, cx25821_boards[dev->board].name,
980 dev->board, card[dev->nr] == dev->board ?
981 "insmod option" : "autodetected");
982
983 /* init hardware */
984 cx25821_initialize(dev);
985
986 cx25821_i2c_register(&dev->i2c_bus[0]);
987 /* cx25821_i2c_register(&dev->i2c_bus[1]);
988 * cx25821_i2c_register(&dev->i2c_bus[2]); */
989
990 CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
991 dev->i2c_bus[0].i2c_rc);
992
993 cx25821_card_setup(dev);
994
995 if (medusa_video_init(dev) < 0)
996 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
997
998 cx25821_video_register(dev);
999
1000 /* register IOCTL device */
1001 dev->ioctl_dev = cx25821_vdev_init(dev, dev->pci,
1002 &cx25821_videoioctl_template, "video");
1003
1004 if (video_register_device
1005 (dev->ioctl_dev, VFL_TYPE_GRABBER, VIDEO_IOCTL_CH) < 0) {
1006 cx25821_videoioctl_unregister(dev);
1007 pr_err("%s(): Failed to register video adapter for IOCTL, so unregistering videoioctl device\n",
1008 __func__);
1009 }
1010
1011 cx25821_dev_checkrevision(dev);
1012 CX25821_INFO("setup done!\n");
1013
1014 return 0;
1015 }
1016
cx25821_start_upstream_video_ch1(struct cx25821_dev * dev,struct upstream_user_struct * up_data)1017 void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
1018 struct upstream_user_struct *up_data)
1019 {
1020 dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0;
1021
1022 dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1023 medusa_set_videostandard(dev);
1024
1025 cx25821_vidupstream_init_ch1(dev, dev->channel_select,
1026 dev->pixel_format);
1027 }
1028
cx25821_start_upstream_video_ch2(struct cx25821_dev * dev,struct upstream_user_struct * up_data)1029 void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
1030 struct upstream_user_struct *up_data)
1031 {
1032 dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0;
1033
1034 dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1035 medusa_set_videostandard(dev);
1036
1037 cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2,
1038 dev->pixel_format_ch2);
1039 }
1040
cx25821_start_upstream_audio(struct cx25821_dev * dev,struct upstream_user_struct * up_data)1041 void cx25821_start_upstream_audio(struct cx25821_dev *dev,
1042 struct upstream_user_struct *up_data)
1043 {
1044 cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B);
1045 }
1046
cx25821_dev_unregister(struct cx25821_dev * dev)1047 void cx25821_dev_unregister(struct cx25821_dev *dev)
1048 {
1049 int i;
1050
1051 if (!dev->base_io_addr)
1052 return;
1053
1054 cx25821_free_mem_upstream_ch1(dev);
1055 cx25821_free_mem_upstream_ch2(dev);
1056 cx25821_free_mem_upstream_audio(dev);
1057
1058 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1059
1060 if (!atomic_dec_and_test(&dev->refcount))
1061 return;
1062
1063 for (i = 0; i < VID_CHANNEL_NUM; i++)
1064 cx25821_video_unregister(dev, i);
1065
1066 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
1067 i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) {
1068 cx25821_video_unregister(dev, i);
1069 }
1070
1071 cx25821_videoioctl_unregister(dev);
1072
1073 cx25821_i2c_unregister(&dev->i2c_bus[0]);
1074 cx25821_iounmap(dev);
1075 }
1076 EXPORT_SYMBOL(cx25821_dev_unregister);
1077
cx25821_risc_field(__le32 * rp,struct scatterlist * sglist,unsigned int offset,u32 sync_line,unsigned int bpl,unsigned int padding,unsigned int lines)1078 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
1079 unsigned int offset, u32 sync_line,
1080 unsigned int bpl, unsigned int padding,
1081 unsigned int lines)
1082 {
1083 struct scatterlist *sg;
1084 unsigned int line, todo;
1085
1086 /* sync instruction */
1087 if (sync_line != NO_SYNC_LINE)
1088 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1089
1090 /* scan lines */
1091 sg = sglist;
1092 for (line = 0; line < lines; line++) {
1093 while (offset && offset >= sg_dma_len(sg)) {
1094 offset -= sg_dma_len(sg);
1095 sg++;
1096 }
1097 if (bpl <= sg_dma_len(sg) - offset) {
1098 /* fits into current chunk */
1099 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL |
1100 bpl);
1101 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1102 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1103 offset += bpl;
1104 } else {
1105 /* scanline needs to be split */
1106 todo = bpl;
1107 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL |
1108 (sg_dma_len(sg) - offset));
1109 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1110 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1111 todo -= (sg_dma_len(sg) - offset);
1112 offset = 0;
1113 sg++;
1114 while (todo > sg_dma_len(sg)) {
1115 *(rp++) = cpu_to_le32(RISC_WRITE |
1116 sg_dma_len(sg));
1117 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1118 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1119 todo -= sg_dma_len(sg);
1120 sg++;
1121 }
1122 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1123 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1124 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1125 offset += todo;
1126 }
1127
1128 offset += padding;
1129 }
1130
1131 return rp;
1132 }
1133
cx25821_risc_buffer(struct pci_dev * pci,struct btcx_riscmem * risc,struct scatterlist * sglist,unsigned int top_offset,unsigned int bottom_offset,unsigned int bpl,unsigned int padding,unsigned int lines)1134 int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1135 struct scatterlist *sglist, unsigned int top_offset,
1136 unsigned int bottom_offset, unsigned int bpl,
1137 unsigned int padding, unsigned int lines)
1138 {
1139 u32 instructions;
1140 u32 fields;
1141 __le32 *rp;
1142 int rc;
1143
1144 fields = 0;
1145 if (UNSET != top_offset)
1146 fields++;
1147 if (UNSET != bottom_offset)
1148 fields++;
1149
1150 /* estimate risc mem: worst case is one write per page border +
1151 one write per scan line + syncs + jump (all 2 dwords). Padding
1152 can cause next bpl to start close to a page border. First DMA
1153 region may be smaller than PAGE_SIZE */
1154 /* write and jump need and extra dword */
1155 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE +
1156 lines);
1157 instructions += 2;
1158 rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1159
1160 if (rc < 0)
1161 return rc;
1162
1163 /* write risc instructions */
1164 rp = risc->cpu;
1165
1166 if (UNSET != top_offset) {
1167 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1168 lines);
1169 }
1170
1171 if (UNSET != bottom_offset) {
1172 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1173 padding, lines);
1174 }
1175
1176 /* save pointer to jmp instruction address */
1177 risc->jmp = rp;
1178 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1179
1180 return 0;
1181 }
1182
cx25821_risc_field_audio(__le32 * rp,struct scatterlist * sglist,unsigned int offset,u32 sync_line,unsigned int bpl,unsigned int padding,unsigned int lines,unsigned int lpi)1183 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1184 unsigned int offset, u32 sync_line,
1185 unsigned int bpl, unsigned int padding,
1186 unsigned int lines, unsigned int lpi)
1187 {
1188 struct scatterlist *sg;
1189 unsigned int line, todo, sol;
1190
1191 /* sync instruction */
1192 if (sync_line != NO_SYNC_LINE)
1193 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1194
1195 /* scan lines */
1196 sg = sglist;
1197 for (line = 0; line < lines; line++) {
1198 while (offset && offset >= sg_dma_len(sg)) {
1199 offset -= sg_dma_len(sg);
1200 sg++;
1201 }
1202
1203 if (lpi && line > 0 && !(line % lpi))
1204 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1205 else
1206 sol = RISC_SOL;
1207
1208 if (bpl <= sg_dma_len(sg) - offset) {
1209 /* fits into current chunk */
1210 *(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL |
1211 bpl);
1212 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1213 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1214 offset += bpl;
1215 } else {
1216 /* scanline needs to be split */
1217 todo = bpl;
1218 *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1219 (sg_dma_len(sg) - offset));
1220 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1221 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1222 todo -= (sg_dma_len(sg) - offset);
1223 offset = 0;
1224 sg++;
1225 while (todo > sg_dma_len(sg)) {
1226 *(rp++) = cpu_to_le32(RISC_WRITE |
1227 sg_dma_len(sg));
1228 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1229 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1230 todo -= sg_dma_len(sg);
1231 sg++;
1232 }
1233 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1234 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1235 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1236 offset += todo;
1237 }
1238 offset += padding;
1239 }
1240
1241 return rp;
1242 }
1243
cx25821_risc_databuffer_audio(struct pci_dev * pci,struct btcx_riscmem * risc,struct scatterlist * sglist,unsigned int bpl,unsigned int lines,unsigned int lpi)1244 int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1245 struct btcx_riscmem *risc,
1246 struct scatterlist *sglist,
1247 unsigned int bpl,
1248 unsigned int lines, unsigned int lpi)
1249 {
1250 u32 instructions;
1251 __le32 *rp;
1252 int rc;
1253
1254 /* estimate risc mem: worst case is one write per page border +
1255 one write per scan line + syncs + jump (all 2 dwords). Here
1256 there is no padding and no sync. First DMA region may be smaller
1257 than PAGE_SIZE */
1258 /* Jump and write need an extra dword */
1259 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1260 instructions += 1;
1261
1262 rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1263 if (rc < 0)
1264 return rc;
1265
1266 /* write risc instructions */
1267 rp = risc->cpu;
1268 rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1269 lines, lpi);
1270
1271 /* save pointer to jmp instruction address */
1272 risc->jmp = rp;
1273 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1274 return 0;
1275 }
1276 EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1277
cx25821_risc_stopper(struct pci_dev * pci,struct btcx_riscmem * risc,u32 reg,u32 mask,u32 value)1278 int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1279 u32 reg, u32 mask, u32 value)
1280 {
1281 __le32 *rp;
1282 int rc;
1283
1284 rc = btcx_riscmem_alloc(pci, risc, 4 * 16);
1285
1286 if (rc < 0)
1287 return rc;
1288
1289 /* write risc instructions */
1290 rp = risc->cpu;
1291
1292 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1);
1293 *(rp++) = cpu_to_le32(reg);
1294 *(rp++) = cpu_to_le32(value);
1295 *(rp++) = cpu_to_le32(mask);
1296 *(rp++) = cpu_to_le32(RISC_JUMP);
1297 *(rp++) = cpu_to_le32(risc->dma);
1298 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1299 return 0;
1300 }
1301
cx25821_free_buffer(struct videobuf_queue * q,struct cx25821_buffer * buf)1302 void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf)
1303 {
1304 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1305
1306 BUG_ON(in_interrupt());
1307 videobuf_waiton(q, &buf->vb, 0, 0);
1308 videobuf_dma_unmap(q->dev, dma);
1309 videobuf_dma_free(dma);
1310 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1311 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1312 }
1313
cx25821_irq(int irq,void * dev_id)1314 static irqreturn_t cx25821_irq(int irq, void *dev_id)
1315 {
1316 struct cx25821_dev *dev = dev_id;
1317 u32 pci_status, pci_mask;
1318 u32 vid_status;
1319 int i, handled = 0;
1320 u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1321
1322 pci_status = cx_read(PCI_INT_STAT);
1323 pci_mask = cx_read(PCI_INT_MSK);
1324
1325 if (pci_status == 0)
1326 goto out;
1327
1328 for (i = 0; i < VID_CHANNEL_NUM; i++) {
1329 if (pci_status & mask[i]) {
1330 vid_status = cx_read(dev->channels[i].
1331 sram_channels->int_stat);
1332
1333 if (vid_status)
1334 handled += cx25821_video_irq(dev, i,
1335 vid_status);
1336
1337 cx_write(PCI_INT_STAT, mask[i]);
1338 }
1339 }
1340
1341 out:
1342 return IRQ_RETVAL(handled);
1343 }
1344
cx25821_print_irqbits(char * name,char * tag,char ** strings,int len,u32 bits,u32 mask)1345 void cx25821_print_irqbits(char *name, char *tag, char **strings,
1346 int len, u32 bits, u32 mask)
1347 {
1348 unsigned int i;
1349
1350 printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1351
1352 for (i = 0; i < len; i++) {
1353 if (!(bits & (1 << i)))
1354 continue;
1355 if (strings[i])
1356 pr_cont(" %s", strings[i]);
1357 else
1358 pr_cont(" %d", i);
1359 if (!(mask & (1 << i)))
1360 continue;
1361 pr_cont("*");
1362 }
1363 pr_cont("\n");
1364 }
1365 EXPORT_SYMBOL(cx25821_print_irqbits);
1366
cx25821_dev_get(struct pci_dev * pci)1367 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1368 {
1369 struct cx25821_dev *dev = pci_get_drvdata(pci);
1370 return dev;
1371 }
1372 EXPORT_SYMBOL(cx25821_dev_get);
1373
cx25821_initdev(struct pci_dev * pci_dev,const struct pci_device_id * pci_id)1374 static int __devinit cx25821_initdev(struct pci_dev *pci_dev,
1375 const struct pci_device_id *pci_id)
1376 {
1377 struct cx25821_dev *dev;
1378 int err = 0;
1379
1380 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1381 if (NULL == dev)
1382 return -ENOMEM;
1383
1384 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1385 if (err < 0)
1386 goto fail_free;
1387
1388 /* pci init */
1389 dev->pci = pci_dev;
1390 if (pci_enable_device(pci_dev)) {
1391 err = -EIO;
1392
1393 pr_info("pci enable failed!\n");
1394
1395 goto fail_unregister_device;
1396 }
1397
1398 pr_info("Athena pci enable !\n");
1399
1400 err = cx25821_dev_setup(dev);
1401 if (err) {
1402 if (err == -EBUSY)
1403 goto fail_unregister_device;
1404 else
1405 goto fail_unregister_pci;
1406 }
1407
1408 /* print pci info */
1409 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1410 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1411 pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1412 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1413 dev->pci_lat, (unsigned long long)dev->base_io_addr);
1414
1415 pci_set_master(pci_dev);
1416 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1417 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1418 err = -EIO;
1419 goto fail_irq;
1420 }
1421
1422 err = request_irq(pci_dev->irq, cx25821_irq,
1423 IRQF_SHARED, dev->name, dev);
1424
1425 if (err < 0) {
1426 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1427 goto fail_irq;
1428 }
1429
1430 return 0;
1431
1432 fail_irq:
1433 pr_info("cx25821_initdev() can't get IRQ !\n");
1434 cx25821_dev_unregister(dev);
1435
1436 fail_unregister_pci:
1437 pci_disable_device(pci_dev);
1438 fail_unregister_device:
1439 v4l2_device_unregister(&dev->v4l2_dev);
1440
1441 fail_free:
1442 kfree(dev);
1443 return err;
1444 }
1445
cx25821_finidev(struct pci_dev * pci_dev)1446 static void __devexit cx25821_finidev(struct pci_dev *pci_dev)
1447 {
1448 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1449 struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1450
1451 cx25821_shutdown(dev);
1452 pci_disable_device(pci_dev);
1453
1454 /* unregister stuff */
1455 if (pci_dev->irq)
1456 free_irq(pci_dev->irq, dev);
1457
1458 mutex_lock(&cx25821_devlist_mutex);
1459 list_del(&dev->devlist);
1460 mutex_unlock(&cx25821_devlist_mutex);
1461
1462 cx25821_dev_unregister(dev);
1463 v4l2_device_unregister(v4l2_dev);
1464 kfree(dev);
1465 }
1466
1467 static DEFINE_PCI_DEVICE_TABLE(cx25821_pci_tbl) = {
1468 {
1469 /* CX25821 Athena */
1470 .vendor = 0x14f1,
1471 .device = 0x8210,
1472 .subvendor = 0x14f1,
1473 .subdevice = 0x0920,
1474 }, {
1475 /* CX25821 No Brand */
1476 .vendor = 0x14f1,
1477 .device = 0x8210,
1478 .subvendor = 0x0000,
1479 .subdevice = 0x0000,
1480 }, {
1481 /* --- end of list --- */
1482 }
1483 };
1484
1485 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1486
1487 static struct pci_driver cx25821_pci_driver = {
1488 .name = "cx25821",
1489 .id_table = cx25821_pci_tbl,
1490 .probe = cx25821_initdev,
1491 .remove = __devexit_p(cx25821_finidev),
1492 /* TODO */
1493 .suspend = NULL,
1494 .resume = NULL,
1495 };
1496
cx25821_init(void)1497 static int __init cx25821_init(void)
1498 {
1499 pr_info("driver version %d.%d.%d loaded\n",
1500 (CX25821_VERSION_CODE >> 16) & 0xff,
1501 (CX25821_VERSION_CODE >> 8) & 0xff,
1502 CX25821_VERSION_CODE & 0xff);
1503 return pci_register_driver(&cx25821_pci_driver);
1504 }
1505
cx25821_fini(void)1506 static void __exit cx25821_fini(void)
1507 {
1508 pci_unregister_driver(&cx25821_pci_driver);
1509 }
1510
1511 module_init(cx25821_init);
1512 module_exit(cx25821_fini);
1513