1 /* 2 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on 3 * AVR32 systems.) 4 * 5 * Copyright (C) 2007 Atmel Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef DW_DMAC_H 12 #define DW_DMAC_H 13 14 #include <linux/dmaengine.h> 15 16 /** 17 * struct dw_dma_platform_data - Controller configuration parameters 18 * @nr_channels: Number of channels supported by hardware (max 8) 19 * @is_private: The device channels should be marked as private and not for 20 * by the general purpose DMA channel allocator. 21 */ 22 struct dw_dma_platform_data { 23 unsigned int nr_channels; 24 bool is_private; 25 #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 26 #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 27 unsigned char chan_allocation_order; 28 #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 29 #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 30 unsigned char chan_priority; 31 }; 32 33 /** 34 * enum dw_dma_slave_width - DMA slave register access width. 35 * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses 36 * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses 37 * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses 38 */ 39 enum dw_dma_slave_width { 40 DW_DMA_SLAVE_WIDTH_8BIT, 41 DW_DMA_SLAVE_WIDTH_16BIT, 42 DW_DMA_SLAVE_WIDTH_32BIT, 43 }; 44 45 /* bursts size */ 46 enum dw_dma_msize { 47 DW_DMA_MSIZE_1, 48 DW_DMA_MSIZE_4, 49 DW_DMA_MSIZE_8, 50 DW_DMA_MSIZE_16, 51 DW_DMA_MSIZE_32, 52 DW_DMA_MSIZE_64, 53 DW_DMA_MSIZE_128, 54 DW_DMA_MSIZE_256, 55 }; 56 57 /* flow controller */ 58 enum dw_dma_fc { 59 DW_DMA_FC_D_M2M, 60 DW_DMA_FC_D_M2P, 61 DW_DMA_FC_D_P2M, 62 DW_DMA_FC_D_P2P, 63 DW_DMA_FC_P_P2M, 64 DW_DMA_FC_SP_P2P, 65 DW_DMA_FC_P_M2P, 66 DW_DMA_FC_DP_P2P, 67 }; 68 69 /** 70 * struct dw_dma_slave - Controller-specific information about a slave 71 * 72 * @dma_dev: required DMA master device 73 * @tx_reg: physical address of data register used for 74 * memory-to-peripheral transfers 75 * @rx_reg: physical address of data register used for 76 * peripheral-to-memory transfers 77 * @reg_width: peripheral register width 78 * @cfg_hi: Platform-specific initializer for the CFG_HI register 79 * @cfg_lo: Platform-specific initializer for the CFG_LO register 80 * @src_master: src master for transfers on allocated channel. 81 * @dst_master: dest master for transfers on allocated channel. 82 * @src_msize: src burst size. 83 * @dst_msize: dest burst size. 84 * @fc: flow controller for DMA transfer 85 */ 86 struct dw_dma_slave { 87 struct device *dma_dev; 88 dma_addr_t tx_reg; 89 dma_addr_t rx_reg; 90 enum dw_dma_slave_width reg_width; 91 u32 cfg_hi; 92 u32 cfg_lo; 93 u8 src_master; 94 u8 dst_master; 95 u8 src_msize; 96 u8 dst_msize; 97 u8 fc; 98 }; 99 100 /* Platform-configurable bits in CFG_HI */ 101 #define DWC_CFGH_FCMODE (1 << 0) 102 #define DWC_CFGH_FIFO_MODE (1 << 1) 103 #define DWC_CFGH_PROTCTL(x) ((x) << 2) 104 #define DWC_CFGH_SRC_PER(x) ((x) << 7) 105 #define DWC_CFGH_DST_PER(x) ((x) << 11) 106 107 /* Platform-configurable bits in CFG_LO */ 108 #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ 109 #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) 110 #define DWC_CFGL_LOCK_CH_XACT (2 << 12) 111 #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ 112 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) 113 #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) 114 #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ 115 #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ 116 #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ 117 #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ 118 119 /* DMA API extensions */ 120 struct dw_cyclic_desc { 121 struct dw_desc **desc; 122 unsigned long periods; 123 void (*period_callback)(void *param); 124 void *period_callback_param; 125 }; 126 127 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 128 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 129 enum dma_data_direction direction); 130 void dw_dma_cyclic_free(struct dma_chan *chan); 131 int dw_dma_cyclic_start(struct dma_chan *chan); 132 void dw_dma_cyclic_stop(struct dma_chan *chan); 133 134 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan); 135 136 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan); 137 138 #endif /* DW_DMAC_H */ 139