1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT7915_H
5 #define __MT7915_H
6
7 #include <linux/interrupt.h>
8 #include <linux/ktime.h>
9 #include "../mt76_connac.h"
10 #include "regs.h"
11
12 #define MT7915_MAX_INTERFACES 19
13 #define MT7915_WTBL_SIZE 288
14 #define MT7916_WTBL_SIZE 544
15 #define MT7915_WTBL_RESERVED (mt7915_wtbl_size(dev) - 1)
16 #define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \
17 MT7915_MAX_INTERFACES)
18
19 #define MT7915_WATCHDOG_TIME (HZ / 10)
20 #define MT7915_RESET_TIMEOUT (30 * HZ)
21
22 #define MT7915_TX_RING_SIZE 2048
23 #define MT7915_TX_MCU_RING_SIZE 256
24 #define MT7915_TX_FWDL_RING_SIZE 128
25
26 #define MT7915_RX_RING_SIZE 1536
27 #define MT7915_RX_MCU_RING_SIZE 512
28
29 #define MT7915_FIRMWARE_WA "mediatek/mt7915_wa.bin"
30 #define MT7915_FIRMWARE_WM "mediatek/mt7915_wm.bin"
31 #define MT7915_ROM_PATCH "mediatek/mt7915_rom_patch.bin"
32
33 #define MT7916_FIRMWARE_WA "mediatek/mt7916_wa.bin"
34 #define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin"
35 #define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin"
36
37 #define MT7986_FIRMWARE_WA "mediatek/mt7986_wa.bin"
38 #define MT7986_FIRMWARE_WM "mediatek/mt7986_wm.bin"
39 #define MT7986_FIRMWARE_WM_MT7975 "mediatek/mt7986_wm_mt7975.bin"
40 #define MT7986_ROM_PATCH "mediatek/mt7986_rom_patch.bin"
41 #define MT7986_ROM_PATCH_MT7975 "mediatek/mt7986_rom_patch_mt7975.bin"
42
43 #define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin"
44 #define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin"
45 #define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin"
46 #define MT7986_EEPROM_MT7975_DEFAULT "mediatek/mt7986_eeprom_mt7975.bin"
47 #define MT7986_EEPROM_MT7975_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7975_dual.bin"
48 #define MT7986_EEPROM_MT7976_DEFAULT "mediatek/mt7986_eeprom_mt7976.bin"
49 #define MT7986_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7986_eeprom_mt7976_dbdc.bin"
50 #define MT7986_EEPROM_MT7976_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7976_dual.bin"
51
52 #define MT7915_EEPROM_SIZE 3584
53 #define MT7916_EEPROM_SIZE 4096
54
55 #define MT7915_EEPROM_BLOCK_SIZE 16
56 #define MT7915_TOKEN_SIZE 8192
57
58 #define MT7915_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
59 #define MT7915_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
60
61 #define MT7915_THERMAL_THROTTLE_MAX 100
62 #define MT7915_CDEV_THROTTLE_MAX 99
63
64 #define MT7915_SKU_RATE_NUM 161
65
66 #define MT7915_MAX_TWT_AGRT 16
67 #define MT7915_MAX_STA_TWT_AGRT 8
68 #define MT7915_MIN_TWT_DUR 64
69 #define MT7915_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 2)
70
71 struct mt7915_vif;
72 struct mt7915_sta;
73 struct mt7915_dfs_pulse;
74 struct mt7915_dfs_pattern;
75
76 enum mt7915_txq_id {
77 MT7915_TXQ_FWDL = 16,
78 MT7915_TXQ_MCU_WM,
79 MT7915_TXQ_BAND0,
80 MT7915_TXQ_BAND1,
81 MT7915_TXQ_MCU_WA,
82 };
83
84 enum mt7915_rxq_id {
85 MT7915_RXQ_BAND0 = 0,
86 MT7915_RXQ_BAND1,
87 MT7915_RXQ_MCU_WM = 0,
88 MT7915_RXQ_MCU_WA,
89 MT7915_RXQ_MCU_WA_EXT,
90 };
91
92 enum mt7916_rxq_id {
93 MT7916_RXQ_MCU_WM = 0,
94 MT7916_RXQ_MCU_WA,
95 MT7916_RXQ_MCU_WA_MAIN,
96 MT7916_RXQ_MCU_WA_EXT,
97 MT7916_RXQ_BAND0,
98 MT7916_RXQ_BAND1,
99 };
100
101 struct mt7915_twt_flow {
102 struct list_head list;
103 u64 start_tsf;
104 u64 tsf;
105 u32 duration;
106 u16 wcid;
107 __le16 mantissa;
108 u8 exp;
109 u8 table_id;
110 u8 id;
111 u8 protection:1;
112 u8 flowtype:1;
113 u8 trigger:1;
114 u8 sched:1;
115 };
116
117 struct mt7915_sta {
118 struct mt76_wcid wcid; /* must be first */
119
120 struct mt7915_vif *vif;
121
122 struct list_head poll_list;
123 struct list_head rc_list;
124 u32 airtime_ac[8];
125
126 unsigned long changed;
127 unsigned long jiffies;
128 unsigned long ampdu_state;
129
130 struct mt76_sta_stats stats;
131
132 struct mt76_connac_sta_key_conf bip;
133
134 struct {
135 u8 flowid_mask;
136 struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT];
137 } twt;
138 };
139
140 struct mt7915_vif_cap {
141 bool ht_ldpc:1;
142 bool vht_ldpc:1;
143 bool he_ldpc:1;
144 bool vht_su_ebfer:1;
145 bool vht_su_ebfee:1;
146 bool vht_mu_ebfer:1;
147 bool vht_mu_ebfee:1;
148 bool he_su_ebfer:1;
149 bool he_su_ebfee:1;
150 bool he_mu_ebfer:1;
151 };
152
153 struct mt7915_vif {
154 struct mt76_vif mt76; /* must be first */
155
156 struct mt7915_vif_cap cap;
157 struct mt7915_sta sta;
158 struct mt7915_phy *phy;
159
160 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
161 struct cfg80211_bitrate_mask bitrate_mask;
162 };
163
164 /* per-phy stats. */
165 struct mib_stats {
166 u32 ack_fail_cnt;
167 u32 fcs_err_cnt;
168 u32 rts_cnt;
169 u32 rts_retries_cnt;
170 u32 ba_miss_cnt;
171 u32 tx_bf_cnt;
172 u32 tx_mu_mpdu_cnt;
173 u32 tx_mu_acked_mpdu_cnt;
174 u32 tx_su_acked_mpdu_cnt;
175 u32 tx_bf_ibf_ppdu_cnt;
176 u32 tx_bf_ebf_ppdu_cnt;
177
178 u32 tx_bf_rx_fb_all_cnt;
179 u32 tx_bf_rx_fb_he_cnt;
180 u32 tx_bf_rx_fb_vht_cnt;
181 u32 tx_bf_rx_fb_ht_cnt;
182
183 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */
184 u32 tx_bf_rx_fb_nc_cnt;
185 u32 tx_bf_rx_fb_nr_cnt;
186 u32 tx_bf_fb_cpl_cnt;
187 u32 tx_bf_fb_trig_cnt;
188
189 u32 tx_ampdu_cnt;
190 u32 tx_stop_q_empty_cnt;
191 u32 tx_mpdu_attempts_cnt;
192 u32 tx_mpdu_success_cnt;
193 u32 tx_pkt_ebf_cnt;
194 u32 tx_pkt_ibf_cnt;
195
196 u32 tx_rwp_fail_cnt;
197 u32 tx_rwp_need_cnt;
198
199 /* rx stats */
200 u32 rx_fifo_full_cnt;
201 u32 channel_idle_cnt;
202 u32 rx_vector_mismatch_cnt;
203 u32 rx_delimiter_fail_cnt;
204 u32 rx_len_mismatch_cnt;
205 u32 rx_mpdu_cnt;
206 u32 rx_ampdu_cnt;
207 u32 rx_ampdu_bytes_cnt;
208 u32 rx_ampdu_valid_subframe_cnt;
209 u32 rx_ampdu_valid_subframe_bytes_cnt;
210 u32 rx_pfdrop_cnt;
211 u32 rx_vec_queue_overflow_drop_cnt;
212 u32 rx_ba_cnt;
213
214 u32 tx_amsdu[8];
215 u32 tx_amsdu_cnt;
216 };
217
218 struct mt7915_hif {
219 struct list_head list;
220
221 struct device *dev;
222 void __iomem *regs;
223 int irq;
224 };
225
226 struct mt7915_phy {
227 struct mt76_phy *mt76;
228 struct mt7915_dev *dev;
229
230 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
231
232 struct ieee80211_vif *monitor_vif;
233
234 struct thermal_cooling_device *cdev;
235 u8 cdev_state;
236 u8 throttle_state;
237 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
238
239 u32 rxfilter;
240 u64 omac_mask;
241 u8 band_idx;
242
243 u16 noise;
244
245 s16 coverage_class;
246 u8 slottime;
247
248 u8 rdd_state;
249
250 u32 trb_ts;
251
252 u32 rx_ampdu_ts;
253 u32 ampdu_ref;
254
255 struct mib_stats mib;
256 struct mt76_channel_state state_ts;
257
258 #ifdef CONFIG_NL80211_TESTMODE
259 struct {
260 u32 *reg_backup;
261
262 s32 last_freq_offset;
263 u8 last_rcpi[4];
264 s8 last_ib_rssi[4];
265 s8 last_wb_rssi[4];
266 u8 last_snr;
267
268 u8 spe_idx;
269 } test;
270 #endif
271 };
272
273 struct mt7915_dev {
274 union { /* must be first */
275 struct mt76_dev mt76;
276 struct mt76_phy mphy;
277 };
278
279 struct mt7915_hif *hif2;
280 struct mt7915_reg_desc reg;
281 u8 q_id[MT7915_MAX_QUEUE];
282 u32 q_int_mask[MT7915_MAX_QUEUE];
283 u32 wfdma_mask;
284
285 const struct mt76_bus_ops *bus_ops;
286 struct tasklet_struct irq_tasklet;
287 struct mt7915_phy phy;
288
289 /* monitor rx chain configured channel */
290 struct cfg80211_chan_def rdd2_chandef;
291 struct mt7915_phy *rdd2_phy;
292
293 u16 chainmask;
294 u16 chainshift;
295 u32 hif_idx;
296
297 struct work_struct init_work;
298 struct work_struct rc_work;
299 struct work_struct reset_work;
300 wait_queue_head_t reset_wait;
301 u32 reset_state;
302
303 struct list_head sta_rc_list;
304 struct list_head sta_poll_list;
305 struct list_head twt_list;
306 spinlock_t sta_poll_lock;
307
308 u32 hw_pattern;
309
310 bool dbdc_support;
311 bool flash_mode;
312 bool muru_debug;
313 bool ibf;
314
315 struct dentry *debugfs_dir;
316 struct rchan *relay_fwlog;
317
318 void *cal;
319
320 struct {
321 u8 debug_wm;
322 u8 debug_wa;
323 u8 debug_bin;
324 } fw;
325
326 struct {
327 u16 table_mask;
328 u8 n_agrt;
329 } twt;
330
331 struct reset_control *rstc;
332 void __iomem *dcm;
333 void __iomem *sku;
334 };
335
336 enum {
337 WFDMA0 = 0x0,
338 WFDMA1,
339 WFDMA_EXT,
340 __MT_WFDMA_MAX,
341 };
342
343 enum {
344 MT_RX_SEL0,
345 MT_RX_SEL1,
346 MT_RX_SEL2, /* monitor chain */
347 };
348
349 enum mt7915_rdd_cmd {
350 RDD_STOP,
351 RDD_START,
352 RDD_DET_MODE,
353 RDD_RADAR_EMULATE,
354 RDD_START_TXQ = 20,
355 RDD_CAC_START = 50,
356 RDD_CAC_END,
357 RDD_NORMAL_START,
358 RDD_DISABLE_DFS_CAL,
359 RDD_PULSE_DBG,
360 RDD_READ_PULSE,
361 RDD_RESUME_BF,
362 RDD_IRQ_OFF,
363 };
364
365 static inline struct mt7915_phy *
mt7915_hw_phy(struct ieee80211_hw * hw)366 mt7915_hw_phy(struct ieee80211_hw *hw)
367 {
368 struct mt76_phy *phy = hw->priv;
369
370 return phy->priv;
371 }
372
373 static inline struct mt7915_dev *
mt7915_hw_dev(struct ieee80211_hw * hw)374 mt7915_hw_dev(struct ieee80211_hw *hw)
375 {
376 struct mt76_phy *phy = hw->priv;
377
378 return container_of(phy->dev, struct mt7915_dev, mt76);
379 }
380
381 static inline struct mt7915_phy *
mt7915_ext_phy(struct mt7915_dev * dev)382 mt7915_ext_phy(struct mt7915_dev *dev)
383 {
384 struct mt76_phy *phy = dev->mt76.phy2;
385
386 if (!phy)
387 return NULL;
388
389 return phy->priv;
390 }
391
mt7915_check_adie(struct mt7915_dev * dev,bool sku)392 static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku)
393 {
394 u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK;
395
396 if (!is_mt7986(&dev->mt76))
397 return 0;
398
399 return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask;
400 }
401
402 extern const struct ieee80211_ops mt7915_ops;
403 extern const struct mt76_testmode_ops mt7915_testmode_ops;
404 extern struct pci_driver mt7915_pci_driver;
405 extern struct pci_driver mt7915_hif_driver;
406 extern struct platform_driver mt7986_wmac_driver;
407
408 #ifdef CONFIG_MT7986_WMAC
409 int mt7986_wmac_enable(struct mt7915_dev *dev);
410 void mt7986_wmac_disable(struct mt7915_dev *dev);
411 #else
mt7986_wmac_enable(struct mt7915_dev * dev)412 static inline int mt7986_wmac_enable(struct mt7915_dev *dev)
413 {
414 return 0;
415 }
416
mt7986_wmac_disable(struct mt7915_dev * dev)417 static inline void mt7986_wmac_disable(struct mt7915_dev *dev)
418 {
419 }
420 #endif
421 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
422 void __iomem *mem_base, u32 device_id);
423 void mt7915_wfsys_reset(struct mt7915_dev *dev);
424 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
425 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
426 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
427
428 int mt7915_register_device(struct mt7915_dev *dev);
429 void mt7915_unregister_device(struct mt7915_dev *dev);
430 int mt7915_eeprom_init(struct mt7915_dev *dev);
431 void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
432 struct mt7915_phy *phy);
433 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,
434 struct ieee80211_channel *chan,
435 u8 chain_idx);
436 s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band);
437 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2);
438 void mt7915_dma_prefetch(struct mt7915_dev *dev);
439 void mt7915_dma_cleanup(struct mt7915_dev *dev);
440 int mt7915_mcu_init(struct mt7915_dev *dev);
441 int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
442 struct mt7915_vif *mvif,
443 struct mt7915_twt_flow *flow,
444 int cmd);
445 int mt7915_mcu_add_dev_info(struct mt7915_phy *phy,
446 struct ieee80211_vif *vif, bool enable);
447 int mt7915_mcu_add_bss_info(struct mt7915_phy *phy,
448 struct ieee80211_vif *vif, int enable);
449 int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
450 struct ieee80211_sta *sta, bool enable);
451 int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev,
452 struct ieee80211_ampdu_params *params,
453 bool add);
454 int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev,
455 struct ieee80211_ampdu_params *params,
456 bool add);
457 int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif,
458 struct cfg80211_he_bss_color *he_bss_color);
459 int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
460 int enable, u32 changed);
461 int mt7915_mcu_add_obss_spr(struct mt7915_dev *dev, struct ieee80211_vif *vif,
462 bool enable);
463 int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif,
464 struct ieee80211_sta *sta, bool changed);
465 int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif,
466 struct ieee80211_sta *sta);
467 int mt7915_set_channel(struct mt7915_phy *phy);
468 int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd);
469 int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif);
470 int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req);
471 int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev,
472 struct ieee80211_vif *vif,
473 struct ieee80211_sta *sta,
474 void *data, u32 field);
475 int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);
476 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset);
477 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num);
478 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,
479 bool hdr_trans);
480 int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode,
481 u8 en);
482 int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band);
483 int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable);
484 int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy);
485 int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len);
486 int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action);
487 int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val);
488 int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev,
489 const struct mt7915_dfs_pulse *pulse);
490 int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index,
491 const struct mt7915_dfs_pattern *pattern);
492 int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val);
493 int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev);
494 int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy);
495 int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch);
496 int mt7915_mcu_get_temperature(struct mt7915_phy *phy);
497 int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state);
498 int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif,
499 struct ieee80211_sta *sta, struct rate_info *rate);
500 int mt7915_mcu_rdd_background_enable(struct mt7915_phy *phy,
501 struct cfg80211_chan_def *chandef);
502 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set);
503 int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
504 int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);
505 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
506 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
507 void mt7915_mcu_exit(struct mt7915_dev *dev);
508
mt7915_wtbl_size(struct mt7915_dev * dev)509 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
510 {
511 return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE;
512 }
513
mt7915_eeprom_size(struct mt7915_dev * dev)514 static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev)
515 {
516 return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE;
517 }
518
519 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg,
520 u32 clear, u32 set);
521
mt7915_irq_enable(struct mt7915_dev * dev,u32 mask)522 static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask)
523 {
524 if (dev->hif2)
525 mt7915_dual_hif_set_irq_mask(dev, false, 0, mask);
526 else
527 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
528
529 tasklet_schedule(&dev->irq_tasklet);
530 }
531
mt7915_irq_disable(struct mt7915_dev * dev,u32 mask)532 static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask)
533 {
534 if (dev->hif2)
535 mt7915_dual_hif_set_irq_mask(dev, true, mask, 0);
536 else
537 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
538 }
539
540 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw);
541 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask);
542 void mt7915_mac_reset_counters(struct mt7915_phy *phy);
543 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy);
544 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy);
545 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
546 struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
547 struct ieee80211_key_conf *key, u32 changed);
548 void mt7915_mac_set_timing(struct mt7915_phy *phy);
549 int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
550 struct ieee80211_sta *sta);
551 void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
552 struct ieee80211_sta *sta);
553 void mt7915_mac_work(struct work_struct *work);
554 void mt7915_mac_reset_work(struct work_struct *work);
555 void mt7915_mac_sta_rc_work(struct work_struct *work);
556 void mt7915_mac_update_stats(struct mt7915_phy *phy);
557 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,
558 struct mt7915_sta *msta,
559 u8 flowid);
560 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw,
561 struct ieee80211_sta *sta,
562 struct ieee80211_twt_setup *twt);
563 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
564 enum mt76_txq_id qid, struct mt76_wcid *wcid,
565 struct ieee80211_sta *sta,
566 struct mt76_tx_info *tx_info);
567 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
568 void mt7915_tx_token_put(struct mt7915_dev *dev);
569 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
570 struct sk_buff *skb);
571 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
572 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
573 void mt7915_stats_work(struct work_struct *work);
574 int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force);
575 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy);
576 void mt7915_set_stream_he_caps(struct mt7915_phy *phy);
577 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy);
578 void mt7915_update_channel(struct mt76_phy *mphy);
579 int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable);
580 int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy, void *ms);
581 int mt7915_init_debugfs(struct mt7915_phy *phy);
582 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len);
583 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len);
584 #ifdef CONFIG_MAC80211_DEBUGFS
585 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
586 struct ieee80211_sta *sta, struct dentry *dir);
587 #endif
588
589 #endif
590