1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Rickard E. (Rik) Faith <faith@valinux.com>
29 * Kevin E. Martin <martin@valinux.com>
30 * Gareth Hughes <gareth@valinux.com>
31 * Michel D�nzer <daenzerm@student.ethz.ch>
32 */
33
34 #ifndef __R128_DRV_H__
35 #define __R128_DRV_H__
36 #include <asm/delay.h>
37
38 #define GET_RING_HEAD(ring) readl( (volatile u32 *) (ring)->head )
39 #define SET_RING_HEAD(ring,val) writel( (val), (volatile u32 *) (ring)->head )
40
41 typedef struct drm_r128_freelist {
42 unsigned int age;
43 drm_buf_t *buf;
44 struct drm_r128_freelist *next;
45 struct drm_r128_freelist *prev;
46 } drm_r128_freelist_t;
47
48 typedef struct drm_r128_ring_buffer {
49 u32 *start;
50 u32 *end;
51 int size;
52 int size_l2qw;
53
54 volatile u32 *head;
55 u32 tail;
56 u32 tail_mask;
57 int space;
58
59 int high_mark;
60 } drm_r128_ring_buffer_t;
61
62 typedef struct drm_r128_private {
63 drm_r128_ring_buffer_t ring;
64 drm_r128_sarea_t *sarea_priv;
65
66 int cce_mode;
67 int cce_fifo_size;
68 int cce_running;
69
70 drm_r128_freelist_t *head;
71 drm_r128_freelist_t *tail;
72
73 int usec_timeout;
74 int is_pci;
75 unsigned long phys_pci_gart;
76 dma_addr_t bus_pci_gart;
77 unsigned long cce_buffers_offset;
78
79 atomic_t idle_count;
80
81 int page_flipping;
82 int current_page;
83 u32 crtc_offset;
84 u32 crtc_offset_cntl;
85
86 u32 color_fmt;
87 unsigned int front_offset;
88 unsigned int front_pitch;
89 unsigned int back_offset;
90 unsigned int back_pitch;
91
92 u32 depth_fmt;
93 unsigned int depth_offset;
94 unsigned int depth_pitch;
95 unsigned int span_offset;
96
97 u32 front_pitch_offset_c;
98 u32 back_pitch_offset_c;
99 u32 depth_pitch_offset_c;
100 u32 span_pitch_offset_c;
101
102 drm_map_t *sarea;
103 drm_map_t *fb;
104 drm_map_t *mmio;
105 drm_map_t *cce_ring;
106 drm_map_t *ring_rptr;
107 drm_map_t *buffers;
108 drm_map_t *agp_textures;
109 } drm_r128_private_t;
110
111 typedef struct drm_r128_buf_priv {
112 u32 age;
113 int prim;
114 int discard;
115 int dispatched;
116 drm_r128_freelist_t *list_entry;
117 } drm_r128_buf_priv_t;
118
119 /* r128_cce.c */
120 extern int r128_cce_init( struct inode *inode, struct file *filp,
121 unsigned int cmd, unsigned long arg );
122 extern int r128_cce_start( struct inode *inode, struct file *filp,
123 unsigned int cmd, unsigned long arg );
124 extern int r128_cce_stop( struct inode *inode, struct file *filp,
125 unsigned int cmd, unsigned long arg );
126 extern int r128_cce_reset( struct inode *inode, struct file *filp,
127 unsigned int cmd, unsigned long arg );
128 extern int r128_cce_idle( struct inode *inode, struct file *filp,
129 unsigned int cmd, unsigned long arg );
130 extern int r128_engine_reset( struct inode *inode, struct file *filp,
131 unsigned int cmd, unsigned long arg );
132 extern int r128_fullscreen( struct inode *inode, struct file *filp,
133 unsigned int cmd, unsigned long arg );
134 extern int r128_cce_buffers( struct inode *inode, struct file *filp,
135 unsigned int cmd, unsigned long arg );
136
137 extern void r128_freelist_reset( drm_device_t *dev );
138 extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
139
140 extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
141
142 static inline void
r128_update_ring_snapshot(drm_r128_ring_buffer_t * ring)143 r128_update_ring_snapshot( drm_r128_ring_buffer_t *ring )
144 {
145 ring->space = (GET_RING_HEAD( ring ) - ring->tail) * sizeof(u32);
146 if ( ring->space <= 0 )
147 ring->space += ring->size;
148 }
149
150 extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
151 extern int r128_do_cleanup_cce( drm_device_t *dev );
152 extern int r128_do_cleanup_pageflip( drm_device_t *dev );
153
154 /* r128_state.c */
155 extern int r128_cce_clear( struct inode *inode, struct file *filp,
156 unsigned int cmd, unsigned long arg );
157 extern int r128_cce_swap( struct inode *inode, struct file *filp,
158 unsigned int cmd, unsigned long arg );
159 extern int r128_cce_vertex( struct inode *inode, struct file *filp,
160 unsigned int cmd, unsigned long arg );
161 extern int r128_cce_indices( struct inode *inode, struct file *filp,
162 unsigned int cmd, unsigned long arg );
163 extern int r128_cce_blit( struct inode *inode, struct file *filp,
164 unsigned int cmd, unsigned long arg );
165 extern int r128_cce_depth( struct inode *inode, struct file *filp,
166 unsigned int cmd, unsigned long arg );
167 extern int r128_cce_stipple( struct inode *inode, struct file *filp,
168 unsigned int cmd, unsigned long arg );
169 extern int r128_cce_indirect( struct inode *inode, struct file *filp,
170 unsigned int cmd, unsigned long arg );
171
172
173 /* Register definitions, register access macros and drmAddMap constants
174 * for Rage 128 kernel driver.
175 */
176
177 #define R128_AUX_SC_CNTL 0x1660
178 # define R128_AUX1_SC_EN (1 << 0)
179 # define R128_AUX1_SC_MODE_OR (0 << 1)
180 # define R128_AUX1_SC_MODE_NAND (1 << 1)
181 # define R128_AUX2_SC_EN (1 << 2)
182 # define R128_AUX2_SC_MODE_OR (0 << 3)
183 # define R128_AUX2_SC_MODE_NAND (1 << 3)
184 # define R128_AUX3_SC_EN (1 << 4)
185 # define R128_AUX3_SC_MODE_OR (0 << 5)
186 # define R128_AUX3_SC_MODE_NAND (1 << 5)
187 #define R128_AUX1_SC_LEFT 0x1664
188 #define R128_AUX1_SC_RIGHT 0x1668
189 #define R128_AUX1_SC_TOP 0x166c
190 #define R128_AUX1_SC_BOTTOM 0x1670
191 #define R128_AUX2_SC_LEFT 0x1674
192 #define R128_AUX2_SC_RIGHT 0x1678
193 #define R128_AUX2_SC_TOP 0x167c
194 #define R128_AUX2_SC_BOTTOM 0x1680
195 #define R128_AUX3_SC_LEFT 0x1684
196 #define R128_AUX3_SC_RIGHT 0x1688
197 #define R128_AUX3_SC_TOP 0x168c
198 #define R128_AUX3_SC_BOTTOM 0x1690
199
200 #define R128_BRUSH_DATA0 0x1480
201 #define R128_BUS_CNTL 0x0030
202 # define R128_BUS_MASTER_DIS (1 << 6)
203
204 #define R128_CLOCK_CNTL_INDEX 0x0008
205 #define R128_CLOCK_CNTL_DATA 0x000c
206 # define R128_PLL_WR_EN (1 << 7)
207 #define R128_CONSTANT_COLOR_C 0x1d34
208 #define R128_CRTC_OFFSET 0x0224
209 #define R128_CRTC_OFFSET_CNTL 0x0228
210 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
211
212 #define R128_DP_GUI_MASTER_CNTL 0x146c
213 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
214 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
215 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
216 # define R128_GMC_BRUSH_NONE (15 << 4)
217 # define R128_GMC_DST_16BPP (4 << 8)
218 # define R128_GMC_DST_24BPP (5 << 8)
219 # define R128_GMC_DST_32BPP (6 << 8)
220 # define R128_GMC_DST_DATATYPE_SHIFT 8
221 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
222 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
223 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
224 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
225 # define R128_GMC_AUX_CLIP_DIS (1 << 29)
226 # define R128_GMC_WR_MSK_DIS (1 << 30)
227 # define R128_ROP3_S 0x00cc0000
228 # define R128_ROP3_P 0x00f00000
229 #define R128_DP_WRITE_MASK 0x16cc
230 #define R128_DST_PITCH_OFFSET_C 0x1c80
231 # define R128_DST_TILE (1 << 31)
232
233 #define R128_GEN_RESET_CNTL 0x00f0
234 # define R128_SOFT_RESET_GUI (1 << 0)
235
236 #define R128_GUI_SCRATCH_REG0 0x15e0
237 #define R128_GUI_SCRATCH_REG1 0x15e4
238 #define R128_GUI_SCRATCH_REG2 0x15e8
239 #define R128_GUI_SCRATCH_REG3 0x15ec
240 #define R128_GUI_SCRATCH_REG4 0x15f0
241 #define R128_GUI_SCRATCH_REG5 0x15f4
242
243 #define R128_GUI_STAT 0x1740
244 # define R128_GUI_FIFOCNT_MASK 0x0fff
245 # define R128_GUI_ACTIVE (1 << 31)
246
247 #define R128_MCLK_CNTL 0x000f
248 # define R128_FORCE_GCP (1 << 16)
249 # define R128_FORCE_PIPE3D_CP (1 << 17)
250 # define R128_FORCE_RCP (1 << 18)
251
252 #define R128_PC_GUI_CTLSTAT 0x1748
253 #define R128_PC_NGUI_CTLSTAT 0x0184
254 # define R128_PC_FLUSH_GUI (3 << 0)
255 # define R128_PC_RI_GUI (1 << 2)
256 # define R128_PC_FLUSH_ALL 0x00ff
257 # define R128_PC_BUSY (1 << 31)
258
259 #define R128_PCI_GART_PAGE 0x017c
260 #define R128_PRIM_TEX_CNTL_C 0x1cb0
261
262 #define R128_SCALE_3D_CNTL 0x1a00
263 #define R128_SEC_TEX_CNTL_C 0x1d00
264 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
265 #define R128_SETUP_CNTL 0x1bc4
266 #define R128_STEN_REF_MASK_C 0x1d40
267
268 #define R128_TEX_CNTL_C 0x1c9c
269 # define R128_TEX_CACHE_FLUSH (1 << 23)
270
271 #define R128_WAIT_UNTIL 0x1720
272 # define R128_EVENT_CRTC_OFFSET (1 << 0)
273 #define R128_WINDOW_XY_OFFSET 0x1bcc
274
275
276 /* CCE registers
277 */
278 #define R128_PM4_BUFFER_OFFSET 0x0700
279 #define R128_PM4_BUFFER_CNTL 0x0704
280 # define R128_PM4_MASK (15 << 28)
281 # define R128_PM4_NONPM4 (0 << 28)
282 # define R128_PM4_192PIO (1 << 28)
283 # define R128_PM4_192BM (2 << 28)
284 # define R128_PM4_128PIO_64INDBM (3 << 28)
285 # define R128_PM4_128BM_64INDBM (4 << 28)
286 # define R128_PM4_64PIO_128INDBM (5 << 28)
287 # define R128_PM4_64BM_128INDBM (6 << 28)
288 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
289 # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
290 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
291
292 #define R128_PM4_BUFFER_WM_CNTL 0x0708
293 # define R128_WMA_SHIFT 0
294 # define R128_WMB_SHIFT 8
295 # define R128_WMC_SHIFT 16
296 # define R128_WB_WM_SHIFT 24
297
298 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
299 #define R128_PM4_BUFFER_DL_RPTR 0x0710
300 #define R128_PM4_BUFFER_DL_WPTR 0x0714
301 # define R128_PM4_BUFFER_DL_DONE (1 << 31)
302
303 #define R128_PM4_VC_FPU_SETUP 0x071c
304
305 #define R128_PM4_IW_INDOFF 0x0738
306 #define R128_PM4_IW_INDSIZE 0x073c
307
308 #define R128_PM4_STAT 0x07b8
309 # define R128_PM4_FIFOCNT_MASK 0x0fff
310 # define R128_PM4_BUSY (1 << 16)
311 # define R128_PM4_GUI_ACTIVE (1 << 31)
312
313 #define R128_PM4_MICROCODE_ADDR 0x07d4
314 #define R128_PM4_MICROCODE_RADDR 0x07d8
315 #define R128_PM4_MICROCODE_DATAH 0x07dc
316 #define R128_PM4_MICROCODE_DATAL 0x07e0
317
318 #define R128_PM4_BUFFER_ADDR 0x07f0
319 #define R128_PM4_MICRO_CNTL 0x07fc
320 # define R128_PM4_MICRO_FREERUN (1 << 30)
321
322 #define R128_PM4_FIFO_DATA_EVEN 0x1000
323 #define R128_PM4_FIFO_DATA_ODD 0x1004
324
325
326 /* CCE command packets
327 */
328 #define R128_CCE_PACKET0 0x00000000
329 #define R128_CCE_PACKET1 0x40000000
330 #define R128_CCE_PACKET2 0x80000000
331 #define R128_CCE_PACKET3 0xC0000000
332 # define R128_CNTL_HOSTDATA_BLT 0x00009400
333 # define R128_CNTL_PAINT_MULTI 0x00009A00
334 # define R128_CNTL_BITBLT_MULTI 0x00009B00
335 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
336
337 #define R128_CCE_PACKET_MASK 0xC0000000
338 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
339 #define R128_CCE_PACKET0_REG_MASK 0x000007ff
340 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff
341 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800
342
343 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
344 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
345 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
346 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
347 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
348 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
349 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
350 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
351 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
352 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
353 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
354 #define R128_CCE_VC_CNTL_NUM_SHIFT 16
355
356 #define R128_DATATYPE_CI8 2
357 #define R128_DATATYPE_ARGB1555 3
358 #define R128_DATATYPE_RGB565 4
359 #define R128_DATATYPE_RGB888 5
360 #define R128_DATATYPE_ARGB8888 6
361 #define R128_DATATYPE_RGB332 7
362 #define R128_DATATYPE_RGB8 9
363 #define R128_DATATYPE_ARGB4444 15
364
365 /* Constants */
366 #define R128_AGP_OFFSET 0x02000000
367
368 #define R128_WATERMARK_L 16
369 #define R128_WATERMARK_M 8
370 #define R128_WATERMARK_N 8
371 #define R128_WATERMARK_K 128
372
373 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
374
375 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
376 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
377 #define R128_MAX_VB_AGE 0x7fffffff
378 #define R128_MAX_VB_VERTS (0xffff)
379
380 #define R128_RING_HIGH_MARK 128
381
382 #define R128_PERFORMANCE_BOXES 0
383
384
385 #define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
386 #define R128_ADDR(reg) (R128_BASE( reg ) + reg)
387
388 #define R128_READ(reg) readl( (volatile u32 *) R128_ADDR(reg) )
389 #define R128_WRITE(reg,val) writel( (val) , (volatile u32 *) R128_ADDR(reg))
390
391 #define R128_READ8(reg) readb( (volatile u8 *) R128_ADDR(reg) )
392 #define R128_WRITE8(reg,val) writeb( (val), (volatile u8 *) R128_ADDR(reg) )
393
394 #define R128_WRITE_PLL(addr,val) \
395 do { \
396 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
397 ((addr) & 0x1f) | R128_PLL_WR_EN); \
398 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
399 } while (0)
400
401 extern int R128_READ_PLL(drm_device_t *dev, int addr);
402
403
404 #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
405 ((n) << 16) | ((reg) >> 2))
406 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
407 (((reg1) >> 2) << 11) | ((reg0) >> 2))
408 #define CCE_PACKET2() (R128_CCE_PACKET2)
409 #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
410 (pkt) | ((n) << 16))
411
412
413 /* ================================================================
414 * Misc helper macros
415 */
416
417 #define DEV_INIT_TEST_WITH_RETURN(_dev_priv) \
418 do { \
419 if (!_dev_priv) { \
420 DRM_ERROR("called with no initialization\n"); \
421 return -EINVAL; \
422 } \
423 } while (0)
424
425 #define LOCK_TEST_WITH_RETURN( dev ) \
426 do { \
427 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
428 dev->lock.pid != current->pid ) { \
429 DRM_ERROR( "%s called without lock held\n", \
430 __FUNCTION__ ); \
431 return -EINVAL; \
432 } \
433 } while (0)
434
435 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
436 do { \
437 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
438 if ( ring->space < ring->high_mark ) { \
439 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
440 r128_update_ring_snapshot( ring ); \
441 if ( ring->space >= ring->high_mark ) \
442 goto __ring_space_done; \
443 udelay( 1 ); \
444 } \
445 DRM_ERROR( "ring space check failed!\n" ); \
446 return -EBUSY; \
447 } \
448 __ring_space_done: ; \
449 break; \
450 } while (0)
451
452 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
453 do { \
454 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
455 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
456 int __ret = r128_do_cce_idle( dev_priv ); \
457 if ( __ret < 0 ) return __ret; \
458 sarea_priv->last_dispatch = 0; \
459 r128_freelist_reset( dev ); \
460 } \
461 } while (0)
462
463 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
464 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
465 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
466 } while (0)
467
468
469 /* ================================================================
470 * Ring control
471 */
472
473 #if defined(__powerpc__)
474 #define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
475 #else
476 #define r128_flush_write_combine() mb()
477 #endif
478
479
480 #define R128_VERBOSE 0
481
482 #define RING_LOCALS \
483 int write; unsigned int tail_mask; volatile u32 *ring;
484
485 #define BEGIN_RING( n ) do { \
486 if ( R128_VERBOSE ) { \
487 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
488 (n), __FUNCTION__ ); \
489 } \
490 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
491 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
492 } \
493 dev_priv->ring.space -= (n) * sizeof(u32); \
494 ring = dev_priv->ring.start; \
495 write = dev_priv->ring.tail; \
496 tail_mask = dev_priv->ring.tail_mask; \
497 } while (0)
498
499 /* You can set this to zero if you want. If the card locks up, you'll
500 * need to keep this set. It works around a bug in early revs of the
501 * Rage 128 chipset, where the CCE would read 32 dwords past the end of
502 * the ring buffer before wrapping around.
503 */
504 #define R128_BROKEN_CCE 1
505
506 #define ADVANCE_RING() do { \
507 if ( R128_VERBOSE ) { \
508 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
509 write, dev_priv->ring.tail ); \
510 } \
511 if ( R128_BROKEN_CCE && write < 32 ) { \
512 memcpy( dev_priv->ring.end, \
513 dev_priv->ring.start, \
514 write * sizeof(u32) ); \
515 } \
516 r128_flush_write_combine(); \
517 dev_priv->ring.tail = write; \
518 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); \
519 } while (0)
520
521 #define OUT_RING( x ) do { \
522 if ( R128_VERBOSE ) { \
523 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
524 (unsigned int)(x), write ); \
525 } \
526 ring[write++] = cpu_to_le32( x ); \
527 write &= tail_mask; \
528 } while (0)
529
530 #endif /* __R128_DRV_H__ */
531